Vertical gallium nitride tunneling power diode and manufacturing method thereof

Abstract

The invention discloses a vertical gallium nitride tunneling power diode, which mainly solves the problem that the traditional vertical gallium nitride junction barrier power diode cannot simultaneously realize low turn-on voltage, large conduction current and high breakdown voltage, and comprises a substrate (1), a drift layer (2), an anode (8) and a cathode (9), a gradient tunneling layer (4) and a modulation layer (7) are sequentially arranged above the groove; 2n-1 rectangular array holes (5) which are arranged at equal intervals and are the same in size are formed in the middle of the gradient tunneling layer; a tunneling enhancement layer (6) is arranged in the array hole and is used for improving forward conduction current; and the anode is positioned on the upper surface of the modulation layer and the upper surface of the tunneling enhancement layer, forms Schottky contact with the gradient tunneling layer and forms ohmic contact with the modulation layer so as to realize electrical connection. According to the invention, the turn-on voltage and the reverse leakage current are reduced, the conduction current and the breakdown voltage are improved, and the device can be used as a power switch device of a power electronic system.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a Schottky diode device which can be used in a power electronic system. Technical Background

[0002] With the growing demand for renewable energy systems, electric vehicles, aerospace systems, and consumer electronics will require more efficient and fast power electronic devices, among which power switching devices, as important components of power electronic systems, are important components for energy conversion and control. In order to break the limitations of silicon-based materials on device performance, third-generation semiconductor gallium nitride materials have begun to be widely used in the preparation of power devices. Due to the advantages of large bandgap, high saturated electron drift rate, and high critical electric field strength, gallium nitride materials can achieve higher current density and higher withstand voltage range.

[0003] In recent years, a lot of research has been carried out on high-performance vertical GaN diodes at home and abroad. Generally, vertical GaN PN junction diodes have higher voltage resistance and lower leakage current than vertical GaN Schottky diodes. However, the turn-on voltage of vertical GaN PN junction diodes is greater than 3V, resulting in large conduction losses in power switch circuits.

[0004] In order to reduce the switching loss of the device while maintaining the withstand voltage capability, the reference Mg-implanted vertical GaN junction barrier Schottky rectifiers with low on resistance, low turn-on voltage, and nearly ideal nondestructive breakdown voltage, Applied Physics Letters, Vol. 121, No. 20, 2022 discloses a vertical gallium nitride junction barrier power diode, such as Figure 1As shown. It includes: substrate 1, drift layer 2, P-type block 3, anode 4, cathode 5; in this structure, anode 4 forms Schottky contact with drift layer 2 and ohmic contact with P-type block 3. When working in the forward direction, the Schottky junction conduction device is turned on. When working in the reverse direction, the depletion region of P-type block 3 expands to transfer the electric field peak to the inside of drift layer 2 to protect the Schottky junction interface. Although this structure can improve the reverse withstand voltage capability to a certain extent, the high breakdown voltage requires a smaller spacing between P-type blocks. Conversely, low on-resistance and high on-current require a larger spacing between P-type blocks, and a larger spacing between P-type blocks will result in a larger reverse leakage current of the device and a smaller breakdown voltage. Therefore, this contradiction makes it impossible for the device to achieve low on-resistance and high breakdown voltage at the same time. In addition, the preparation conditions of local P-type gallium nitride materials are relatively complex, the equipment requirements are high, and the impurity activation rate is not high, resulting in the reverse leakage of the junction barrier Schottky diode is still relatively large and the withstand voltage capability is relatively low. Therefore, it is necessary to reduce forward conduction loss and reverse leakage current and realize a power diode with high breakdown voltage and low on-resistance. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a vertical gallium nitride tunneling power diode, which achieves a low turn-on voltage while reducing the reverse leakage of the device, so as to increase the reverse breakdown voltage and reduce the on-resistance, thereby solving the technical problem that the existing vertical gallium nitride junction barrier power diode is difficult to achieve high breakdown voltage and low on-resistance at the same time.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] 1. A vertical gallium nitride tunneling power diode, comprising: a substrate 1, a drift layer 2, an anode 8, and a cathode 9, wherein grooves 3 are provided on the left and right sides of the drift layer 2, characterized in that:

[0008] A gradient tunneling layer 4 and a modulation layer 7 are sequentially arranged above the groove 3, 2n-1 rectangular array holes 5 of equal spacing and the same size are arranged in the middle of the gradient tunneling layer 4, and a tunneling enhancement layer (6) is arranged in the array hole 5 to increase the forward conduction current;

[0009] The anode 8 is located on the upper surface of the modulation layer 7 and the upper surface of the tunneling enhancement layer 6 for achieving electrical connection.

[0010] Furthermore, the substrate 1 is made of gallium nitride material; the graded tunneling layer 4 is made of AlGaN material with an increasing Al composition from bottom to top, and the Al composition ranges from 0 to 35%. When the device conducts forward, it forms an AlGaN / GaN heterojunction structure with the drift layer 2, polarizing a two-dimensional electron gas, increasing the forward conduction current, and increasing the current during the turn-on process by enhancing the tunneling probability of carriers, reducing the forward turn-on voltage of the device. When the device blocks reversely, it is beneficial to increase the barrier layer height of the Schottky junction and reduce the reverse leakage current.

[0011] Furthermore, the tunneling enhancement layer 6 is made of Ta 2 O 5 、ZrO 2 、HfO 2 、TiO 2 or any one of the high-K dielectric materials with a dielectric constant greater than that of the AlGaN material, which is used to enhance the tunneling probability of carriers, increase the forward conduction current, and reduce the turn-on voltage.

[0012] The modulation layer 7 is made of P-type NiO material with a hole concentration of 1×10 18 ~8×10 20 cm -3 , which is used to inject holes into the drift layer 2 to attract more electrons to participate in conduction and increase the forward conduction current. When the device blocks reversely, it shields the Schottky surface electric field, transfers the electric field peak to the inside of the drift layer 2, avoids premature breakdown of the device at the Schottky junction, and improves the breakdown voltage of the device.

[0013] Furthermore, for the groove 3, its depth is a, its width is b, and the distance between adjacent two grooves is c, and b < c is satisfied; for the graded tunneling layer 4, its thickness k 1 is 5 - 10 nm, and the length k 2 of its left and right ends extending laterally outside the groove 3 is 20 - 100 nm; for the modulation layer 7, its thickness k 3 is 80 - 300 nm, and the lateral overlapping length k 4 of its left and right ends with the graded tunneling layer 4 outside the groove 3 is 10 - 50 nm.

[0014] Furthermore, the tunneling enhancement layer 6 is composed of 2n - 1 equally spaced and identical rectangular high-K dielectric blocks, the lateral width of each high-K dielectric block is t, the interval between adjacent two high-K dielectric blocks is c 2 , the lateral distance between the first high-K dielectric block on the left and the modulation layer 7 on the left is c 1 , the lateral distance between the first high-K dielectric block on the right and the modulation layer 7 on the right is c 1 , and c 1 > 0, c 2 > t > 0, c1 =c 2 .

[0015] Furthermore, a Schottky contact is formed between the anode 8 and the gradient tunneling layer 4 ; and an Ohmic contact is formed between the anode 8 and the modulation layer 7 .

[0016] 2. A method for manufacturing a vertical gallium nitride tunneling power diode, characterized in that it comprises the following steps:

[0017] A) epitaxial growth of n on substrate 1 - Type GaN semiconductor material, forming a drift layer 2;

[0018] B) making a mask on the drift layer 2 for the first time, and etching the drift layer 2 using the mask to form a groove 3;

[0019] C) making a mask on the drift layer 2 for the second time, and using the mask to epitaxially grow AlGaN semiconductor material on the upper surface of the drift layer 2 and the bottom and sidewalls of the groove 3 to form a graded tunneling layer 4 with a thickness of 5 to 10 nm;

[0020] D) making a mask for the third time on the drift layer 2 and the gradient tunneling layer 4, and using the mask to etch the gradient tunneling layer 4 to form array holes 5;

[0021] E) making a mask for the fourth time on the drift layer 2 and the graded tunneling layer 4, and using the mask to fill the array holes 5 with a high-K medium to form a tunneling enhancement layer 6;

[0022] F) making a mask for the fifth time on the back of the substrate 1, using the mask to deposit metal on the back of the substrate 1, and performing rapid thermal annealing to form a cathode 9;

[0023] G) making a mask for the sixth time on the drift layer 2, the graded tunneling layer 4 and the tunneling enhancement layer 6, using the mask to sputter a P-type NiO material on the graded tunneling layer 4, and forming a modulation layer (7) with a thickness of 80 to 300 nm by a lift-off process;

[0024] H) A mask is made for the seventh time on the drift layer 2, the graded tunneling layer 4 and the modulation layer 7, and a metal is deposited using the mask to form an anode 8, thereby completing the preparation of the entire device.

[0025] Compared with the traditional vertical gallium nitride junction barrier power diode, the device of the present invention has the following advantages:

[0026] First, the device of the present invention, due to the addition of a gradient tunneling layer formed of AlGaN material, can generate electron tunneling current under a small forward voltage, quickly reach the current required when the device is turned on, thereby reducing the opening time of the device.

[0027] Voltage; in reverse blocking, since the bandgap width of AlGaN is greater than that of GaN, the barrier height of the Schottky junction can be increased, the probability of electrons in the metal flowing into the semiconductor can be reduced, and the reverse leakage current under the same voltage can be suppressed; at the same time, since the gradient tunneling layer is inserted between the modulation layer and the drift layer, the reverse leakage current of the heterojunction formed by P-type NiO and N-type gallium nitride can be suppressed

[0028] Secondly, since the device of the present invention is provided with 2n-1 rectangular array holes of equal intervals and the same size in the middle of the gradient tunneling layer, and a tunneling enhancement layer is provided in the array hole, the different properties of the dielectric constants of the gradient tunneling layer and the tunneling enhancement layer can be utilized to change the peak value of the transverse electric field during forward conduction, so that it causes a sudden change at the interface of the two materials, inducing the potential barrier width at the interface to narrow, thereby greatly improving the tunneling probability of the carriers, increasing the forward conduction current, and reducing the turn-on voltage.

[0029] Third, the device of the present invention uses P-type NiO material to form a modulation layer. Compared with P-type gallium nitride materials with low impurity activation rate and difficult to increase hole concentration, P-type NiO material has a simple preparation process and high hole concentration, which increases the number of carriers injected into the drift layer when the device is forward-conducted, thereby increasing the on-current and reducing the on-resistance.

[0030] Fourthly, the device of the present invention adopts a groove structure to allow the P-type NiO material to penetrate into the drift layer. When the device is reverse blocked, the heterogeneous PN junction depletion region formed by the modulation layer and the drift layer can be expanded, which can greatly reduce the electric field peak on the surface of the Schottky junction and improve the voltage resistance of the device.

[0031] Fifthly, the gradient tunneling layer of the device of the present invention is inserted between the modulation layer and the drift layer, which can suppress the reverse leakage current of the heterojunction formed by P-type NiO and N-type gallium nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is the structural diagram of a traditional vertical GaN junction barrier power diode;

[0033] Figure 2 is a structural diagram of a vertical gallium nitride tunneling power diode of the present invention;

[0034] Figure 3 It is a schematic diagram of the process of preparing a vertical gallium nitride tunneling power diode according to the present invention;

[0035] Figure 4 It is a forward conduction curve diagram simulating the device of the present invention and the traditional vertical gallium nitride junction barrier power diode;

[0036] Figure 5 It is a reverse breakdown curve diagram of the simulated device of the present invention and a traditional vertical gallium nitride junction barrier power diode. DETAILED DESCRIPTION

[0037] The embodiments and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0038] Reference Figure 2 The vertical gallium nitride tunneling power diode of this example includes: a substrate 1, a drift layer 2, a groove 3, a gradient tunneling layer 4, an array hole 5, a tunneling enhancement layer 6, a modulation layer 7, an anode 8, and a cathode 9. Among them:

[0039] The substrate 1 is a gallium nitride homogeneous substrate;

[0040] The drift layer 2 is located on the upper part of the substrate 1 and is made of gallium nitride;

[0041] The groove 3 is located on the left and right sides of the drift layer 2, and its depth a is 10-200nm, width b is 10-500nm, and the distance c between two adjacent grooves is 5-450nm, and b satisfies <c;

[0042] The gradient tunneling layer 4 is located on the upper surface of the drift layer 2 and the bottom and sidewall of the groove 3. It is made of AlGaN material with Al content gradually increasing from bottom to top. The Al content range is 0-20%. Its thickness k 1 The length k of the left and right ends extending laterally outside the groove 3 is 5 to 10 nm. 2 20~100nm;

[0043] The array holes 5 are located between two grooves on the upper surface of the drift layer 2;

[0044] The tunneling enhancement layer 6 is located inside the array hole 5 and is made of Ta 2 O 5 、ZrO 2 , HfO 2 、TiO 2 Any high-K dielectric material having a dielectric constant greater than that of AlGaN material;

[0045] The modulation layer 7 is located on the gradient tunneling layer 4 and is made of P-type NiO material with a thickness k 3 80~300nm, hole concentration is 1×10 19 ~8×10 20 cm -3 The lateral overlap length k between the left and right ends of the gradient tunneling layer 4 outside the groove 3 is 4 10~50nm;

[0046] The anode 8 is located on the graded tunneling layer 4 , the tunneling enhancement layer 6 and the modulation layer 7 , and forms a Schottky contact with the graded tunneling layer 4 and an Ohmic contact with the modulation layer 7 , respectively.

[0047] The cathode 9 is located on the lower surface of the substrate 1, and an ohmic contact is formed between the two.

[0048] Reference Figure 3 The present invention provides a method for manufacturing a vertical gallium nitride tunneling power diode, and provides the following three embodiments.

[0049] Example 1: Fabrication of a gradient tunneling layer 4 with a thickness k 1 The Al content is 5 nm, the Al content is in the range of 0-20%, and the length k of the left and right ends extending laterally outside the groove 3 is 2 The array hole is 20nm, the array hole is 5, the width t of each array hole is 1μm, and the distance between two adjacent holes is c 2 is 1.5 μm, and the distance c between the outermost hole and the side modulation layer 7 is 1 7μm, the tunneling enhancement layer 6 is made of HfO 2 Vertical GaN tunneling power diodes.

[0050] Step 1. Prepare the drift layer 2, such as Figure 3 a.

[0051] Using metal organic chemical vapor deposition technology, a 5 μm thick epitaxial layer with a doping concentration of 1×10 14 cm -3 n - The process conditions are: temperature 800℃, pressure 30Torr, SiH 4 As the doping source, the hydrogen flow rate is 4000sccm, the ammonia flow rate is 4000sccm, and the gallium source flow rate is 100μmol / min.

[0052] Step 2. Make groove 3, such as Figure 3 b.

[0053] A mask is first made on the drift layer 2, and a groove is etched on the drift layer 2 using the reactive ion etching technology with a depth of 2 μm, a width of 10 μm, and a spacing of 30 μm between adjacent grooves, to form a groove 3. The etching process conditions are: Cl 2 The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.

[0054] Step 3. Make a gradient tunneling layer 4, such as Figure 3 c.

[0055] A mask is made on the drift layer 2 for the second time, and the mask is used to epitaxially grow AlGaN material with a thickness of 5 nm on the drift layer 2 and the bottom and sidewall of the groove 3 using metal organic chemical vapor deposition technology to form a graded tunneling layer 4. The process conditions are: temperature of 800°C, pressure of 30 Torr, hydrogen flow rate of 4000sccm, ammonia flow rate of 3500sccm, gallium source flow rate of 30μmol / min, and aluminum source flow rate of 5μmol / min.

[0056] Step 4. Make array holes 5, such as Figure 3 d.

[0057] A mask is made on the drift layer 2 and the gradient tunneling layer 4 for the third time, and the gradient tunneling layer 4 is etched by reactive ion etching technology using the mask, with an etching depth of 5 nm to form array holes 5. The process conditions are: Cl 2 The flow rate is 10sccm, the pressure is 5mTorr, and the power is 50W.

[0058] Step 5. Make a tunneling enhancement layer 6, such as Figure 3 e.

[0059] A mask is fabricated on the drift layer 2 and the graded tunneling layer 4 for the fourth time, and HfO is deposited in the array holes 5 by using the mask using the radio frequency magnetron reactive sputtering technology. 2 , forming a tunneling enhancement layer 6. The process conditions are: the sputtering pressure in the reaction chamber is 0.1 Pa, O 2 The flow rates of Ar and Ar were 1 sccm and 8 sccm respectively, and the temperature was 200°C.

[0060] Step 6. Make cathode 9, such as Figure 3 f.

[0061] A mask is made for the fifth time on the back of the substrate 1, and the mask is used to deposit metal on the back of the substrate 1 using electron beam evaporation technology. The deposited metal is a combination of Ti / Au / Ni metals, that is, Ti, Au and Ni from bottom to top, with thicknesses of 0.02μm, 0.3μm and 0.05μm, respectively. The process conditions of electron beam evaporation are: vacuum degree of 1.8×10 -3 Pa, the power is 350W, and the evaporation rate is

[0062] The deposited metal is then rapidly thermally annealed to form a cathode 9, wherein the thermal annealing process conditions are: temperature of 850° C. and time of 35 seconds.

[0063] Step 7. Make a modulation layer 7, such as Figure 3 g.

[0064] The sixth mask is made on the drift layer 2, the graded tunneling layer 4 and the tunneling enhancement layer 6. The mask is used to sputter P-type NiO material on the graded tunneling layer 4 using low-temperature sputtering technology, and a modulation layer 7 with a thickness of 80 nm is formed by a lift-off process. The process conditions are: vacuum degree 4.0×10 -4 Pa, RF power is 100W, O 2 The flow rates are 1 sccm and the Ar flow rate is 1 sccm respectively.

[0065] Step 8. Make anode 8, such as Figure 3 h.

[0066] A seventh mask is made on the drift layer 2, the gradient tunneling layer 4 and the modulation layer 7. The mask is used to deposit metal on the gradient tunneling layer 4 and the modulation layer 7 by electron beam evaporation technology. The deposited metal is Ni. The process conditions are: vacuum degree 5×10 -4 Pa, the power is 200W, and the evaporation rate is The anode 8 is formed to complete the preparation of the entire device.

[0067] Example 2: Making a gradient tunneling layer 4 with a thickness k 1 The Al content is 0-20%, and the length k of the left and right ends extending laterally outside the groove 3 is 2 is 50nm, the number of array holes 5 is 11, the width t of each hole is 1.5μm, and the distance c between two adjacent holes is 2 is 2 μm, and the distance c between the outermost hole and the left modulation layer 7 or the right modulation layer 7 is 1 5μm, the tunneling enhancement layer 6 is made of TiO 2 Vertical GaN tunneling power diodes.

[0068] Step 1. Make a drift layer 2, such as Figure 3 a.

[0069] Using metal organic chemical vapor deposition technology, under the process conditions of temperature of 900 ° C, pressure of 45 Torr, hydrogen flow rate of 5000 sccm, ammonia flow rate of 4600 sccm, and gallium source flow rate of 160 μmol / min, an epitaxial layer with a thickness of 10 μm and a doping concentration of 5×10 15 cm -3 n - type GaN, forming the drift layer 2.

[0070] Step 2. Make groove 3, such as Figure 3 b.

[0071] The first mask is made on the top of the drift layer 2. 2Under the process conditions of flow rate of 15 sccm, pressure of 10 mTorr and power of 110 W, reactive ion etching technology is used to etch on both sides of the drift layer 2, with an etching depth of 4 μm, a width of 15 μm and a spacing of 50 μm between adjacent grooves, to form grooves 3.

[0072] Step 3. Make a gradient tunneling layer 4, such as Figure 3 c.

[0073] A mask is made on the drift layer 2 for the second time. Under the process conditions of temperature of 950°C, pressure of 45 Torr, hydrogen flow rate of 5000 sccm, ammonia flow rate of 3800 sccm, gallium source flow rate of 40 μmol / min, and aluminum source flow rate of 5 μmol / min, a metal organic chemical vapor deposition technique is used to epitaxially grow a layer with a thickness of k on the drift layer 2 and the two grooves 3. 1 The AlGaN material is 8 nm thick and forms a graded tunneling layer 4.

[0074] Step 4. Make array holes 5, such as Figure 3 d.

[0075] A mask is formed on the drift layer 2 and the graded tunnel layer 4 for the third time. 2 Under the process conditions of a flow rate of 10 sccm, a pressure of 5 mTorr, and a power of 50 W, the gradient tunneling layer 4 is etched using a reactive ion etching technique with an etching depth of 8 nm to form array holes 5 .

[0076] Step 5. Make a tunneling enhancement layer 6, such as Figure 3 e.

[0077] The fourth mask is made on the drift layer 2 and the graded tunneling layer 4. The sputtering pressure in the reaction chamber is about 50 Pa. 2 Under the process conditions of Ar flow rate of 10 sccm and 50 sccm respectively and temperature of 200 °C, TiO was deposited in the array hole 5 by using radio frequency magnetron reactive sputtering technology. 2 , forming a tunneling enhancement layer 6.

[0078] Step 6. Make cathode 9, such as Figure 3 f.

[0079] 6.1) The fifth mask is made on the back of substrate 1 at a vacuum degree of 8×10 -4 Pa, the power is 400W, and the evaporation rate is Under the process conditions of , electron beam evaporation technology is used to deposit metal on the back of the substrate 1, wherein the deposited metal is a combination of Ti / Al / Au / Ni metals, that is, Ti, Al, Ni, Au from bottom to top, and their thicknesses are 0.02μm, 0.14μm, 0.055μm, and 0.045μm, respectively;

[0080] 6.2) The deposited metal is subjected to rapid thermal annealing at a temperature of 860° C. for 30 seconds to form a cathode 9.

[0081] Step 7. Make a modulation layer 7, such as Figure 3 g.

[0082] The sixth mask is made on the drift layer 2, the graded tunneling layer 4 and the tunneling enhancement layer 6. - 4 Pa, RF power is 100W, O 2 Under the process conditions of 1 sccm flow rate and 1 sccm Ar flow rate, a layer of thickness k is sputtered on the graded tunneling layer 4 using RF magnetron reactive sputtering technology. 3 The modulation layer 7 is formed by a 150nm thick P-type NiO material.

[0083] Step 8. Make anode 8, such as Figure 3 h.

[0084] The seventh mask is made on the drift layer 2, the graded tunneling layer 4 and the modulation layer 7. -3 Pa, the power is 350W, and the evaporation rate is Under the process conditions, the metal Wu is deposited on the tunneling layer 4 and the modulation layer 5 by electron beam evaporation technology to form the anode 8, thereby completing the preparation of the entire device.

[0085] Example 3: Fabrication of a gradient tunneling layer 4 with a thickness k 1 The array has 13 holes, each hole has a width of 3 μm, and the distance between two adjacent holes is c. 2 is 5 μm, and the distance c between the outermost hole and the modulation layer 7 is 1 10μm; the tunneling enhancement layer 6 is made of Ta 2 O 5 Vertical GaN tunneling power diodes.

[0086] Step A. Prepare the drift layer 2, such as Figure 3 a.

[0087] Set the vacuum degree to 1.0×10 -10 mbar, the RF power is 400W, and the reactant is N 2 , the process conditions of high-purity Ga source, using molecular beam epitaxy technology on substrate 1 with an epitaxial thickness of 12μm and a doping concentration of 1×10 16 cm -3 n - type GaN, forming the drift layer 2.

[0088] Step B. Make groove 3, such as Figure 3 b.

[0089] Setting Cl 2 Under the process conditions of flow rate of 15 sccm, pressure of 10 mTorr and power of 100 W, a mask is made on the drift layer 2 for the first time, and etching is performed on both sides of the drift layer 2 with a depth of 5 μm and a width of 20 μm using reactive ion etching technology to form two grooves 3 with a spacing of 80 μm.

[0090] Step C. Making a gradient tunneling layer 4, such as Figure 3 c.

[0091] The process conditions are set to 900°C, 80 Torr, 4800 sccm hydrogen flow, 4900 sccm ammonia flow, 150 μmol / min gallium source flow, and 50 μmol / min aluminum source flow. A mask is made on the drift layer 2 for the second time, and a metal organic chemical vapor deposition technique is used to epitaxially grow a thickness k on the upper surface of the drift layer 2 and the bottom and sidewall of the groove 3. 1 The AlGaN material is 10 nm thick and forms a graded tunneling layer 4.

[0092] Step D. Make array holes 5, such as Figure 3 d.

[0093] Setting Cl 2 Under the process conditions of flow rate of 10 sccm, pressure of 5 mTorr and power of 50 W, a mask is made on the drift layer 2 and the gradient tunneling layer 4 for the third time, and the gradient tunneling layer 4 is etched to a depth of 10 nm using reactive ion etching technology to form array holes 5.

[0094] Step E. Fabricate the tunneling enhancement layer 6, such as Figure 3 e.

[0095] The sputtering pressure in the reaction chamber was set to 300 Pa, O 2 Under the process conditions of 50 sccm and 100 sccm of Ar and 900°C, a mask is made on the drift layer 2 and the graded tunneling layer 4 for the fourth time, and Ta is deposited in the array hole 5 using the RF magnetron reactive sputtering technology. 2 O 5 , forming a tunneling enhancement layer 6.

[0096] Step F. Prepare cathode 9, such as Figure 3 f.

[0097] The fifth mask is made on the back of the substrate 1, and the vacuum degree is less than 1.8×10 -3 Pa, the power is 500W, and the evaporation rate is Under process conditions, electron beam evaporation technology is used to deposit metal on the back of the substrate 1, wherein the deposited metal is a Ti / Al / Mo / Au metal combination, that is, Ti, Al, Mo and Au from bottom to top, with thicknesses of 0.02μm, 0.1μm, 0.03μm and 0.03μm respectively, and then rapid thermal annealing is performed under process conditions of 860°C and 30s to form a cathode 9.

[0098] Step G. Make a modulation layer 7, such as Figure 3 g.

[0099] The sixth mask is made on the drift layer 2, the graded tunneling layer 4 and the tunneling enhancement layer 6, and the vacuum degree is set to 300 Pa. 2 Under the process conditions of a flow rate of 50 sccm and an Ar flow rate of 100 sccm, a RF magnetron reactive sputtering technique was used to sputter a layer of thickness k on the gradient tunneling layer 4 using the mask made in the sixth step. 3 The modulation layer 7 is formed by a 300nm thick P-type NiO material.

[0100] Step H. Make anode 8, such as Figure 3 h.

[0101] The seventh mask is made on the drift layer 2, the gradient tunneling layer 4 and the modulation layer 7, and the vacuum degree is set to 1.8×10 - 3 Pa, the power is 1000W, and the evaporation rate is Under the process conditions, the metal Mo is deposited on the gradient tunneling layer 4 and the modulation layer 7 by using the electron beam evaporation technology using the mask made for the seventh time to form the anode 8, thereby completing the manufacture of the entire device.

[0102] The effect of the present invention can be further illustrated by the following simulation results.

[0103] Simulation 1: Using the simulation software Silvaco, the forward conduction characteristics of the conventional vertical GaN junction barrier power diode and the device of the third embodiment of the present invention are simulated respectively. The results are as follows: Figure 4 As shown. Figure 4 It can be seen that the turn-on voltage of the device of the present invention is 0.4 V, and the turn-on voltage of the traditional junction barrier Schottky diode is 0.7 V. This shows that the device of the present invention has the advantages of large on-state current and small on-state resistance.

[0104] Simulation 2: Using the simulation software Silvaco, the breakdown characteristics of the conventional vertical GaN junction barrier power diode and the device of the third embodiment of the present invention are simulated. The results are as follows: Figure 5 As shown. Figure 5It can be seen that the breakdown voltage of the device of the present invention is about 1560V, and the breakdown voltage of the traditional vertical gallium nitride junction barrier power diode is only about 660V, indicating that the device of the present invention has better voltage resistance than the traditional device.

[0105] The above descriptions are only three specific embodiments of the present invention and do not constitute a limitation of the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, they can make various modifications and changes in form and details according to the method of the present invention without departing from the principles and scope of the present invention. For example, in addition to using metal organic chemical vapor deposition technology and molecular beam epitaxy technology to prepare AlGaN and GaN materials, hydride vapor phase epitaxy technology and atomic layer deposition technology can also be used; in addition to using radio frequency magnetron reactive sputtering technology to prepare tunneling enhancement layers, atomic layer deposition technology and plasma enhanced chemical vapor deposition technology can also be used; in addition to using Ta to prepare tunneling enhancement layers 2 O 5 、ZrO 2 , HfO 2 In addition to the medium, TiO 2 Medium; molecular beam epitaxy technology uses a pressure of 1.0×10 - 10 mbar, the RF power is 400W, and the pressure can also be 1.0×10 -10 ~7.0×10 -10 mbar, and other process parameters within the range of RF power of 100 to 800 W, but these modifications and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A vertical gallium nitride tunneling power diode, comprising: A substrate (1), a drift layer (2), an anode (8), and a cathode (9), wherein grooves (3) are provided on the left and right sides of the drift layer (2), and the characteristics are: A gradient tunneling layer (4) and a modulation layer (7) are sequentially arranged above the groove (3); 2n-1 rectangular array holes (5) of equal spacing and the same size are arranged in the middle of the gradient tunneling layer (4); a tunneling enhancement layer (6) is arranged in the array hole (5) for increasing the forward conduction current; The anode (8) is located on the upper surface of the modulation layer (7) and the upper surface of the tunneling enhancement layer (6) and is used to achieve electrical connection.

2. The device according to claim 1, characterized in that: The substrate (1) is made of gallium nitride material. The gradient tunneling layer (4) is made of AlGaN material whose Al content gradually increases from bottom to top, and the Al content range is 0-35%. When the device is forward-conducted, it forms an AlGaN / GaN heterojunction structure with the drift layer (2), polarizes a two-dimensional electron gas, increases the forward conduction current, and can increase the current during the turn-on process by improving the tunneling probability of carriers, thereby reducing the forward turn-on voltage of the device. When the device is reverse-blocked, it is beneficial to increase the barrier layer height of the Schottky junction and reduce the reverse leakage current.

3. The device according to claim 1, characterized in that: The tunneling enhancement layer (6) is made of any one of Ta2O5, ZrO2, HfO2 and TiO2, a high-K dielectric material with a dielectric constant greater than that of AlGaN material, and is used to increase the tunneling probability of carriers, increase the forward conduction current and reduce the turn-on voltage; The modulation layer (7) is made of P-type NiO material with a hole concentration of 1×10 18 ~8×10 20 cm -3 , which is used to attract more electrons to participate in conduction by injecting holes into the drift layer (2), thereby increasing the forward conduction current; when the device is reversely blocked, the Schottky surface electric field is shielded, and the electric field peak is transferred to the inside of the drift layer (2), thereby preventing the device from breaking down prematurely at the Schottky junction and improving the voltage resistance of the device.

4. The device according to claim 1, characterized in that: The groove (3) has a depth of a, a width of b, a distance between two adjacent grooves of c, and satisfies b <c; The gradient tunneling layer (4) has a thickness k1 of 5 to 10 nm, and a length k2 of 20 to 100 nm extending laterally from the left and right ends of the gradient tunneling layer (4) outside the groove (3); The modulation layer (7) has a thickness k3 of 80 to 300 nm, and a lateral overlap length k4 between its left and right ends and the gradient tunneling layer (4) outside the groove (3) of 10 to 50 nm.

5. The device according to claim 1, characterized in that: The tunneling enhancement layer (6) is composed of 2n-1 rectangular high-K dielectric blocks that are equally spaced and of the same size, the lateral width of each high-K dielectric block is t, the interval between two adjacent high-K dielectric blocks is c2, the lateral spacing between the first high-K dielectric block on the left and the left modulation layer (7) is c1, the lateral spacing between the first high-K dielectric block on the right and the right modulation layer (7) is c1, and c1>0, c2>t>0, and c1=c2.

6. The device according to claim 1, characterized in that: A Schottky contact is formed between the anode (8) and the gradient tunneling layer (4); An ohmic contact is formed between the anode (8) and the modulation layer (7).

7. A method for manufacturing a vertical gallium nitride tunneling power diode, characterized in that: The steps include: A) epitaxial growth of n on substrate (1) - type GaN semiconductor material, forming a drift layer (2); B) making a mask on the drift layer (2) for the first time, and etching the drift layer (2) using the mask to form a groove (3); C) making a mask on the drift layer (2) for the second time, and using the mask to epitaxially grow AlGaN semiconductor material on the upper surface of the drift layer (2) and the bottom and side walls of the groove (3) to form a graded tunneling layer (4) with a thickness of 5 to 10 nm; D) making a mask for the third time on the drift layer (2) and the gradient tunneling layer (4), and using the mask to etch on the gradient tunneling layer (4) to form array holes (5); E) forming a mask for the fourth time on the drift layer (2) and the graded tunneling layer (4), and using the mask to fill a high-K medium in the array hole (5) to form a tunneling enhancement layer (6); F) making a mask for the fifth time on the back of the substrate (1), using the mask to deposit metal on the back of the substrate (1), and performing rapid thermal annealing to form a cathode (9); G) making a mask for the sixth time on the drift layer (2), the gradient tunneling layer (4) and the tunneling enhancement layer (6), using the mask to sputter a P-type NiO material on the gradient tunneling layer (4), and forming a modulation layer (7) with a thickness of 80 to 300 nm by a lift-off process; H) Making a mask for the seventh time on the drift layer (2), the gradient tunneling layer (4) and the modulation layer (7), and using the mask to deposit metal to form an anode (8), thereby completing the preparation of the entire device.

8. The method according to claim 7, characterized in that: The step A) epitaxial growth n - The step C) epitaxially growing AlGaN semiconductor material is performed by metal organic chemical vapor deposition technology or molecular beam epitaxy technology, wherein: The process conditions of the metal organic chemical vapor deposition technology are as follows: The temperature is 800-1000°C, the pressure is 30-100 Torr, and the hydrogen flow rate is 4000-6000 sccm. The ammonia flow rate is 3500-5500 sccm, and the gallium source flow rate is 100-300 μmol / min. The aluminum source flow rate is 5-50 μmol / min; The molecular beam epitaxy technology has the following process conditions: The pressure is 1.0×10 -10 ~7.0×10 -10 mbar, RF power is 100~800W, The reactants are N2 and a high-purity Ga source.

9. The method according to claim 7, characterized in that: The tunneling enhancement layer in step E) and the modulation layer in step G) are both prepared by radio frequency magnetron reactive sputtering technology, and the process conditions are as follows: The sputtering pressure in the reaction chamber is 0.1~300Pa. O2 flow rate is 1~50sccm, Ar flow rate is 1~100sccm, The temperature is 100~600℃. The cathode in step F) and the anode in step H) are both prepared by electron beam evaporation technology to deposit metals, and the process conditions are as follows: Vacuum degree: 5×10 -4 ~1.8×10 -3 Pa, Power: 200~1000W, evaporation rate is less than The rapid thermal annealing process conditions are: temperature of 800-900° C. and time of 30-75 seconds.

10. The method according to claim 7, characterized in that: The grooves in step B) and the array holes in step D) are both made by reactive ion etching technology, and the process conditions are as follows: Cl2 flow rate: 15~60sccm, Pressure: 10~100mTorr, The power is: 100~500W.

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