Semiconductor device and method of manufacture, power module, power conversion circuit, vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors. The semiconductor body comprises a first surface and a second surface arranged oppositely, the first surface is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body. A gate structure is located in the gate trench. A first barrier layer is located between the gate structure and the inner wall of the gate trench, and a second barrier layer covers at least a third surface of the gate structure away from the second surface. In the process of forming the second barrier layer, the sharp corners of the gate structure in the related art are smoothed by oxidation, the connection between the side surface of the gate structure and the third surface is relatively smooth, charge concentration can be avoided, the risk of gate-source-drain current is greatly reduced, the reliability of the device is improved, the source-drain conduction resistance of the device is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] In silicon carbide dual-trench devices, the gate structure is typically formed by depositing polysilicon within the gate trench and then etching it. Due to the polysilicon etching process, some sharp corners will form on the surface of the gate structure within the gate trench after etching. In semiconductor devices, these sharp corners can lead to electric field concentration, easily causing gate-source leakage and affecting device reliability. Summary of the Invention

[0003] This application provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, aiming to improve device reliability.

[0004] In a first aspect, this application provides a semiconductor device, including a semiconductor body, a gate structure, a source, a drain, a first barrier layer, and a second barrier layer. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. A gate trench is formed on the first surface, extending from the first surface into the semiconductor body, and the gate structure is located within the gate trench. The first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure on the side furthest from the second surface. The source is located on the first surface, and the drain is located on the second surface.

[0005] In some embodiments, the gate structure further includes a side surface near the inner wall of the gate trench, and a third surface is connected to the side surface. The minimum included angle between the third surface and the side surface ranges from 80° to 100°.

[0006] In some embodiments, in the direction from the second surface to the first surface, the projection of the first barrier layer on the first surface falls into the projection of the second barrier layer on the first surface.

[0007] In some embodiments, the first surface is further provided with a source trench extending from the first surface into the semiconductor body. The semiconductor device also includes a source trench structure located within the source trench. A first barrier layer is also located between the source trench structure and the inner wall of the source trench, and a second barrier layer further covers the side of the first barrier layer away from the second surface.

[0008] In some embodiments, the first barrier layer and the second barrier layer are made of the same material, both comprising silicon oxide.

[0009] Secondly, this application also provides a method for fabricating a semiconductor device, comprising the following steps S01 to S04:

[0010] Step S01: Form a gate trench on the semiconductor body, wherein the semiconductor body is configured as a first conductivity type, the semiconductor body includes a first surface and a second surface disposed opposite to each other, and the gate trench extends from the first surface into the semiconductor body.

[0011] Step S02: A gate structure is formed in the gate trench, and a first barrier layer and a second barrier layer are formed. The first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers the third surface of the gate structure on the side away from the second surface.

[0012] Step S03: Form the source electrode on the first surface.

[0013] Step S04: Form a drain electrode on the second surface.

[0014] In some embodiments, forming the second barrier layer includes thermally oxidizing the third surface of the gate structure to form the second barrier layer.

[0015] On the other hand, embodiments of this application also provide a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0016] In another aspect, embodiments of this application also provide a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as described in any of the above embodiments, the semiconductor device being electrically connected to the circuit board.

[0017] In another aspect, embodiments of this application also provide a vehicle, which includes a load and a power conversion circuit as described in the above embodiments. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0018] In the embodiments provided in this application, the semiconductor body includes a first surface and a second surface disposed opposite to each other. A gate trench is formed on the first surface, extending from the first surface into the semiconductor body. The semiconductor body also includes a first barrier layer and a second barrier layer located within the gate trench. The gate structure is located within the gate trench, the first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure on the side furthest from the second surface. In related technologies, to form patterned gate structures and source trench structures, the deposited polysilicon material needs to be etched. Due to the influence of the device structure, after etching, sharp corners will exist on the surface edges of the gate structure. In semiconductor devices, these sharp corners can lead to electric field concentration and gate-source leakage, affecting device reliability. Furthermore, they require a wider gate insulating layer to protect the gate structure, which is detrimental to the miniaturization of semiconductor devices. In this application, during the thermal oxidation process of the third surface of the gate structure to form the second barrier layer, the third surface of the gate structure is modified. Sharp corners, common in related technologies, are smoothed by oxidation, resulting in a smoother connection between the side of the gate structure and the third surface. This avoids charge concentration, significantly reduces the risk of gate-source leakage, improves device reliability, and helps reduce the source-drain on-resistance and enhance device performance. Furthermore, it facilitates reducing the width of the gate insulating layer, which is beneficial for increasing the dimensions and overlay accuracy in subsequent interconnect etching processes, reducing the difficulty of subsequent processes, and ultimately enabling the miniaturization of semiconductor devices.

[0019] The power module, power conversion circuit, and vehicle described above have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0021] Figure 1 This is a schematic diagram of a sharp corner at the gate structure in a related technology;

[0022] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0023] Figure 3 This is a flowchart of a method for fabricating a semiconductor device provided in an embodiment of this application;

[0024] Figures 4-12 The following are diagrams illustrating the steps involved in fabricating a semiconductor device, as provided in the embodiments of this application.

[0025] Figure 13 A structural diagram of the power module provided in the embodiments of this application;

[0026] Figure 14 This is a structural diagram of the power conversion circuit provided in an embodiment of this application;

[0027] Figure 15 This is a structural diagram of the vehicle provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0030] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0031] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0032] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0033] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0034] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0035] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0036] As mentioned in the background section, in silicon carbide dual-trench devices, due to the polysilicon etching process, some sharp corners will form on the surface of the 12' gate structure within the gate trench, such as... Figure 1 As shown in the dashed box. Figure 1 This is a schematic diagram of a sharp corner in the gate structure of a related technology. In semiconductor devices, sharp corners of the gate structure can lead to electric field concentration, which can easily cause gate-source leakage and affect device reliability.

[0037] Based on this, this application provides a semiconductor device, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0038] The semiconductor device 10 includes a semiconductor body 11, a gate structure 12, a source 14, a drain 15, a first barrier layer 16, and a second barrier layer 17. The semiconductor body 11 is configured with a first conductivity type and includes a first surface P1 and a second surface P2 disposed opposite to each other. A gate trench T1 is formed on the first surface P1, extending from the first surface P1 into the semiconductor body 11. The gate structure 12 is located within the gate trench T1. The first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1. The second barrier layer 17 at least covers a third surface P3 of the gate structure 12 on the side away from the second surface P2. The source 14 is located on the first surface P1, and the drain 15 is located on the second surface P2.

[0039] In some embodiments, both the first barrier layer 16 and the second barrier layer 17 are at least partially located within the gate trench T1.

[0040] For example, such as Figure 2As shown, in some embodiments, the semiconductor body 11 further includes a well region 101 configured with a second conductivity type, a first region 102 configured with a first conductivity type, and a second region 103 configured with a second conductivity type. The first conductivity type can be N-type, and correspondingly, the second conductivity type is P-type. That is, the semiconductor device is an N-type semiconductor device. Accordingly, the well region 101 can also be called a "P-well," and the first region 102 can also be called an "N-type well." + "Contact Area", the second area 103 can also be called "P" + The semiconductor device 10 also includes an ohmic contact layer 18 located between the first surface P1 and the source electrode 14 to form a good electrical contact. The ohmic contact metal of the ohmic contact layer 18 may include at least one of nickel (Ni), titanium (Ti), or a nickel-titanium alloy (NiTi alloy metal). Alternatively, in other embodiments, the first conductivity type may be P-type, the second conductivity type may be N-type, and correspondingly, the semiconductor device is a P-type semiconductor device.

[0041] Taking an N-type semiconductor device as an example, by transmitting a turn-on voltage to the gate structure 12, when the semiconductor device 10 is forward-biased and the operating current is small, the operating current flows from the drain 15 through the semiconductor body 11, the well region 101, the first region 102, the ohmic contact layer 18, and finally to the source 14. Since the second region 103 has a higher concentration of P-type ions than the well region 101, the second region 103 can form more PN junctions with the semiconductor body 11. When the operating current is large, the operating current flows from the drain 15 through the semiconductor body 11, the second region 103, the ohmic contact layer 18, and finally to the source 14, preventing a large operating current from flowing through the well region 101 and protecting the channel in the well region 101.

[0042] In this embodiment of the application, the first barrier layer 16 and the second barrier layer 17 are located in the gate trench T1. The first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1. Here, the first barrier layer 16 is an insulating dielectric layer, which can be used to provide good electrical insulation performance, prevent current leakage, and protect the gate structure 12.

[0043] The third surface P3 of the gate structure 12 is covered by a second barrier layer 17, which can be used to modify the gate structure 12. For example, the second barrier layer 17 is formed by thermal oxidation of the third surface P3 of the gate structure 12.

[0044] The material of gate structure 12 includes polysilicon, combined with Figure 1As can be understood from the fabrication steps diagram below, in related technologies, in order to form a patterned gate structure, the deposited polysilicon material needs to be etched. Due to the influence of the device structure, after etching, there will be sharp corners on the surface edge of the gate structure. In semiconductor devices, these sharp corners will cause electric field concentration and gate-source leakage, affecting device reliability. Furthermore, it will also cause the gate insulating layer of the semiconductor device to need to be wider to protect the gate structure, which is not conducive to the size reduction of semiconductor devices.

[0045] In this embodiment, by thermally oxidizing the third surface P3 of the gate structure 12 to form a second barrier layer 17, the third surface P3 of the gate structure 12 can be modified. The second barrier layer 17 forms a relatively flat surface, and the sharp corners in the related technology are oxidized and smoothed. The connection between the side of the gate structure 12 and the third surface P3 is relatively smooth, which can avoid charge concentration, greatly reduce the risk of gate-source leakage, improve device reliability, and help reduce the source-drain on-resistance of the device and improve device performance.

[0046] Furthermore, since the sharp corners are smoothed by oxidation, the risk of gate-source leakage is reduced, which is beneficial to reducing the width of the gate insulating layer 104. This is beneficial to expanding the relevant dimensions and overlay accuracy in the subsequent interconnect etching process, reducing the difficulty of subsequent processes, and facilitating the miniaturization of semiconductor devices.

[0047] In some embodiments, such as Figure 2 As shown, the gate structure 12 also includes a side surface near the inner wall of the gate trench T1, and the third surface P3 is connected to the side surface. The minimum included angle between the third surface P3 and the side surface ranges from 80° to 100°.

[0048] Combination Figure 1 ,like Figure 1 As shown in the dashed box, in related technologies, the gate structure has a sharp angle α (that is, the minimum angle between the third surface and the side surface). In some embodiments, the angle of the sharp angle α ranges from 30° to 45°.

[0049] In this embodiment, the third surface P3 of the gate structure 12 is thermally oxidized to form the second barrier layer 17, and the sharp corners are smoothed by oxidation. Figure 2As shown in the dashed box, after processing, the minimum included angle b between the third surface P3 and the side surface ranges from 80° to 100°, for example, 80°, 85°, 90°, or 100°. The included angle between the cross-section at different positions on the third surface P3 and the inner wall of the gate trench may vary. When this included angle is the minimum included angle b, it indicates that the connection between this point and the side surface is the sharpest. In this embodiment, the minimum included angle b ranges from 80° to 100°, indicating a smoother connection between the third surface P3 and the side surface. This avoids charge concentration, significantly reduces the risk of gate-source leakage, improves device reliability, and helps reduce the source-drain on-resistance and improve device performance.

[0050] In some embodiments, in the direction from the second surface P2 to the first surface P1, the projection of the first barrier layer 16 onto the first surface P1 falls into the projection of the second barrier layer 17 onto the first surface P1.

[0051] In this embodiment, the first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1. The second barrier layer 17 at least covers the third surface P3 of the gate structure 12 on the side away from the second surface P2. The second barrier layer 17 is also located on the side of the first barrier layer 16 away from the second surface P2. The projection of the first barrier layer 16 onto the first surface P1 falls into the projection of the second barrier layer 17 onto the first surface P1, which is equivalent to the orthographic projection of the second barrier layer 17 onto the second surface P2, thus covering the orthographic projection of the first barrier layer 16 onto the second surface P2. The first barrier layer 16 and the second barrier layer 17 work together to completely enclose the gate structure 12 within the gate trench T1, enhancing the protection of the gate structure 12, reducing the risk of gate-source leakage, reducing the source-drain on-resistance of the device, and improving device performance.

[0052] In some embodiments, such as Figure 2 As shown, a source trench T2 is also provided on the first surface P1, extending from the first surface P1 into the semiconductor body 11. The semiconductor device also includes a source trench structure 13 located within the source trench T2. A first barrier layer 16 is located between the source trench structure 13 and the inner wall of the source trench T2, and a second barrier layer 17 covers the side of the first barrier layer 16 away from the second surface P2.

[0053] In some embodiments, both the first barrier layer 16 and the second barrier layer 17 are at least partially located within the source trench T2.

[0054] It is understood that in other embodiments, the semiconductor device may not have source trench T2 and source trench structure 13. For example, during the fabrication process, source trench T2 is not formed simultaneously during the formation of gate trench T1, and only the second region 103 is formed at the corresponding position. This will not be elaborated here.

[0055] Alternatively, in other embodiments, a source trench T2 is formed on the first surface P1; however, the source trench T2 does not contain a source trench structure 13. For example, during fabrication, after forming the gate trench T1 and the gate structure 12, the source trench T2 is formed, and then a second region 103 is formed at the corresponding location. The source trench T2 is no longer filled with polysilicon; instead, subsequent processes are performed directly. In this case, the final semiconductor device may contain source material 14 within the source trench T2, or it may also contain a cavity. Further details are omitted here.

[0056] like Figure 2 As shown, taking polysilicon as an example where both the gate structure 12 and the source trench structure 13 are made of, typically, the source trench T2 and the gate trench T1 are formed in the same process, as are the gate structure 12 and the source trench structure 13. The first barrier layer 16 in the source trench T2 and the first barrier layer 16 in the gate trench T1, and the second barrier layer 17 in the source trench T2 and the second barrier layer 17 in the gate trench T1 are also formed in the same process. Therefore, the morphology and relative positional relationship of the gate structure 12, the first barrier layer 16, and the second barrier layer 17 in the source trench T2 are similar to those of the source trench structure 13, the first barrier layer 16, and the second barrier layer 17 in the gate trench T1.

[0057] Furthermore, the semiconductor body 11 is made of silicon carbide, the first region 102 is formed by ion doping of silicon carbide, and the source trench structure 13 is made of polysilicon. The process required to form metal silicide on the surface of silicon carbide is quite different from the process required to form metal silicide on the surface of polysilicon. Exposing part of the source trench structure 13 on the first surface of the semiconductor body 11 will increase the difficulty of forming ohmic contacts.

[0058] For example, in related technologies, after an ohmic contact layer 18 is formed on the first surface P1 of the semiconductor body 11, a high-temperature annealing process is required to make the ohmic contact layer 18 form an ohmic contact with the first region 102. Since the temperature required to form metal silicide on the silicon carbide surface is high, at this temperature, the polysilicon of the source trench structure 13 reacts too violently with the ohmic contact metal, which easily forms erosion defects and thus affects the stability of the device.

[0059] Based on this, in this embodiment of the application, during the process of thermally oxidizing the third surface P3 of the gate structure 12 to form the second barrier layer 17, the second barrier layer 17 is simultaneously formed on the side of the source trench structure 13 away from the second surface P2. The second barrier layer 17 and the first barrier layer 16 work together to wrap the source trench structure 13. This not only modifies the surface of the source trench structure 13 and makes it flat, facilitating the subsequent formation of the ohmic contact layer 18, but also prevents the polysilicon material of the source trench structure 13 from directly contacting the subsequently formed ohmic contact layer 18. This avoids the reaction between the ohmic contact metal and the polysilicon to form erosion defects during the subsequent ohmic contact formation process. In other words, the second barrier layer 17 covers the side of the source trench structure 13 away from the second surface P2, which is beneficial to improving device reliability.

[0060] In some embodiments, the first barrier layer 16 and the second barrier layer 17 are made of the same material, both comprising silicon oxide.

[0061] Based on the silicon carbide material of the semiconductor body 11, the polycrystalline silicon material of the source trench structure 13 and the gate structure 12, the first barrier layer 16 and the second barrier layer 17 can both be formed by oxidation process. Silicon oxide has high stability of insulation properties, which can be used to reduce leakage current, which is beneficial to reducing the risk of gate-source leakage and improving the stability of semiconductor devices.

[0062] Secondly, this application also provides a method for fabricating a semiconductor device, such as... Figure 3 As shown, Figure 3 This is a flowchart of a method for fabricating a semiconductor device provided in an embodiment of this application. Figures 4-12 The diagram shows the steps involved in fabricating a semiconductor device as provided in the embodiments of this application.

[0063] like Figure 3 As shown, the preparation method includes the following steps S01 to S04:

[0064] Step S01: As Figures 4-5 As shown, a gate trench T1 is formed on a semiconductor body 11, wherein the semiconductor body 11 is configured as a first conductivity type, the semiconductor body 11 includes a first surface P1 and a second surface P2 disposed opposite to each other, and the gate trench T1 extends from the first surface P1 into the semiconductor body 11.

[0065] The first conductivity type can be N-type, for example, such as Figure 4 As shown, the semiconductor body 11 has an N-type conductivity. On the first surface P1 of the semiconductor body 11, a mask is formed by photolithography, an ion implantation region is defined, and P is then implanted. + Ion implantation is performed to form well region 101. After removing the mask, a new mask is formed using photolithography to define the ion implantation region and perform N-type electron microscopy.+ Ion implantation forms a first region 102. The ion implantation depth is controlled by controlling the implantation energy, so that the first region 102 is located on the first surface P1, and the well region 101 is located on the side of the first region 102 away from the first surface P1.

[0066] After that, as Figure 5 As shown, the gate trench T1 is formed by an etching process.

[0067] In some embodiments, a source trench T2 is further provided on the first surface P1, extending from the first surface P1 into the semiconductor body 11. During the formation of the gate trench T1, the source trench T2 is also formed simultaneously. After the gate trench T1 and the gate structure 12 are formed, a second region 103 is formed on the surface of the source trench T2. The second region 103 may also be referred to as "P". + The contact area is then formed. Following this, a carbon film is deposited on the device surface and activated by high-temperature annealing. The carbon film is then removed after annealing. This process helps activate the doped ions and repair lattice defects caused by processes such as ion implantation, thus improving the device's yield and reliability.

[0068] Step S02: As Figures 6-11 As shown, a gate structure 12 is formed in a gate trench T1, and a first barrier layer 16 and a second barrier layer 17 are formed. The first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1, and the second barrier layer 17 at least covers the third surface P3 of the gate structure 12 on the side away from the second surface P2.

[0069] In some embodiments, the semiconductor device further includes a source trench structure 13 located within a source trench T2. The source trench structure 13 is also formed simultaneously during the formation of the gate structure 12.

[0070] like Figure 6 As shown, insulating dielectric layers are grown on the sidewalls and bottom of the trench via thermal oxidation using a high-temperature gate oxide process. Specifically, a first barrier layer 16 is formed on the inner wall of the gate trench T1 and on the inner wall of the source trench T2. The first barrier layer 16 provides good electrical insulation to prevent current leakage. Furthermore, the first barrier layer 16 formed on the inner wall of the gate trench T1 also protects the gate structure 12.

[0071] Then, as Figures 7-8 As shown, polysilicon is deposited and polysilicon etching is performed. Finally, a gate structure 12 is formed in the gate trench T1, and a source trench structure 13 is formed in the source trench T2.

[0072] like Figure 8As shown in the dashed box, due to the influence of the device structure, after etching, there will be sharp corners on the surface edge of the gate structure 12.

[0073] To avoid leakage current from the grid source caused by this sharp corner, such as Figure 9 As shown, a second barrier layer 17 can be formed first.

[0074] In some embodiments, forming the second barrier layer 17 includes thermally oxidizing the third surface P3 of the gate structure 12 to form the second barrier layer 17. In some embodiments, the portion of the source trench structure 13 away from the second surface P2 and the portion of the first surface P1 of the semiconductor body 11 exposed are both thermally oxidized simultaneously, that is, the formed second barrier layer 17 also covers the portion of the source trench structure 13 away from the second surface P2 and the first surface P1 of the semiconductor body 11.

[0075] Thermal oxidation can modify the polysilicon surface, making the third surface P3 of the gate structure 12 smoother, thus allowing it to... Figure 8 The sharp corners shown are removed. Similarly, this also makes the surface of the source trench structure 13 away from the second surface P2 smoother.

[0076] Thermal oxidation treatment includes, but is not limited to, high-temperature dry oxygen oxidation, high-temperature wet oxygen oxidation, and rapid thermal oxidation. For example, gases such as oxygen, hydrogen chloride, and nitrogen can be introduced, and thermal oxidation can be carried out at a temperature of 800°C to 1200°C to form a second barrier layer 17 with a thickness ranging from 100 angstroms to 1000 angstroms.

[0077] After that, as Figure 10 As shown, a gate insulating layer 104 is formed, which covers the gate structure 12 and serves to isolate and protect the gate structure 12. In some embodiments, the gate insulating layer 104 is made of the same material as the first barrier layer 16 and the second barrier layer 17, both comprising silicon oxide. In some embodiments, as... Figure 10 As shown, during the patterning process of the gate insulating layer 104, the second barrier layer 17 can be patterned simultaneously to remove unwanted parts of the second barrier layer 17 without the need for additional etching processes.

[0078] Then, as Figure 11 As shown, an ohmic contact layer 18 is formed on the first surface P1. Due to the presence of the second barrier layer 17, the source trench structure 13 will not form erosion defects due to reaction with the ohmic contact metal during the formation of the ohmic contact.

[0079] Step S03: As Figure 12 As shown, a source electrode 14 is formed on the first surface P1. For example, the source electrode 14 is formed by depositing aluminum thickened metal by sputtering or evaporation.

[0080] Step S04: As Figure 12 As shown, a drain electrode 15 is formed on the second surface P2.

[0081] At this point, the semiconductor device 10 is complete.

[0082] In the above fabrication method, after forming the patterned gate structure 12 and source trench structure 13 and before forming the ohmic contact layer 18, a thermal oxidation process is added to thermally oxidize the third surface P3 of the gate structure 12 to form a second barrier layer 17. This modifies the third surface P3 of the gate structure 12, removes sharp corners caused by polysilicon etching, avoids charge concentration, greatly reduces the risk of gate-source leakage, improves device reliability, and helps reduce the source-drain on-resistance and improve device performance. Furthermore, for the source trench structure 13, by adding the thermal oxidation process, a second barrier layer 17 can be formed to protect and cover the source trench structure 13, preventing the polysilicon of the source trench structure 13 from reacting violently with the ohmic contact metal in the subsequent ohmic contact process, thus avoiding erosion defects.

[0083] The added thermal oxidation process is mature, simple, and easy to operate, and requires no additional etching process. The patterning of the second barrier layer 17 can be performed simultaneously during the subsequent patterning of the gate insulating layer 104. Based on this, the device reliability can be greatly improved at a lower cost by adding an extra process.

[0084] On the other hand, embodiments of this application also provide a power module. Figure 13 This is a structural diagram of a power module provided in an embodiment of this application.

[0085] like Figure 13 As shown, the power module 200 includes a substrate 201 and a semiconductor device 10 in any of the above embodiments, with the substrate 201 used to support the semiconductor device 10.

[0086] For example, power module 200 can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of the electronic device. A power regulator adjusts the power output to meet the needs of a specific application.

[0087] On the other hand, embodiments of this application also provide a power conversion circuit. Figure 14 This is a structural diagram of the power conversion circuit provided in an embodiment of this application.

[0088] like Figure 14 As shown, the power conversion circuit 300 includes a circuit board 301 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0089] For example, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current to direct current, the AC / AC converter is used to convert alternating current to alternating current, the DC / DC converter is used to convert direct current to direct current, the DC / AC inverter is used to convert direct current to alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0090] On the other hand, embodiments of this application also provide a vehicle. Figure 15 This is a structural diagram of the vehicle provided in an embodiment of this application.

[0091] like Figure 15 As shown, the vehicle 400 includes a load 401 and a power conversion circuit 300 in the above embodiment. The power conversion circuit 300 is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load 401 to supply power to the load 401.

[0092] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, the semiconductor body being configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other, the first surface being provided with a gate trench, the gate trench extending from the first surface into the semiconductor body; A gate structure is located within the gate trench; the gate structure includes a side surface near the inner wall of the gate trench, a third surface away from the second surface, and a fourth surface connecting the side surface and the third surface, wherein the minimum included angle between the third surface and the fourth surface is 80°~100°. A first barrier layer and a second barrier layer, wherein the first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer is formed by thermal oxidation of the gate structure, and the second barrier layer covers the third surface and the fourth surface; In the direction from the second surface to the first surface, the projection of the first barrier layer onto the first surface falls into the projection of the second barrier layer onto the first surface; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The first surface is further provided with a source trench, which extends from the first surface into the semiconductor body; The semiconductor device further includes a source trench structure, wherein the source trench structure is located within the source trench; The first barrier layer is also located between the source trench structure and the inner wall of the source trench, and the second barrier layer also covers the side of the first barrier layer away from the second surface.

3. The semiconductor device according to claim 1, characterized in that, The first barrier layer and the second barrier layer are made of the same material, both including silicon oxide.

4. A method for fabricating a semiconductor device, characterized in that, include: A gate trench is formed on a semiconductor body, wherein the semiconductor body is configured with a first conductivity type, the semiconductor body includes a first surface and a second surface disposed opposite to each other, and the gate trench extends from the first surface into the semiconductor body; A gate structure is formed within the gate trench, and a first barrier layer and a second barrier layer are formed therein. The first barrier layer is located between the gate structure and the inner wall of the gate trench. The gate structure includes a side surface near the inner wall of the gate trench, a third surface away from the second surface, and a fourth surface connecting the side surface and the third surface. The minimum included angle between the third surface and the fourth surface is 80° to 100°. The second barrier layer is formed by thermal oxidation of the gate structure and covers the third surface and the fourth surface. In the direction from the second surface to the first surface, the projection of the first barrier layer onto the first surface falls into the projection of the second barrier layer onto the first surface. A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

5. A power module, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 3; A substrate for supporting the semiconductor device.

6. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 3, wherein the semiconductor device is electrically connected to the circuit board.

7. A vehicle, characterized in that, include: The load and the power conversion circuit as described in claim 6, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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