Detection substrate, preparation method and detection device

Abstract

The invention relates to the technical field of display, and discloses a detection substrate, a preparation method and a detection device. The grid electrode of the thin film transistor is positioned on one side of the substrate; the first electrode is located on the side, facing the grid electrode, of the substrate and comprises a first part and a second part, and the second part is located outside the first part; the photoelectric conversion layer is located on the side, away from the substrate, of the first electrode, and the orthographic projection of the photoelectric conversion layer on the substrate is located in the orthographic projection of the first part on the substrate; the second electrode is located on the side, away from the substrate, of the photoelectric conversion layer; the first insulating layer is located on the side, away from the substrate, of the grid electrode and the second electrode, the orthographic projection of the grid electrode and the first electrode on the substrate is located in the orthographic projection of the first insulating layer on the substrate, the first insulating layer is provided with a first via hole, and the orthographic projection of the first via hole on the substrate is at least partially overlapped with the orthographic projection of the second part on the substrate. According to the embodiment of the invention, the yield of the flat panel detector can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a detection substrate, a preparation method and a detection device. Background Art

[0002] Flat Panel X-Ray Detector (FPXD) is used to convert X-rays into visible images, which plays a decisive role in the image quality. The detection area of ​​the flat panel detector mainly includes a sensing unit and a control unit. The control unit mainly includes a transistor (Thin Film Transistor, TFT), such as a thin film transistor, and the sensing unit mainly includes a photodiode (PIN). The photodiode generates charge accumulation under X-ray irradiation, and the transistor is controlled to open in sequence to read the charge on the sensing unit, and finally the display image is obtained after processing.

[0003] However, existing flat panel detectors have a low yield. Summary of the invention

[0004] The present application proposes a detection substrate, a preparation method and a detection device, which can improve the yield of the detection substrate.

[0005] In a first aspect, the present application provides a detection substrate, comprising:

[0006] Comprising a detection area, the detection substrate comprises:

[0007] substrate;

[0008] A gate of a thin film transistor is located on one side of the substrate, and the gate is located in the detection area;

[0009] A first electrode, located on a side of the substrate facing the gate and located in the detection area, the first electrode comprising a first portion and a second portion, the second portion being located outside the first portion;

[0010] a photoelectric conversion layer, located on a side of the first electrode facing away from the substrate, wherein an orthographic projection of the photoelectric conversion layer on the substrate is located within an orthographic projection of the first portion on the substrate;

[0011] A second electrode is located on a side of the photoelectric conversion layer away from the substrate;

[0012] a first insulating layer, located on a side of the gate and the second electrode facing away from the substrate, the orthographic projections of the gate and the first electrode on the substrate being located within the orthographic projection of the first insulating layer on the substrate, the first insulating layer being provided with a first via hole, the orthographic projection of the first via hole on the substrate at least partially overlapping with the orthographic projection of the second portion on the substrate;

[0013] The active layer of the thin film transistor is located on a side of the first insulating layer away from the substrate;

[0014] The second metal layer is located on a side of the active layer away from the substrate, and the second metal layer includes a first electrode and a second electrode of the thin film transistor, and the first electrode is connected to the first part through the first via hole.

[0015] In some embodiments, the detection substrate includes a first metal layer, and the first metal layer includes the gate and the first electrode.

[0016] In some embodiments, an orthographic projection of the first via on the substrate is located within an orthographic projection of the second portion on the substrate.

[0017] In some embodiments, the detection substrate also includes an insulating structure layer and a third metal layer, the insulating structure layer is located on the side of the second metal layer away from the substrate, the insulating structure layer is provided with a second via, and the orthographic projection of the second via on the substrate is located within the orthographic projection of the second electrode on the substrate; the third metal layer is located on the side of the insulating structure layer away from the substrate, the third metal layer includes a bias signal line, and the bias signal line is connected to the second electrode through the second via.

[0018] In some embodiments, the insulating structure layer includes a first passivation layer, a first resin layer, and a second passivation layer stacked in sequence, the first resin layer is provided with a third via, and the orthographic projection of the second via on the substrate is located within the orthographic projection of the third via on the substrate.

[0019] In some embodiments, the third metal layer further includes a shielding portion located in the detection area, and an orthographic projection of the active layer on the substrate is located within an orthographic projection of the shielding portion on the substrate.

[0020] In some embodiments, the thickness of the first insulating layer is less than or equal to the thickness of the first passivation layer.

[0021] In some embodiments, the detection substrate further includes a binding area, the detection substrate further includes a third passivation layer and a conductive layer sequentially arranged on a side of the third metal layer away from the substrate, and the first passivation layer, the second passivation layer and the third passivation layer are also located in the binding area; the detection substrate satisfies at least one of the following:

[0022] The conductive layer includes a first binding pin located in the binding area, the third metal layer includes a first transfer portion located in the binding area, the detection substrate also includes a first signal line located in the binding area, the third passivation layer is provided with a fourth via hole, the first passivation layer and the second passivation layer are provided with a fifth via hole, the first binding pin is connected to the first transfer portion through the fourth via hole, the first transfer portion is connected to the first signal line through the fifth via hole, and the first signal line is connected to the gate;

[0023] The conductive layer includes a second binding pin located in the binding area, the third metal layer includes a second transfer portion located in the binding area, the detection substrate also includes a second signal line located in the binding area, the third passivation layer is provided with a sixth via, the first passivation layer and the second passivation layer are provided with a seventh via, the second binding pin is connected to the second transfer portion through the sixth via, the second transfer portion is connected to the second signal line through the seventh via, and the second signal line is connected to the second pole.

[0024] In some embodiments, the detection substrate further includes a second resin layer, and the second resin layer is located on a side of the third passivation layer and the conductive layer facing away from the substrate.

[0025] In some embodiments, the detection substrate includes a plurality of gate lines extending along a first direction and a plurality of read lines extending along a second direction, the plurality of gate lines and the plurality of read lines intersect with each other to define a plurality of detection areas, the gate is connected to the gate line, the second electrode of the thin film transistor is connected to the read line, and the second direction intersects with the first direction.

[0026] In some embodiments, the bias signal line and the read line extend in the same direction.

[0027] In a second aspect, the present application also provides a method for preparing a detection substrate, comprising:

[0028] forming a gate electrode and a first electrode of a thin film transistor on one side of the substrate, wherein the first electrode comprises a first portion and a second portion, and the second portion is located outside the first portion;

[0029] forming a photoelectric conversion layer on a side of the second electrode facing away from the substrate, wherein an orthographic projection of the photoelectric conversion layer on the substrate is located within an orthographic projection of the first portion on the substrate;

[0030] forming a second electrode on a side of the photoelectric conversion layer facing away from the substrate;

[0031] A first insulating layer is formed on a side of the gate and the second electrode facing away from the substrate, the orthographic projections of the gate and the first electrode on the substrate are located within the orthographic projection of the first insulating layer on the substrate, the first insulating layer is provided with a first via hole, and the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the second portion on the substrate;

[0032] An active layer of the thin film transistor and a second metal layer are sequentially formed on a side of the first insulating layer away from the substrate. The second metal layer includes a first electrode and a second electrode of the thin film transistor. The first electrode is connected to the first portion through the first via hole.

[0033] In some embodiments, it also includes:

[0034] forming a first passivation layer on a side of the second metal layer facing away from the substrate;

[0035] forming a first resin layer on a side of the first passivation layer facing away from the substrate, wherein the first resin layer is provided with a third via hole, and an orthographic projection of the third via hole on the substrate is located within an orthographic projection of the second electrode on the substrate;

[0036] forming a second passivation layer on a side of the first resin layer facing away from the substrate, wherein the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the third via hole on the substrate, and the second passivation layer is provided with a second via hole, and the second via hole penetrates the second passivation layer and the first passivation layer;

[0037] A third metal layer is formed on a side of the second passivation layer facing away from the substrate. The third metal layer includes a bias signal line. The bias signal line is connected to the second electrode through the second via hole.

[0038] In some embodiments, the method further includes: forming a third passivation layer on a side of the second passivation layer and the third metal layer facing away from the substrate; and forming a conductive layer and a second resin layer on a side of the third passivation layer facing away from the substrate.

[0039] In a third aspect, the present application further provides a detection device, comprising a detection substrate as described in any one of the first aspects.

[0040] The advantages of the present application are: in the related art, the first and second electrodes of the thin film transistor are formed before the photoelectric conversion layer, which makes the photoelectric conversion layer easily affected by the steps formed by the first or second electrodes, so that the photoelectric conversion layer cannot be formed on a flat surface. In comparison, in the present disclosure, the photoelectric conversion layer is located on the side of the first electrode away from the substrate, the first insulating layer is located on the side of the gate and the second electrode away from the substrate, and the first and second electrodes of the thin film transistor are located on the side of the first insulating layer away from the substrate, that is, the first and second electrodes of the thin film transistor are formed after the photoelectric conversion layer, so that the first and second electrodes of the thin film transistor will not affect the flatness of the lower surface of the photoelectric conversion layer, so that the photoelectric conversion layer can be formed on the flat surface of the first electrode, improve the leakage abnormality caused by the uneven bottom of the photoelectric conversion layer, and improve the product yield; in addition, before forming the active layer, the first electrode and the second electrode of the thin film transistor, the first insulating layer has covered the photoelectric conversion layer, which plays a protective role on the photoelectric conversion layer, improves the scratch resistance of the photoelectric conversion layer in the subsequent process, and then improves the stability of the photoelectric conversion layer, and further improves the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0042] Figure 1 is a schematic diagram of a film layer structure of a flat panel detector in the related art;

[0043] Figure 2 is a schematic diagram of a film structure of a detection substrate provided by the present application;

[0044] Figure 3 It is a schematic diagram of a gate line and a read line of a detection substrate provided by the present application; Figure 4 is a schematic diagram of a pixel plane of a detection substrate provided by the present application;

[0045] Figure 5A It is a schematic diagram of a film structure of a gate drive signal with only one via overlapped on a detection substrate provided by the present application;

[0046] Figure 5B It is a schematic diagram of a film structure of a data reading signal with only one via overlapped on a detection substrate provided by the present application;

[0047] Fig. 6A is a schematic diagram of a film layer structure of a gate drive signal of a flat panel detector in the related art;

[0048] Figure 6B It is a schematic diagram of the film structure of the data reading signal of the existing flat panel detector;

[0049] Figure 7 It is a schematic diagram of the steps of a method for preparing a detection substrate provided by the present application;

[0050] Figure 8 It is a schematic diagram of forming a first electrode in a method for preparing a detection substrate provided by the present application;

[0051] Fig. 9 It is a schematic diagram of forming a photoelectric conversion layer and a second electrode in a method for preparing a detection substrate provided by the present application;

[0052] Fig.10 It is a schematic diagram of forming a first via hole in a method for preparing a detection substrate provided by the present application;

[0053] Fig.11 It is a schematic diagram of forming a third via hole in a method for preparing a detection substrate provided by the present application;

[0054] Fig.12 is a schematic diagram of a pixel plane of a flat panel detector in the related art. DETAILED DESCRIPTION

[0055] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should be the common meanings understood by those skilled in the art to which this application belongs.

[0056] It can be understood that the thin film transistor includes a gate, an active layer, a first electrode and a second electrode, wherein one of the first electrode and the second electrode is a source electrode and the other is a drain electrode.

[0057] like Figure 1As shown, it is a flat panel detector of the related art, which includes: a substrate 20, a gate insulating layer 21, a second gate 22, a second active layer 23, a first electrode 241 and a second electrode 242 of a thin film transistor, a second bottom electrode 25, a fourth insulating layer 26, a second photoelectric conversion layer 27, a buffer layer 28, a second top electrode 35, a fourth resin layer 29, a fifth insulating layer 30, a fourth metal layer 31, a sixth insulating layer 32, a second conductive layer 33, and a fifth resin layer 34. Among them, the material of the second conductive layer 33 includes a transparent conductive material, and the fourth metal layer 31 includes a bias signal line. In the manufacturing process of the existing flat panel detector products, the TFT device TFT2 (transistor) is first manufactured, and then the second photoelectric conversion layer 27 of the PIN device PIN2 (photodiode) is manufactured. The second electrode 242 of the TFT device and the second bottom electrode 25 of the PIN device are connected through a via to complete the signal transmission. However, in this process, since there is a step difference in the vertical direction between the region A of the second bottom electrode 25 at the via hole position of the fourth insulating layer 26 (the portion above the gate insulating layer 21, the second electrode 242 and the fourth insulating layer 26) and the region B of the second bottom electrode 25 below the second photoelectric conversion layer 27 (the portion above the gate insulating layer 21 and the fourth insulating layer 26), in the actual product manufacturing process, the second photoelectric conversion layer 27 is likely to overlap with the mesa C formed at the via hole in the region overlapping with the TFT device. However, in the actual product manufacturing process, the requirement for manufacturing the second photoelectric conversion layer 27 in the region overlapping with the TFT device is that the second photoelectric conversion layer 27 cannot overlap with the mesa C formed at the via hole, otherwise the leakage current of the side wall caused by the uneven bottom of the second photoelectric conversion layer 27 will be abnormal, causing the flat panel detector to present pixel grayscale abnormalities in the final image detection, such as gray dark spots, bad pixels (Leakage Pixel), etc., thereby affecting the yield of the produced flat panel detector products.

[0058] In order to solve some problems in the related art, an embodiment of the present disclosure provides a detection substrate, and the technical solution of the present disclosure will be described in detail through specific embodiments below.

[0059] Embodiment 1

[0060] like Figure 2As shown, it is a schematic diagram of a detection substrate provided by an embodiment of the present application, the detection substrate includes a detection area, and the detection substrate includes: a substrate 10; a gate electrode 212 of a thin film transistor TFT1, located on one side of the substrate 10, and the gate electrode 212 is located in the detection area; a first electrode 211, located on the side of the substrate 10 facing the gate electrode 212 and located in the detection area, the first electrode 211 includes a first part 211A and a second part 211B, and the second part 211B is located outside the first part 211A; a photoelectric conversion layer 500, located on the side of the first electrode 211 away from the substrate 10, and the orthographic projection of the photoelectric conversion layer 500 on the substrate 10 is located within the orthographic projection of the first part 211A on the substrate 10. Since the first electrode 211 is located on the upper surface of the substrate 10, the photoelectric conversion layer 500 is located on the upper surface of the first electrode 211, so that the first electrode 211 is formed on a flat surface, and the photoelectric conversion layer 500 is formed on the flat upper surface of the first electrode 211, which ensures that the photoelectric conversion layer 500 is formed on a flat surface.

[0061] The detection substrate further includes: a second electrode 810, located on the side of the photoelectric conversion layer 500 facing away from the substrate 10; a first insulating layer 310, located on the side of the gate 212 and the second electrode facing away from the substrate 10, and the orthographic projections of the gate 212 and the first electrode 211 on the substrate 10 are located within the orthographic projection of the first insulating layer 310 on the substrate 10. In this way, the first insulating layer 310 covers the photoelectric conversion layer 500, which can protect the photoelectric conversion layer 500. The first insulating layer 310 is provided with a first via hole, and the orthographic projection of the first via hole on the substrate 10 at least partially overlaps with the orthographic projection of the second portion 211B on the substrate 10.

[0062] The detection substrate also includes: an active layer 400 of a thin film transistor TFT1, located on the side of the first insulating layer 310 away from the substrate 10; a second metal layer 220, located on the side of the active layer 400 away from the substrate 10, the second metal layer 220 includes a first electrode 221 and a second electrode 222 of the thin film transistor TFT1, and the first electrode 221 is connected to the first part 211A through a first via hole.

[0063] In related technologies, such as Figure 1 As shown, the first electrode and the second electrode of the thin film transistor are formed before the photoelectric conversion layer, which makes the photoelectric conversion layer easily affected by the mesa C formed by the first electrode or the second electrode, and it is impossible to ensure that the photoelectric conversion layer is formed on a flat surface.

[0064] In the technical solution disclosed in the present invention, the photoelectric conversion layer is located on the side of the first electrode away from the substrate, the first insulating layer is located on the side of the gate and the second electrode away from the substrate, and the first pole and the second pole of the thin film transistor are located on the side of the first insulating layer away from the substrate, that is, the first pole and the second pole of the thin film transistor are formed after the photoelectric conversion layer, so that the first pole and the second pole of the thin film transistor will not affect the flatness of the lower surface of the photoelectric conversion layer, so that the photoelectric conversion layer can be formed on the flat surface of the first electrode, improving the leakage abnormality caused by the uneven bottom of the photoelectric conversion layer and improving the product yield. In addition, before forming the active layer, the first electrode and the second electrode of the thin film transistor, the first insulating layer has covered the photoelectric conversion layer, which protects the photoelectric conversion layer, improves the scratch resistance of the photoelectric conversion layer in the subsequent process, and then improves the stability of the photoelectric conversion layer, further improving the product yield.

[0065] like Figure 2 As shown, the detection substrate includes a first metal layer 210, and the first metal layer 210 includes a gate 212 and a first electrode 211. Therefore, the gate 212 and the first electrode 211 are arranged in the same layer, so that the first electrode 221 and the second electrode 222 of the thin film transistor can be formed after the photoelectric conversion layer 500 is formed, thereby avoiding affecting the flatness of the lower surface of the photoelectric conversion layer 500 during the process of forming the first electrode 221 and the second electrode 222 of the thin film transistor, and further enabling the photoelectric conversion layer 500 to be formed on the flat surface of the first electrode, thereby improving the leakage abnormality caused by the uneven bottom of the photoelectric conversion layer 500 and improving the product yield.

[0066] like Figure 2 As shown, the orthographic projection of the first via hole 91 on the substrate 10 is located within the orthographic projection of the second portion 211B on the substrate 10 .

[0067] By dividing the first electrode 211 into a first part 211A and a second part 211B, the orthographic projection of the first via 91 on the substrate 10 is located within the orthographic projection of the second part 211B on the substrate 10, thereby avoiding overlap between the first via 91 and the first part 211B, thereby avoiding affecting the photoelectric conversion layer 500 formed on the side of the first part 211A away from the substrate 10, protecting the integrity of the side wall of the photoelectric conversion layer 500, avoiding defects in the side wall of the photoelectric conversion layer 500, and protecting the performance of the photodiode.

[0068] like Figure 2As shown, the detection substrate also includes an insulating structure layer 900 and a third metal layer 230. The insulating structure layer 900 is located on the side of the second metal layer 220 away from the substrate 10. The insulating structure layer 900 is provided with a second via 92. The orthographic projection of the second via 92 on the substrate 10 is located within the orthographic projection of the second electrode 810 on the substrate 10. The third metal layer 230 is located on the side of the insulating structure layer 900 away from the substrate 10. The third metal layer 230 includes a bias signal line 231, and the bias signal line 231 is connected to the second electrode 810 through the second via 92.

[0069] An insulating structure layer 900 is formed on a side of the second metal layer 220 facing away from the substrate 10 to protect the photoelectric conversion layer 500 .

[0070] like Figure 2 As shown, the insulating structure layer 900 includes a first passivation layer 610, a first resin layer 710 and a second passivation layer 620 stacked in sequence, the first resin layer 710 is provided with a third via 93, and the orthographic projection of the second via 92 on the substrate 10 is located within the orthographic projection of the third via 93 on the substrate 10.

[0071] The first passivation layer 610, the first resin layer 710 and the second passivation layer 620 are arranged in the insulating structure layer 900, so that the fourth insulating layer 26, which is arranged on the side of the second bottom electrode 25 away from the second photoelectric conversion layer 27 in the related art, is used as a part of the insulating structure layer 900 in the embodiment of the present application, covering the side of the photoelectric conversion layer 500 away from the substrate 10, thereby not only avoiding the impact on the flatness of the photoelectric conversion layer 500, but also protecting the photoelectric conversion layer 500 and improving the scratch resistance of the photoelectric conversion layer 500.

[0072] like Figure 2 As shown, the third metal layer 230 further includes a shielding portion located in the detection area, and the orthographic projection of the active layer 400 on the substrate 10 is located within the orthographic projection of the shielding portion on the substrate 10 .

[0073] By arranging the active layer 400 within the orthographic projection of the shielding portion on the substrate 10 , it is prevented that static electricity generated by the detection substrate during operation may damage the performance of the thin film transistor TFT1 .

[0074] In one embodiment, the thickness of the first insulating layer 310 is less than or equal to the thickness of the first passivation layer 610 .

[0075] Since an insulating structure layer 900 is also provided on the side of the first insulating layer 310 facing away from the substrate 10, the first insulating layer 310 does not need to be very thick to protect the photoelectric conversion layer 500. By making the thickness of the first insulating layer 310 less than or equal to the thickness of the first passivation layer 610, the thickness of the detection substrate can be reduced.

[0076] like Figure 3 As shown, the detection substrate 1000 includes a plurality of gate lines GL extending along a first direction and a plurality of read lines SDL extending along a second direction. The plurality of gate lines GL and the plurality of read lines SDL cross each other to define a plurality of detection areas 1001. The gate 212 is connected to the gate line GL, and the second electrode 222 of the thin film transistor is connected to the read line SDL. The second direction intersects with the first direction.

[0077] like Figure 4 As shown in FIG. 1 , the bias signal line 231 extends in the same direction as the read line SDL. Figure 2 shown.

[0078] In one embodiment, Figure 3 As shown, the detection substrate also includes a binding region D, such as Figure 5A Shown and Figure 5B As shown, the detection substrate further includes a third passivation layer 630 and a conductive layer 820 sequentially arranged on the side of the third metal layer 230 away from the substrate 10, and the first passivation layer 610, the second passivation layer 620 and the third passivation layer 630 are also located in the binding area D; the detection substrate satisfies at least one of the following:

[0079] The conductive layer 820 includes a first binding pin E1 located in the binding area D, the third metal layer 230 includes a first transfer portion 232 located in the binding area D, the detection substrate also includes a first signal line located in the binding area D, the third passivation layer 630 is provided with a fourth via 94, the first passivation layer 610 and the second passivation layer 620 are provided with a fifth via 95, the first binding pin E1 is connected to the first transfer portion 232 through the fourth via 94, the first transfer portion 232 is connected to the first signal line through the fifth via 95, and the first signal line is connected to the gate 212. The first signal line is used to connect the first electrode 212 to the gate line GL.

[0080] The conductive layer 820 includes a second binding pin F1 located in the binding area D, the third metal layer 230 includes a second transfer portion 233 located in the binding area D, the detection substrate also includes a second signal line located in the binding area D, the third passivation layer 630 is provided with a sixth via 96, the first passivation layer 610 and the second passivation layer 620 are provided with a seventh via 97, the second binding pin F1 is connected to the second transfer portion 233 through the sixth via 96, the second transfer portion 233 is connected to the second signal line through the seventh via 97, and the second signal line is connected to the second pole 222. The second signal line is used to connect the first pole 221 to the read line SDL.

[0081] The above connection method reduces the transition of one metal layer (SD2 layer) in the implementation mode of the present application, thereby reducing the additional loss and noise impact caused by the overlapping of metal wires during signal transmission.

[0082] like Fig. 6A FIG. 1 is a schematic diagram of a film structure for detecting a gate drive signal of a substrate in the related art. Figure 6B The figure shows a schematic diagram of a data reading signal film structure of a detection substrate in the related art. Fig. 6A and Figure 6B As shown, in the related art, the peripheral signal of the detection substrate goes from the second conductive layer 33 to the fourth metal layer 31, the second bottom electrode 25 (the lower electrode metal layer of the PIN device), and finally reaches the second gate 22 and the source data line layer 24. The thickness of the non-metal layer from the second conductive layer 33 to the second gate 22 / source data line layer 24 includes the gate insulating layer 21, the fourth insulating layer 26, the buffer layer 28, the fifth insulating layer 30 and the sixth insulating layer 32. Among them, the source data line layer includes the first electrode 241 and the second electrode 242 of the thin film transistor.

[0083] like Figure 5A FIG. 1 is a schematic diagram of a film structure loaded with a gate drive signal according to the present invention, wherein: Figure 5A The schematic diagram of the film structure loaded with the gate drive signal is shown as follows: Figure 3 The cross section corresponding to the dashed line EE. Figure 5A As shown, the peripheral gate drive signal of the embodiment of the present application passes through the conductive layer 820 to the third metal layer 230, and finally reaches the gate 212 through the first via 91. Figure 5B FIG. 1 is a schematic diagram of a film structure for outputting a data read signal according to the present invention, wherein: Figure 5B The schematic diagram of the film structure of the data reading signal output is shown as follows: Figure 3 The cross section corresponding to the dotted line FF in the middle. The read signal goes from the conductive layer 820 to the third metal layer 230, and finally reaches the first electrode 221 through the second via 92. The depth of the entire second via 92 includes the thickness of the first passivation layer 610, the second passivation layer 620 and the third passivation layer 630. Since the thickness of the non-metallic layer passed by the formed second via 92 is reduced, the difficulty and risk of the second via 92 in the manufacturing process are reduced. At the same time, for the loading of peripheral signals, compared with Fig. 6A and Figure 6B As shown in the related technology, the transition of a layer of metal (SD2 layer) is reduced in the implementation mode of the present application, thereby reducing the additional loss and noise impact caused by the overlapping of metal wires during signal transmission.

[0084] In one embodiment, the detection substrate further includes a second resin layer 720 , and the second resin layer 720 is located on a side of the third passivation layer 630 and the conductive layer 820 facing away from the substrate 10 .

[0085] The second resin layer 720 is used to protect the conductive layer 820 .

[0086] The material of the first insulating layer 310 can be the same as any one of the first passivation layer 610, the second passivation layer 620 and the third passivation layer 630; the materials of the second electrode 810 and the conductive layer 820 include: indium tin oxide (ITO), indium zinc oxide (IZO) and other materials that can form a transparent conductive film. The second resin layer 720 can be a top resin layer (TopResin) of the detection area.

[0087] Embodiment 2

[0088] like Figure 7 As shown, the present application also provides a method for preparing a detection substrate, comprising:

[0089] S101, such as Figure 8 As shown, a gate electrode 212 and a first electrode 211 of a thin film transistor are formed on one side of the substrate 10. The first electrode 211 includes a first portion 211A and a second portion 211B, and the second portion 211B is located outside the first portion 211A.

[0090] S102, such as Fig. 9 As shown, a photoelectric conversion layer 500 is formed on the side of the second electrode 810 facing away from the substrate 10, and the orthographic projection of the photoelectric conversion layer 500 on the substrate 10 is located within the orthographic projection of the first portion 211A on the substrate 10;

[0091] S103, forming a second electrode 810 on a side of the photoelectric conversion layer 500 facing away from the substrate 10;

[0092] S104, such as Fig.10 As shown, a first insulating layer 310 is formed on the side of the gate 212 and the second electrode 810 facing away from the substrate 10, the orthographic projections of the gate 212 and the first electrode 211 on the substrate 10 are located within the orthographic projection of the first insulating layer 310 on the substrate 10, and the first insulating layer 310 is provided with a first via hole 91, and the orthographic projection of the first via hole 91 on the substrate 10 at least partially overlaps with the orthographic projection of the second portion 211B on the substrate 10;

[0093] S105, such as Fig.11 As shown, an active layer 400 of a thin film transistor and a second metal layer 220 are sequentially formed on the side of the first insulating layer 310 facing away from the substrate 10 . The second metal layer 220 includes a first electrode 221 and a second electrode 222 of the thin film transistor. The first electrode 221 is connected to the first portion 211A through a first via 91 .

[0094] The first electrode 211 is the bottom electrode of the photodiode in the detection area, and the second electrode 810 is the top electrode of the photodiode in the detection area; the first insulating layer 310 is used to protect the structure of the photodiode and the gate 212 and the first electrode 211. The first via hole 91 formed in the first insulating layer 310 is used to overlap the first pole 221 with the first electrode 211 later.

[0095] In the embodiment of the present application, the side wall of the photoelectric conversion layer 500 needs to be protected after the second electrode 810 is manufactured. Since the process of manufacturing the first passivation layer 610 on the second electrode 810 and the photoelectric conversion layer 500 involves the manufacturing of the active layer 400, the first pole 221 and the second pole 222, and the etching process will cause over-etching or residual effects on the photoelectric conversion layer 500, thereby increasing the defects of the side wall of the photoelectric conversion layer 500 and deteriorating the performance of the photodiode. Therefore, the embodiment of the present application does not use the first passivation layer 610 to protect the side wall of the photoelectric conversion layer 500, but immediately manufactures the first insulating layer 310 to protect the side wall of the photoelectric conversion layer 500 after the second electrode 810 is manufactured, thereby avoiding defects on its side wall and protecting the performance of the photodiode.

[0096] In the implementation manner of the present application, since the first electrode 211 is manufactured in the first layer, if problems such as high incidence of foreign matter are found in process monitoring, such as in the process detection after the first electrode 211 is manufactured, the foreign matter situation on the first electrode 211 will be determined. If there are too many abnormalities, rework processing can be performed, such as decapping processing, that is, the first electrode 211 or the first metal layer 210 is removed by etching, and then the first metal layer 210 is deposited again or the first electrode 211 is manufactured, so that after the first layer (first metal layer 210) is manufactured, if the monitoring fails, the first metal layer 210 can be removed and remade. In this way, the higher requirements of the photoelectric conversion layer 500 for the flatness of the bottom can be met, and the risks of abnormality caused by foreign matter in the batch process can be avoided, thereby improving the product yield. However, if Figure 1 In the conventional flat panel detector product shown, there are two film layers (fourth insulating layer 26 and gate insulating layer 21 ) below the second bottom electrode layer 25 , so the second bottom electrode layer 25 cannot be reworked.

[0097] In one embodiment, the method further includes: forming a first passivation layer 610 on a side of the second metal layer 220 facing away from the substrate 10; Fig.11As shown, a first resin layer 710 is formed on the side of the first passivation layer 610 facing away from the substrate 10, and the first resin layer 710 is provided with a third via hole 93, and the orthographic projection of the third via hole 93 on the substrate 10 is located within the orthographic projection of the second electrode 810 on the substrate 10; Figure 2 As shown, a second passivation layer 620 is formed on the side of the first resin layer 710 facing away from the substrate 10, the orthographic projection of the second via 92 on the substrate 10 is located within the orthographic projection of the third via 93 on the substrate 10, and the second passivation layer 620 is provided with a second via 92, and the second via 92 passes through the second passivation layer 620 and the first passivation layer 610; a third metal layer 230 is formed on the side of the second passivation layer 620 facing away from the substrate 10, and the third metal layer 230 includes a bias signal line 231, and the bias signal line 231 is connected to the second electrode 810 through the second via 92.

[0098] In one embodiment, the method further includes: forming a third passivation layer 630 on a side of the second passivation layer 620 and the third metal layer 230 facing away from the substrate 10 ; and forming a conductive layer 820 and a second resin layer 720 on a side of the third passivation layer 630 facing away from the substrate 10 .

[0099] The first passivation layer 610 and the first insulating layer 310 below the third via hole 93 of the first resin layer 710 can be etched by dry etching to expose the second electrode 810. Then, the third metal layer 230, the third passivation layer 630, the conductive layer 820 and the second resin layer 720 are manufactured.

[0100] In related technologies, such as Figure 1 As shown, the number of mask layers required for the production of the flat-panel detector product includes: a second gate 22, a second active layer 23, a source metal wire layer 24, a fourth insulating layer 26, a second bottom electrode 25, a second photoelectric conversion layer 27 and a second top electrode 35, a fourth resin layer 29, a fifth insulating layer 30, a fourth metal layer 31, a sixth insulating layer 32, a second conductive layer 33 and a fifth resin layer 34, totaling 12; and in the process of detecting the substrate in the embodiment of the present application, the number of mask layers required includes: a first metal layer 210 (a first electrode 211 and a gate 212), a photoelectric conversion layer 500 and a second electrode 810, a first insulating layer 310, an active layer 400, a second metal layer 220 (a first pole 221 and a second pole 222), a first resin layer 701, a second passivation layer 620, a third metal layer 230, a third passivation layer 630, a conductive layer 820 and a second resin layer 720, totaling 11 layers. Compared with the production of existing flat-panel detector products, in the process of preparing the detection substrate of the embodiment of the present application, the number of masks required is reduced from 12 to 11, thereby reducing production costs.

[0101] like Fig.12, which is a schematic diagram of a pixel plane of a flat panel detector in the related art, wherein 41 is a via hole in the fourth insulating layer 26, and 42 is a via hole in the fourth resin layer 29 and the fifth insulating layer 30. The stacked layers in the second active layer 23 are obviously more.

[0102] In an embodiment of the present application, the deposition of the first insulating layer 310, the first passivation layer 610, the active layer 400, the photoelectric conversion layer 500, the second passivation layer 620, the third passivation layer 630 and the vias formed in these layers (such as the first via 91, the second via 92, the third via 93) can be formed by dry etching; the formation of the first metal layer 210 (the first electrode 211 and the gate 212), the first electrode 221, the second electrode 810, the third metal layer 230 and the conductive layer 820 can use wet etching; the first resin layer 701 and the second resin layer 720 are formed by exposure.

[0103] Embodiment 3

[0104] The present application also provides a detection device, comprising a detection substrate as described in any one of the first aspects.

[0105] The detection device provided in this embodiment is based on the same concept as the above-mentioned detection substrate, so it can at least achieve the beneficial effects that can be achieved by the above-mentioned detection substrate, which will not be described in detail here.

[0106] In the implementation scheme of the present application, this scheme uses the first insulating layer to combine the gate insulating layer and the buffer layer into the same layer, which can improve the protection ability of the side wall of the photoelectric conversion layer. The photoelectric conversion layer is formed first, and then the first pole and the second pole (source and drain) are made, which can ensure the flatness of the first electrode, thereby improving the product yield. In addition, all non-metallic layers involved in the process are covered directly above the photodiode. Therefore, compared with the solutions in the related art, the protective layer above the photodiode structure of the implementation scheme of the present application is thicker, which can reduce the interference caused by the surface contact of the product to the photodiode, thereby improving the scratch resistance of the photodiode and the stability of the photoelectric conversion layer. At the same time, for the loading of peripheral signals, the implementation scheme of the present application reduces the number of overlaps of the metal layer, which can reduce the loss and distortion during signal transmission. By making the gate electrode of the thin film transistor and the bottom electrode (first electrode) of the photodiode in the same layer, and then making the photoelectric conversion layer of the photodiode first, and then making the source and drain electrodes (first pole and second pole) of the thin film transistor, the overlapping order of the first electrode and the source data line is changed through this change in structural design, that is, the source data line overlaps the first pole in the scheme in the related art to the first pole overlaps the first electrode, thereby ensuring the flatness under the photoelectric conversion layer and reducing the complexity of making the base and vias of the first pole. In addition, by making the photodiode first and then completing the thin film transistor structure, while ensuring the flatness of the bottom of the photodiode, it also improves the defects caused by the abnormal bad points caused by the leakage current of the side wall, thereby improving the product yield and production capacity. In the process of preparing the detection substrate of the embodiment of the present application, the number of masks required is reduced from 12 to 11, reducing the production cost.

[0107] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way.

[0108] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of means or steps not listed in the claims. The word "a" or "an" preceding a means does not exclude the presence of a plurality of such means. The present application may be implemented by means of hardware comprising several different means and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0109] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A detection substrate, characterized in that: Comprising a detection area, the detection substrate comprises: substrate; A gate of a thin film transistor is located on one side of the substrate, and the gate is located in the detection area; A first electrode, located on a side of the substrate facing the gate and located in the detection area, the first electrode comprising a first portion and a second portion, the second portion being located outside the first portion; a photoelectric conversion layer, located on a side of the first electrode facing away from the substrate, wherein an orthographic projection of the photoelectric conversion layer on the substrate is located within an orthographic projection of the first portion on the substrate; A second electrode is located on a side of the photoelectric conversion layer away from the substrate; a first insulating layer, located on a side of the gate and the second electrode facing away from the substrate, the orthographic projections of the gate and the first electrode on the substrate being located within the orthographic projection of the first insulating layer on the substrate, the first insulating layer being provided with a first via hole, the orthographic projection of the first via hole on the substrate at least partially overlapping with the orthographic projection of the second portion on the substrate; The active layer of the thin film transistor is located on a side of the first insulating layer away from the substrate; The second metal layer is located on a side of the active layer away from the substrate, and the second metal layer includes a first electrode and a second electrode of the thin film transistor, and the first electrode is connected to the first part through the first via hole.

2. The detection substrate according to claim 1, characterized in that: The detection substrate includes a first metal layer, and the first metal layer includes the gate and the first electrode.

3. The detection substrate according to claim 1, characterized in that An orthographic projection of the first via hole on the substrate is located within an orthographic projection of the second portion on the substrate.

4. The detection substrate according to claim 1, characterized in that: The detection substrate further comprises an insulating structure layer and a third metal layer, wherein the insulating structure layer is located on a side of the second metal layer away from the substrate, the insulating structure layer is provided with a second via hole, and the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the second electrode on the substrate; The third metal layer is located on a side of the insulating structure layer away from the substrate. The third metal layer includes a bias signal line. The bias signal line is connected to the second electrode through the second via hole.

5. The detection substrate according to claim 4, characterized in that: The insulating structure layer includes a first passivation layer, a first resin layer, and a second passivation layer which are stacked in sequence. The first resin layer is provided with a third via hole. The orthographic projection of the second via hole on the substrate is located within the orthographic projection of the third via hole on the substrate.

6. The detection substrate according to claim 4, characterized in that: The third metal layer further includes a shielding portion located in the detection area, and an orthographic projection of the active layer on the substrate is located within an orthographic projection of the shielding portion on the substrate.

7. The detection substrate according to claim 5, characterized in that: The thickness of the first insulating layer is less than or equal to the thickness of the first passivation layer.

8. The detection substrate according to claim 5, characterized in that: The detection substrate further includes a binding area, and the detection substrate further includes a third passivation layer and a conductive layer sequentially arranged on a side of the third metal layer away from the substrate, and the first passivation layer, the second passivation layer and the third passivation layer are also located in the binding area; the detection substrate satisfies at least one of the following: The conductive layer includes a first binding pin located in the binding area, the third metal layer includes a first transfer portion located in the binding area, the detection substrate also includes a first signal line located in the binding area, the third passivation layer is provided with a fourth via hole, the first passivation layer and the second passivation layer are provided with a fifth via hole, the first binding pin is connected to the first transfer portion through the fourth via hole, the first transfer portion is connected to the first signal line through the fifth via hole, and the first signal line is connected to the gate; The conductive layer includes a second binding pin located in the binding area, the third metal layer includes a second transfer portion located in the binding area, the detection substrate also includes a second signal line located in the binding area, the third passivation layer is provided with a sixth via, the first passivation layer and the second passivation layer are provided with a seventh via, the second binding pin is connected to the second transfer portion through the sixth via, the second transfer portion is connected to the second signal line through the seventh via, and the second signal line is connected to the second pole.

9. The detection substrate according to claim 8, characterized in that: The detection substrate further includes a second resin layer, and the second resin layer is located on a side of the third passivation layer and the conductive layer facing away from the substrate.

10. The detection substrate according to claim 1, characterized in that: The detection substrate includes a plurality of gate lines extending along a first direction and a plurality of read lines extending along a second direction. The plurality of gate lines and the plurality of read lines intersect with each other to define a plurality of detection areas. The gate is connected to the gate line, and the second electrode of the thin film transistor is connected to the read line. The second direction intersects with the first direction.

11. The detection substrate according to claim 10, characterized in that: The bias signal line and the read line extend in the same direction.

12. A method for preparing a detection substrate, characterized in that: include: forming a gate electrode and a first electrode of a thin film transistor on one side of the substrate, wherein the first electrode comprises a first portion and a second portion, and the second portion is located outside the first portion; forming a photoelectric conversion layer on a side of the second electrode facing away from the substrate, wherein an orthographic projection of the photoelectric conversion layer on the substrate is located within an orthographic projection of the first portion on the substrate; forming a second electrode on a side of the photoelectric conversion layer facing away from the substrate; A first insulating layer is formed on a side of the gate and the second electrode facing away from the substrate, the orthographic projections of the gate and the first electrode on the substrate are located within the orthographic projection of the first insulating layer on the substrate, the first insulating layer is provided with a first via hole, and the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the second portion on the substrate; An active layer of the thin film transistor and a second metal layer are sequentially formed on a side of the first insulating layer away from the substrate. The second metal layer includes a first electrode and a second electrode of the thin film transistor. The first electrode is connected to the first portion through the first via hole.

13. The preparation method according to claim 12, characterized in that: Also includes: forming a first passivation layer on a side of the second metal layer facing away from the substrate; forming a first resin layer on a side of the first passivation layer facing away from the substrate, wherein the first resin layer is provided with a third via hole, and an orthographic projection of the third via hole on the substrate is located within an orthographic projection of the second electrode on the substrate; forming a second passivation layer on a side of the first resin layer facing away from the substrate, wherein the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the third via hole on the substrate, and the second passivation layer is provided with a second via hole, and the second via hole penetrates the second passivation layer and the first passivation layer; A third metal layer is formed on a side of the second passivation layer facing away from the substrate. The third metal layer includes a bias signal line. The bias signal line is connected to the second electrode through the second via hole.

14. The preparation method according to claim 13, characterized in that: Also includes: forming a third passivation layer on a side of the second passivation layer and the third metal layer facing away from the substrate; A conductive layer and a second resin layer are formed on a side of the third passivation layer facing away from the substrate.

15. A detection device, characterized in that: The method comprises the detection substrate according to any one of claims 1 to 11.

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