A method for preparing a solar cell and a solar cell

Abstract

An embodiment of the present invention discloses a method for preparing a solar cell and a solar cell. The preparation method first provides an N-type silicon-based process wafer, and performs a boron diffusion doping treatment on one side of a first surface of the N-type silicon-based process wafer, and performs a phosphorus diffusion doping treatment on one side of a second surface of the N-type silicon-based process wafer, then uses an extreme ultraviolet laser light source to perform a local doping push-up treatment on a gate line area on the second surface, and then performs an annealing activation treatment on the second surface after the local doping push-up treatment, so that the gate line area on the second surface forms a heavily doped region, and the non-gate line area on the second surface forms a lightly doped region, then forms a first passivation film layer on the first surface, and forms a second passivation film layer on the second surface, and finally performs screen printing and sintering treatment on a side of the first passivation film layer away from the first surface and a side of the second passivation film layer away from the second surface, respectively, to form an electrode structure to prepare a solar cell.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of solar cells, and in particular to a method for preparing a solar cell and the solar cell. Background Art

[0002] The continuous upgrading of photovoltaic cell structures has led to a continuous accumulation of old production capacity, and cost reduction and efficiency improvement have become key issues for the photovoltaic industry. Compared with P-type crystalline silicon cells, N-type crystalline silicon cells have advantages such as longer minority carrier lifetime, no photodegradation, better low-light performance, and a low temperature coefficient. They hold the greatest hope for achieving a breakthrough in the theoretical maximum efficiency of crystalline silicon solar cells.

[0003] Currently, in the preparation process of N-type TOPCon (Tunnel Oxide Passivating Contact) cells, a high-temperature diffusion furnace is generally used to diffuse phosphorus across the entire back surface of the cell, achieving a higher phosphorus doping concentration in the polysilicon layer. However, during this process, some phosphorus atoms will penetrate the tunnel oxide layer from the polysilicon layer and enter the N-type silicon substrate, increasing the impurity concentration in the N-type silicon substrate and leading to increased Auger recombination. Auger recombination is a carrier recombination mechanism that causes photogenerated carriers generated within the cell to recombine before reaching the electrode, significantly reducing the cell's short-circuit current density and photoelectric conversion efficiency. Summary of the Invention

[0004] An embodiment of the present invention provides a method for preparing a solar cell and a solar cell, so as to improve the doping concentration and distribution of phosphorus atoms in the polysilicon layer on the back side of the solar cell, and make the gate line area on the back side heavily doped and the non-gate line area on the back side lightly doped, thereby effectively reducing metal recombination and surface recombination, improving the open circuit voltage, short circuit current and fill factor, and improving the photoelectric conversion efficiency of the solar cell.

[0005] In a first aspect, an embodiment of the present invention provides a method for preparing a solar cell, comprising:

[0006] Providing an N-type silicon-based process wafer, and performing a boron diffusion doping treatment on a first surface side of the N-type silicon-based process wafer, and performing a phosphorus diffusion doping treatment on a second surface side of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are opposite to each other, and the first surface is a suede surface, and the second surface is a polished surface;

[0007] Using an extreme ultraviolet laser light source, performing a local doping boost process on the gate line area on the second surface;

[0008] performing an annealing activation process on the second surface after the local doping boost process, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area;

[0009] forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface;

[0010] Screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface respectively to form an electrode structure to manufacture the solar cell.

[0011] Optionally, the wavelength range of the extreme ultraviolet laser light source is 10-100 nm; and / or the energy range of the extreme ultraviolet laser light source is 2-100 mJ / cm 2 .

[0012] Optionally, the temperature range of the annealing activation treatment is 700-900°C.

[0013] Optionally, after performing a local doping boost process on the gate line region on the second surface using an extreme ultraviolet laser light source, the method further includes:

[0014] A buffered oxide etching solution is used to clean the second surface after the local doping drive-in treatment.

[0015] Optionally, the N-type silicon-based process wafer includes an N-type silicon substrate, a tunneling oxide layer and a polysilicon layer;

[0016] Provide N-type silicon-based process wafers, including:

[0017] forming the tunneling oxide layer on one side surface of the N-type silicon substrate;

[0018] The polysilicon layer is formed on a surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the surface of the polysilicon layer away from the tunneling oxide layer is the second surface, and the surface of the N-type silicon substrate on which the tunneling oxide layer is not formed is the first surface.

[0019] Optionally, the thickness of the polysilicon layer is in the range of 80-200 nm.

[0020] Optionally, the polysilicon layer is prepared at a temperature in a range of 550-650° C.; and / or the polysilicon layer is prepared at a pressure in a range of 10-100 mTorr.

[0021] Optionally, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer;

[0022] Forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface, comprising:

[0023] forming the anti-ultraviolet attenuation film layer on the first surface;

[0024] forming the first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface;

[0025] The second anti-reflection layer is formed on the second surface.

[0026] Optionally, the material of the anti-ultraviolet attenuation film layer includes aluminum oxide; and / or the material of the first anti-reflection layer includes silicon nitride; and / or the material of the second anti-reflection layer includes silicon nitride.

[0027] In a second aspect, an embodiment of the present invention further provides a solar cell, which is prepared using the method for preparing a solar cell as described in any one of the first aspects.

[0028] An embodiment of the present invention provides a method for preparing a solar cell and a solar cell. The preparation method first provides an N-type silicon-based process wafer, and performs a boron diffusion doping treatment on one side of a first surface of the N-type silicon-based process wafer, and performs a phosphorus diffusion doping treatment on one side of a second surface of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are opposite to each other, and the first surface is a velvet surface, and the second surface is a polished surface; then, an extreme ultraviolet laser light source is used to perform a local doping push-up treatment on the gate line area on the second surface, and then an annealing activation treatment is performed on the second surface after the local doping push-up treatment, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area; then, a first passivation film layer is formed on the first surface, and a second passivation film layer is formed on the second surface; finally, screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface, respectively, to form an electrode structure to prepare a solar cell. By using the above method, the second surface of the N-type silicon-based process wafer is sequentially subjected to phosphorus diffusion doping treatment, local doping push treatment and annealing activation treatment, which effectively improves the doping concentration and distribution of phosphorus atoms in the polysilicon layer on the back of the solar cell, reduces metal recombination and surface recombination, and makes the gate line area on the back side heavily doped, that is, makes the contact area of the metal electrode heavily doped, which can significantly reduce the contact resistance between the metal electrode on the back side and the N-type silicon substrate, reduces the scattering and recombination of carriers at the contact interface, improves the fill factor and short-circuit current density of the solar cell, and makes the non-gate line area on the back side lightly doped, that is, makes the non-metallic electrode contact area lightly doped. The domain is lightly doped, which reduces the recombination rate of the non-gate line area, reduces the recombination losses such as Auger recombination inside the solar cell, and improves the open circuit voltage and overall performance of the solar cell. In addition, differentiated doping is performed on the gate line area and the non-gate line area on the back, which optimizes the electrode structure, so that the carrier collection efficiency and transmission performance inside the solar cell are significantly improved, thereby improving the photoelectric conversion efficiency and operational reliability of the solar cell. The thickness of the polysilicon layer on the back of the solar cell can be made thinner, which increases the red light response in the long-wave region of sunlight and avoids the parasitic light absorption caused by an overly thick polysilicon layer, which is conducive to the realization of ultra-thin design of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 11 is a schematic flow chart of a method for preparing a solar cell provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic flow chart of another method for preparing a solar cell provided by an embodiment of the present invention;

[0032] Figure 3 This is a schematic flow chart of another method for preparing a solar cell provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0034] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described based on the angles shown in the accompanying drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but can also be formed indirectly "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not indicate any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] The term "including" and its variations used in the present invention are open inclusions, that is, "including but not limited to." The term "based on" means "based at least in part on." The term "one embodiment" means "at least one embodiment."

[0036] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or mutual dependence.

[0037] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0038] Figure 1This is a schematic flow chart of a method for preparing a solar cell provided by an embodiment of the present invention. The method for preparing a solar cell can be applied to the process of preparing a solar cell. The method for preparing a solar cell can be used to prepare a solar cell. Figure 1 As shown, the preparation method comprises:

[0039] S110. Provide an N-type silicon-based process wafer, and perform boron diffusion doping treatment on one side of a first surface of the N-type silicon-based process wafer, and perform phosphorus diffusion doping treatment on one side of a second surface of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer facing away from each other, and the first surface is a velvet surface, and the second surface is a polished surface.

[0040] Specifically, an N-type silicon-based process wafer is provided, comprising a first surface and a second surface facing away from each other. Exemplarily, the first surface can be understood as the front side of the N-type silicon-based process wafer, and the second surface can be understood as the back side of the N-type silicon-based process wafer. Exemplarily, the N-type silicon-based process wafer may comprise an N-type silicon substrate, a tunneling oxide layer, and a polysilicon layer, wherein the tunneling oxide layer is located on a side surface of the N-type silicon substrate, and the polysilicon layer is located on a side surface of the tunneling oxide layer away from the N-type silicon substrate. Thus, the side surface of the polysilicon layer away from the tunneling oxide layer is the second surface of the N-type silicon-based process wafer, and the side surface of the N-type silicon substrate not formed with the tunneling oxide layer is the first surface of the N-type silicon-based process wafer.

[0041] The first surface of the N-type silicon-based process wafer has a textured surface, that is, the surface of the N-type silicon substrate on the side not formed with the tunneling oxide layer has a textured surface. Exemplarily, the first surface of the N-type silicon-based process wafer can be subjected to a texturing treatment to impart a textured surface to the first surface of the N-type silicon-based process wafer. Exemplarily, the textured surface exhibits a pyramidal structure when tested under a microscope. The texturing treatment can remove organic contaminants and metallic impurities from the surface of the N-type silicon-based process wafer, remove mechanical damage layers generated during the cutting process of the N-type silicon-based process wafer, reduce recombination centers, and form an uneven textured surface to facilitate the light trapping effect, thereby increasing the N-type silicon-based process wafer's absorption rate of sunlight and reducing its reflectivity. This also increases the surface area of the N-type silicon-based process wafer, thereby also increasing the area of the PN junction formed on the surface.

[0042] After the first surface of the N-type silicon-based process wafer undergoes texturing, a boron diffusion doping treatment may be performed on one side of the first surface of the N-type silicon-based process wafer to form a PN junction on the first surface of the N-type silicon-based process wafer. The junction formation process involves forming semiconductor layers of different conductivity types on a semiconductor substrate. For example, the boron diffusion doping treatment may be performed in a high-temperature diffusion furnace.

[0043] The second surface of the N-type silicon-based process wafer is a polished surface, that is, the surface of the polysilicon layer away from the tunneling oxide layer is a polished surface. It should be noted that one side of the surface of the N-type silicon substrate can be polished. Then, after the tunneling oxide layer and the polysilicon layer are subsequently formed on one side of the surface of the N-type silicon substrate, the surface of the polysilicon layer away from the tunneling oxide layer can be understood as the polished surface. That is, after the first surface of the N-type silicon-based process wafer is subjected to boron diffusion doping treatment, the second surface of the N-type silicon substrate can be chain pickled and alkaline polished to ensure that the second surface of the N-type silicon substrate is a polished surface, so that the N-type silicon-based process wafer forms a polished surface with high reflectivity, thereby improving the flatness of the battery surface and increasing the reflection of long-wave light to promote secondary absorption of light, increase short-circuit current and reduce leakage current.

[0044] After polishing the second surface of the N-type silicon-based process wafer, a phosphorus diffusion doping treatment can be performed on one side of the second surface of the N-type silicon-based process wafer to form a PN junction on the second surface of the N-type silicon-based process wafer. The junction formation process is to grow a semiconductor layer of different conductivity types on a piece of semiconductor substrate material. For example, the phosphorus diffusion doping treatment can be performed in a high-temperature diffusion furnace. It should be understood that this embodiment only describes the example of first performing a boron diffusion doping treatment on the first surface of the N-type silicon-based process wafer and then performing a phosphorus diffusion doping treatment on the second surface of the N-type silicon-based process wafer. In practice, the phosphorus diffusion doping treatment can also be performed on the second surface of the N-type silicon-based process wafer first and then performing a boron diffusion doping treatment on the first surface of the N-type silicon-based process wafer, or the boron diffusion doping treatment can be performed on the first surface of the N-type silicon-based process wafer and the phosphorus diffusion doping treatment can be performed simultaneously on the second surface of the N-type silicon-based process wafer, without specific limitation.

[0045] In addition, after the second surface of the N-type silicon-based process wafer is subjected to phosphorus diffusion doping treatment, the second surface of the N-type silicon-based process wafer can be subjected to chain pickling and etching treatment to ensure that the second surface of the N-type silicon-based process wafer is clean and free of impurities.

[0046] S120, using an extreme ultraviolet laser light source to perform local doping boost processing on the gate line area on the second surface.

[0047] The gateline region on the second surface of the N-type silicon-based process wafer refers to the area where the back electrode structure (or back gateline) will be subsequently formed. Specifically, laser doping boost refers to the process of bombarding impurity atoms or ions (e.g., phosphorus atoms or ions in this embodiment) deposited on the second surface of the N-type silicon-based process wafer with high-energy-density laser pulses, and then doping these impurity atoms or ions into the electrically active region within the N-type silicon-based process wafer. It should be noted that in this embodiment, an extreme ultraviolet laser light source can be used to perform a localized doping boost on the gateline region on the second surface of the N-type silicon-based process wafer after the phosphorus diffusion doping treatment. This melts a portion of the phosphosilicate glass deposited on the second surface of the N-type silicon-based process wafer, allowing phosphorus in the melted phosphosilicate glass to diffuse into the N-type silicon-based process wafer, increasing the phosphorus doping concentration in the laser-irradiated area and thereby redistributing the phosphorus source within the N-type silicon-based process wafer. For example, after the localized doping boost treatment using the extreme ultraviolet laser light source, a micron-scale pyramid structure or a smooth etched surface is formed on the second surface of the N-type silicon-based process wafer to reduce surface recombination and optimize electrode contact performance. Among them, the extreme ultraviolet laser light source has the characteristics of ultra-high energy density and precise penetration, which is far superior to other laser light sources, and can more easily, quickly, accurately and efficiently realize the laser doping propulsion process in this embodiment.

[0048] S130 , performing an annealing activation process on the second surface after the local doping drive-in process, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area.

[0049] Specifically, after the phosphorus diffusion doping process and the localized doping boost process, the phosphorus source is still primarily distributed on the surface of the N-type silicon-based process wafer. At this point, the N-type silicon-based process wafer needs to be placed again in a high-temperature annealing furnace for an annealing activation process. During this process, the phosphorus source deposited on the surface of the N-type silicon-based process wafer can be utilized to further diffuse into the polysilicon layer at high temperatures. During this diffusion process, the dopant is simultaneously activated. At high temperatures, the dopants that enter the polysilicon lattice, namely phosphorus atoms, occupy positions in the polysilicon lattice, becoming effective donor or acceptor impurities, changing the conductivity type and carrier concentration of the polysilicon. Furthermore, the annealing activation process can form an oxide protection layer on the second surface of the N-type silicon-based process wafer, which can repair lattice losses caused by the laser doping boost process.

[0050] Among them, the area that has been treated with laser doping advancement and the area that has not been treated with laser doping advancement will have different advancement rates due to the different surface phosphorus source distributions, which will cause the laser-doped area to form the junction depth required for the solar cell after high-temperature treatment, thereby forming a heavily doped area in the gate line area on the second surface of the N-type silicon-based process wafer, and forming a lightly doped area in the non-gate line area on the second surface of the N-type silicon-based process wafer. That is, a heavily doped area is formed in the area where the metal gate line contacts the silicon wafer, and a lightly doped area is formed in the area between the metal gate lines. To put it in a more understandable way, for the gate line area on the second surface of the N-type silicon-based process wafer, it has undergone laser doping advancement and annealing activation treatment, and heavy doping can be formed in this area, while for the non-gate line area on the second surface of the N-type silicon-based process wafer, it has undergone annealing activation treatment, and light doping can be formed in this area. It should be noted that the light doping and heavy doping mentioned here are relative, that is, the doping concentration of phosphorus atoms in the gate line area on the second surface of the N-type silicon-based process wafer is higher than the doping concentration of phosphorus atoms in the non-gate line area on the second surface of the N-type silicon-based process wafer. Therefore, the gate line area on the second surface of the N-type silicon-based process wafer is heavily doped relative to the non-gate line area on the second surface, and the non-gate line area on the second surface of the N-type silicon-based process wafer is lightly doped relative to the gate line area on the second surface.

[0051] S140 , forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface.

[0052] Specifically, a passivation film layer can be formed on the first surface and the second surface of the N-type silicon-based process wafer using processes such as atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and coating. It is understood that the first passivation film layer and the second passivation film layer have passivation and anti-ultraviolet attenuation properties, which can effectively prevent the entire solar cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire solar cell. In addition, this embodiment does not limit the preparation order of the first passivation film layer and the second passivation film layer. For example, the first passivation film layer can be formed on the first surface first, and then the second passivation film layer can be formed on the second surface. Alternatively, the second passivation film layer can be formed on the second surface first, and then the first passivation film layer can be formed on the first surface. Alternatively, the first passivation film layer and the second passivation film layer can be formed simultaneously.

[0053] S150 , screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface, respectively, to form an electrode structure, thereby manufacturing a solar cell.

[0054] Specifically, screen printing is one of the core processes in the manufacturing process of solar cells and is mainly used for forming electrodes for solar cells. This process uses the basic principle that the mesh holes of the patterned part of the screen are permeable to the slurry, while the mesh holes of the non-patterned part are not permeable to the slurry for printing. During the printing process, the slurry is accurately squeezed through the mesh holes of the screen onto the N-type silicon substrate. The slurry is evenly distributed on the surface of the solar cell in the form of a wire, forming the required electrode pattern. Generally, the slurry for screen printing can include but is not limited to silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to treat the electrode material screen-printed onto the surface of the cell at high temperature, dry the slurry on the N-type silicon-based process wafer, burn out the organic components of the slurry, and the slurry can corrode through the passivation film layer and connect to the PN junction, so that the metal grid lines and the N-type silicon-based process wafer form good ohmic contact, achieving the purpose of collecting and conducting current.

[0055] Furthermore, the screen-printed solar cells are sintered at a temperature of 740-760°C before undergoing a light injection process. Laser-induced photodiode formation after light injection triggers silver-silicon interdiffusion, significantly reducing contact resistance and increasing the cell's fill factor, effectively boosting cell efficiency.

[0056] It should also be noted that Table 1 is a performance table of a solar cell prepared by a method for preparing a solar cell provided in an embodiment of the present invention. As shown in Table 1, the solar cell prepared in the embodiment of the present invention has been subjected to relevant experiments. It can be concluded that compared with the existing solar cell / control group, the performance parameters such as the photoelectric conversion efficiency Eta, open circuit voltage Voc, short circuit current Isc, fill factor FF, series resistance Rs, parallel resistance Rsh and reverse leakage current Irev of the solar cell in the embodiment of the present invention are better than those of the control group.

[0057] Table 1

[0058]

[0059] The technical solution in the embodiment of the present invention sequentially performs phosphorus diffusion doping treatment, local doping push treatment and annealing activation treatment on the second surface of the N-type silicon-based process wafer, effectively improving the doping concentration and distribution of phosphorus atoms in the polysilicon layer on the back of the solar cell, reducing metal recombination and surface recombination, so that the gate line area on the back is heavily doped, that is, the contact area of the metal electrode is heavily doped, which can significantly reduce the contact resistance between the metal electrode on the back and the N-type silicon substrate, reduce the scattering and recombination of carriers at the contact interface, improve the fill factor and short-circuit current density of the solar cell, and make the non-gate line area on the back lightly doped, that is, the non-metallic electrode is lightly doped. The contact area is lightly doped, which reduces the recombination rate of the non-gate line area, reduces the recombination losses such as Auger recombination inside the solar cell, and improves the open circuit voltage and overall performance of the solar cell. In addition, differentiated doping is performed on the gate line area and the non-gate line area on the back side, which optimizes the electrode structure, so that the carrier collection efficiency and transmission performance inside the solar cell are significantly improved, thereby improving the photoelectric conversion efficiency and operational reliability of the solar cell. The thickness of the polysilicon layer on the back side of the solar cell can be made thinner, which increases the red light response in the long-wave region of sunlight and avoids the parasitic light absorption caused by an overly thick polysilicon layer, which is conducive to the realization of ultra-thin design of solar cells.

[0060] Optionally, the wavelength range of the extreme ultraviolet laser light source is 10-100 nm; and / or the energy range of the extreme ultraviolet laser light source is 2-100 mJ / cm 2 .

[0061] Specifically, in this embodiment, an extreme ultraviolet (EUV) laser light source is used for local doping boost processing. The wavelength range of EUV (10-100nm) is much shorter than that of traditional laser light sources (such as infrared or visible light), and its photon energy is higher, which can achieve precise penetration at a nanometer depth and directly act on the polysilicon layer without damaging the underlying tunneling oxide layer (SiO2). This prevents phosphorus atoms from penetrating the tunneling oxide layer into the N-type silicon substrate and reduces the risk of Auger recombination. In addition, due to its short wavelength characteristics, EUV can achieve high-precision local doping, reduce lateral diffusion, and improve the square resistance uniformity of the gate line area (such as square resistance difference <5%). Exemplarily, the wavelength of the extreme ultraviolet laser light source can be 13.5 nm. Exemplarily, the exposure energy of the extreme ultraviolet laser light source can be 50 mJ / cm 2. This extreme ultraviolet laser light source can laser groove the slurry printing area on the second surface side of the N-type silicon-based process wafer, and realize the heavy phosphorus atom doping treatment of the grooved area of the polysilicon layer. For example, the groove depth of the extreme ultraviolet laser light source needs to match the thickness of the polysilicon layer (80-200 nm). The groove depth range of the extreme ultraviolet laser light source can be 50-150 nm. In this way, it is ensured that the heavily doped area penetrates the polysilicon layer without damaging the tunnel oxide layer.

[0062] Furthermore, the EUV laser light source can, for example, have a scanning speed range of 1-5 m / s. The design of the scanning spot type of the EUV laser light source is associated with the scanning speed. For example, the laser light source can have a square pattern with a side length range of 10-100 μm, or a circular pattern with a diameter range of 10-100 μm. For example, the overlap rate of the laser light source's spot scanning can range from 10-80% to ensure uniform doping.

[0063] Optionally, the temperature range of the annealing activation treatment is 700-900°C.

[0064] Specifically, the N-type silicon-based process wafer after the polysilicon layer on one side of the second surface is grooved can be placed in a high-temperature annealing furnace for annealing activation treatment. Exemplarily, the temperature of the annealing activation treatment can be 800°C. In addition, the time of the annealing activation treatment can be adjusted according to the required doping depth and doping concentration, generally ranging from a few minutes to tens of minutes, to ensure that the phosphorus doping diffuses into the polysilicon. It should also be noted that this embodiment uses an extreme ultraviolet laser light source in conjunction with the annealing activation treatment. After the laser treatment, annealing at 700-900°C is required to activate the doping atoms and repair lattice defects, ultimately achieving a contact resistance corresponding to the heavily doped region of less than 1 mΩ•cm² and a recombination rate corresponding to the lightly doped region of less than 50 cm / s.

[0065] Optionally, after using an extreme ultraviolet laser light source to perform a local doping drive-in treatment on the gate line region on the second surface, the method further includes: using a buffered oxide etching solution to clean the second surface after the local doping drive-in treatment.

[0066] Specifically, the buffered oxide etchant (BOE) is a mixture of hydrofluoric acid and ammonium fluoride in a specific ratio. The BOE solution removes the polysilicon layer from the front and edges of the N-type silicon-based process wafer. It also removes excess phosphosilicate glass or borosilicate glass from the front of the N-type silicon-based process wafer, thereby ensuring the surface cleanliness of the N-type silicon-based process wafer. In other words, the BOE solution effectively removes residues and optimizes the quality of the passivation film.

[0067] Figure 2This is a flow chart of another method for preparing a solar cell provided by an embodiment of the present invention. This embodiment is optimized based on the above embodiment. Optionally, the N-type silicon-based process wafer includes an N-type silicon substrate, a tunneling oxide layer, and a polysilicon layer;

[0068] Provide N-type silicon-based process wafers, including:

[0069] forming a tunneling oxide layer on a surface of one side of the N-type silicon substrate;

[0070] A polysilicon layer is formed on the surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the surface of the polysilicon layer away from the tunneling oxide layer is the second surface, and the surface of the N-type silicon substrate without the tunneling oxide layer is the first surface.

[0071] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 2 As shown, the preparation method comprises:

[0072] S210 , forming a tunneling oxide layer on a surface of one side of the N-type silicon substrate.

[0073] S220, forming a polysilicon layer on a surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the surface of the polysilicon layer away from the tunneling oxide layer is a second surface, and the surface of the N-type silicon substrate on which the tunneling oxide layer is not formed is a first surface.

[0074] Specifically, before phosphorus diffusion doping is performed on the second surface of the N-type silicon substrate, a tunneling oxide layer and a polysilicon layer are sequentially stacked on one side of the N-type silicon substrate. The tunneling oxide layer and polysilicon layer allow majority carriers (electrons) to tunnel smoothly through the substrate while preventing the recombination of minority carriers (holes). This allows for selective carrier collection, reduces surface recombination, and improves the cell's open-circuit voltage and fill factor, thereby enhancing the overall solar cell's photoelectric conversion efficiency. The combined layer of the tunneling oxide layer and polysilicon layer forms a passivating contact structure, effectively reducing both surface recombination and metal contact recombination within the entire solar cell. In other words, depositing an ultra-thin tunneling oxide layer on the surface of the N-type silicon substrate provides excellent interface passivation and a tunneling barrier for different carriers. Depositing a polysilicon layer on the tunneling oxide layer increases electron mobility while suppressing hole mobility. Furthermore, the polysilicon layer contacts the subsequent metal electrode, acting as a bridge for electron transfer. For example, LPCVD technology can be used to first form an ultra-thin silicon dioxide layer on the surface of an N-type silicon substrate as the tunneling oxide layer. Subsequently, a thin layer of polycrystalline silicon is deposited on the ultra-thin silicon dioxide layer to form a polycrystalline silicon layer that satisfies the passivation effect. For example, the thickness of the tunneling oxide layer can range from 1 to 2 nm.

[0075] Optionally, the thickness of the polysilicon layer is in a range of 80-200 nm. Exemplarily, the thickness of the polysilicon layer is in a range of 100-150 nm.

[0076] Optionally, the polysilicon layer is prepared at a temperature in a range of 550-650° C.; and / or the polysilicon layer is prepared at a pressure in a range of 10-100 mTorr.

[0077] Specifically, LPCVD technology can be used, with silane (SiH4) as the reaction gas, at a preparation temperature of 550-650°C and a preparation pressure of 10-100mTorr, to cause the reaction SiH4→Si+2H2 to grow a polysilicon layer of the required thickness on the surface of the tunnel oxide layer away from the N-type silicon substrate. The polysilicon layer is also the object of subsequent phosphorus diffusion doping treatment.

[0078] S230, using an extreme ultraviolet laser light source to perform local doping boost processing on the gate line area on the second surface.

[0079] S240 , performing an annealing activation process on the second surface after the local doping drive-in process, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area.

[0080] S250 , forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface.

[0081] S260 , screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface, respectively, to form an electrode structure, thereby manufacturing a solar cell.

[0082] Figure 3 This is a flow chart of another method for preparing a solar cell provided by an embodiment of the present invention. This embodiment is optimized based on the above embodiment. Optionally, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer;

[0083] Forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface, comprising:

[0084] forming an anti-ultraviolet attenuation film layer on the first surface;

[0085] forming a first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface;

[0086] A second anti-reflection layer is formed on the second surface.

[0087] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 3As shown, the preparation method comprises:

[0088] S310. Provide an N-type silicon-based process wafer, and perform boron diffusion doping treatment on one side of a first surface of the N-type silicon-based process wafer, and perform phosphorus diffusion doping treatment on one side of a second surface of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer facing away from each other, and the first surface is a velvet surface, and the second surface is a polished surface.

[0089] S320, using an extreme ultraviolet laser light source to perform local doping boost processing on the gate line area on the second surface.

[0090] S330 , performing an annealing activation process on the second surface after the local doping drive-in process, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area.

[0091] S340, forming an anti-ultraviolet attenuation film layer on the first surface.

[0092] Specifically, the first passivation film layer includes an anti-UV attenuation film layer and a first anti-reflection layer. Exemplarily, atomic layer deposition (ALD) technology can be used to form the anti-UV attenuation film layer on the first surface of the N-type silicon-based process wafer, effectively providing UV protection and passivating the front surface of the N-type silicon-based process wafer. Exemplarily, the ALD process temperature can be 200-300°C, and the deposition time can be 8-10 minutes. Deposition can be performed 20 times in a cycle at a TMA flow rate of 1500 sccm, an oxygen flow rate of 1800 sccm, and a temperature of 278°C, for a deposition time of 6 minutes. Optionally, the anti-UV attenuation film layer includes aluminum oxide. Optionally, the thickness of the anti-UV attenuation film layer ranges from 6 to 10 nm.

[0093] S350 , forming a first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface.

[0094] Specifically, a coating process can be used to form a first anti-reflection layer on the side of the anti-UV attenuation film layer away from the first surface. The first anti-reflection layer can further improve the passivation and anti-UV attenuation performance of the entire solar cell. It can also reduce the reflection of sunlight, increase the absorption of sunlight, and improve the photoelectric conversion efficiency of the entire solar cell. At the same time, it can reduce surface recombination, increase carrier mobility, and improve the overall performance of the entire solar cell. Optionally, the material of the first anti-reflection layer includes silicon nitride. Optionally, the refractive index of the first anti-reflection layer ranges from 2.2% to 2.3%.

[0095] S360, forming a second anti-reflection layer on the second surface.

[0096] Specifically, the second passivation film layer includes a second anti-reflection layer. A coating process can be used to form the second anti-reflection layer on the second surface of the N-type silicon-based process wafer. The second anti-reflection layer can further enhance the passivation and UV attenuation resistance of the overall solar cell. Optionally, the material of the second anti-reflection layer includes silicon nitride. Optionally, the refractive index of the second anti-reflection layer ranges from 2.2% to 2.3%. Furthermore, the first and second anti-reflection layers can be understood as being prepared simultaneously, differing only in their placement; the remaining materials, parameters, and other parameters are identical.

[0097] S370 , screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface, respectively, to form an electrode structure, thereby manufacturing a solar cell.

[0098] Based on the same inventive concept, embodiments of the present invention further provide a solar cell. This solar cell is manufactured using the solar cell manufacturing method provided in any of the embodiments of the present invention. Therefore, this solar cell has the functional modules and beneficial effects corresponding to the solar cell manufacturing method.

[0099] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing an N-type silicon-based process wafer, and performing a boron diffusion doping treatment on a first surface side of the N-type silicon-based process wafer, and performing a phosphorus diffusion doping treatment on a second surface side of the N-type silicon-based process wafer; wherein the first surface and the second surface are two surfaces of the N-type silicon-based process wafer that are opposite to each other, and the first surface is a suede surface, and the second surface is a polished surface; Using an extreme ultraviolet laser light source, performing a local doping boost process on the gate line area on the second surface; performing an annealing activation process on the second surface after the local doping boost process, so that the gate line area on the second surface forms a heavily doped area, and the non-gate line area on the second surface forms a lightly doped area; forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface; Screen printing and sintering are performed on the side of the first passivation film layer away from the first surface and the side of the second passivation film layer away from the second surface respectively to form an electrode structure to manufacture the solar cell.

2. The preparation method according to claim 1, characterized in that The wavelength range of the extreme ultraviolet laser light source is 10-100 nm; and / or the energy range of the extreme ultraviolet laser light source is 2-100 mJ / cm 2 .

3. The preparation method according to claim 1, characterized in that The temperature range of the annealing activation treatment is 700-900°C.

4. The preparation method according to claim 1, characterized in that After performing a local doping boost process on the gate line region on the second surface using an extreme ultraviolet laser light source, the method further includes: A buffered oxide etching solution is used to clean the second surface after the local doping drive-in treatment.

5. The preparation method according to claim 1, characterized in that The N-type silicon-based process wafer includes an N-type silicon substrate, a tunneling oxide layer and a polysilicon layer; Provide N-type silicon-based process wafers, including: forming the tunneling oxide layer on one side surface of the N-type silicon substrate; The polysilicon layer is formed on a surface of the tunneling oxide layer away from the N-type silicon substrate; wherein the surface of the polysilicon layer away from the tunneling oxide layer is the second surface, and the surface of the N-type silicon substrate on which the tunneling oxide layer is not formed is the first surface.

6. The preparation method according to claim 5, characterized in that The thickness of the polysilicon layer is in the range of 80-200 nm.

7. The preparation method according to claim 5, characterized in that The polysilicon layer is prepared at a temperature in a range of 550-650° C.; and / or the polysilicon layer is prepared at a pressure in a range of 10-100 mTorr.

8. The preparation method according to claim 1, characterized in that The first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer; Forming a first passivation film layer on the first surface, and forming a second passivation film layer on the second surface, comprising: forming the anti-ultraviolet attenuation film layer on the first surface; forming the first anti-reflection layer on a side of the anti-ultraviolet attenuation film layer away from the first surface; The second anti-reflection layer is formed on the second surface.

9. The preparation method according to claim 8, characterized in that The material of the anti-ultraviolet attenuation film layer includes aluminum oxide; and / or the material of the first anti-reflection layer includes silicon nitride; and / or the material of the second anti-reflection layer includes silicon nitride.

10. A solar cell, characterized in that: The solar cell is prepared by the method for preparing the solar cell according to any one of claims 1 to 9.

Images