LED chip and preparation method thereof
By using multiple etching and deposition of multi-layer hard film layers in the LED chip manufacturing process, the process complexity problems caused by multiple use and degluing treatment of photoresist layers in the prior art are solved, and the effect of process simplification and process complexity is achieved.
Patent Information
- Application Number
- CN202510250698.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2025-06-06
AI Technical Summary
In the existing LED chip manufacturing process, the patterned photoresist layer requires multiple use and degluing treatment, resulting in complicated process steps and increased process complexity.
By forming multi-layer structures on the hard film layer and using these hard film layers as multiple etching and deposition masks, the frequency of photoresist usage is reduced and the process steps are simplified.
Multiple utilization of the hard film layer is realized, which significantly reduces the frequency of photoresist usage, simplifies the preparation process steps of LED chips, and reduces the complexity of the process.
Smart Images
Figure CN120112013A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to an LED chip and a preparation method thereof. Background Art
[0002] At present, in the manufacturing process of LED chips, the patterned photoresist layer is used as a key mask for fine etching or precise deposition of functional film layers. However, this photoresist mask is usually used once and needs to be completely removed through a stripping process after completing its function. Since the manufacturing process of LED chips requires repeated photolithography steps many times, the process steps increase significantly, thereby increasing the complexity of the process. Summary of the invention
[0003] The purpose of the present invention is to overcome the deficiencies of the prior art. The present invention provides an LED chip and a method for preparing the same. By repeatedly utilizing the hard film layer, the steps of preparing the LED chip can be effectively simplified, thereby helping to reduce the complexity of the process.
[0004] The present invention provides a method for preparing an LED chip, comprising the following steps:
[0005] S1, depositing an initial hard film layer on the first patterned epitaxial layer;
[0006] S2, forming a first patterned photoresist layer having a cutting lane pattern on the original hard film layer;
[0007] S3, using the first patterned photoresist layer as a mask, etching the original hard film layer to obtain a first patterned hard film layer and a second patterned photoresist layer having the cutting lane pattern;
[0008] S4, using the second patterned photoresist layer and the first patterned hard film layer as masks, etching the first patterned epitaxial layer to obtain a second patterned epitaxial layer and a second patterned hard film layer having the cutting lane pattern;
[0009] S5, using the second patterned hard film layer as a mask, roughening the cutting lane pattern of the second patterned epitaxial layer;
[0010] S6, performing photolithography patterning processing on the second patterned hard film layer to obtain a third patterned hard film layer;
[0011] S7. Using the third patterned hard film layer as a mask, sequentially deposit an ITO film layer and a silver reflective structure on the second patterned epitaxial layer, and retain the third patterned hard film layer as a diffusion barrier layer for the ITO film layer and the silver reflective structure.
[0012] Specifically, the first patterned epitaxial layer is prepared by the following method:
[0013] An N-GaN layer, an MQW quantum well layer and a P-GaN layer are sequentially grown on a patterned sapphire substrate to form a primary epitaxial layer;
[0014] A plurality of N-type holes are etched in the original epitaxial layer to obtain the first patterned epitaxial layer; the N-type holes extend from the surface of the P-GaN layer into the N-GaN layer; the first patterned epitaxial layer is separated into a plurality of mesa structures based on the plurality of N-type holes.
[0015] Specifically, the original hard film layer is formed by stacking a first structural layer and a second structural layer in sequence, and the material of the first structural layer is SiO 2 、SiN x or TiO 2 The thickness of the first structural layer is in the range of 500 to 2000 nm; the material of the second structural layer is SiO 2 、SiN x 、TiO 2 or Al 2 O 3 , the thickness of the second structural layer ranges from 100 to 500 nm.
[0016] Specifically, the thickness ratio of the first structural layer to the second structural layer is in the range of 3:1 to 4:1.
[0017] Specifically, the material of the first patterned photoresist layer is positive photoresist, and the thickness of the first patterned photoresist layer is in the range of 3000 to 6000 nm.
[0018] Specifically, before step S2, the method further includes: spraying a tackifier on the original hard film layer; and / or
[0019] After step S2, the method further includes: baking the first patterned photoresist layer in an environment of 120-160° C. for 30-40 minutes.
[0020] Specifically, the thickness of the second patterned photoresist layer is in the range of 1000 to 3000 nm; and / or
[0021] The thickness of the second patterned hard film layer is in the range of 100 to 500 nm.
[0022] Specifically, the roughening process includes:
[0023] At 35 to 80° C., chemically roughening the cutting lane pattern of the second patterned epitaxial layer with a roughening solution for 5 to 40 seconds;
[0024] After the roughening is completed, the cutting lane pattern of the second patterned epitaxial layer is rinsed with water and then spin-dried.
[0025] Specifically, the diffusion barrier layer covers the sidewalls of the ITO film layer, the sidewalls of the silver reflective structure, and the inner walls of the plurality of N-type holes.
[0026] The present invention also provides an LED chip, and the LED chip is prepared by the LED chip preparation method.
[0027] Compared with the prior art, the present invention has the following beneficial effects:
[0028] In the method for preparing the LED chip of the present invention, the first patterned photoresist layer is completely consumed during the etching process of step S4, and no additional degumming process is required, which simplifies the steps of the preparation process of the LED chip and helps to reduce the complexity of the process;
[0029] In the preparation method of the LED chip of the present invention, the first patterned hard film layer formed by patterning the original hard film layer can be used as an etching mask for the first patterned epitaxial layer; the remaining part of the first patterned hard film layer after the first patterned epitaxial layer etching process, that is, the second patterned hard film layer, can be used as a protective mask during the roughening treatment of the cutting walkway pattern of the second patterned epitaxial layer; the second patterned hard film layer is subjected to photolithography patterning treatment, and the third patterned hard film layer obtained can be used as a deposition mask for the ITO film layer and the silver reflective structure; the third patterned hard film layer can also be retained as a diffusion barrier layer for the ITO film layer and the silver reflective structure; it can be seen that the preparation method of the present invention realizes multiple utilization of the hard film layer, which can significantly reduce the frequency of use of the photoresist, that is, reduce the process steps of coating, pre-baking, exposure, development, post-baking, and degumming of the photoresist, thereby effectively simplifying the preparation process steps of the LED chip, which is conducive to reducing the complexity of the process. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0031] Figure 1 is a schematic flow chart of a method for preparing an LED chip in an embodiment of the present invention;
[0032] Figure 2 is a schematic structural diagram of an original hard film layer in an embodiment of the present invention;
[0033] Figure 3 is a schematic structural diagram of the primary epitaxial layer in an embodiment of the present invention;
[0034] Figure 4 is a schematic structural diagram of a first patterned epitaxial layer in an embodiment of the present invention;
[0035] Figure 5 is a schematic structural diagram of a first patterned photoresist layer in an embodiment of the present invention;
[0036] Figure 6 is a schematic structural diagram of a first patterned hard film layer and a second patterned photoresist layer in an embodiment of the present invention;
[0037] Figure 7 is a schematic structural diagram of a second patterned epitaxial layer and a second patterned hard film layer in an embodiment of the present invention;
[0038] Figure 8 is a schematic structural diagram of a second patterned epitaxial layer after the cutting lane pattern is roughened in an embodiment of the present invention;
[0039] Fig. 9 is a schematic structural diagram of a third patterned hard film layer in an embodiment of the present invention;
[0040] Fig.10 Schematic diagram of the structure of the ITO film layer and the silver reflection structure in an embodiment of the present invention;
[0041] Fig.11 Schematic diagram of the structure of the LED chip in the embodiment of the present invention.
[0042] In the accompanying drawings, 2, patterned sapphire substrate; 10, original hard film layer; 11, first patterned hard film layer; 12, second patterned hard film layer; 13, third patterned hard film layer; 20, original epitaxial layer; 21, first patterned epitaxial layer; 22, second patterned epitaxial layer; 31, N-GaN layer; 32, MQW quantum well layer; 33, P-GaN layer; 41, N-type holes; 42, mesa structure; 51, first patterned photoresist layer; 52, second patterned photoresist layer; 61, ITO film layer; 62, silver reflection structure; 71, first passivation protection layer; 72, electrode connection layer; 73, second passivation protection layer; 74, electrode layer; 100, cutting walkway pattern. DETAILED DESCRIPTION
[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0044] The present invention provides a method for preparing an LED chip. Figure 1 The schematic diagram of the process of preparing the LED chip in the embodiment of the present invention is shown, which includes the following steps:
[0045] S1, depositing an initial hard film layer on the first patterned epitaxial layer;
[0046] Figure 2 The schematic diagram of the structure of the original hard film layer in the embodiment of the present invention is shown.
[0047] The texture of the original hard film layer 10 is harder than that of the cured photoresist, is not easily affected by temperature changes, has good structural stability, and is not easy to deform. This lays the physical foundation for the subsequent multiple use of the hard film layer and is also beneficial to improving the accuracy of the subsequent cutting aisle pattern 100 transfer.
[0048] Specifically, the original hard film layer 10 is deposited on the entire surface of the first patterned epitaxial layer 21 using plasma enhanced chemical vapor deposition (PECVD) technology, which is beneficial for the original hard film layer 10 to be well attached to the surface of the first patterned epitaxial layer 21 .
[0049] In some specific embodiments, the original hard film layer 10 is formed by sequentially stacking a first structural layer and a second structural layer, which is beneficial to improving the structural stability of the original hard film layer 10 .
[0050] Specifically, the material of the first structural layer is SiO 2 、SiN x or TiO 2 The material of the second structural layer is SiO 2 、SiN x 、TiO 2 or Al 2 O 3 , these materials can meet the hardness requirements of the original hard film layer 10; preferably, the material of the first structural layer is SiO 2 , the material of the second structural layer is SiN x , SiO 2 and SiN x The combination has good insulation and high density.
[0051] SiO 2 The preparation process of the first structural layer of the material is as follows: depositing SiO 2 The source gas used is SiH 4 and N 2 O, and pass into N 2 As carrier gas; among them, SiH 4 The gas flow rate is controlled to 5~25sccm, SiH4 With N 2 The gas flow ratio of O is controlled at 1:70-1:90, the deposition power is controlled at 70-300 W, and the deposition temperature is controlled at 250-320° C. This is conducive to ensuring that the first structure layer formed has good density.
[0052] SiN x The preparation process of the second structural layer of the material is as follows: depositing SiN x The source gas used is SiH 4 and NH 3 , and pass into N 2 As carrier gas; among them, SiH 4 The gas flow rate is controlled to 5~50sccm, SiH 4 With NH 3 The gas flow ratio is controlled at 1:1-3:1, the deposition power is controlled at 50-150W, and the deposition temperature is controlled at 250-320°C. This is conducive to ensuring that the second structural layer formed has good density.
[0053] Furthermore, the thickness of the first structural layer is in the range of 500-2000 nm, and the thickness of the second structural layer is in the range of 100-500 nm. The combination of the thick first structural layer and the thin second structural layer is beneficial to reducing the internal stress of the original hard film layer 10. Among them, the thickness ratio of the first structural layer to the second structural layer is in the range of 3:1-4:1, which ensures that the thickness of the first structural layer is dominant, and has a positive effect on improving the structural stability of the original hard film layer 10.
[0054] In some specific embodiments, the first patterned epitaxial layer 21 is made by the following method:
[0055] Figure 3 A schematic diagram of the structure of the primary epitaxial layer in an embodiment of the present invention is shown.
[0056] An N-GaN layer 31, an MQW quantum well layer 32 and a P-GaN layer 33 are sequentially grown on a patterned sapphire substrate 2 to form a primary epitaxial layer 20;
[0057] Figure 4 A schematic structural diagram of the first patterned epitaxial layer in an embodiment of the present invention is shown.
[0058] A plurality of N-type holes 41 are etched in the original epitaxial layer 20 to obtain the first patterned epitaxial layer 21; the N-type holes 41 extend from the surface of the P-GaN layer 33 to the inside of the N-GaN layer 31, and the depth of the N-type holes 41 ranges from 700 to 1300 nm; the first patterned epitaxial layer 21 is separated into a plurality of mesa structures 42 based on the plurality of N-type holes 41.
[0059] The structure of the first patterned epitaxial layer 21 is existing, and lays a foundation for the subsequent etching of the cutting lanes.
[0060] S2, forming a first patterned photoresist layer having a cutting lane pattern on the original hard film layer;
[0061] Figure 5 A schematic structural diagram of a first patterned photoresist layer in an embodiment of the present invention is shown.
[0062] The material of the first patterned photoresist layer 51 is positive photoresist, which has good development contrast and is beneficial to improving the resolution of the cutting aisle pattern 100; the thickness of the first patterned photoresist layer 51 ranges from 3000 to 6000 nm, which can provide sufficient etching margin to avoid the risk of penetration.
[0063] The preparation process of the first patterned photoresist layer 51 is as follows: coating photoresist on the original hard film layer 10 (before coating the photoresist, a tackifier may be sprayed on the original hard film layer 10 to increase the surface viscosity between the original hard film layer 10 and the photoresist), exposing and developing to form a cutting lane pattern 100 of the core particle - obtaining the first patterned photoresist layer 51, and after development, baking the first patterned photoresist layer 51 in an environment of 120 to 160° C. for 30 to 40 minutes, which is beneficial to improving the etching resistance of the first patterned photoresist layer 51; in addition, the angle range of the cutting lane pattern 100 of the first patterned photoresist layer 51 after baking is 60 to 90°.
[0064] S3, using the first patterned photoresist layer as a mask, etching the original hard film layer to obtain a first patterned hard film layer and a second patterned photoresist layer having the cutting lane pattern;
[0065] Figure 6 A schematic structural diagram of a first patterned hard film layer and a second patterned photoresist layer in an embodiment of the present invention is shown.
[0066] By using the first patterned photoresist layer 51 as a mask and adopting inductively coupled plasma etching technology (ICP) to etch the original hard film layer 10, the cutting lane pattern 100 can be transferred to the original hard film layer 10; the etching process is relatively short, which can ensure that the pattern and angle of the first patterned photoresist layer 51 are complete and will not be deformed during the etching process, so that the pattern and angle of the first patterned photoresist layer 51 are more completely transferred to the original hard film layer 10, forming a first patterned hard film layer 11 with a cutting lane pattern 100; the thickness of the first patterned photoresist layer 51 will be lost during the etching process, thereby forming a second patterned photoresist layer 52, and the second patterned photoresist layer 52 still has the cutting lane pattern 100.
[0067] Specifically, pass CF 4 and O 2 The original hard film layer 10 is etched, CF 4 The gas flow rate is controlled at 50~180sccm, CF 4 and O 2 The gas flow ratio is controlled at 8:1 to 16:1, the power is controlled at 100 to 300 W, the etching selectivity ratio of the first patterned photoresist layer 51 to the original hard film layer 10 is controlled at 1:1 to 3:1, and the remaining thickness of the first patterned photoresist layer 51 after etching is M 1 , that is, the thickness of the second patterned photoresist layer 52 is M 1 , 1000nm≤M 1 ≤3000nm; the second patterned photoresist layer 52 can provide a buffer for the first patterned hard film layer 11 when the first patterned epitaxial layer 21 is subsequently etched.
[0068] S4, using the second patterned photoresist layer and the first patterned hard film layer as masks, etching the first patterned epitaxial layer to obtain a second patterned epitaxial layer and a second patterned hard film layer having the cutting lane pattern;
[0069] Figure 7 A schematic structural diagram of a second patterned epitaxial layer and a second patterned hard film layer in an embodiment of the present invention is shown.
[0070] By using the second patterned photoresist layer 52 and the first patterned hard film layer 11 as masks and adopting inductively coupled plasma etching technology (ICP) to etch the first patterned epitaxial layer 21, the cutting lane pattern 100 can be transferred to the first patterned epitaxial layer 21; this etching process takes a relatively long time, and the second patterned photoresist layer 52 that acts as a buffer will be completely etched away, without the need for an additional de-gumming process; and the first patterned hard film layer 11 is not easily affected by changes in the etching temperature environment, and even a long etching process can effectively maintain the stability of the pattern and angle, so that the cutting lane pattern 100 can be accurately transferred to the first patterned epitaxial layer 21.
[0071] The obtained second patterned epitaxial layer 22 having the cutting lane pattern 100 has a large angle, a smooth edge and high definition.
[0072] Specifically, Cl 2 and BCl 3 The first patterned epitaxial layer 21 is etched. 2 The gas flow rate is controlled at 80-200 sccm, Cl 2 and BCl3 The gas flow ratio is controlled at 8:1 to 30:1, the power is controlled at 80 to 320 W, the etching selectivity ratio of the second patterned photoresist layer 52 to the first patterned epitaxial layer 21 is controlled at 1:1 to 2:1, the etching selectivity ratio of the first patterned hard film layer 11 to the first patterned epitaxial layer 21 is controlled at 1:3 to 1:1, and the remaining thickness of the first patterned hard film layer 11 after etching is M 2 , that is, the thickness of the second patterned hard film layer 12 is M 2 , 100nm≤M 2 ≤500nm; the second patterned hard film layer 12 can act as a protective mask in the subsequent roughening process to prevent the area outside the cutting aisle pattern 100 from being roughened, which is beneficial to ensure the front light emitting effect of the LED chip.
[0073] The second patterned epitaxial layer 22 having a cutting lane pattern 100 is formed with a plurality of cutting lanes. The cutting lane structure is an existing structure extending from the surface of the P-GaN layer 33 to the surface of the patterned sapphire substrate 2. The plurality of cutting lanes separate the epitaxial layer to form a plurality of basic core particles.
[0074] S5, using the second patterned hard film layer as a mask, roughening the cutting lane pattern of the second patterned epitaxial layer;
[0075] Figure 8 A schematic diagram of the structure of the second patterned epitaxial layer after the cutting lane pattern is roughened in an embodiment of the present invention is shown.
[0076] The second patterned hard film layer 12 is used as a protective mask during the roughening of the cutting walkway pattern 100 of the second patterned epitaxial layer 22. There is no need to re-make the protective mask with photoresist, which reduces the process steps of photoresist coating, pre-baking, exposure, development, post-baking, and stripping, thereby effectively simplifying the preparation process steps of the LED chip and helping to reduce the complexity of the process.
[0077] After the cutting lane pattern 100 of the second patterned epitaxial layer 22 is roughened (ie, the sidewalls of the epitaxial layer exposed at the cutting lanes are roughened), the total reflection of light by the sidewall surface of the basic core particle can be reduced, thereby facilitating further improving the light extraction efficiency of the LED chip.
[0078] Specifically, at a temperature of 35 to 80° C., the cutting path pattern 100 of the second patterned epitaxial layer 22 is chemically roughened for 5 to 40 seconds using a roughening liquid, so that the cutting path pattern 100 of the second patterned epitaxial layer 22 is effectively roughened and excessive roughening is avoided; wherein the roughening liquid mainly comprises KOH, H 2 O 2and DI water, which has a good roughening effect on the epitaxial layer of gallium nitride. After the roughening is completed, the cutting lane pattern 100 of the second patterned epitaxial layer 22 is rinsed with water and spin-dried.
[0079] S6, performing photolithography patterning processing on the second patterned hard film layer to obtain a third patterned hard film layer;
[0080] Fig. 9 A schematic structural diagram of a third patterned hard film layer in an embodiment of the present invention is shown.
[0081] Specifically, the photolithography patterning process of the second patterned hard film layer 12 includes: using a photoresist as a mask, etching the second patterned hard film layer 12 using a 16:1 BOE solution, removing part of the second patterned hard film layer 12 on the top of the base core particle, retaining the second patterned hard film layer 12 inside the N-type hole 41 and on both sides of the top, and also retaining the second patterned hard film layer 12 on both sides of the top of the cutting path of the second patterned epitaxial layer 22 as the third patterned hard film layer 13; the third patterned hard film layer 13 can be used as a deposition mask for subsequently depositing an ITO film layer 61 and a silver reflective structure 62 on the second patterned epitaxial layer 22 in sequence.
[0082] S7, using the third patterned hard film layer as a mask, sequentially depositing an ITO film layer and a silver reflective structure on the second patterned epitaxial layer, and retaining the third patterned hard film layer as a diffusion barrier layer for the ITO film layer and the silver reflective structure;
[0083] Fig.10 A schematic structural diagram of an ITO film layer and a silver reflective structure in an embodiment of the present invention is shown.
[0084] The thickness of the ITO film layer 61 is in the range of 10 to 60 nm. Annealing the ITO film layer 61 after forming it can effectively increase the current diffusion capacity of the ITO film layer 61. The silver reflective structure 62 is composed of various metals such as Ag, Ni, Ti, W, Pt, and Cu, and has a thickness of 500 to 1000 nm.
[0085] The third patterned hard film layer 13 can not only serve as a deposition mask for the ITO film layer 61 and the silver reflective structure 62, but also serve as a diffusion barrier layer for the ITO film layer 61 and the silver reflective structure 62. Specifically, the diffusion barrier layer covers the side walls of the ITO film layer 61, the side walls of the silver reflective structure 62, and the inner walls of the plurality of N-type holes 41, which can prevent the metal components in the ITO film layer 61 and the silver reflective structure 62 from migrating to both sides at high temperatures, which is beneficial to improving the yield of the LED chip.
[0086] Fig.11The schematic diagram of the structure of the LED chip in the embodiment of the present invention is shown.
[0087] After step S7, conventional technical means may be used to further fabricate the functional film layers (the first passivation protection layer 71, the electrode connection layer 72, the second passivation protection layer 73, and the electrode layer 74).
[0088] Specifically, PECVD or physical vapor deposition (PVD) technology is used to deposit and form the first passivation protection layer 71; a through hole in contact with the P-GaN layer 33 and the N-GaN layer 31 is formed by photolithography and etching processes, and a metal contact is formed with the P-GaN layer 33 and the N-GaN layer 31 through the electrode connection layer 72; a second passivation protection layer 73 is formed by PECVD or PVD deposition; a through hole in contact with the electrode connection layer 72 is formed by photolithography and etching processes, and an electrode layer 74 is manufactured on the surface of the second passivation protection layer 73 by electron beam evaporation technology.
[0089] Furthermore, the first passivation protection layer 71 is made of SiO 2 、SiN x The first passivation protection layer 71 has a thickness ranging from 500 to 800 nm; the electrode connection layer 72 is composed of a plurality of Cr, Ti, Ni, Al, Pt, and Cu; the second passivation protection layer 73 is composed of SiO 2 、SiN x The second passivation protection layer 73 is composed of one or two of the following: the thickness range of the second passivation protection layer 73 is 700-1500nm; the electrode layer 74 is composed of Cr, Ti, Ni, Pt, AuSn, etc., and the thickness range of the electrode layer 74 is 3500-5000nm.
[0090] After the production of each functional film layer is completed, independent and complete core particles are obtained after subsequent grinding, cutting, testing and sorting.
[0091] In the method for preparing the LED chip of the present invention, the first patterned photoresist layer 51 will be completely consumed during the etching process, and there is no need to perform an additional degumming process, which simplifies the steps of the preparation process of the LED chip and helps to reduce the complexity of the process. Moreover, in the method for preparing the LED chip of the present invention, the first patterned hard film layer 11 formed by patterning the original hard film layer 10 can be used as an etching mask for the first patterned epitaxial layer 21; the remaining portion of the first patterned hard film layer 11 after the first patterned epitaxial layer 21 has undergone the etching process, that is, the second patterned hard film layer 12, can be used as a protective mask during the roughening of the cutting walkway pattern 100 of the second patterned epitaxial layer 22; the second patterned hard film layer 12 is subjected to a photolithography patterning process, and the third patterned hard film layer 13 obtained can be used as an ITO film layer 61 and a silver reflective structure 6 2; the third patterned hard film layer 13 can also be retained as a diffusion barrier layer for the ITO film layer 61 and the silver reflective structure 62, which can prevent the metal components in the ITO film layer 61 and the silver reflective structure 62 from migrating to both sides at high temperature, which is beneficial to improving the yield of the LED chip; it can be seen that the preparation method of the present invention realizes the multiple use of the hard film layer, which can significantly reduce the frequency of use of the photoresist, that is, reduces the process steps of photoresist coating, pre-baking, exposure, development, post-baking, and degumming, thereby effectively simplifying the preparation process steps of the LED chip, which is beneficial to reducing the complexity of the process.
[0092] Moreover, in the preparation method of the LED chip of the present invention, by using a combination of a photoresist and a hard film layer as a double etching mask for forming a cutting walkway of the epitaxial layer, the pattern and angle of the photoresist can be accurately transferred to the epitaxial layer, which is beneficial to improving the etching angle of the cutting walkway and reducing the problems of a smaller etching angle and uneven walkway edge caused by deformation of the photoresist mask during the etching process, thereby achieving the purpose of reducing the area loss of the light-emitting area.
[0093] In addition, the side walls of the epitaxial layer exposed at the cutting path are roughened, which can reduce the total reflection of light by the side wall surface of the core particle, thereby facilitating further improving the light extraction efficiency of the LED chip.
[0094] The present invention also provides an LED chip, which is manufactured by the LED chip manufacturing method and has high light extraction efficiency and high yield rate.
[0095] The above is a detailed introduction to an LED chip and a preparation method thereof provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A method for preparing an LED chip, characterized in that: The following steps are involved: S1, depositing an initial hard film layer on the first patterned epitaxial layer; S2, forming a first patterned photoresist layer having a cutting lane pattern on the original hard film layer; S3, using the first patterned photoresist layer as a mask, etching the original hard film layer to obtain a first patterned hard film layer and a second patterned photoresist layer having the cutting lane pattern; S4, using the second patterned photoresist layer and the first patterned hard film layer as masks, etching the first patterned epitaxial layer to obtain a second patterned epitaxial layer and a second patterned hard film layer having the cutting lane pattern; S5, using the second patterned hard film layer as a mask, roughening the cutting lane pattern of the second patterned epitaxial layer; S6, performing photolithography patterning processing on the second patterned hard film layer to obtain a third patterned hard film layer; S7. Using the third patterned hard film layer as a mask, sequentially deposit an ITO film layer and a silver reflective structure on the second patterned epitaxial layer, and retain the third patterned hard film layer as a diffusion barrier layer for the ITO film layer and the silver reflective structure.
2. The method for preparing an LED chip according to claim 1, wherein: The first patterned epitaxial layer is prepared by the following method: An N-GaN layer, an MQW quantum well layer and a P-GaN layer are sequentially grown on a patterned sapphire substrate to form a primary epitaxial layer; Etching a plurality of N-type holes in the original epitaxial layer to obtain the first patterned epitaxial layer; the N-type holes extend from the surface of the P-GaN layer to the N-GaN layer; The first patterned epitaxial layer is divided into a plurality of mesa structures based on the plurality of N-type holes.
3. The method for preparing an LED chip according to claim 1, wherein: The original hard film layer is formed by stacking a first structural layer and a second structural layer in sequence, and the material of the first structural layer is SiO2, SiN x or TiO2, the thickness of the first structural layer is in the range of 500 to 2000 nm; the material of the second structural layer is SiO2, SiN x , TiO2 or Al2O3, and the thickness of the second structural layer ranges from 100 to 500 nm.
4. The method for preparing an LED chip according to claim 3, characterized in that: The thickness ratio of the first structural layer to the second structural layer is in a range of 3:1 to 4:
1.
5. The method for preparing an LED chip according to claim 1, wherein: The material of the first patterned photoresist layer is positive photoresist, and the thickness of the first patterned photoresist layer ranges from 3000 to 6000 nm.
6. The method for preparing an LED chip according to claim 1, wherein: Before step S2, the method further includes: spraying a tackifier on the original hard film layer; and / or After step S2, the method further includes: baking the first patterned photoresist layer in an environment of 120-160° C. for 30-40 minutes.
7. The method for preparing an LED chip according to claim 1, wherein: The thickness of the second patterned photoresist layer is in the range of 1000 to 3000 nm; and / or The thickness of the second patterned hard film layer is in the range of 100 to 500 nm.
8. The method for preparing an LED chip according to claim 1, wherein: The roughening process comprises: At 35 to 80° C., chemically roughening the cutting lane pattern of the second patterned epitaxial layer with a roughening solution for 5 to 40 seconds; After the roughening is completed, the cutting lane pattern of the second patterned epitaxial layer is rinsed with water and then spin-dried.
9. The method for preparing an LED chip according to claim 2, wherein: The diffusion barrier layer covers the side wall of the ITO film layer, the side wall of the silver reflective structure and the inner walls of the plurality of N-type holes.
10. An LED chip, characterized in that: The LED chip is manufactured by the method for manufacturing an LED chip according to any one of claims 1 to 9.