Capacitive micromachined ultrasonic transducer array on printed circuit board

Abstract

A capacitive micromachined ultrasonic transducer (CMUT) may be fabricated on a prefabricated and interconnected substrate, such as a printed circuit board (PCB). The PCB may be rigid or flexible. The substrate may also be ceramic. The CMUT may be polymer-based or silicon-based. An array of CMUTs may also be fabricated, where the array is fabricated from CMUT elements, and where each CMUT element is fabricated from a single CMUT cell. CMUT elements on a substrate, such as a PCB, may be electrically connected to electrical interconnects (vias), respectively, allowing selective control of individual elements. The CMUT may be fabricated by various deposition, patterning, and etching away materials on the substrate, where the solvent used for etching is selected to be chemically compatible with the substrate and other materials deposited on the substrate.

Description

Technical Field

[0001] The present application relates generally to capacitive micromachined ultrasound transducer arrays, and more particularly to methods of manufacturing those transducer arrays using prefabricated and interconnected substrates, such as printed circuit boards (PCBs). Background Art

[0002] Ultrasound systems have traditionally used piezoelectric materials as their transducers since the 1930s. Materials such as piezoelectric crystals (e.g., quartz), ceramics (e.g., lead zirconate titanate [PZT]), and polymers (e.g., polyvinylidene fluoride [PVDF]) are known transducer materials [1]. Despite the fact that piezoelectric transducer technology is mature, it has many disadvantages, such as technical challenges in manufacturing large two-dimensional arrays due to chip-level interconnects and integration challenges [1].

[0003] Acoustic impedance (the speed of sound in a material multiplied by its density, measured in Rayleighs) is a measure of the opposition a system exhibits to the acoustic pressure applied to the system. It is an important quantity in piezoelectric-based ultrasound systems because it determines how much acoustic power is effectively delivered to the target material being imaged. "Acoustic matching layers" are mandatory structures in piezoelectric-based systems that are used to reduce the impedance mismatch between the impedance of the piezoelectric crystal and the lower or higher impedance of the target material (e.g., tissue or metal). These matching layers are typically made of a high-density rubber combined with a liquid gel and are located between the crystal and the target material.

[0004] Capacitive micromachined ultrasonic transducers (CMUTs) are an alternative technology to current piezoelectric-based transducers [1]. A CMUT is essentially a parallel plate capacitor with electrodes at the bottom fixed to a substrate and a membrane suspended above the cavity and sealed along its edges. Metal electrodes are patterned on top of the suspended membrane. Ultrasonic waves are generated by the CMUT when an AC signal superimposed on a DC voltage is applied across the electrodes. Ultrasonic waves can be detected by measuring the change in capacitance of the device when a DC voltage is applied in the presence of incoming ultrasound. Most CMUTs are made of silicon-based materials on a silicon substrate. However, silicon has a higher acoustic impedance than soft tissue and a lower acoustic impedance than metals or composites, so even with a CMUT, there is still an acoustic mismatch.

[0005] U.S. Patent Nos. 10,509,013, 10,564,132, and 10,598,632 describe microfabrication of ultrasonic transducers using polymer membranes, all of which are hereby incorporated by reference in their entirety. These polymer-based CMUTs (polyCMUTs) can operate using lower operating voltages than piezoelectric transducers or silicon-based CMUTs in at least some cases.

[0006] U.S. Patents Nos. 10,509,013, 10,564,132, and 10,598,632 collectively describe two ways of micromachining a CMUT: surface micromachining and wafer bonding. In surface micromachining, the cavity beneath the membrane is formed by depositing or growing a sacrificial layer on a carrier substrate. After membrane deposition, the sacrificial layer is removed with an etchant that is specifically selected to dissolve the sacrificial material via etching channels without damaging the membrane material. In wafer bonding, the membrane and cavity are defined on separate wafers that are bonded together under vacuum conditions. Since etching channels are not required, the manufacturing process is simplified and higher fill factors can be achieved.

[0007] Silicon nitride and polysilicon are the most common materials used to make CMUT membranes, while chromium and aluminum are often used to pattern electrodes on top of these membranes. These materials are chosen primarily for their mechanical properties, allowing the membrane to be as thin as possible in order to minimize the effective gap between the bottom electrode and the top (or "hot") electrode. By reducing the effective gap between the electrodes, the electric field can be increased, and the impedance match to the electronics driving the CMUT can be improved. Once the desired operating frequency and maximum bias voltage have been confirmed, the CMUT membrane is preferably designed to be as thick as possible, given that the bandwidth of the CMUT membrane increases linearly with thickness.

[0008] Through Silicon Vias (TSVs) are vertical electrical interconnects that pass through a silicon wafer or chip to connect circuits at different layers. TSVs are used to achieve better performance, smaller form factors, and higher integration of semiconductor devices. They offer several advantages, including reduced signal propagation delays, increased bandwidth, and the ability to connect multiple chip layers in a compact manner. The main limitation of TSVs is that they only allow communication between opposite sides (front and back) of a substrate through vertical conductive channels.

[0009] Printed circuit boards (PCBs) can facilitate routing in different layers through the use of vias and multi-layer construction. Vias pass through the entire thickness of the PCB, connecting all layers. They are often used for components and traces that require strong connections. Blind and buried vias connect only specific layers of the PCB. Blind vias connect an outer layer to one or more inner layers, while buried vias connect two or more inner layers. Both types of vias allow for more complex routing without affecting the outer layers. Modern PCBs often consist of multiple layers of copper traces separated by insulating material in the form of the PCB substrate. Inner layers are sandwiched between outer layers. Each layer can be used for routing, power planes, or ground planes.

[0010] PCBs can be manufactured using materials such as FR-4 (glass-reinforced epoxy), high Tg materials for elevated temperatures, flexible materials like polyimide and polyester, rigid-flex materials that combine rigidity with flexibility, metal core materials for improved heat dissipation, ceramic materials for high temperature stability, RF / microwave materials for high-frequency applications, and materials like Teflon for specific performance requirements. TM (PTFE). The choice depends on factors such as application, thermal management, operating frequency, and desired electrical and mechanical properties.

[0011] Low temperature co-fired ceramic (or LTCC) is a ceramic electronic technology used in ceramic PCB or PCBA (i.e., PCB assembly where all components are on the PCB) manufacturing. LTCC, which evolved from HTCC (high temperature co-fired ceramic) technology in 1982, is a multi-layer low temperature ceramic PCB manufacturing technology. HTCC is based on alumina (Al 2 O 3 ) and aluminum nitride (AlN). LTCC is a ceramic in which glass is mixed in alumina, and is also generally referred to as "glass ceramic". HTCC substrates are cured at 1500°C or higher. In order to cure at high temperatures, tungsten (W) and molybdenum (Mo) having high melting points are used for circuit electrodes. For LTCC substrates, the curing temperature can be lowered to 900°C by mixing glass into alumina ceramics. Therefore, silver or copper with low conductivity can be used for wiring.

[0012] PCBs made with FR-4 utilize a composite material of glass fibers and epoxy to provide moderate electrical insulation and mechanical strength suitable for standard electronic devices. FR-4 is versatile and cost-effective for general-purpose electronic devices and can be manufactured by a large number of manufacturing facilities around the world. In contrast, PCBs made with LTCC involve laminating ceramic strips with embedded conductors, resulting in excellent electrical performance, high thermal stability, and suitability for high-frequency and high-temperature applications, making them ideal for RF modules, microwave devices, and sensors in harsh environments. Summary of the invention

[0013] According to one aspect of the present disclosure, a method for manufacturing a capacitive micromachined ultrasonic transducer is provided, the method comprising: removing a layer from a top surface of a substrate, wherein at least one pair of electrical interconnects extend at least partially through the substrate and are exposed on the top surface; after the removal, depositing a first conductive material on the top surface, wherein the first conductive material covers the pair of electrical interconnects; patterning the first conductive material to form a bottom electrode and a contact area for a top electrode, wherein the bottom electrode is electrically connected to one of the pair of electrical interconnects and the contact area for the top electrode is electrically connected to the other of the pair of electrical interconnects; After ionization, a sacrificial material is deposited on the bottom electrode; the sacrificial material is patterned to form a sacrificial membrane area connected to at least one sacrificial etch channel; after the sacrificial material is patterned, a first polymer or silicon layer is deposited on the substrate, the bottom electrode, the contact area and the sacrificial material; the first polymer or silicon layer is patterned to form at least one via leading to at least one sacrificial etch channel; a second conductive material is deposited on the first polymer or silicon layer and on the contact area for the top electrode; the second conductive material is patterned to avoid electrical connection with the bottom electrode; and the sacrificial membrane area is etched away using the at least one via.

[0014] After the sacrificial material is patterned, a first polymer layer may be deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material, and the method may further include: depositing a second polymer layer on top of the second conductive material and the sacrificial film area; and patterning the second polymer layer to avoid blocking at least one via. Alternatively, after the sacrificial material is patterned, a silicon layer may be deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material.

[0015] The substrate may include a printed circuit board. The printed circuit board may be flexible.

[0016] The substrate may include ceramic.

[0017] Removing the layer may be performed mechanically. For example, removing the layer may include polishing or grinding the top surface of the substrate.

[0018] Removing the layer may be accomplished chemically. For example, removing the layer may include etching the top surface of the substrate.

[0019] Prior to removing the layer, pads of the conductive material may be electrically coupled to the pair of electrical interconnects, respectively, on the top surface, and removing the layer may include removing portions of the pads and the substrate.

[0020] After removal, the surface roughness of the top surface may be no greater than 50 nanometers.

[0021] The first conductive material may include a gold layer between two chromium layers.

[0022] The thickness of the first conductive material may be approximately 100 nm.

[0023] The sacrificial material may be approximately 200 nm thick.

[0024] Depositing the sacrificial material may include depositing a lift-off resist layer and then depositing a positive photoresist layer.

[0025] Patterning the sacrificial material may be performed by wet etching using an aqueous solution including tetramethylammonium hydroxide.

[0026] The first polymer layer may be approximately 700 nm thick.

[0027] Depositing the second electrically conductive material may include depositing a titanium layer and then depositing a gold layer.

[0028] The method may further include encapsulating the transducer with an encapsulation material.

[0029] The bottom surface of the substrate may include pads of conductive material electrically coupled to the pair of electrical interconnects, respectively, and the method may further include covering the pads on the bottom surface before packaging the transducer to prevent the pads from being covered by the packaging material.

[0030] The method may further include, after removing the layer of the top surface and before depositing the first conductive material: depositing a planarization layer on the top surface; and patterning the planarization layer such that the electrical interconnect remains exposed on the top surface.

[0031] The planarization layer may be approximately 1 μm thick.

[0032] The planarization layer may include SU-8 photoresist.

[0033] The roughness of the planarization layer may be no greater than 50 nanometers.

[0034] The method may also include, before removing the layer from the top surface of the substrate: depositing a substrate conductive material on the surface of the substrate; patterning the substrate conductive material to form a substrate conductive region for a bottom electrode and a substrate conductive region for a top electrode, wherein the substrate conductive region for the bottom electrode is electrically connected to one of the pair of electrical interconnects and the other of the substrate conductive region is electrically connected to the other of the pair of electrical interconnects; and depositing a planarization layer on the substrate and the substrate conductive region; wherein the substrate conductive region and the contact region for the bottom electrode are electrically connected to the same electrical interconnect and the substrate conductive region and the contact region for the top electrode are electrically connected to the same electrical interconnect, and wherein the layer removed from the top surface of the substrate includes the planarization layer above the substrate conductive material.

[0035] The planarization layer may include epoxy.

[0036] The thickness of the planarization layer may be equal to or greater than the thickness of the substrate conductive material.

[0037] The method may further include degassing the planarization layer after depositing the planarization layer and before removing the layer from the top surface of the substrate.

[0038] The planarization layer may include a solder resist layer of a printed circuit board.

[0039] The layer removed from the top surface of the substrate may include an upper substrate layer adhered to the substrate. Between the substrate and the upper substrate layer may be a substrate conductive region for a bottom electrode and a substrate conductive region for a top electrode, wherein the substrate conductive region for the bottom electrode is electrically connected to one of the pair of electrical interconnects and the other of the substrate conductive region is electrically connected to the other of the pair of electrical interconnects. The substrate conductive region and the contact region for the bottom electrode may be electrically connected to the same electrical interconnect, and the substrate conductive region and the contact region for the top electrode may be electrically connected to the same electrical interconnect.

[0040] The electrical interconnects may extend non-linearly through the substrate.

[0041] The capacitive micromachined ultrasonic transducer may be one of an array of capacitive micromachined ultrasonic transducers simultaneously fabricated by the method.

[0042] According to another aspect of the present disclosure, a capacitive micromachined ultrasonic transducer assembly is provided, comprising: a printed circuit board (PCB), comprising at least one pair of electrical interconnects, the at least one pair of electrical interconnects extending at least partially through the PCB and exposed on a top surface of the PCB; a capacitive micromachined ultrasonic transducer unit on the PCB, wherein the capacitive micromachined ultrasonic transducer unit comprises: a bottom electrode, electrically connected to one of the pair of electrical interconnects on the top surface; a top electrode, electrically connected to the other of the pair of electrical interconnects on the top surface; a polymer or silicon layer, between the top electrode and the bottom electrode; and a sealed cavity, between the polymer or silicon layer and the bottom electrode.

[0043] The PCB may be flexible.Alternatively, the PCB may comprise ceramic.

[0044] The bottom electrode may be directly on the PCB. Alternatively, the bottom electrode may be on a planarization layer.

[0045] The bottom electrode may be on a planarization layer, and the planarization layer may include a solder resist layer.

[0046] The bottom electrode may be coplanar with a portion of a layer of the PCB.

[0047] The bottom electrode may be coplanar with a portion of the planarization layer.

[0048] The bottom electrode may be coplanar with a bottom portion of the polymer or silicon layer.

[0049] The capacitive micromachined ultrasonic transducer unit may be one of an array of capacitive micromachined ultrasonic transducer units. The array may include capacitive micromachined ultrasonic transducer elements corresponding to different groups selected from a plurality of capacitive micromachined ultrasonic transducer units, and the capacitive micromachined ultrasonic transducer elements may be electrically connected to the electrical interconnects, respectively.

[0050] A polymer layer may be between the top electrode and the bottom electrode. Alternatively, a silicon layer may be between the top electrode and the bottom electrode.

[0051] The electrical interconnects may extend non-linearly through the substrate.

[0052] According to another aspect of the present disclosure, a device is provided that includes a printed circuit board with exposed interconnects and a polymer-based capacitive micromachined ultrasonic structure having connectors positioned on the exposed interconnects of the printed circuit board.

[0053] Printed circuit boards can have a roughness of less than one micron.

[0054] Polymer-based capacitive micromachined ultrasonic structures can be transducers.

[0055] Polymer-based capacitive micromachined ultrasonic structures can be sensors.

[0056] Polymer-based capacitive micromachined ultrasonic structures can be receivers.

[0057] The printed circuit board may include a layer of polishable material.

[0058] The layer of polishable material may be polished to achieve a roughness of less than one micron.

[0059] According to another aspect of the present disclosure, a method is provided, the method comprising: obtaining a printed circuit board having a bottom electrode thereon, wherein the bottom electrode is positioned so that the bottom electrode is electrically coupled to a first via of the printed circuit board; depositing a sacrificial layer on top of the bottom electrode; depositing a first polymer layer on top of the sacrificial layer; depositing a top electrode on top of the first polymer layer, wherein the top electrode is deposited so that the top electrode is electrically coupled to a second via of the printed circuit board; depositing a second polymer layer on top of the top electrode; removing the sacrificial layer to obtain a cavity; and encapsulating the bottom electrode, the first polymer layer, the top electrode, the second polymer material, and the cavity in an encapsulation material on the printed circuit board. The selection of materials for the printed circuit board can be selected based on factors such as the intended application, budget, performance requirements, and manufacturing processes. Exemplary materials include FR-4 (flame retardant 4), high Tg (glass transition temperature) materials, flexible materials (e.g., polyimide and polyester fibers), rigid-flex materials from Rigiflex Technology Inc., metal core materials (MCPCB), ceramic materials, and RF / microwave materials with low dielectric constants.

[0060] Obtaining the printed circuit board having the bottom electrode thereon may include depositing the bottom electrode on the printed circuit board.

[0061] The method may further include polishing the printed circuit board prior to depositing the bottom electrode.

[0062] Printed circuit boards can be polished to a roughness of less than one micron.

[0063] The method may further include depositing a planarization layer between the printed circuit board and the bottom electrode.

[0064] The method may further include depositing a planarization layer on the bottom electrode.

[0065] The method may further include polishing the planarization layer before depositing the sacrificial layer to obtain a polished surface of the bottom electrode.

[0066] Obtaining a printed circuit board having a bottom electrode thereon may include patterning the bottom electrode in an inner layer of the printed circuit board, and the method may further include grinding and polishing the printed circuit board before depositing the sacrificial layer to obtain a polished surface of the bottom electrode.

[0067] According to another aspect of the present disclosure, a device manufactured according to the above method is provided.

[0068] According to another aspect of the present disclosure, there is provided a device comprising: a printed circuit board including a polished surface and a pair of vias extending through the polished surface; and a polymer-based capacitive micromachined ultrasonic structure located on the polished surface and including a top electrode and a bottom electrode, wherein the top electrode is electrically coupled to one of the vias and the bottom electrode is electrically coupled to the other of the vias.

[0069] According to another aspect of the present disclosure, there is provided a device comprising: a printed circuit board, fabricated using low temperature co-fired ceramic (LTCC) or high temperature co-fired ceramic (HTCC) technology, comprising a polished surface and a pair of vias extending through the polished surface; and a silicon-based capacitive micromachined ultrasonic structure, located on the polished surface and comprising a top electrode and a bottom electrode, wherein the top electrode is electrically coupled to one of the vias and the bottom electrode is electrically coupled to the other of the vias. LTCC and HTCC technology allow for the fabrication of silicon-based CMUTs because the process temperatures (over 900°C) are compatible with standard deposition methods for silicon, polysilicon, silicon dioxide, and silicon nitride layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Other features and advantages of the present disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0071] Figure 1A and Figure 1B A top view and a cross-sectional view of a substrate with prefabricated conductive vias according to a first embodiment are shown, respectively.

[0072] Figure 2A and Figure 2B They are shown respectively Figure 1A and Figure 1B The substrate shown in FIG. 1 is a top view and a cross-sectional view after mechanical polishing of the substrate, removing the annular ring and leaving a planarized surface.

[0073] Figure 3A and Figure 3B They are shown respectively Figure 2A and Figure 2B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a first conductive layer to form a bottom electrode of a polyCMUT cell.

[0074] Figure 4A and Figure 4B They are shown respectively Figure 3A and Figure 3B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a sacrificial layer. The sacrificial layer will become the cavity of the polyCMUT cell.

[0075] Figure 5A and Figure 5B They are shown respectively Figure 4A and Figure 4B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a first polymer layer.

[0076] Fig. 6A and Figure 6B They are shown respectively Figure 5A and Figure 5B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a second conductive layer.

[0077] Fig. 7A and Figure 7B They are shown respectively Fig. 6A and Figure 6B , a top view and a cross-sectional view of a substrate after deposition and patterning of a second polymer layer, wherein the vias on the first polymer layer remain open so that the sacrificial layer can be etched.

[0078] Fig. 8A and Figure 8B They are shown respectively Fig. 7A and Figure 7B A top view and a cross-sectional view of the substrate shown in FIG. 5 after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with a cavity filled with air.

[0079] Fig. 9A and Fig. 9B They are shown respectively Fig. 8A and Figure 8B 0048] The substrate shown in FIG. 1 is a top view and a cross-sectional view after the assembly has been sealed by an encapsulation material deposited in a low pressure chamber.

[0080] Fig. 10A and Fig. 10B A top view and a cross-sectional view of a substrate with prefabricated conductive vias according to a second embodiment are shown, respectively.

[0081] Fig.11A and Fig. 11B They are shown respectively Fig. 10A and Fig. 10B The substrate shown in FIG. 1 is a top view and a cross-sectional view after mechanical polishing of the substrate, removing the annular ring and leaving a planarized surface.

[0082] Fig. 12A and Fig. 12B They are shown respectively Fig.11A and Fig. 11B A top view and a cross-sectional view of the substrate shown in FIG. 1 after the planarization layer is deposited and patterned. The area on the substrate leading to the via remains open for subsequent processing.

[0083] Fig.13A and Fig. 13B They are shown respectively Fig. 12A and Fig. 12B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a first conductive layer to form a bottom electrode of a polyCMUT cell.

[0084] Fig.14A and Fig. 14B They are shown respectively Fig.13A and Fig. 13B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a sacrificial layer. The sacrificial layer will become the cavity of the polyCMUT cell.

[0085] Fig.15A and Fig. 15B They are shown respectively Fig.14A and Fig. 14B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a first polymer layer.

[0086] Fig.16A and Fig. 16B They are shown respectively Fig.15A and Fig. 15B A top view and a cross-sectional view of the substrate shown in FIG. 1 after deposition and patterning of a second conductive layer. An electrical connection exists between one of the vias in the substrate and the second conductive layer.

[0087] Fig.17A and Fig. 17B They are shown respectively Fig.16A and Fig. 16B Top view and cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a second polymer layer; the vias on the first polymer layer remain open so that the sacrificial layer can be etched.

[0088] Fig.18A and Fig.18B They are shown respectively Fig.17A and Fig. 17B A top view and a cross-sectional view of the substrate shown in FIG. 5 after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with a cavity filled with air.

[0089] Fig.19A and Fig.19B They are shown respectively Fig.18A and Fig.18B 0048] The substrate shown in FIG. 1 is a top view and a cross-sectional view after the assembly has been sealed by an encapsulation material deposited in a low pressure chamber.

[0090] Fig. 20A and Fig. 20B A top view and a cross-sectional view are shown, respectively, of a substrate with prefabricated conductive vias and a centrally located patterned conductive area according to a third embodiment.

[0091] Fig.21A and Fig.21B They are shown respectively Fig. 20A and Fig. 20B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a planarization layer.

[0092] Fig.22A and Fig. 22B They are shown respectively Fig.21A and Fig.21B 0048] The substrate shown in FIG. 1 is a top view and a cross-sectional view after mechanical polishing of the substrate, thereby removing a portion of the planarization layer.

[0093] Fig.23A and Fig. 23B They are shown respectively Fig.22A and Fig. 22B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a sacrificial layer.

[0094] Fig.24A and Fig. 24B They are shown respectively Fig.23A and Fig. 23B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a first polymer layer.

[0095] Fig.25A and Fig.25B They are shown respectively Fig.24A and Fig. 24B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a second conductive layer.

[0096] Fig.26A and Fig.26B They are shown respectively Fig.25A and Fig.25B Top view and cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a second polymer layer; the vias on the first polymer layer remain open so that the sacrificial layer can be etched.

[0097] Fig.27A and Fig.27B They are shown respectively Fig.26A and Fig.26B A top view and a cross-sectional view of the substrate shown in FIG. 5 after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with a cavity filled with air.

[0098] Fig.28A and Fig.28B They are shown respectively Fig.27A and Fig.27B 0048] The substrate shown in FIG. 1 is a top view and a cross-sectional view after the assembly has been sealed by an encapsulation material deposited in a low pressure chamber.

[0099] Fig.29A and Fig.29BA top view and a cross-sectional view are shown, respectively, of a substrate with multiple layers and prefabricated conductive vias according to a fourth embodiment.

[0100] Fig. 30A and Fig. 30B They are shown respectively Fig.29A and Fig.29B A top view and a cross-sectional view of the substrate shown in FIG. 5 after mechanical polishing of the substrate to remove a portion of the substrate layer and expose the conductive area.

[0101] Fig.31A and Fig.31B They are shown respectively Fig. 30A and Fig. 30B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a sacrificial layer. The sacrificial layer will become the cavity of the polyCMUT cell.

[0102] Fig.32A and Fig.32B They are shown respectively Fig.31A and Fig.31B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a first polymer layer.

[0103] Fig.33A and Fig.33B They are shown respectively Fig.32A and Fig.32B A top view and a cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a second conductive layer.

[0104] Fig.34A and Fig.34B They are shown respectively Fig.33A and Fig.33B Top view and cross-sectional view of the substrate shown in FIG. 5 after deposition and patterning of a second polymer layer; the vias on the first polymer layer remain open so that the sacrificial layer can be etched.

[0105] Fig.35A and Fig.35B They are shown respectively Fig.34A and Fig.34B A top view and a cross-sectional view of the substrate shown in FIG. 5 after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with a cavity filled with air.

[0106] Fig.36A and Fig.36B They are shown respectively Fig.35A and Fig.35B 0048] The substrate shown in FIG. 1 is a top view and a cross-sectional view after the assembly has been sealed by an encapsulation material deposited in a low pressure chamber.

[0107] Fig.37A and Fig.37BA top view and a cross-sectional view of a silicon-based CMUT fabricated on a printed circuit board according to a fifth embodiment are shown respectively. The material of the printed circuit board can withstand the process conditions (over 400° C.) of silicon, polysilicon, silicon dioxide and silicon nitride layer deposition.

[0108] Fig.38A and Fig.38B The front side and the back side of a substrate having a circular shape and a plurality of conductive vias according to an exemplary embodiment are respectively shown.

[0109] Fig.39A and Fig.39B Shown respectively from Fig.38A and Fig.38B Top isometric view and top plan view of an exemplary polyCMUT linear array fabricated on a substrate.

[0110] Fig.40A and Fig.40B They are shown respectively Fig.39A and Fig.39B Bottom isometric view and bottom plan view of the polyCMUT linear array.

[0111] Fig.41 Shows Fig.39A and Fig.39B Cross-sectional view of a polyCMUT linear array.

[0112] Fig.42A and Fig.42B Shown are top and bottom isometric views, respectively, of an exemplary polyCMUT matrix array fabricated in accordance with an exemplary embodiment.

[0113] Fig.43A Shows Fig.42A and Fig.42B Top view of a polyCMUT matrix array. The polyCMUTs are fabricated on a polished surface with embedded vias.

[0114] Fig.43B Shows Fig.43A Detail A in Figure 1 shows multiple polyCMUT elements in a matrix array. The vias are not visible.

[0115] Fig.44A Shows Fig.42A and Fig.42B Bottom view of the polyCMUT matrix array.

[0116] Fig.44B Shows Fig.44A Detail A, showing multiple conductive vias and annular rings.

[0117] Fig.45AA bottom view of a polyCMUT linear array fabricated according to an exemplary embodiment is shown. Fig.45A An electrical contact assembly is shown mounted at the rear of an array having a plurality of electrical tracks.

[0118] Fig.45B Shows Fig.45A Detail A shown in FIG. Optional electronic components (or circuits containing electronic components, such as biasing tees) are mounted between the vias and the electrical contact assembly.

[0119] Fig.46A Shows Fig.45A Top view of a polyCMUT linear array, showing multiple polyCMUT elements.

[0120] Fig.46B Shows Fig.46A The cross-sectional view AA' in FIG. 1 shows multiple buried regions. The polyCMUT element is on the top portion.

[0121] Fig.46C Shows Fig.46A Bottom view of a polyCMUT linear array, showing the multiple contact areas.

[0122] Fig.46D Shows Fig.46B Detail B in FIG. 1 , which illustrates several layers of a substrate with embedded electronic components.

[0123] Fig.47 An exploded view of a polyCMUT transducer assembly fabricated according to an exemplary embodiment is shown. An acoustic lens is mounted on top of the polyCMUT linear array and a contact assembly is mounted at the back.

[0124] Fig.48A , Fig.48B and Fig.48C Cross-sectional views of polyCMUT linear arrays with different thicknesses fabricated in accordance with an exemplary embodiment and their relative curvature along at least one axis are shown. The thinner the substrate, the less curvature is caused.

[0125] Fig.49A and Fig.49B is a photograph of a substrate having a circular shape and a plurality of conductive vias.

[0126] Fig.50A Shows Fig.49B Detail B shown in FIG. A plurality of contact areas of a conventional electrical plug connector can be mounted on Fig.50A It is obvious.

[0127] Fig.50B Shows Fig.50A Detail C is shown. A single annular ring or even a conductive via in Fig.50B It is obvious.

[0128] Fig.51 Shows Fig.49A Details in A. Fig.51 In the figure, multiple vias that will be connected to the top electrode in the polyCMUT element are evident.

[0129] Fig.52A and Fig.52B Shows Fig.49A and Fig.49B The measured values ​​of the surface roughness of the substrate before and after the substrate is polished.

[0130] Fig.53A According to an exemplary embodiment, a Fig.49A and Fig.49B A circular substrate with several polyCMUT arrays fabricated on top of the substrate.

[0131] Fig.53B shows the substrate after dicing to mechanically separate the arrays in the substrate Fig.53A Several polyCMUT arrays.

[0132] Fig.54A A linear polyCMUT array manufactured according to an exemplary embodiment is shown. The contact components are soldered at the bottom of the array.

[0133] Fig.54B shows the Fig.54A The polyCMUT elements can be controlled independently using this test circuit.

[0134] Fig.55A Shows Fig.54B Time domain response of a polyCMUT array in water. The CMUT transducers have short pulse characteristics.

[0135] Fig.55B shows the use of Fast Fourier Transform (FFT) Fig.55A The frequency domain response of .

[0136] Fig.56A A computer design of a substrate PCB shown in the inset having a circular shape and multiple conductive vias is shown.

[0137] Fig.56B Shows Fig.56A FIG. 1 is a rear view of a substrate showing a plurality of contact pads electrically coupled to conductive vias of the substrate.

[0138] Fig.57A Shown based on Fig.56A Front view of the physical substrate PCB manufactured with the design and having a circular shape and multiple conductive vias. The protective solder mask acts as a planarization layer.

[0139] Fig.57B Shows Fig.57A Front view of the substrate in FIG. 1 after polishing the conductive layer and the planarization layer.

[0140] Fig.58A The microscope obtained Fig.57B A photograph of a polished substrate in which the polished surface has a mirror-like finish.

[0141] Fig.58B Shows Fig.58A 0026] An enlarged view of a polished substrate in FIG. 1 showing the polished conductive material and the polished planarization layer.

[0142] Fig.59A Shows the measurement Fig.57B Stylus profilometer photograph of the surface roughness of the substrate.

[0143] Fig.59B Shown along Fig.59A The profilometer measures the longitudinal axis of the substrate in order to measure the curvature or "bow" of the substrate.

[0144] Fig.59C Shown along Fig.59B Profilometer measurements in the longitudinal axis of the substrate are taken to measure the surface roughness of the polished conductive material and planarization layer.

[0145] Fig.60A Profilometer measurements along the X and Y axes of a standard 100 mm premium grade silicon wafer with an oxide layer are shown to measure the curvature or "bow" of the substrate.

[0146] Fig.60B Shown along Fig.59A The profilometer measures the X and Y axis of the substrate to measure the curvature or "bow" of the substrate.

[0147] Fig.61A Shown are short profilometer measurements along the X-axis of the center area of ​​a standard 100 mm premium grade silicon wafer with an oxide layer to measure the surface roughness of the substrate.

[0148] Fig.61B Shown along Fig.59A The short profilometer measures the value of the X-axis in the center area of ​​the substrate to measure the surface roughness of the substrate.

[0149] Fig.62A Shown along Fig.59A A short profilometer measurement of the X-axis of the planarized layer area to measure the surface roughness.

[0150] Fig.62B Shown along Fig.59A The even shorter profilometer measurements of the X-axis of the central region of the substrate (relative to Fig.62A ) to measure the surface roughness of the substrate.

[0151] Fig.63 Table showing expected ringing effect with a substrate composed of FR4. The expected ringing is related to the thickness of the substrate.

[0152] Fig.64A and Fig.64B A cross-sectional view of an ultrasound assembly including a polyCMUT fabricated according to an exemplary embodiment is shown.

[0153] Fig.65A , Fig.65B and Fig.65C A probe assembly is shown having a flexible polyCMUT array at its base made according to an exemplary embodiment. The polyCMUT array deflects inwardly depending on the pressure in the internal chamber of the probe assembly.

[0154] Fig.66A , Fig.66B and Fig.66C A probe assembly is shown having at its bottom a flexible polyCMUT array manufactured according to an exemplary embodiment. Due to the deflection mechanism, the polyCMUT array is deflected inwards.

[0155] Fig.67 A polyCMUT linear array fabricated according to an exemplary embodiment is shown, the array comprising two planar inductors embedded in its substrate. DETAILED DESCRIPTION

[0156] As used in this article:

[0157] a. An "annular ring" is an area of ​​copper pad surrounding a drilled and finished via. There is enough conductive material (such as copper) around the via to form a strong connection between the conductive trace and the via in a multilayer PCB. Therefore, the main purpose of the annular ring is to establish a good connection between the via and the conductive trace leading to the via. In some cases, the via can be formed without the need for an annular ring, or the annular ring can be small enough to be comparable to the diameter of the via. The annular ring is a specific example of a conductive pad that is electrically connected to the via.

[0158] b. A CMUT "array" is a set of CMUT elements (e.g., 128 elements) aligned side by side in a one-dimensional (1-D) arrangement (a "1-D array" or "linear array"), multiple linear arrays positioned side by side (a "1.5-D array"), or a two-dimensional array of CMUT elements connected to each other in both dimensions of the array (a "2-D array", also called a "matrix array"). All of these types of arrays are capable of communicating with a user interface (once connected or activated) via wired communication or wireless signals.

[0159] c. A "CMUT" is a capacitive micromachined ultrasonic transducer and includes polyCMUTs and silicon-based CMUTs unless the context indicates otherwise.

[0160] d. A CMUT "cell" is a single CMUT transducer with a single moving membrane.

[0161] e. A CMUT "element" is a group of CMUT cells (typically, between 100 and 300 cells). A CMUT element is typically the smallest grouping of CMUTs connected to a single electrical connection that is electrically coupled (i.e., an actuation signal along the single electrical connection correspondingly actuates all CMUT cells forming the CMUT element).

[0162] f. "Embedding" an electrode within a polymer layer means completely covering the electrode with the polymer, except for any electrical connections made to the electrode. These connections are formed prior to completely embedding the electrode within the polymer layer.

[0163] g. To "pattern" a material means either directly (e.g., if it is photosensitive) or by using a masking layer (e.g., in the LOR TM component) to selectively remove the material.

[0164] h. The term "polymer-based capacitive micromachined ultrasonic transducer" ("poly-CMUT" or "polyCMUT") means a layered ultrasonic device with a polymer membrane that contains an embedded upper electrode suspended above a cavity. An example of a poly-CMUT is found in U.S. Pat. No. 10,598,362 to Gerardo, Rohling, and Cretu. Combined with forming a sufficiently thin CMUT cavity, this structure permits the CMUT to reach the MHz operating region without requiring unacceptably high operating voltages. A "poly-CMUT" element can be formed, for example, by the methods disclosed in U.S. Pat. No. 10,598,362 to Cretu et al. or U.S. Pat. No. 7,673,375 to Chang et al.

[0165] LOR is used to manufacture poly-CMUT TMA stripping resist composition comprising: cyclopentanone, PGME, a polyfatty imide copolymer and a proprietary dye (less than 2% of the total volume) and a surfactant; and "SU-8", an optically clear polymer-based photoresist material comprising bisphenol A Novolac dissolved in an organic solvent TM Epoxides and include up to 10 wt% of triarylsulfonium / hexafluoroantimonate. LOR TM The components and SU-8 photoresist and the corresponding SU-8 developer are available from Kayaku Advanced Materials in Massachusetts.

[0166] i. "Substrate" means the underlying material or layer on which the poly-CMUT device is fabricated. Substrates can include a range of metallic materials (e.g., aluminum), non-metallic materials (e.g., ceramics, composites), semiconductors (e.g., silicon), and even polymer-based materials such as polyimide, Kapton, TM , plexiglass or Lexan TM . The substrate may also include an optically transparent or translucent material, such as glass or indium tin oxide (ITO). The substrate may be rigid, semi-rigid, or flexible. The substrate may also include a combination of the foregoing options: for example, a piece of glass covered by a layer of indium tin oxide, or a piece of polyimide covered by a metal layer. A substrate in the form of a PCB may be rigid, semi-rigid, moderately flexible (i.e., bendable only to a certain radius of curvature), or fully flexible (i.e., bendable to the point where opposing parts of the PCB touch each other and prevent further bending). For example, in particular, a fully flexible PCB may be manufactured using polyimide as a substrate.

[0167] j. A "via" in a substrate (such as a PCB) is an electrical interconnect that extends at least partially through the substrate. For example, a via can be a conductive path formed when a hole or opening is filled with a conductive material. The via can connect two or more surfaces in a multilayer substrate (e.g., a PCB). Typically, vias are formed mechanically (by using drilling or laser ablation) or chemically (using abrasive materials to selectively etch the substrate). These holes can later be electroplated to form a conductive path, thereby forming a via. In some embodiments, a common material used for electroplating is copper (Cu). If a hollow via is formed (i.e., the hole for the via is not completely covered by a conductive material), the filler can be a conductive or non-conductive epoxy. This is done to avoid material contamination and prevent particles from accumulating in the hole. The via can be a plugged via, a capped via, a via, a blind via, a buried via, a staggered via, or a micro via.

[0168] The vias may follow non-linear paths through the substrate (i.e., the vias need not be direct vertical connections between the top and bottom layers of the substrate). For example, inner layers of the substrate may be interconnected using conductive traces to facilitate deviations from linear vias extending linearly between the top and bottom layers of the substrate.

[0169] k. "X-ray mammography" means the practice of using radiographic imaging of a patient's breast to screen for breast cancer. In particular, young women have a high percentage of dense breast tissue. During radiographic imaging, dense breast tissue absorbs x-rays in a manner somewhat similar to underlying tumor tissue, making it difficult to distinguish dense breast tissue from underlying tumor tissue. Poly-CMUT arrays are useful in x-ray mammography.

[0170] List of identifiers

[0171] For quick reference, the following table shows the identifiers used in this document:

[0172] 10 Components

[0173] 11 base plate

[0174] 12 Top

[0175] 13 Bottom

[0176] 14 Upper substrate layer

[0177] 15 Lower substrate layer

[0178] 21 Vias

[0179] 22 Ring

[0180] 23. Substrate conductive material

[0181] 24 Substrate conductive area for bottom electrode

[0182] 25 Substrate conductive area for top electrode

[0183] 26 Substrate conductive contact area

[0184] 27 Substrate Conductive Track

[0185] 30 Polishing substrate

[0186] 31 Polishing vias

[0187] 32 polished annular ring

[0188] 33 Polishing substrate conductive material

[0189] 34 Bottom electrode

[0190] 35 Polished conductive area for top electrode

[0191] 36 Polishing the upper substrate layer

[0192] 40 Planarization layer

[0193] 41 Planarization layer vias

[0194] 50 Polishing planarization layer

[0195] 100 substrates

[0196] 101 First Conductive Material

[0197] 102 Bottom electrode

[0198] 103 Contact area for top electrode

[0199] 105 Sacrificial Materials

[0200] 106 Sacrificial Etched Channel

[0201] 107 Sacrificial membrane area

[0202] 110 first polymer layer

[0203] 111 First polymer via

[0204] 115 second conductive material

[0205] 116 Top electrode area

[0206] 117 Top Electrode Interconnect

[0207] 120 second polymer layer

[0208] 121 second polymer film region

[0209] 125 Air Zone

[0210] 130 Packaging materials

[0211] 131 Vacuum Area

[0212] 140 Silicon-based materials

[0213] 141 Silicon-based material vias

[0214] 201 polyCMUT components

[0215] 202 polyCMUT linear array

[0216] 203 polyCMUT matrix array

[0217] 204 polyCMUT array

[0218] 205 polyCMUT array group

[0219] 210 Wafer Substrate

[0220] 211 Wafer substrate front side

[0221] 212 Wafer substrate backside

[0222] 221 Electrical Interconnection Track

[0223] 230 Electrical contact assembly

[0224] 231 Electrical contact assembly connector

[0225] 232 Electrical contact mating connector

[0226] 233 Electrical test circuit board

[0227] 234 Electrical interface board

[0228] 240 Acoustic Lens

[0229] 241 Electronic components

[0230] 242 Planar Inductor

[0231] 250 Transducer Assembly

[0232] 251 Probe Assembly

[0233] 252 Probe housing

[0234] 260 channels

[0235] 261 Internal chamber

[0236] 262 Deflection mechanism

[0237] 263 Deflection distance

[0238] 270 Ultrasound

[0239] 271 Unfocused Ultrasonic Beam

[0240] 272 Focused Ultrasonic Beam

[0241] 273 Focus

[0242] 280 wireless signal In this context, at least some embodiments focus on specific customization of poly-CMUT technology for clinical purposes and non-destructive testing of physical structures.

[0243] The drawings for some of the various embodiments are as follows:

[0244] · Figures 1A to 9B It is about the manufacturing process of the polyCMUT according to the first embodiment, in which a PCB with pre-existing vias is ground and polished to obtain a surface roughness of about several nanometers or less.

[0245] · FIG. 10A to FIG. 19B It is about the manufacturing process of a polyCMUT according to a second embodiment, in which a PCB with pre-existing vias is ground and polished to obtain a surface roughness of the order of tens or hundreds of nanometers. Subsequently, a planarization layer is deposited to reduce the surface roughness to a few nanometers or less. This can be achieved by, for example, spin coating a polymer layer on top.

[0246] · Figures 20A to 28B The present invention relates to a manufacturing process of a polyCMUT according to a third embodiment, wherein a PCB with pre-existing vias and pre-existing bottom electrodes is covered by a planarization layer. The substrate is then ground and polished to obtain a surface roughness of about tens or hundreds of nanometers, thereby exposing the polished surface of the bottom electrode.

[0247] · FIG. 29A to FIG. 36B The present invention relates to the manufacturing process of a PolyCMUT according to a fourth embodiment and involves a multilayer PCB with more than two layers and pre-existing vias accessible from the bottom surface. The bottom electrode of the depicted polyCMUT is patterned in one of the inner layers surrounded by subsequent layers of the same core material. The substrate is then ground and polished to obtain a surface roughness of the order of tens or hundreds of nanometers, exposing the polished surface of the bottom electrode. Since the core material surrounds and encapsulates the bottom electrode, no planarization layer needs to be added.

[0248] · Fig.37A and 37B It is about a manufacturing process of a silicon-based CMUT according to a fifth embodiment, wherein the silicon-based CMUT is manufactured on a ceramic substrate.

[0249] exist Figure 1A (Top view) and Figure 1B (along Figure 1AIn a first embodiment illustrated in FIG. 1 (a cross-sectional view taken along line XX' of FIG. 1 ), component 10 includes substrate 11 with an exposed top surface 12, a bottom surface 13, and a via 21 fabricated in substrate 11. In some embodiments (not shown), bottom surface 13 has additional layers including a protective layer for conducting vias or for protecting substrate 11. Vias 21 and annular ring 22 are also exposed. The diameter D2 of annular ring 22 extends beyond the diameter D1 of via 21. In these figures, for illustrative purposes, via 21 is shown as being completely filled. The surface roughness of the top surface is determined by the manufacturing process of via 21 and the type of material used as substrate 11. The thickness TC of substrate conductive material 23 for annular ring 22 is determined by the expected current in conductive material 23; the thicker the layer, the greater the current allowed to flow through the conductive trace. The thickness T1 of substrate 11 is determined by manufacturing specifications.

[0250] Now refer to Figure 2A (Top view) and Figure 2B (Along Figure 2A 2 (a cross-sectional view of line XX' of FIG. 1 ), a portion of the top surface 12 of the component 10 is removed by mechanical means (such as a grinder or polisher) or by chemical means (such as a solvent that etches both the substrate 11 and the conductive material used in the via 21 and the annular ring 22). The thickness of the removed material is equal to or greater than the thickness TC of the annular ring 22. After the material is removed, the initial thickness T1 of the substrate 11 is reduced to a thickness T2. A polished substrate 30 and a component 10 with a polished via 31 having a surface roughness of a few nanometers or less are obtained. The surface roughness depends on the removal mechanism.

[0251] Now refer to Figure 3A (Top view) and Figure 3B (Along Figure 3A), a first conductive material 101 is deposited on top of the polished substrate 30 and the polished via 31. The first conductive material 101 can be patterned using photolithography techniques, such as stripping or etching a capping layer of conductive material. In some embodiments, the first conductive material 101 is a chromium layer, followed by a gold layer, followed by another chromium layer. In some embodiments, the first conductive material 101 can be deposited using a physical vapor deposition system, such as an electron beam metal evaporator. In some embodiments, the typical thickness of the first conductive material 101 is tens of nanometers (typically 100 nm). The first conductive material 101 is patterned, here patterned into a geometric shape, to form a bottom electrode 102 and a contact area 103 for a top electrode. Although the bottom electrode 102 and the contact area 103 for the top electrode are made of the same first conductive material 101, they are not electrically connected; and there are areas where the polished substrate 30 is still exposed. The bottom electrode 102 will become the bottom electrode in the polyCMUT cell. The contact area 103 for the top electrode will become the electrical connection for the top electrode in the polyCMUT cell.

[0252] Now refer to Figure 4A (Top view) and Figure 4B (Along Figure 4A ), a sacrificial material 105 is deposited on top of the assembly 10, covering the polishing substrate 30 and a portion of the first conductive material 101. The sacrificial material 105 may be patterned using photolithography techniques such as stripping or etching the covering layer of conductive material. In some embodiments, the sacrificial material 105 is, but is not limited to, LOR. TM The resist layer is stripped, followed by a positive photoresist layer, followed by patterning via wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). The layer of sacrificial material 105 can be deposited directly on a flat or curved surface in a very controllable thickness using spin coating or spray coating. For example, the sacrificial material 105 can be deposited using a photolithographic coating technique (such as a spin coater). In some embodiments, the typical thickness of the sacrificial material 105 ranges from tens of nanometers to hundreds of nanometers (typically 200nm), and even a few microns in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form a sacrificial etch channel 106 that contacts the sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in the polyCMUT unit. In Figure 4B In the XX' cross-sectional view, only the sacrificial membrane area 107 is visible.

[0253] like Figure 5A (Top view) and Figure 5B (along Figure 5AAs shown in the cross-sectional view of line XX' of the component 10, the first polymer layer 110 is deposited on top of the component 10, thereby covering the polished substrate 30, the first conductive material 101 and the portion of the sacrificial material 105. The first polymer layer 110 can be (but not limited to) a UV photosensitive material, such as SU-8 photoresist. The first polymer layer 110 can be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer. The first polymer layer 110 can also be patterned using photolithography techniques (such as stripping or etching a polymer cover layer). In some embodiments, the first polymer layer 110 can be deposited using a photolithography coating technique (such as a spin coater). The typical thickness of the first polymer layer 110 ranges from (but not limited to) tens of nanometers to several microns. In at least some embodiments, it is 700nm. The thickness of the first polymer layer 110 is tailored for the specific design of the ultrasonic transducer and can withstand normal operating voltages. The first polymer layer 110 is patterned (in a geometric shape) to form a uniform layer with some first polymer vias 111. The bottom portion of the first polymer layer 110 between the bottom electrode 102 and the contact area 103 for the top electrode is coplanar with the bottom electrode 102 and the contact area 103 for the top electrode. The first polymer via 111 directly contacts a portion of the sacrificial etch channel 106 from the outside. The first polymer via 111 allows the sacrificial material 105 to be etched using a solvent, which allows the sacrificial membrane area 107 to become a cavity in the polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channel 106 are formed in a cavity. Figure 5A The first polymer layer 110 covers the unconnected areas of the polishing substrate 30 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.

[0254] exist Fig. 6A (Top view) and Figure 6B (Along Fig. 6AIn a cross-sectional view taken along line XX' of FIG. 1 , a second conductive material 115 is deposited on top of component 10, covering portions of first polymer layer 110 and portions of contact region 103 for a top electrode. In some embodiments, second conductive material 115 may be patterned using photolithography techniques such as stripping or etching a covering layer of conductive material. In at least some embodiments, second conductive material 115 is a titanium layer covered by a gold layer. In some embodiments, the second conductive material 115 is deposited using a physical vapor deposition system such as a sputtering system for conformal coverage. In some embodiments, the typical thickness of second conductive material 115 is tens of nanometers (including, for example, up to 100 nm). Second conductive material 115 is patterned (in a geometric shape) to form a top electrode region 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in such a way as to avoid any overlap with the first polymer via 111 and to avoid any electrical contact with the bottom electrode 102; typically, the second conductive material 115 is patterned so as not to form a short circuit between the bottom electrode and the top electrode of the polyCMUT cell. The second conductive material 115 is patterned in such a way as to maintain electrical contact with the contact area 103 for the top electrode; thus, the second conductive material 115 is patterned in such a way as to maintain electrical contact with only one of the vias 21 (i.e. Figure 6B The top electrode interconnect 117 is used to form an electrical connection with an adjacent polyCMUT cell (not shown) and allows the formation of a polyCMUT element 201. There is at least one connection point between the top electrode interconnect 117 and the contact area for the top electrode 103. The second conductive layer 115 will become the top electrode in the polyCMUT cell.

[0255] Now refer to Fig. 7A (Top view) and Figure 7B (Along Fig. 7A), a second polymer layer 120 is deposited on top of the component 10, thereby covering the first polymer layer 110 and a portion of the second conductive material 115. In some embodiments, the second polymer layer 120 can be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system, and then patterned using, for example, wet etching using SU-8 developer. The second polymer layer 120 can also be patterned using photolithography techniques (such as stripping or etching a polymer cover layer). In some embodiments, the second polymer layer 120 can be deposited using photolithography coating techniques (such as a spin coater). In some embodiments, the typical thickness of the second polymer layer 120 ranges from hundreds of nanometers to tens of microns (typically 5um). The thickness of the second polymer layer 120 is customized for the specific design of the ultrasonic transducer and can withstand normal operating voltages. The second polymer layer 120 is patterned (in a geometric shape) to form a second polymer film region 121 that avoids sealing or blocking the first polymer via 111. The second polymer layer 120 can also uniformly cover the entire component 10 ( Fig. 7A or Figure 7B The second polymer layer 120 is not shown in the figure, except in the area where the first polymer via 111 is located. One purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in the polyCMUT unit and to be able to operate at relatively high frequencies (such as between 1 MHz and 10 MHz). The sacrificial membrane area 107 and the sacrificial etched channel 106 are Fig. 7A Appears as a dotted line.

[0256] exist Fig. 8A (Top view) and Figure 8B (Along Fig. 8A In a cross-sectional view taken along line XX' of FIG, the sacrificial material 105 (including the sacrificial etching channel 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically). In some embodiments, the sacrificial material can be removed using wet etching using a solvent or dry etching using a gas. In some embodiments, when wet etching is used, the component 10 is immersed in an aqueous solution including tetramethylammonium hydroxide (TMAH). Doing so dissolves the sacrificial material 105 without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 is dissolved (etched), the component 10 is transferred to a container filled with isopropyl alcohol (IPA); the IPA accordingly replaces the aqueous solution including TMAH. Finally, the component 10 is transferred to a chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO 2) enters the chamber and replaces the IPA; then, as the pressure in the chamber gradually decreases to atmospheric pressure, the liquid CO 2 Converted into gaseous CO 2 Once the assembly 10 is removed from the critical point dryer system, the area that was once the sacrificial material 105 is replaced by an air area 125. The air area 125 allows the membrane in the polyCMUT cell to move, but due to the presence of the first polymer via 111, it may not be suitable for water coupling operation.

[0257] Now refer to Fig. 9A (Top view) and Fig. 9B (Along Fig. 9A ), the encapsulation material 130 is uniformly coated over the entire component 10, thereby covering the polishing substrate 30, the first conductive material 101, the first polymer layer 110, the second conductive material 115, and portions of the second polymer layer 120. In some embodiments, the encapsulation material 130 can be polyparaxylene C. In some embodiments, the encapsulation material 130 can be deposited using a low pressure chamber (e.g., vacuum). The encapsulation material 130 conformally coats the top surface 12 of the component 10 and gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are sealed. The thickness of the encapsulation material 130 can be at least half the thickness of the sacrificial material 105 so that the sacrificial etch channels 106 are properly sealed. The bottom surface 13 of the component 10 can be protected (using, for example, a peelable tape) to prevent the encapsulation material 130 from covering the annular ring 22. The area that was once the air area 125 is correspondingly replaced by the vacuum area 131. The vacuum region 131 allows the membrane in the polyCMUT cell to move in liquid-coupled applications such as biomedical ultrasound.The vacuum region 131 becomes a sealed cavity in the polyCMUT cell.

[0258] In another embodiment, Fig. 10A (Top view) and Fig. 10B (Along Fig. 10A As shown in a cross-sectional view taken along line XX' of FIG. 1 , component 10 includes a substrate 11 with an exposed top surface 12 and a bottom surface 13 and a via 21 fabricated in substrate 11. Bottom surface 13 may have additional layers (not shown) that may include a protective layer for conducting via 21 or for protecting substrate 10. Via 21 and annular ring 22 are exposed. Note that diameter D2 of annular ring 22 extends beyond diameter D1 of via 21. In this figure, for illustrative purposes, via 21 is shown as being completely filled. The surface roughness of top surface 12 depends on the manufacturing process of via 21 and the type of material used as substrate 11. The thickness TC of substrate conductive material 23 for annular ring 22 is determined by manufacturing specifications. The thickness T1 of substrate 11 is determined by manufacturing specifications.

[0259] exist Fig.11A (Top view) and Fig. 11B (Along Fig.11A 2 ), a portion of the top surface 12 of the component 10 is removed by mechanical means, such as a grinder or polisher, or by chemical means, such as a solvent that etches both the substrate 11 and the conductive material used in the via 21 and the annular ring 22. In at least some embodiments, the thickness of the removed material is equal to or greater than the thickness TC of the annular ring 22. After the material is removed, the initial thickness T1 of the substrate 11 is reduced to a thickness T2. In at least some embodiments, a component 10 is obtained with a front surface including a polished substrate 30 and a polished via 31 having a surface roughness of a few nanometers or less. The surface roughness depends on the removal mechanism.

[0260] Now refer to Fig. 12A (Top view) and Fig. 12B (Along Fig. 12A ), a planarization layer 40 is deposited on top of the component 10, covering a portion of the polished substrate 30 and a portion of the polished via 31. In some embodiments, the planarization layer 40 may be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the planarization layer 40 may be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer. The planarization layer 40 may also be patterned using photolithography techniques such as stripping or etching a polymer cover layer. In some embodiments, the planarization layer 40 may be deposited using photolithography coating techniques such as a spin coater. In some embodiments, the typical thickness of the planarization layer 40 ranges from tens of nanometers to several micrometers (typically 1 um). The thickness of the planarization layer 40 is selected based on the surface roughness of the polished substrate 30. The purpose of the planarization layer is to reduce the surface roughness to a few nanometers or less. The planarization layer 40 is patterned to form a uniform layer, with some planarization layer vias 41 exposed to subsequent layers. Planarization layer via 41 allows electrical conductivity between via 21 and a subsequent conductive layer through which via 21 extends.

[0261] exist Fig.13A (Top view) and Fig. 13B (Along Fig.13A), a first conductive material 101 is deposited on top of the planarization layer 40 and the polished via 31. In some embodiments, the first conductive material 101 is patterned using a photolithography technique, such as stripping or etching a capping layer of conductive material. In some embodiments, the first conductive material 101 may be a chromium layer, followed by a gold layer, followed by a chromium layer. In some embodiments, the first conductive material 101 may be deposited using a physical vapor deposition system, such as a sputtering system. In some embodiments, the first conductive material 101 has a typical thickness of tens of nanometers (typically 100 nm). The first conductive material 101 is patterned (in a geometric shape) to form a bottom electrode 102 and a contact area 103 for a top electrode. Even though the bottom electrode 102 and the contact area 103 for the top electrode are made of the same first conductive material 101, they are not electrically connected to each other; accordingly, there are areas where the planarization layer 40 is still exposed. The bottom electrode 102 will become the bottom electrode in the polyCMUT cell. The contact area 103 for the top electrode will become the electrical connection for the top electrode in the polyCMUT cell.

[0262] Now refer to Fig.14A (Top view) and Fig. 14B (Along Fig.14A ), a sacrificial material 105 is deposited on top of the component 10, covering the planarization layer 40 and portions of the first conductive material 101. In some embodiments, the sacrificial material 105 can be patterned using photolithography techniques, such as stripping or etching a capping layer of conductive material. The sacrificial material 105 can be a LORTM stripping resist layer in some embodiments, followed by a positive photoresist in some embodiments. The sacrificial material 105 is then patterned, for example, by wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). In some embodiments, the sacrificial material 105 can be deposited using photolithography coating techniques, such as a spin coater. In some embodiments, the typical thickness of the sacrificial material 105 ranges from tens of nanometers to hundreds of nanometers (typically 200 nm), and even a few microns in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form a sacrificial etch channel 106 that contacts a sacrificial membrane region 107. The sacrificial membrane region 107 will become the cavity in the polyCMUT unit. In Fig. 14B In the cross-sectional view of , only the sacrificial membrane area 107 is visible.

[0263] exist Fig.15A (Top view) and Fig. 15B (Along Fig.15AIn the cross-sectional view taken along the line XX' of FIG. 1 ), the first polymer layer 110 is deposited on the top of the component 10, thereby covering the planarization layer 40, the first conductive material 101 and the portion of the sacrificial material 105. In some embodiments, the first polymer layer 110 may be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the first polymer layer 110 may be patterned directly using a UV exposure system, and then patterned by (not limited to) wet etching using SU-8 developer. The first polymer layer 110 may also be patterned using photolithography techniques (such as stripping or etching the polymer cover layer). In some embodiments, the first polymer layer 110 may be deposited using photolithography coating techniques (such as a spin coater). In some embodiments, the typical thickness of the first polymer layer 110 ranges from tens of nanometers to several micrometers (typically 700nm). The thickness of the first polymer layer 110 is customized for the specific design of the ultrasonic transducer and can withstand normal operating voltages. The first polymer layer 110 is patterned (in a geometric shape) to form a uniform layer with some first polymer vias 111. The first polymer vias 111 form a direct contact with a portion of the sacrificial etch channel 106 from the outside. The first polymer vias 111 allow the sacrificial material 105 to be etched using a solvent, which allows the sacrificial membrane area 107 to become a cavity in the polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channel 106 are formed in a cavity. Fig.15A The first polymer layer 110 covers the unconnected areas of the planarization layer 40 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.

[0264] exist Fig.16A (Top view) and Fig. 16B (Along Fig.16AIn a cross-sectional view taken along line XX' of FIG. 1 , a second conductive material 115 is deposited on top of the component 10, covering portions of the first polymer layer 110 and portions of the contact area 103 for the top electrode. In some embodiments, the second conductive material 115 may be patterned using photolithography techniques, such as stripping or etching a covering layer of conductive material. In some embodiments, the second conductive material 115 may be a titanium layer followed by a gold layer. In some embodiments, the second conductive material 115 may be deposited using a physical vapor deposition system, such as a sputtering system, for conformal coverage. In some embodiments, the second conductive material 115 has a thickness of tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (in a geometric shape) to form a top electrode region 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in a manner to avoid any overlap with the first polymer via 111. The second conductive material 115 is also patterned in such a way as to avoid any electrical contact with the bottom electrode 102, so that no short circuit is formed between the bottom electrode and the top electrode of the polyCMUT cell. The second conductive material 115 is also patterned in such a way as to maintain electrical contact with the contact area 103 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 (i.e. the via 21 on the right in FIG. 20 ). The top electrode interconnect 117 is used to form an electrical connection with an adjacent polyCMUT cell (not shown) and allows the polyCMUT element 201 to be formed. There is at least one connection point between the top electrode interconnect 117 and the contact area 103 for the top electrode. The second conductive layer 115 will become the top electrode in the polyCMUT cell.

[0265] exist Fig.17A (Top view) and Fig. 17B (Along Fig.17AIn the cross-sectional view taken along the line XX' of the component 10, the second polymer layer 120 is deposited on the top of the component 10, thereby covering the first polymer layer 110 and the portion of the second conductive material 115. In some embodiments, the second polymer layer 120 can be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system, and then patterned by (not limited to) wet etching using SU-8 developer. The second polymer layer 120 can also be patterned using photolithography techniques (such as stripping or etching the polymer cover layer). In some embodiments, the second polymer layer 120 can be deposited using photolithography coating techniques (such as a spin coater). In some embodiments, the typical thickness of the second polymer layer 120 ranges from hundreds of nanometers to tens of microns (typically 5um). The thickness of the second polymer layer 120 is customized for the specific design of the ultrasonic transducer and can withstand normal operating voltages. The second polymer layer 120 is patterned (in a geometric shape) to form a second polymer film region 121 that avoids sealing or blocking the first polymer via 111. The second polymer layer 120 can also uniformly cover the entire component 10 ( Fig.17A or Fig. 17B The second polymer layer 120 is not shown in the figure, except in the area where the first polymer via 111 is located. One purpose of this second polymer layer 120 is to increase the total thickness of the membrane in the polyCMUT unit to increase its maximum operating frequency. The sacrificial membrane area 107 and the sacrificial etched channel 106 are Fig.17A Appears as a dotted line.

[0266] Now refer to Fig.18A (Top view) and Fig.18B (Along Fig.18A ), the sacrificial material 105 (including the sacrificial etching channel 106 and the sacrificial film area 107) is etched, dissolved, or removed. In some embodiments, the sacrificial material 105 can be removed using wet etching using a solvent or dry etching using a gas. When wet etching is used, in some embodiments, the component 10 is immersed in an aqueous solution containing tetramethylammonium hydroxide (TMAH), thereby dissolving the sacrificial material 105 without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 is dissolved, the component 10 is transferred to a container filled with isopropyl alcohol (IPA); the IPA replaces the aqueous solution containing TMAH. Finally, the component 10 is transferred to a chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO 2 ) enters the chamber and replaces the IPA; then, as the pressure in the chamber gradually decreases to atmospheric pressure, the liquid CO 2Converted into gaseous CO 2 Once the assembly is removed from the critical point dryer system, the area that was once the sacrificial material 105 is replaced by an air area 125. The air area 125 allows the membrane in the polyCMUT cell to move, but due to the presence of the first polymer via 111, it may not be suitable for water coupling operation.

[0267] Now refer to Fig.19A (Top view) and Fig.19B (Along Fig.19A ), encapsulation material 130 is uniformly coated over the entire component 10, thereby covering portions of the planarization layer 40, the first conductive material 101, the first polymer layer 110, the second conductive material 115, and the second polymer layer 120. In some embodiments, the encapsulation material 130 can be polyparaxylene C, and in some embodiments, the encapsulation material is deposited using a low pressure chamber (which will be considered a vacuum). The encapsulation material 130 conformally coats the top surface 12 of the component 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are blocked. In at least some embodiments, the thickness of the encapsulation material 130 can be half the thickness of the sacrificial material 105 to help ensure that the sacrificial etch channels 106 are properly sealed. The bottom surface 13 of the component 10 can be protected (e.g., using a peelable tape) to prevent the encapsulation material 130 from covering the annular ring 22. The area that was once the air area 125 is also replaced by the vacuum area 131. The vacuum region 131 allows the membrane in the polyCMUT cell to move in liquid-coupled applications such as biomedical ultrasound.The vacuum region 131 becomes a sealed cavity in the polyCMUT cell.

[0268] In a third embodiment, if Fig. 20A (Top view) and Fig. 20B (Along Fig. 20AAs shown in a cross-sectional view taken along line XX' of FIG. 1 , component 10 includes a substrate 11 with an exposed top surface 12 and a bottom surface 13 and a via 21 manufactured in substrate 11. In some embodiments (not shown), bottom surface 13 has additional layers including a protective layer for conducting via 21 or for protecting substrate 11. Via 21 and annular ring 22 are exposed. The diameter D2 of annular ring 22 extends beyond the diameter D1 of via 21. In this figure, for illustrative purposes, via 21 is shown as being completely filled. The surface roughness of top surface 12 depends on the manufacturing process of via 21 and the type of material used as substrate 11. The thickness TC of substrate conductive material 23 for annular ring 22 is determined by manufacturing specifications. The thickness T1 of substrate 11 is determined by manufacturing specifications. In component 10, substrate conductive material 23 is patterned to obtain substrate conductive region 24 for bottom electrode and substrate conductive region 25 for top electrode. In some embodiments, during the manufacture of the assembly 10, the substrate conductive material 23 is patterned using a photolithography technique, such as a mask and etch like the mask and etch used in a PCB manufacturing facility. The via 21 forms a direct electrical connection between the substrate conductive region 24 for the bottom electrode on the top surface 12 and the annular ring 22 on the bottom surface 13. The via 21 also forms a direct electrical connection between the substrate conductive region 25 for the top electrode on the top surface 12 and the annular ring 22 on the bottom surface 13. Even though the substrate conductive region 24 for the bottom electrode and the substrate conductive region 25 for the top electrode are made of the same substrate conductive material 23, they are not electrically connected to each other.

[0269] exist Fig.21A (Top view) and Fig.21B (Along Fig.21A In the cross-sectional view taken along the line XX' of FIG. 1 , a planarization layer 40 is deposited on top of the component 10, thereby covering a portion of the substrate 11, a portion of the substrate conductive region 24 for the bottom electrode, and a portion of the substrate conductive region 25 for the top electrode. In some embodiments, the planarization layer 40 can be an epoxy resin, such as Epotek-302 TM or Epotek-302-3M TM . In some embodiments, the planarization layer 40 can be deposited using a photolithographic coating technique (such as a spin coater). In at least some embodiments, the thickness of the planarization layer 40 is equal to or greater than the thickness TC of the substrate conductive material 23. The planarization layer 40 conformally covers all faces of the substrate conductive material 23 that are not in contact with the substrate 11. An optional degassing stage can be used to remove any bubbles that may be trapped during the deposition of the planarization layer 40. The purpose of the planarization layer 40 is to fill the exposed areas on the top surface 12 of the substrate 11 that are not yet covered by the substrate conductive material 23.

[0270] Now refer to Fig.22A (Top view) and Fig. 22B (Along Fig.22A 2 ), a portion of the top surface 12 of the component 10 is removed by mechanical means (such as a grinder or a polisher) or by chemical means (such as a solvent that etches both the planarization layer 40 and the substrate conductive material 23). After the material is removed, the thickness TCP of the polished substrate conductive material 33 is less than the original thickness TC of the substrate conductive material 23. The component 10 with the polished substrate conductive material 33 and the polished planarization layer 50 is obtained with a surface roughness of a few nanometers or even much less. The surface roughness depends on the removal mechanism. After this polishing step, the thickness of the polished substrate conductive material 33 and the polished planarization layer 50 have the same thickness TCP. Maintaining a flat and level surface is important for the next manufacturing steps for forming the polyCMUT unit and ultimately forming the polyCMUT element 201 and the polyCMUT array 204. A portion of the polished planarization layer 50 between the polished conductive area serving as the bottom electrode 34 and the polished conductive area 35 for the top electrode is coplanar with the bottom electrode 34 and the conductive area 35.

[0271] exist Fig.23A (Top view) and Fig. 23B (Along Fig.23A In the cross-sectional view taken along line XX' of FIG. 1 , the sacrificial material 105 is deposited on top of the component 10, thereby covering the polishing planarization layer 50 and a portion of the polishing substrate conductive material 33. In some embodiments, the sacrificial material 105 can be patterned using photolithography techniques (such as stripping or etching the covering layer of conductive material). The sacrificial material 105 can be LOR in some embodiments. TM The resist layer is stripped, followed by a positive photoresist layer in some embodiments, and then patterned via wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). In some embodiments, the sacrificial material 105 can be deposited using a photolithographic coating technique (such as a spin coater). In some embodiments, the typical thickness of the sacrificial material 105 ranges from tens of nanometers to hundreds of nanometers (typically 200nm), and even a few microns in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form a sacrificial etch channel 106 that contacts the sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in the polyCMUT unit. In Fig. 23B In the cross-sectional view in , only the sacrificial membrane area 107 is visible.

[0272] Now refer to Fig.24A (Top view) and Fig. 24B(a cross-sectional view taken along line XX' of FIG. 24), a first polymer layer 110 is deposited on top of the assembly 10, covering the polishing planarization layer 50, the polishing substrate conductive material 33, and portions of the sacrificial material 105. In some embodiments, the first polymer layer 110 may be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the first polymer layer 110 may be patterned directly using a UV exposure system and then patterned using wet etching using SU-8 developer in some embodiments. The first polymer layer 110 may also be patterned using photolithography techniques such as stripping or etching a polymer cover layer. In some embodiments, the first polymer layer 110 may be deposited using photolithography coating techniques such as a spin coater. In some embodiments, the typical thickness of the first polymer layer 110 ranges from tens of nanometers to several micrometers (typically 700 nm). The thickness of the first polymer layer 110 is tailored for a specific design of the ultrasonic transducer and is capable of withstanding normal operating voltages ranging from 10V to 100V. The first polymer layer 110 is patterned (in geometric shapes) to form a uniform layer with some first polymer vias 111. The first polymer vias 111 form a direct connection from the outside to some parts of the sacrificial etch channel 106. The first polymer vias 111 allow the sacrificial material 105 to be etched using a solvent, which allows the sacrificial membrane area 107 to become a cavity in the polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channel 106 are formed in a Fig.24A The first polymer layer 110 covers the unconnected areas of the polished planarization layer 50 and prevents short circuits between the polished conductive areas serving as the bottom electrodes 34 and the polished conductive areas 35 for the top electrodes.

[0273] exist Fig.25A (Top view) and Fig.25B (Along Fig.25AIn a cross-sectional view taken along line XX' of FIG. 1 ), a second conductive material 115 is deposited on top of the component 10, covering portions of the first polymer layer 110 and portions of the polished conductive area for the top electrode 35. In some embodiments, the second conductive material 115 can be patterned using a photolithography technique, such as stripping or etching a capping layer of conductive material. In some embodiments, the second conductive material 115 can be a titanium layer followed by a gold layer. In some embodiments, the second conductive material 115 can be deposited using a physical vapor deposition system, such as a sputtering system, for conformal coverage. In some embodiments, the second conductive material 115 has a typical thickness of tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (in a geometric shape) to form a top electrode region 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in a manner to avoid any overlap with the first polymer via 111. The second conductive material 115 is patterned in such a way as to avoid any electrical contact with the polished conductive area serving as the bottom electrode 34, so as to avoid shorting the bottom electrode of the polyCMUT cell with the top electrode. The second conductive material 115 is patterned in such a way as to maintain electrical contact with the polished conductive area 35 for the top electrode; therefore, the second conductive material 115 is patterned in such a way as to maintain electrical contact with only one of the vias 21 (i.e. Fig.25B The top electrode interconnect 117 is used to form an electrical connection with an adjacent polyCMUT cell (not shown) and allows the formation of a polyCMUT element 201. There is at least one connection point between the top electrode interconnect 117 and the polished conductive region 35 for the top electrode. The second conductive layer 115 will become the top electrode in the polyCMUT cell.

[0274] Now refer to Fig.26A (Top view) and Fig.26B (Along Fig.26A), a second polymer layer 120 is deposited on top of the component 10, thereby covering the first polymer layer 110 and a portion of the second conductive material 115. In some embodiments, the second polymer layer 120 can be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be patterned directly using a UV exposure system, and then patterned using, for example, wet etching using SU-8 developer. The second polymer layer 120 can also be patterned using photolithography techniques (such as stripping or etching a polymer cover layer). In some embodiments, the second polymer layer 120 can be deposited using photolithography coating techniques (such as a spin coater). In some embodiments, the typical thickness of the second polymer layer 120 ranges from hundreds of nanometers to tens of microns (typically 5um). The thickness of the second polymer layer 120 is customized for the specific design of the ultrasonic transducer and can withstand normal operating voltages. The second polymer layer 120 is patterned (in a geometric shape) to form a second polymer film region 121 that avoids sealing or blocking the first polymer via 111. The second polymer layer 120 can also uniformly cover the entire component 10 ( Fig.26A or Fig.26B The second polymer layer 120 is not shown in the figure, except in the area where the first polymer via 111 is located. The purpose of this second polymer layer 120 is to increase the total thickness of the membrane in the polyCMUT unit to be able to operate at frequencies between 1 MHz and 10 MHz. The sacrificial membrane area 107 and the sacrificial etched channel 106 are Fig.26A Appears as a dotted line.

[0275] exist Fig.27A (Top view) and Fig.27B (Along Fig.27A In a cross-sectional view taken along line XX' of FIG, the sacrificial material 105 (including the sacrificial etch channel 106 and the sacrificial membrane region 107) is etched, dissolved, or otherwise removed (e.g., mechanically). In some embodiments, the sacrificial material 105 can be removed using wet etching using a solvent or dry etching using a gas. When wet etching is used, in some embodiments, the component 10 is immersed in an aqueous solution containing tetramethylammonium hydroxide (TMAH), in which the sacrificial material 105 is dissolved without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 is dissolved, the component is transferred to a container filled with isopropyl alcohol (IPA); the IPA replaces the aqueous solution containing TMAH. Finally, the component 10 is transferred to a chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO 2) enters the chamber at high pressure and replaces the IPA; then, as the pressure in the chamber gradually decreases to atmospheric pressure, the liquid CO 2 Converted into gaseous CO 2 Once the assembly 10 is removed from the critical point dryer system, the area that was once the sacrificial material 105 is now replaced by an air area 125. The air area 125 allows the membrane in the polyCMUT cell to move, but due to the presence of the first polymer via 111, it is not suitable for water coupling operation.

[0276] exist Fig.28A (Top view) and Fig.28B (Along Fig.28A ), the encapsulation material 130 is uniformly coated over the entire component 10, thereby covering the polishing planarization layer 50, the polishing substrate conductive material 33, the first polymer layer 110, the second conductive material 115, and portions of the second polymer layer 120. In some embodiments, the encapsulation material 130 can be polyparaxylene C. In an embodiment, the encapsulation material 130 can be deposited using a low pressure chamber (such as in a vacuum). The encapsulation material 130 conformally coats the top surface 12 of the component 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are sealed. In at least some embodiments, the thickness of the encapsulation material 130 is at least half the thickness of the sacrificial material 105 so that the sacrificial etch channels 106 are properly sealed. The bottom surface 13 of the component 10 can be protected (using, for example, a peelable tape) to prevent the encapsulation material 130 from covering the annular ring 22. The area that was once the air area 125 is replaced by the vacuum area 131. The vacuum region 131 allows the membrane in the polyCMUT cell to move in liquid-coupled applications such as biomedical ultrasound.The vacuum region 131 becomes a sealed cavity in the polyCMUT cell.

[0277] In a fourth embodiment, if Fig.29A (Top view) and Fig.29B (Along Fig.29A As shown in the cross-sectional view taken along the line XX' of FIG. 1 ), the component 10 includes a substrate 11 bonded to and correspondingly adhered to an upper substrate layer 14. The upper substrate layer 14 is made of the same material as the substrate 11. In some embodiments, the material used for the substrate 11 and the upper substrate layer 14 typically includes a glass-reinforced epoxy laminate (generally referred to as "FR4") or a carbon-hydrogen ceramic laminate (generally referred to as "Rogers material"). The substrate 11 and the upper substrate layer 14 are typically bonded at a high temperature in a vacuum to avoid any bubbles or voids therebetween. The component 10 may have an additional lower substrate layer 15 ( Fig.29A or Fig.29B). The optional lower substrate layer 15 has the same physical properties as the upper substrate layer 14. The optional lower substrate layer 15 may have vias 21 to maintain electrical connection with the substrate conductive material 23. The bottom surface 13 of the substrate 11 may have additional layers (not shown), which may include protective layers for conductive vias 21 or for protecting the substrate 11. The vias 21 and the annular rings 22 are exposed. The diameter D2 of the annular rings 22 extends beyond the diameter D1 of the vias 21. For illustrative purposes, the vias 21 are shown as being completely filled. The thickness TC of the substrate conductive material 23 for the annular rings 22 is determined by manufacturing specifications. The thickness T1 of the substrate 11 and the thickness T3 of the upper substrate layer 14 are determined by manufacturing specifications; typically, T3 is greater than T1. In the component 10, the substrate conductive material 23 between the substrate 11 and the upper substrate layer 14 is patterned to obtain substrate conductive regions 24 for the bottom electrode and substrate conductive regions 25 for the top electrode 25 (in Fig.29A 13). In some embodiments, during the manufacture of the assembly 10, the substrate conductive material 23 is patterned using a photolithography technique, such as a mask and etch like that used in a PCB manufacturing facility. The via 21 forms a direct electrical connection between the substrate conductive region 24 for the bottom electrode on the top surface 12 and the annular ring 22 on the bottom surface 13. The via 21 forms a direct electrical connection between the substrate conductive region 25 for the top electrode and the annular ring 22 on the bottom surface 13. Even though the substrate conductive region 24 for the bottom electrode and the substrate conductive region 25 for the top electrode are made of the same substrate conductive material 23, they are not electrically connected to each other.

[0278] Now refer to Fig. 30A (Top view) and Fig. 30B (Along Fig. 30A ), parts of the component 10 are removed by mechanical means (such as a grinder or a polisher) or by chemical means (such as a solvent that etches both the upper substrate layer 14 and the substrate conductive material 23). After the material is removed, the thickness TCP of the polished substrate conductive material 33 is less than the original thickness TC of the substrate conductive material 23. The component 10 with the polished substrate conductive material 33 and the polished upper substrate layer 36 is obtained, with a surface roughness of a few nanometers or less. The surface roughness depends on the removal mechanism. After this polishing step, the polished substrate conductive material 33 and the polished upper substrate layer 36 have the same thickness TCP. The manufacturing according to the depicted embodiment can be completed without depositing the planarization layer 40, which is referred to above. Fig.21AMaintaining a flat and level surface is important for the subsequent manufacturing steps used to form the polyCMUT cells and ultimately the polyCMUT element 201 and the polyCMUT array 204. A portion of the PCB itself (i.e., the polished upper substrate layer 36) between the polished conductive area serving as the bottom electrode 34 and the polished conductive area 35 for the top electrode is coplanar with the bottom electrode 34 and the conductive area 35.

[0279] exist Fig.31A (Top view) and Fig.31B (Along Fig.31A In the cross-sectional view taken along line XX' of FIG. 1 , the sacrificial material 105 is deposited on top of the component 10, thereby covering the polished upper substrate layer 36 and a portion of the polished substrate conductive material 33. In some embodiments, the sacrificial material 105 can be patterned using photolithography techniques (such as stripping or etching the covering layer of conductive material). In some embodiments, the sacrificial material 105 can be LOR. TM The resist layer is stripped, followed by a positive photoresist layer in some embodiments, and then patterned using, for example, wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). In some embodiments, the sacrificial material 105 can be deposited using a photolithographic coating technique (such as a spin coater). In some embodiments, the typical thickness of the sacrificial material 105 ranges from tens of nanometers to hundreds of nanometers (typically 200nm), and even a few microns in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form a sacrificial etch channel 106 that contacts the sacrificial membrane area 107. The sacrificial membrane area 107 will become the cavity in the polyCMUT unit. In Fig.31B In FIG. 1 , only the sacrificial membrane area 107 is visible.

[0280] Now refer to Fig.32A (Top view) and Fig.32B (Along Fig.32A), a first polymer layer 110 is deposited on top of the component 10, thereby covering the polished upper substrate layer 36, the polished substrate conductive material 33, and portions of the sacrificial material 105. In some embodiments, the first polymer layer 110 may be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the first polymer layer 110 may be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer. The first polymer layer 110 may also be patterned using photolithography techniques such as stripping or etching a polymer cover layer. In some embodiments, the first polymer layer 110 may be deposited using photolithography coating techniques such as a spin coater. In some embodiments, the typical thickness of the first polymer layer 110 ranges from tens of nanometers to several micrometers (typically 700 nm). The thickness of the first polymer layer 110 is tailored for a specific design of the ultrasonic transducer and is capable of withstanding normal operating voltages ranging between 10V and 100V. The first polymer layer 110 is patterned (in geometric shapes) to form a uniform layer with some first polymer vias 111. The first polymer vias 111 form a direct connection from the outside to some parts of the sacrificial etch channel 106. The first polymer vias 111 allow the sacrificial material 105 to be etched using a solvent, which will allow the sacrificial membrane area 107 to become the cavity in the polyCMUT cell. The sacrificial membrane area 107 and the sacrificial etch channel 106 are formed in a Fig.32A The first polymer layer 110 covers the electrically unconnected area of ​​the polished upper substrate layer 36 and prevents short circuits between the polished conductive area serving as the bottom electrode 34 and the polished conductive area 35 for the top electrode.

[0281] Now refer to Fig.33A (Top view) and Fig.33B (Along Fig.33AIn a cross-sectional view taken along line XX' of FIG. 1 ), a second conductive material 115 is deposited on top of the component 10, covering portions of the first polymer layer 110 and portions of the polished conductive region 35 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using photolithography techniques, such as stripping or etching a capping layer of conductive material. In some embodiments, the second conductive material 115 can be a titanium layer followed by a gold layer. In some embodiments, the second conductive material 115 can be deposited using a physical vapor deposition system, such as a sputtering system, for conformal coverage. In some embodiments, the second conductive material 115 has a typical thickness of a few nanometers to tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (in a geometric shape) to form a top electrode region 116 and a top electrode interconnect 117. The second conductive material 115 is patterned in a manner to avoid any overlap with the first polymer via 111. The second conductive material 115 is patterned in such a way as to avoid any electrical contact with the polished conductive area serving as the bottom electrode 34; otherwise, this would form a short circuit between the bottom electrode and the top electrode of the polyCMUT cell. The second conductive material 115 is patterned in such a way as to maintain electrical contact with the polished conductive area 35 serving as the top electrode; therefore, the second conductive material 115 is patterned in such a way as to maintain electrical contact with only one of the vias 21 (i.e., Fig.25B The top electrode interconnect 117 is used to form an electrical connection with an adjacent polyCMUT cell (not shown) and allows the formation of a polyCMUT element 201. There is at least one connection point between the top electrode interconnect 117 and the polished conductive region 35 for the top electrode. The second conductive layer 115 will become the top electrode in the polyCMUT cell.

[0282] Now refer to Fig.34A (Top view) and Fig.34B (Along Fig.34A), a second polymer layer 120 is deposited on top of the component 10, thereby covering the first polymer layer 110 and a portion of the second conductive material 115. In some embodiments, the second polymer layer 120 may be a UV photosensitive material, such as SU-8 photoresist. In some embodiments, the second polymer layer 120 may be patterned directly using a UV exposure system, and then patterned using, for example, wet etching using SU-8 developer. The second polymer layer 120 may also be patterned using photolithography techniques (such as stripping or etching a polymer cover layer). In some embodiments, the second polymer layer 120 may be deposited using photolithography coating techniques (such as a spin coater). In some embodiments, the typical thickness of the second polymer layer 120 ranges from hundreds of nanometers to tens of micrometers (typically 5um). The thickness of the second polymer layer 120 is customized for a specific design of an ultrasonic transducer and is capable of withstanding normal operating voltages ranging between 10V and 100V. The second polymer layer 120 is patterned (in a geometric shape) to form a second polymer film region 121 that avoids sealing or blocking the first polymer via 111. The second polymer layer 120 can also uniformly cover the entire component 10 ( Fig.34A or Fig.34B The second polymer layer 120 is not shown in the figure, except in the area where the first polymer via 111 is located. The purpose of this second polymer layer 120 is to increase the total thickness of the membrane in the polyCMUT unit and to be able to reach the desired frequency between 1 MHz and 10 MHz. The sacrificial membrane area 107 and the sacrificial etched channel 106 are Fig.34A Appears as a dotted line.

[0283] Now refer to Fig.35A (Top view) and Fig.35B (Along Fig.35A ), the sacrificial material 105 (including the sacrificial etch channel 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically). In some embodiments, the sacrificial material can be removed by (in some embodiments) wet etching using a solvent or dry etching using a gas. When wet etching is used, in some embodiments, the component 10 is immersed in an aqueous solution containing tetramethylammonium hydroxide (TMAH), in which the sacrificial material 105 is dissolved without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 is dissolved, the component is transferred to a container filled with isopropyl alcohol (IPA); the IPA replaces the aqueous solution containing TMAH. Finally, the component 10 is transferred to a chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO 2) enters the chamber at high pressure and replaces the IPA; then, as the pressure in the chamber gradually decreases to atmospheric pressure, the liquid CO 2 Converted into gaseous CO 2 Once the assembly 10 is removed from the critical point dryer system, the area that was once the sacrificial material 105 is replaced by an air area 125. The air area 125 allows the membrane in the polyCMUT cell to move, but due to the presence of the first polymer via 111, it may not be suitable for water coupling operation.

[0284] Now refer to Fig.36A (Top view) and Fig.36B (Along Fig.36A ), the encapsulation material 130 is uniformly coated over the entire component 10, thereby covering the polished upper substrate layer 36, the polished substrate conductive material 33, the first polymer layer 110, the second conductive material 115, and portions of the second polymer layer 120. In some embodiments, the encapsulation material 130 may be polyparaxylene C. In some embodiments, the encapsulation material 130 may be deposited using a low pressure chamber that can be operated as a vacuum. The encapsulation material 130 conformally coats the top surface of the component 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are blocked and thereby sealed. In at least some embodiments, the thickness of the encapsulation material 130 is at least half the thickness of the sacrificial material 105 so that the sacrificial etch channels 106 are properly sealed. The bottom surface 13 of the component 10 may be protected (using, for example, a peelable tape) to prevent the encapsulation material 130 from covering the annular ring 22. The area that was once the air area 125 is replaced by the vacuum area 131. The vacuum region 131 allows the membrane in the polyCMUT cell to move in liquid-coupled applications such as biomedical ultrasound.The vacuum region 131 becomes a sealed cavity in the polyCMUT cell.

[0285] exist Figures 1A to 37B The solvents for wet etching in the first to fourth embodiments depicted in the drawings are selected to be chemically compatible with the substrate 11 and other materials deposited on the substrate (such as various polymer layers 110, 120 for electrodes and conductive materials 115). That is, the solvent is selected to etch away the sacrificial material 105 without dissolving or damaging the substrate 11 and those other materials. An example suitable solvent for wet etching includes a SU-8 developer, the main components of which are 1-methoxy-2-propanol acetate and tetramethylammonium hydroxide (TMAH). Other suitable solvents may include only 1-methoxy-2-propanol acetate or include acetone and isopropyl alcohol (IPA) when part of the other component is not a SU-8 developer.

[0286] Now refer to Fig.37A (Top view) and Fig.37B(Along Fig.37A ), the encapsulation material 130 is uniformly coated over the entire component 10, thereby covering the polished upper substrate layer 36, the polished substrate conductive material 33, the silicon-based material 110, and portions of the second conductive material 115. In some embodiments, the encapsulation material 130 may be silicon nitride, silicon dioxide, or polysilicon. In some embodiments, the encapsulation material 130 may be deposited using a low-pressure chamber that can be operated as a vacuum. The encapsulation material 130 conformally coats the top surface of the component 10, enters the silicon-based material vias 141, and gradually accumulates on the inner walls of the sacrificial etch channels 106 until they are blocked and thereby sealed. In at least some embodiments, the thickness of the encapsulation material 130 is at least half the thickness of the sacrificial material 105 to enable proper sealing of the sacrificial etch channels 106. The bottom surface 13 of the component 10 may be protected (using, for example, a masking layer) to prevent the encapsulation material 130 from covering the annular ring 22. The area that was once the air region 125 is replaced by the vacuum region 131. The vacuum region 131 allows the membrane in the silicon-based CMUT cell to move in liquid-coupled applications such as biomedical ultrasound. The vacuum region 131 becomes a sealed cavity in the silicon-based CMUT cell. The material of the substrate 11 can withstand process conditions that occur at over 400°C for depositing silicon, polysilicon, silicon dioxide, and silicon nitride layers. The substrate 11 can also be a product of a process like LTCC or HTCC.

[0287] Although about Fig.37A and Fig.37B The fabrication of silicon-based CMUTs is clearly described, but Figures 1A to 36B The manufacturing processes of the first to fourth embodiments described can also be used to manufacture silicon-based CMUTs, as long as the substrate 11 used is made of a material that can withstand the temperature required for the silicon-based CMUT to be manufactured (i.e., more than 400° C.), and a solvent is used that is compatible with the selected substrate 11 and the materials deposited thereon, as described above. A polyCMUT can similarly be manufactured on a ceramic substrate.

[0288] operate

[0289] Fig.38A and Fig.38B The front side 211 and back side 212 of a wafer substrate 210 manufactured in a PCB manufacturing facility are depicted respectively. The front side 211 of the wafer substrate has hundreds of exposed vias 21 and annular rings 22 that are too small to be printed on the wafer substrate. Fig.38AThe positions of these vias 21 and annular rings 22 match the positions of the polyCMUT array 204 to be fabricated on the front side 211 of the wafer substrate. The back side 212 of the wafer substrate has hundreds of contact pads that are electrically connected to the vias 21 on the front side 211 of the wafer substrate. These electrical contact pads allow soldering of electrical contact components 230 ( Fig.38A or Fig.38B ) (not shown) ) permits interaction with external electronic devices such as ultrasonic pulse generators and amplifiers.

[0290] Now refer to Fig.39A and Fig.39B , respectively, show a top isometric view and a top plan view of a 3D visualization of a polyCMUT array 204 in the form of a polyCMUT linear array 202 fabricated on a substrate 11. The polyCMUT linear array 202 is obtained from Fig.38A and Fig.38B The polyCMUT linear array 202 includes 128 polyCMUT elements 201 stacked one on top of the other along the length of the array 202, wherein each of the polyCMUT elements includes 300 polyCMUT cells (not shown separately). The polyCMUT elements are electrically connected to independent vias 21 (not shown separately) on the substrate 11, which extend to the bottom surface 13 of the substrate 11. The electrical contact assembly 230 is mounted on the bottom surface 13 of the substrate 11 and electrically connected to the vias 21. The 128 polyCMUT elements are electrically coupled to the 128 vias 21, respectively. In the embodiment according to the first embodiment and according to Figures 1A to 9B A polyCMUT linear array 202 is fabricated on top of a polished substrate 30 as depicted.

[0291] Now refer to Fig.40A and Fig.40B , respectively showing Fig.39A and Fig.39B 1 and 2 are isometric and bottom views of a 3D visualization of the bottom surface 13 of the polyCMUT linear array 202. The polyCMUT linear array 202 located on the top surface of the substrate 11 is not shown. The electrical contact assembly 230 has dozens of independent electrical contact assembly connectors 231. Each of these electrical contact assembly connectors 231 is connected to the via 21 and, accordingly, is also electrically connected to the second conductive material 115 of their corresponding polyCMUT element 201 (not shown).

[0292] Now refer to Fig.41 , showing Fig.39A and Fig.39B1 is a cross-sectional view of a polyCMUT linear array 202. On the top surface 12 are polyCMUT elements 201 fabricated on top of a polished substrate 30 through which vias 21 extend to annular rings 22 located on the bottom surface 13. An electrical contact assembly 230 comprising electrical contact assembly connectors 231 is adhered to substrate conductive contact areas 26. Each individual electrical contact assembly connector 231 is connected to an individual via 21 through a substrate conductive contact area 26 patterned on the bottom surface 13 of the substrate 11. The substrate conductive contact areas 26 are typically patterned by a manufacturing facility (e.g., a PCB factory).

[0293] Now refer to Fig.42A and Fig.42B , respectively showing a top isometric view and a bottom isometric view of a polyCMUT array 204. On top of a polished substrate 30, a polyCMUT matrix array 203 including hundreds of polyCMUT elements 201 arranged in dozens of rows and dozens of columns is fabricated. On the bottom surface 13, there are hundreds of substrate conductive contact areas 26 electrically isolated from each other. These substrate conductive contact areas 26 each have a direct path from the bottom surface 13 to a single polyCMUT element 201 on the top surface 12 through a via 21 (not shown) extending through the polished substrate 30. The polished substrate 30 may include one or more layers of substrate conductive material 23, which allows for appropriate routing and distribution of the substrate conductive contact areas 26. For example, a printed circuit board may have two, four, six or more layers interconnected by internal vias.

[0294] Now refer to Fig.43A and Fig.43B , respectively. Fig.42A and Fig.42B Detailed view of area A in a top view of a polyCMUT array 204 of FIG. On top of a polished substrate 30, a polyCMUT matrix array 203 is fabricated that includes hundreds of polyCMUT elements 201 in tens of rows and tens of columns along the X-axis and the Y-axis. In some embodiments, the polyCMUT matrix array 203 has independent connections for the top and bottom electrodes of the polyCMUT cells (not shown). In some embodiments, the polyCMUT matrix array 203 has independent connections for the top electrodes and common electrical connections for the bottom electrodes (not shown).

[0295] Now refer to Fig.44A and Fig.44B , respectively showing Fig.42A and Fig.42B2 and a bottom view and a detail view of region A in the top view of the polyCMUT array 204 of FIG. There is an array of electrically isolated substrate conductive contact areas 26, each of which has a direct electrical path to a single polyCMUT element 201 on the top surface 12 through a via 21 (not shown) extending through the polished substrate 30. The polished substrate 30 may include one or more layers of substrate conductive material 23, which allows for appropriate routing and distribution of the substrate conductive contact areas 26. For example, the printed circuit board may have two, four, six or more layers interconnected by internal vias.

[0296] Now refer to Fig.45A and Fig.45B , showing a bottom view and a detail view of region A of the polyCMUT array 204, respectively. An electrical contact assembly 230 (shown as a dashed rectangle) is mounted on the bottom surface 13 of the polyCMUT array 204. The detail view shows a substrate conductive contact area 26 with segmented portions, forming substrate conductive contact tracks 27, which then lead to the annular ring 22. Electronic components 241 (e.g., surface mount devices such as inductors) can be soldered or adhered between the substrate conductive contact tracks 27 to act as an electrical impedance matching circuit to cancel the capacitive reactance typical of CMUTs and polyCMUTs. The substrate conductive contact area 26 can be divided into two or more substrate conductive contact tracks 27 (not shown) to allow mounting of two or more electronic components 241; for example, an array including resistors and capacitors can be mounted to corresponding substrate conductive contact tracks 27 to form a "bias tee" circuit to add DC and AC voltages.

[0297] Now refer to Fig.46A , Fig.46B , Fig.46C and Fig.46D , respectively showing Fig.45A A top view of the polyCMUT array 204, along Fig.46A A cross-sectional view taken along the line A-A', a rear view and Fig.46B Detail of region B of FIG. A polyCMUT linear array 202 including polyCMUT elements 201 is constructed on a polished substrate 30. The substrate 11 includes two or more substrate sublayers 16 arranged in a stack. FIG. 46A to FIG. 46D1, but internal vias 21 and internal substrate conductive material 23 are present between the substrate sublayers 16. There are buried regions 250 in the substrate 11 that may contain a plurality of embedded electronic components 241, such as inductors, resistors, capacitors, microprocessors, or circuits formed by these embedded electronic components 241. These embedded electronic components 241 may be electrically connected to a single polyCMUT element 201 or multiple polyCMUT elements 201. This integration helps to reduce the overall footprint of the polyCMUT array 204 that interacts with the embedded electronic components 241. These embedded electronic components 241 may be directly integrated during manufacturing, or may be added after the substrate 11 is completed by etching some areas on the bottom surface 13 of the substrate and then filling those areas with a material having similar mechanical and chemical properties to the substrate 11, such as FR4 resin.

[0298] Now refer to Fig.47 , shows an exploded view of the transducer assembly 250. It includes an electrical contact assembly 230. The electrical contact assembly 230 includes a plurality of electrical contact assembly connectors 231 and is attached (e.g., adhered or welded) to the polyCMUT array 204. The polyCMUT array 204 can be a polyCMUT linear array 202 or a polyCMUT matrix array 203 (not shown). An acoustic lens 240 is also attached (e.g., adhered or cast) to the top surface of the polyCMUT array 204. The purpose of the acoustic lens 240 is to produce a concentrated ultrasound beam. In some embodiments, the acoustic lens 240 can be cast directly on top of the polyCMUT array 204 using a mold (not shown), or in other embodiments, can be cast on a separate mold and then glued into place with an adhesive compatible with the materials of the acoustic lens 240 and the polyCMUT array 204.

[0299] Now refer to Fig.48A , Fig.48B and Fig.48C , three cross-sectional views of a polyCMUT linear array 202 of substrates 11 with different thicknesses (T4, T5, and T6) are illustrated, and a single polyCMUT element 201 can be seen on its top surface. When the polyCMUT linear array 202 is bent about the X-axis (not shown, the axis coming out of the page), the thicker substrate (T4) results in a larger radius of curvature (R4), such that T4>T5>T6 and R4>R5>R6. In some embodiments, some substrates 11 with vias 21 (not shown) can be manufactured in thin substrates (typically 0.4 mm thick), which results in a semi-rigid / bendable polyCMUT linear array 202.

[0300] Examples

[0301] Now refer to Fig.49A , illustrates a photograph of a wafer substrate 210 manufactured in a printed circuit board manufacturing facility. The wafer substrate front side 211 has hundreds of exposed vias 21 and annular rings 22 (too small to be printed on the Fig.49A The positions of these vias 21 and annular rings 22 match the positions of the polyCMUT array 204 to be fabricated on the front side 211 of the wafer substrate. Fig.51 A detailed view of area A is shown in FIG.

[0302] Now refer to Fig.49B , shows a photograph of a wafer substrate 210 being manufactured in a printed circuit board manufacturing facility. The wafer substrate back side 212 has hundreds of electrical contact pads that have independent electrical paths to vias 21 on the wafer substrate front side 211. These electrical contact pads allow for soldering of electrical contact components 230 (such as plug connectors or sockets used in the PCB industry) to interface with external electronic devices (such as ultrasonic pulse generators and amplifiers). Fig.50A A detailed view of region B is shown in FIG.

[0303] Now refer to Fig.50A , showing that in Fig.49B Detail of the region B shown in FIG. It corresponds to a microscopic view of the back side 212 of the wafer substrate.

[0304] Now refer to Fig.50B , which shows the Fig.50A Detail of the area C shown in FIG. 2 . It corresponds to a microscopic view of the wafer substrate back side 212 . The annular ring 22 is electrically connected to the substrate conductive contact area 26 via a plurality of substrate conductive tracks 27 patterned using the same substrate conductive material 23 .

[0305] Now refer to Fig.51 , showing that in Fig.49A Detail of the area B shown in FIG. 2. It corresponds to a microscopic view of the wafer substrate back side 211. Polishing the substrate 30 is achieved by using a mechanical grinding and polishing system together with polishing chemicals and abrasives. Some polishing vias 31 are also shown; these polishing vias will be used to connect to the top electrodes in the individual polyCMUT elements 201 that will be manufactured on the top (not shown). The polishing system uniformly planarizes the wafer substrate front side 211 until a surface roughness of a few nm is achieved.

[0306] Now refer to Fig.52A , shows the front surface 211 of the wafer substrate before the polishing stage along the distance L (in Fig.51 The average surface roughness is 2.092um. This measurement was made using DektakXTTM Obtained by a stylus profilometer.

[0307] Now refer to Fig.52B , shows the front surface 211 of the wafer substrate after the polishing stage along the distance L (in Fig.51 The average surface roughness is 52.805 nm. This measurement was made using DektakXT TM Obtained by a stylus profilometer.

[0308] Now refer to Fig.53A , shows a photograph of a wafer substrate 210 with several polyCMUT arrays 204 fabricated on top after the wafer substrate 210 has been polished in a grinding / polishing machine. There are seven identical polyCMUT linear arrays 202 in the center, plus three additional polyCMUT linear arrays 202 on the sides. There is also a small polyCMUT matrix array 203 on the northwest corner. Later, this wafer substrate 210 will be sliced ​​in a dicing saw to separate the polyMUT arrays 204 individually.

[0309] Now refer to Fig.53B , shows a photograph of a group of polyCMUT arrays 205. The polyCMUT arrays 204 are separated using a dicing saw. Only some of the polyCMUT linear arrays 202 are shown in this figure.

[0310] Now refer to Fig.54A , showing that on the substrate 11 (also Fig.53B The polyCMUT linear array 202 comprises 128 polyCMUT elements 201 which are electrically connected to individual vias 21 on the substrate 11 (which are too small to be placed on the substrate 11). Fig.54A The electrical contact assembly 230 is mounted on the bottom surface 13 of the substrate 11. According to the first embodiment described above, the polyCMUT linear array 202 is manufactured on top of the polished substrate 30.

[0311] Now refer to Fig.54B , shows a photograph of a polyCMUT linear array 202 mounted on an electrical test circuit board 233. An electrical contact assembly 230 mounted on the back side of the polyCMUT linear array 202 engages with an electrical contact mating connector 232 integrated into the electrical test circuit board 233. The electrical test circuit board 233 is used to send electrical signals to and receive electrical signals from the polyCMUT linear array 202.

[0312] Fig.54BThe polyCMUT linear array 202 shown in FIG. 1 is partially immersed (positioned face-down) in an acoustic evaluation tank (not shown) containing deionized water (DI water). A calibrated hydrophone manufactured by Onda Corporation of Sunnyvale, California, USA, is immersed in the acoustic evaluation tank and positioned 20 mm from the surface of the polyCMUT linear array 202 to measure the acoustic signals generated by a single polyCMUT element 201. The recorder signal in time is Fig.55A The hydrophone recorded an acoustic signal of 73 kPa.

[0313] Now refer to Fig.55B , showing the Fig.55A The fast Fourier transform (FFT) signal corresponding to the time domain signal shown in FIG. When a combination of 30V AC voltage and 30V DC voltage is applied to the polyCMUT element 201, a center frequency of 7.4MHz and a fractional bandwidth of 83% are shown. This shows that the manufacture and operation of the polyCMUT array 204 is feasible using a prefabricated substrate with vias and electrical connections at the back side.

[0314] Now refer to Fig.56A , illustrates a computer design of a wafer substrate 210 to be manufactured in a printed circuit board manufacturing facility. The inset shows a polished substrate conductive material 33 and a polished conductive area 35 for a top electrode. The polished substrate conductive material 33 comprises more than 95% of the total area of ​​the wafer substrate 210.

[0315] Now refer to Fig.56B , shows a photograph of a wafer substrate 210 manufactured in a printed circuit board manufacturing facility. The wafer substrate back side 212 has hundreds of electrical contact pads that are electrically coupled to vias 21 on the wafer substrate front side 211. These electrical contact pads allow soldering of electrical contact components 230 (such as plug connectors or sockets used in the PCB industry) to permit interaction with external electronic devices (such as ultrasonic pulse generators and amplifiers).

[0316] Now refer to Fig.57A , illustrates a photograph of a wafer substrate 210 manufactured in a printed circuit board manufacturing facility. The substrate conductive material 23 (not shown) is protected by a planarization layer 40 manufactured using a standard solder mask in a PCB manufacturing facility.

[0317] Now refer to Fig.57B , showing Fig.57A2 is a photograph of a wafer substrate 210 after polishing in FIG. The substrate conductive region 24 for the bottom electrode, the substrate conductive region 25 for the top electrode, and the planarization layer 40 are polished simultaneously using a chemical mechanical polisher (CMP). As a result, a wafer substrate 210 is obtained with a polished conductive region serving as a bottom electrode 34 with a mirror-like finish, a similarly polished conductive region 35 for the top electrode, and a polished planarization layer 50.

[0318] Now refer to Fig.58A , showing the image taken using a microscope Fig.57B The mirror-like finish of the polished conductive area that serves as the bottom electrode 34 reflects some of the light from the microscope lamp.

[0319] Now refer to Fig.58B , showing Fig.58A A polished conductive region serving as a bottom electrode 34, a polished conductive region 35 for a top electrode, and a polished planarization layer 50 are shown.

[0320] Now refer to Fig.59A , showing the pin profiler for Fig.57B A profilometer is used to measure the surface roughness of the polished conductive area that serves as the bottom electrode 34.

[0321] Now refer to Fig.59B , showing that along Fig.59A The longitudinal axis of the substrate (refer to Fig.57B The 80 mm long measurement indicates the curvature or "bow" of the substrate as well as some surface roughness parameters.

[0322] Now refer to Fig.59C , showing that along Fig.59A The transverse axis of the substrate (refer to Fig.58B The 1.6 mm long measurement represents the surface profile of the polished conductive area for the top electrode 35 and the polished planarization layer 50.

[0323] Now refer to Fig.60A , shows profilometer measurements along the X and Y axis of a standard 100mm premium grade silicon wafer with an oxide layer. This was performed to measure the curvature or "bow" of a typical silicon wafer used in micromachining. The wafer bow is between 20um and 30um.

[0324] Now refer to Fig.60B , showing that along Fig.59AThe X-axis and Y-axis measurement data of the substrate in FIG. The wafer bow is between 30um and 40um, which is very similar to the bow of a standard silicon wafer. This means that the wafer substrate 210 is suitable for processing in standard micro-machining equipment.

[0325] Now refer to Fig.61A , shows the profilometer measurements along the center area of ​​a standard 100mm premium grade silicon wafer with an oxide layer. This was performed to measure the surface roughness of a typical silicon wafer used in micromachining. The wafer roughness is between 20nm and 40nm.

[0326] Now refer to Fig.61B , showing that along Fig.59A The surface roughness is between 0 nm and 30 nm, which is very similar to the surface roughness of a standard silicon wafer. This means that the wafer substrate 210 is suitable for processing using standard micro-machining equipment and can be used to directly manufacture the polyCMUT array 205.

[0327] Now refer to Fig.62A , showing that along Fig.59A The surface roughness is between -40nm and 20nm. This means that the first polymer layer 110 and the top electrode interconnect 117 can be directly patterned, as described with respect to Fig.25B discussed.

[0328] Now refer to Fig.62B , showing that along Fig.59A The profilometer measured values ​​of the area of ​​the substrate in 100um. The surface roughness was between -5nm and 5nm.

[0329] Now refer to Fig.63 , in contrast to some ringing effects of CMUTs fabricated on silicon substrates [2], any ringing effects for the fabrication method of the present non-silicon embodiment are outside the frequency range of interest due to unwanted acoustic reflections occurring in the silicon substrate that appear as notches in the frequency response. For example, Fig.55B The acoustic signal shown in has a center frequency of 7.4 MHz; for a substrate with a thickness of 1 mm, the ringing effect in the substrate will appear around 1.68 MHz. This frequency is outside the -6 dB lower frequency (around 4.0 MHz).

[0330] advantage

[0331] Poly-CMUTs made according to at least some embodiments herein have advantages over conventional silicon-based CMUTs. For example, the total manufacturing cost of a poly-CMUT can be well below $100 in many cases. Minimal and inexpensive manufacturing equipment can be used for a poly-CMUT (e.g., mask aligners, metal evaporators, critical point dryers). This is an advantage over silicon-based CMUTs, which require expensive and bulky equipment. At least some embodiments of the poly-CMUT array also have advantages such as Fig.48A , Fig.48B and Fig.48C The flexibility shown in the figures shows bendability in one (x) dimension or two (x, y) dimensions. Fig.65A , Fig.65B , Fig.65C , Fig.66A , Fig.66B and Fig.66C This advantage is illustrated in Figure 2. Polymer-based CMUTs can be fabricated on flexible substrates for wearable applications; as discussed above, the PCB can be either flexible or rigid. This cannot be achieved with silicon-based CMUTs (including Fig.37A and Fig.37B The present invention can be accomplished with silicon-based CMUT implementations) because they require a rigid substrate. Similarly, when using ceramic piezoelectric materials to manufacture CMUTs, flexible substrates cannot be used.

[0332] Another advantage of the manufacturing methods described with respect to the embodiments herein is that the multi-layer manufacturing method allows signal cables to be electrically shielded. For example, the individual traces from the CMUT elements can be protected between two ground planes to minimize electromagnetic interference (EMI).

[0333] The epoxy resin (such as FR4) used to manufacture PCBs has a low X-ray mass absorption coefficient. Therefore, the substrate can be considered to be X-ray transparent.

[0334] The application methods described in any of the embodiments are also compatible with wafer bonding fabrication techniques, such as those described in U.S. Patent Nos. 10,509,013, 10,564,132, and 10,598,632. In addition, the fabrication techniques of various embodiments herein are also compatible with more traditional chip bonding using solder bumps.

[0335] Example Applications

[0336] Now refer to Fig.64A and 64B, respectively, showing a cross-sectional front view and a cross-sectional side view of a probe assembly 251. The polyCMUT array 204 with an acoustic lens 240 and an electrical contact assembly 230 is mounted on an existing probe housing 252 containing an electrical contact mating connector 232, which is connected to an electrical interface board 234 containing a plurality of electronic components 241 (e.g., capacitors, inductors, resistors, etc.). An advantage of the manufacturing method described in any of the embodiments herein is that the assembly or repair of an ultrasound probe is greatly simplified. The manufacturing method avoids the wire bonding, packaging, and lens casting processes of conventional piezoelectric and silicon-based transducers.

[0337] Now refer to Fig.65A , Fig.65B and Fig.65C , shows that the probe assembly 251 includes a hermetically sealed probe housing 252 in which the polyCMUT array 204 is mounted. The probe housing 252 has a single channel 260 leading to an internal chamber 261. The internal chamber 261 can be filled with gas or liquid at different pressures (P1, P2 or P3). The polyCMUT array is thin enough to deflect under the pressure in the internal chamber 261. Fig.65B and Fig.65C As shown in , pressure below atmospheric pressure causes the polyCMUT array 204 to deflect inwardly toward the probe housing 252. Pressure equal to atmospheric pressure does not cause deflection, as shown in Fig.65A . Pressure above atmospheric pressure (not shown) will cause the polyCMUT array 204 to deflect outwardly away from the probe housing. Some or all of the polyCMUT elements in the polyCMUT array 204 can be operated simultaneously to generate a single ultrasonic wave 270. Depending on the deflection of the polyCMUT array 204, an unfocused ultrasonic beam 271 or a focused ultrasonic beam 272 can be obtained using a variable focus 273. In some embodiments, this may be beneficial for ultrasonic probes dedicated to therapeutic applications, where it is desired that a physically focused ultrasonic beam 272 is superior to an electronically focused ultrasonic beam to deliver relatively high acoustic energy to accelerate tissue healing.

[0338] Now refer to Fig.66A , Fig.66B and Fig.66C, shows a probe assembly 251 including a probe housing 252 to which a polyCMUT array 204 is assembled to become an ultrasound probe. The probe housing 252 has a deflection mechanism 262 attached to the back of the polyCMUT array 204. The deflection mechanism causes a vertical displacement 263 (D1, D2, and D3) that causes the polyCMUT array 204 to deflect. The polyCMUT array 204 is thin enough to be deflected by the deflection mechanism 262. Some or all of the polyCMUT elements 201 in the polyCMUT array 204 can be operated simultaneously to generate a single ultrasound wave 270. Depending on the deflection of the polyCMUT array 204, an unfocused ultrasound beam 271 or a focused ultrasound beam 272 can be obtained using a variable focus 273. In some embodiments, this may be beneficial for ultrasound probes dedicated to therapeutic applications, where a physically focused ultrasound beam 272 is expected to be superior to an electronically focused ultrasound beam to deliver relatively high acoustic energy to accelerate tissue healing.

[0339] Now refer to Fig.67 , a polyCMUT linear array 202 including polyCMUT elements 201 (not individually identified) is built on a polished substrate 30. The polished substrate 30 includes two or more substrate sub-layers 16 (not individually identified) stacked on each other. Internal vias 21 (not shown) and internal substrate conductive materials 23 (not shown) are located between the substrate sub-layers 16. One or more planar inductors 242 are fabricated on the surface of the substrate layer 16. These planar inductors 242 are capable of generating and receiving wireless signals, such as for power supply (similar to a wireless charger) or for data communication. Fig.67 A potential application of the array 202 is a completely wireless polyCMUT array 204 .

[0340] In this disclosure, the recitation of numerical ranges by endpoints include all numbers subsumed within that range, including all natural numbers, all integers, and all decimal points intermediate thereto (eg, 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5, etc.).

[0341] Reference to a value of "about" or "approximately" a quantity means that the value is within + / - 10% of that quantity, unless the context dictates otherwise.

[0342] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. Thus, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise (e.g., reference to "a via" or "the via" in a claim does not exclude embodiments using multiple vias; and reference to manufacturing a "bottom electrode" and a "top electrode" includes reference to arrays of bottom electrodes and top electrodes being manufactured). It should also be understood that the terms "comprises" and "comprising", when used in this specification, indicate the presence of one or more stated features, integers, steps, operations, elements, and components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and groups. Directional terms such as "top", "bottom", "upwardly", "downwardly", "vertically", and "laterally" are used in the following description only for the purpose of providing relative references and are not intended to imply any limitation on how any article is to be positioned during use or to be installed in an assembly or installed relative to the environment. In addition, the term "connect" and variations thereof, such as "connected," "connects," and "connecting," as used in this specification are intended to include both indirect and direct connections unless otherwise indicated. For example, if a first device is connected to a second device, the coupling may be through a direct connection or through an indirect connection via other devices and connectors. Similarly, if a first device is communicatively connected to a second device, the communication may be through a direct connection or through an indirect connection via other devices and connectors.

[0343] Phrases such as "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," and "A, B, and / or C" are intended to include both a single item in the recited list of items (i.e., only A, only B, or only C) and multiple items in the list (i.e., A and B, B and C, A and C, and A, B, and C). Thus, the phrases "at least one," "one or more," and similar phrases when used in conjunction with a list do not mean that every item in the list must be present, although every item in the list may be present.

[0344] It is contemplated that any portion of any aspect or implementation discussed in this specification may be implemented with or combined with any portion of any other aspect or implementation discussed in this specification, as long as such portions are not mutually exclusive of each other.

[0345] The scope of the claims should not be limited by the embodiments set forth in the examples above, but should be given the broadest interpretation consistent with the entire specification.

[0346] It should be appreciated that the features and aspects of the various examples provided above may be combined into additional examples that also fall within the scope of the present disclosure.In addition, the drawings are not drawn to scale and may have sizes and shapes exaggerated for illustrative purposes.

[0347] References

[0348] [1]O.Oralkan et al., "Capacitive micromachined ultrasonic transducers: Next-generation arrays for acoustic imaging?," Ultrason.Ferroelectr.Freq.Control IEEE Trans.On, vol.49, no.11, pp.1596–1610, 2002.

[0349] [2]KRChapagain, "Integration of Electronics and Mechanics in NextGeneration Ultrasound Transducers in Medical Imaging," NTNU, 2014.Accessed:Dec.21,2021.[Online].Available:https: / / ntnuopen.ntnu.no / ntnu-xmlui / handle / 11250 / 2370933.

Claims

1. A method for manufacturing a capacitive micromachined ultrasonic transducer, the method include: (i) removing a layer from a top surface of a substrate, wherein at least one pair of electrical interconnects extend at least partially through the substrate and are exposed on the top surface; (ii) depositing a first conductive material on the top surface after the removing, wherein the first conductive material covers the pair of electrical interconnects; (iii) patterning the first conductive material to form a bottom electrode and a contact region for a top electrode, wherein the bottom electrode is electrically connected to one of the pair of electrical interconnects and the contact region for the top electrode is electrically connected to the other of the pair of electrical interconnects; (iv) depositing a sacrificial material on the bottom electrode after patterning; (v) patterning the sacrificial material to form a sacrificial membrane region connected to at least one sacrificial etch channel; (vi) depositing a first polymer or silicon layer on the substrate, the bottom electrode, the contact area and the sacrificial material after the sacrificial material is patterned; (vii) patterning the first polymer or silicon layer to form at least one via leading to the at least one sacrificial etch channel; (viii) depositing a second conductive material on the first polymer or silicon layer and on the contact area for the top electrode; (ix) patterning the second conductive material to avoid electrical connection with the bottom electrode; and (x) Etching away the sacrificial film region using the at least one via.

2. The method according to claim 1, in, After the sacrificial material is patterned, depositing the first polymer layer on the substrate, the bottom electrode, the contact area for the top electrode and the sacrificial material, and the method further comprises: (i) depositing a second polymer layer on top of the second conductive material and the sacrificial film region; and (ii) patterning the second polymer layer to avoid blocking the at least one via.

3. The method according to claim 1, in, After the sacrificial material is patterned, the silicon layer is deposited over the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material.

4. The method according to any one of claims 1 to 3, in, The substrate includes a printed circuit board.

5. The method according to claim 4, in, The printed circuit board is flexible.

6. The method according to any one of claims 1 to 3, in, The substrate includes ceramic.

7. The method according to any one of claims 1 to 6, in, Removal of the layer is performed by mechanical means.

8. The method according to claim 7, in, Removing the layer includes polishing or grinding the top surface of the substrate.

9. The method according to any one of claims 1 to 6, in, Removal of the layer is accomplished chemically.

10. The method according to claim 9, in, Removing the layer includes etching the top surface of the substrate.

11. The method according to any one of claims 1 to 10, in, Prior to removing the layer, pads of conductive material electrically coupled to the pair of electrical interconnects, respectively, are on the top surface, and wherein removing the layer includes removing the pads and portions of the substrate.

12. The method according to any one of claims 1 to 11, in, After removal, the top surface has a surface roughness of no more than 50 nanometers.

13. The method according to any one of claims 1 to 12, in, The first conductive material includes a gold layer between two chromium layers.

14. The method according to any one of claims 1 to 13, in, The thickness of the first conductive material is approximately 100 nm.

15. The method according to any one of claims 1 to 14, in, The sacrificial material is approximately 200 nm thick.

16. The method according to any one of claims 1 to 15, in, Depositing the sacrificial material includes depositing a lift-off resist layer and then depositing a positive photoresist layer.

17. The method according to any one of claims 1 to 16, in, Patterning the sacrificial material is performed by wet etching using an aqueous solution including tetramethylammonium hydroxide.

18. The method according to claim 2, in, The first polymer layer is approximately 700 nm thick.

19. The method according to any one of claims 1 to 18, in, Depositing the second electrically conductive material includes depositing a titanium layer and then depositing a gold layer.

20. The method of any one of claims 1 to 19, further comprising encapsulating the transducer with an encapsulation material.

21. The method according to claim 20, in, The bottom surface of the substrate includes pads of conductive material respectively electrically coupled to the pair of electrical interconnects, and the method further includes covering the pads on the bottom surface before packaging the transducer to prevent the pads from being covered by the packaging material.

22. The method of claim 1, further comprising, after removing the layer of the top surface and before depositing the first conductive material: (i) depositing a planarization layer on the top surface; and (ii) patterning the planarization layer such that the electrical interconnects remain exposed on the top surface.

23. The method according to claim 22, in, The planarization layer is approximately 1 μm thick.

24. The method according to claim 22 or 23, in, The planarization layer includes SU-8 photoresist.

25. The method according to any one of claims 22 to 24, in, The roughness of the planarization layer does not exceed 50 nanometers.

26. The method of claim 1, further comprising, before removing the layer from the top surface of the substrate: (i) depositing a substrate conductive material on the surface of the substrate; (ii) patterning the substrate conductive material to form a substrate conductive region for the bottom electrode and a substrate conductive region for the top electrode, wherein the substrate conductive region for the bottom electrode is electrically connected to one of the pair of electrical interconnects and the other of the substrate conductive region is electrically connected to the other of the pair of electrical interconnects; and (iii) depositing a planarization layer on the substrate and the conductive regions of the substrate; wherein the substrate conductive region and the contact region for the bottom electrode are electrically connected to the same electrical interconnect, and the substrate conductive region and the contact region for the top electrode are electrically connected to the same electrical interconnect, and Wherein, the layer removed from the top surface of the substrate includes the planarization layer above the substrate conductive material.

27. The method according to claim 26, in, The planarization layer includes epoxy resin.

28. The method according to claim 26 or 27, in, The thickness of the planarization layer is equal to or greater than the thickness of the substrate conductive material.

29. The method of any one of claims 26 to 28, further comprising degassing the planarization layer after depositing the planarization layer and before removing the layer from the top surface of the substrate.

30. The method according to any one of claims 22 to 29, in, The planarization layer includes a solder resist layer of a printed circuit board.

31. The method according to claim 1, in: (i) the layer removed from the top surface of the substrate includes an upper substrate layer adhered to the substrate; (ii) between the substrate and the upper substrate layer is a substrate conductive region for the bottom electrode and a substrate conductive region for the top electrode, wherein the substrate conductive region for the bottom electrode is electrically connected to one of the pair of electrical interconnects and the other of the substrate conductive regions is electrically connected to the other of the pair of electrical interconnects; and (iii) the substrate conductive region and the contact region for the bottom electrode are electrically connected to the same electrical interconnect, and the substrate conductive region and the contact region for the top electrode are electrically connected to the same electrical interconnect.

32. The method according to any one of claims 1 to 31, in, The electrical interconnect extends non-linearly through the substrate.

33. The method according to any one of claims 1 to 32, in, The capacitive micromachined ultrasonic transducer is one of an array of capacitive micromachined ultrasonic transducers simultaneously fabricated by the method.

34. A capacitive micromachined ultrasonic transducer assembly, include: (i) a printed circuit board (PCB) comprising at least one pair of electrical interconnects extending at least partially through the PCB and exposed on a top surface of the PCB; (ii) a capacitive micromachined ultrasonic transducer unit on the PCB, wherein the capacitive micromachined ultrasonic transducer unit comprises: (A) a bottom electrode electrically connected to one of the pair of electrical interconnects on the top surface; (B) a top electrode electrically connected on the top surface to the other of the pair of electrical interconnects; (C) a polymer or silicon layer between the top electrode and the bottom electrode; and (D) A sealed cavity between the polymer or silicon layer and the bottom electrode.

35. The capacitive micromachined ultrasonic transducer assembly of claim 34, in, The PCB is flexible.

36. The capacitive micromachined ultrasonic transducer assembly of claim 34, in, The PCB includes ceramic.

37. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 36, in, The bottom electrode is directly on the PCB.

38. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 36, in, The bottom electrode is on the planarization layer.

39. The capacitive micromachined ultrasonic transducer assembly of claim 34, in, The bottom electrode is on a planarization layer, and wherein the planarization layer comprises a solder resist layer.

40. A capacitive micromachined ultrasonic transducer assembly according to claim 38 or 39, in, The bottom electrode is coplanar with a portion of a layer of the PCB.

41. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 37, in, The bottom electrode is coplanar with a portion of the planarization layer.

42. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 37, in, The bottom electrode is coplanar with a bottom portion of the polymer or silicon layer.

43. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 42, in, The capacitive micromachined ultrasonic transducer unit is one of an array of capacitive micromachined ultrasonic transducer units, wherein the array includes capacitive micromachined ultrasonic transducer elements corresponding to different groups selected from the plurality of capacitive micromachined ultrasonic transducer units, and wherein the capacitive micromachined ultrasonic transducer elements are electrically connected to the electrical interconnects, respectively.

44. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 43, in, The polymer layer is between the top electrode and the bottom electrode.

45. A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 43, in, The silicon layer is between the top electrode and the bottom electrode.

46. ​​A capacitive micromachined ultrasonic transducer assembly according to any one of claims 34 to 45, in, The electrical interconnect extends non-linearly through the substrate.

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