Array substrate, manufacturing method thereof and display device

Abstract

An array substrate, a manufacturing method thereof and a display device, the array substrate comprising: a substrate (1) having a display area (AA) and a non-display area (BB) surrounding the display area (AA); the multiple grid lines (G1, G2,..., G2N) and the multiple data lines (S1 ', S1, S2', S2,..., SN ', SN) are located on the substrate (1) and located in the display area (AA), and the multiple grid lines (G1, G2,..., G2N) and the multiple data lines (S1', S1, S2 ', S2,..., SN', SN) intersect in an insulated mode to define multiple sub-pixels (P); wherein the plurality of data lines (S1 ', S1, S2', S2,..., SN ', SN) comprise a plurality of display data lines (S1, S2,..., SN) and a plurality of dummy data lines (S1', S2 ',..., SN') which are alternately arranged along the row direction, and the adjacent dummy data lines (S1 ', S2',..., SN ') and the display data lines (S1, S2,..., SN) are respectively arranged between different sub-pixels (P); the common electrode layer (8) is located on the sides, away from the substrate (1), of the multiple grid lines (G1, G2,..., G2N) and the multiple data lines (S1 ', S1, S2', S2,..., SN ', SN), and the common electrode layer (8) is at least located in the display area (AA); the pixel electrodes (51) are located on the side, away from the substrate (1), of the common electrode layer (8), and each pixel electrode (51) is arranged in the corresponding sub-pixel (P); wherein the pixel electrode (51) is a slit electrode with a plurality of slits (511).

Description

Array substrate, manufacturing method thereof and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Liquid crystal displays are currently common flat panel displays, among which thin film transistor liquid crystal displays (TFT-LCD) are the mainstream products among liquid crystal displays.

[0003] With technological advancements, consumers are demanding higher display quality in mobile devices. Conventional TN (Twisted Nematic) LCDs are no longer able to meet market demand. Currently, major manufacturers are gradually incorporating various wide-viewing angle technologies with superior display quality into mobile devices, such as IPS (In-Plane Switching), VA (Vertical Alignment), and AD-SDS (Advanced-Super Dimensional Switching, ADS). In ADS mode, the electric field generated by the edges of the slit electrodes within the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field. This causes all aligned liquid crystal molecules within the liquid crystal cell, between the slit electrodes and directly above the electrodes, to rotate, thereby improving liquid crystal operating efficiency and increasing light transmission efficiency. As a result, ADS technology can enhance the image quality of TFT-LCDs, offering advantages such as high transmittance, wide viewing angle, high aperture ratio, low color difference, low response time, and no push mura.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The specific solutions are as follows:

[0006] An embodiment of the present disclosure provides an array substrate, comprising:

[0007] A base substrate having a display area and a non-display area surrounding the display area;

[0008] A plurality of gate lines and a plurality of data lines are located on the base substrate and within the display area, wherein the plurality of gate lines and the plurality of data lines are insulated and intersected to define a plurality of sub-pixels; wherein the plurality of data lines include a plurality of display data lines and a plurality of dummy data lines alternately arranged along a row direction, and adjacent dummy data lines and display data lines are respectively arranged between different sub-pixels;

[0009] a common electrode layer, located on a side of the plurality of gate lines and the plurality of data lines away from the base substrate, the common electrode layer being at least located in the display area;

[0010] A plurality of pixel electrodes are located on a side of the common electrode layer away from the base substrate, and each of the pixel electrodes is disposed in a corresponding sub-pixel; wherein the pixel electrode is a slit electrode having a plurality of slits.

[0011] In a possible implementation, the array substrate provided in the embodiment of the present disclosure further includes: a first insulating layer located between the gate line, the data line, and the common electrode layer; a second insulating layer located between the common electrode layer and the pixel electrode; and a thin film transistor located between the base substrate and the first insulating layer and provided in each sub-pixel; wherein,

[0012] The thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode stacked in sequence between the base substrate and the first insulating layer, wherein the gate electrode is close to the base substrate; the gate line is provided in the same layer as the gate electrode and is electrically connected to the gate electrode; the data line is provided in the same layer as the source electrode and the drain electrode and is electrically connected to the source electrode;

[0013] The pixel electrode is electrically connected to the drain electrode through a first via hole penetrating the second insulating layer and the first insulating layer.

[0014] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the common electrode layer is a planar electrode arranged on the entire surface, and the common electrode layer has a plurality of second via holes, the second via holes are arranged in a one-to-one correspondence with the first via holes, and the orthographic projection of the first via hole on the base substrate is located within the range of the orthographic projection of the second via hole on the base substrate.

[0015] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, both the first insulating layer and the second insulating layer are inorganic insulating layers.

[0016] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the non-display area includes: a common electrode ring disposed in the same layer as the data line and surrounding the display area, and an overlapping portion disposed in the same layer as the pixel electrode; wherein:

[0017] One end of the overlap portion is electrically connected to the common electrode ring through a third via hole penetrating the second insulating layer and the first insulating layer, and the other end of the overlap portion is electrically connected to a portion of the common electrode layer extending to the non-display area through a fourth via hole penetrating the second insulating layer.

[0018] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the first insulating layer is an organic insulating layer, and the second insulating layer is an inorganic insulating layer.

[0019] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the non-display area includes: a common electrode ring disposed in the same layer as the data line and surrounding the display area, and an overlapping portion disposed in the same layer as the pixel electrode; wherein:

[0020] The overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through a fourth via hole penetrating the second insulating layer, and the portion of the common electrode layer extending to the non-display area is electrically connected to the common electrode ring through a fifth via hole penetrating the first insulating layer.

[0021] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the dummy data line extends to the non-display area and is electrically connected to the common electrode ring.

[0022] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the plurality of sub-pixels are arranged in a multi-row and multi-column array, and the sources of the two columns of thin film transistors on both sides of each display data line are electrically connected to the display data line;

[0023] Two gate lines are provided on both sides of each row of sub-pixels along the column direction, and the gate electrodes of the thin film transistors of each row of sub-pixels are alternately electrically connected to the two gate lines.

[0024] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the sub-pixels in the same column have the same luminous color, and the sub-pixels in the same row include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a circular pattern along the row direction, and the luminous color of the first sub-pixel, the luminous color of the second sub-pixel, and the luminous color of the third sub-pixel are different.

[0025] In a possible implementation, in the array substrate provided in the embodiment of the present disclosure, the material of the common electrode layer and the material of the pixel electrode are both transparent conductive materials.

[0026] Correspondingly, an embodiment of the present disclosure also provides a display device, including a display panel, wherein the display panel includes an array substrate and an opposing substrate arranged opposite to each other, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate, and the array substrate is any one of the array substrates described above provided in the embodiment of the present disclosure.

[0027] Accordingly, an embodiment of the present disclosure further provides a method for manufacturing an array substrate, comprising:

[0028] Providing a base substrate, the base substrate having a display area and a non-display area surrounding the display area;

[0029] forming a plurality of gate lines and a plurality of data lines in a display area of ​​the base substrate, wherein the plurality of gate lines and the plurality of data lines are insulated and cross-linked to define a plurality of sub-pixels;

[0030] forming a common electrode layer at least located in the display area on a side of the plurality of gate lines and the plurality of data lines away from the base substrate;

[0031] A pixel electrode is formed in each sub-pixel on a side of the common electrode layer away from the base substrate; wherein the pixel electrode is a slit electrode having a plurality of slits.

[0032] In a possible implementation, in the above-mentioned manufacturing method provided in an embodiment of the present disclosure, a plurality of gate lines and a plurality of data lines are formed in the display area of ​​the base substrate, specifically: a plurality of gate lines are formed on the base substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the base substrate;

[0033] While forming the plurality of data lines, the method also includes forming a source electrode and a drain electrode in each of the sub-pixels and forming a common electrode ring in the non-display area;

[0034] After forming the plurality of data lines and before forming the common electrode layer, the method further includes depositing a first insulating layer on a side of the plurality of data lines away from the base substrate; wherein the first insulating layer is an inorganic insulating layer;

[0035] Forming the common electrode layer specifically includes: depositing a first transparent conductive layer on a side of the first insulating layer facing away from the base substrate, and patterning the first transparent conductive layer to form the common electrode layer having a plurality of second via holes, wherein the second via holes are arranged corresponding to the drain electrodes;

[0036] After forming the common electrode layer and before forming the pixel electrode, the method further includes depositing a second insulating layer on a side of the common electrode layer facing away from the base substrate, wherein the second insulating layer is an inorganic insulating layer; and patterning the first insulating layer and the second insulating layer using a single patterning process to respectively form: a plurality of first via holes arranged in one-to-one correspondence with the drain electrodes, a third via hole arranged corresponding to the common electrode ring, and a fourth via hole arranged corresponding to a portion of the common electrode layer extending to the non-display area; the orthographic projections of the first via holes on the base substrate are within the range of the orthographic projections of the second via holes on the base substrate;

[0037] Forming the pixel electrode specifically includes: depositing a second transparent conductive layer on the side of the second insulating layer facing away from the base substrate, patterning the second transparent conductive layer to form the pixel electrode and forming an overlapping portion located in the non-display area; wherein, one end of the overlapping portion is electrically connected to the common electrode ring through the third via hole, and the other end of the overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through the fourth via hole.

[0038] In a possible implementation, in the above-mentioned manufacturing method provided in an embodiment of the present disclosure, a plurality of gate lines and a plurality of data lines are formed in the display area of ​​the base substrate, specifically: a plurality of gate lines are formed on the base substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the base substrate;

[0039] While forming the plurality of data lines, the method also includes forming a source electrode and a drain electrode in each of the sub-pixels and forming a common electrode ring in the non-display area;

[0040] After forming the plurality of data lines and before forming the common electrode layer, the method further includes forming a first insulating layer on a side of the plurality of data lines facing away from the base substrate using a single patterning process; wherein the first insulating layer is an organic insulating layer and has first sub-via holes arranged in one-to-one correspondence with the drain electrodes and fifth via holes arranged in correspondence with the common electrode ring;

[0041] Forming the common electrode layer specifically includes: depositing a first transparent conductive layer on a side of the first insulating layer facing away from the base substrate, patterning the first transparent conductive layer to form the common electrode layer having a plurality of second via holes, wherein the second via holes are arranged corresponding to the drain electrodes; wherein a portion of the common electrode layer extending to the non-display area is electrically connected to the common electrode ring through the fifth via hole;

[0042] After forming the common electrode layer and before forming the pixel electrode, the method further includes forming a second insulating layer on a side of the common electrode layer facing away from the base substrate using a single patterning process; wherein the second insulating layer is an inorganic insulating layer, and has: a plurality of second sub-via holes arranged in a one-to-one correspondence with the first sub-via holes, and a fourth via hole arranged corresponding to a portion of the common electrode layer extending to the non-display area; the second sub-via holes and the first sub-via holes constitute a first via hole, and the orthographic projection of the first via hole on the base substrate is within the range of the orthographic projection of the second via hole on the base substrate;

[0043] The formation of the pixel electrode specifically includes: depositing a second transparent conductive layer on the side of the second insulating layer facing away from the base substrate, patterning the second transparent conductive layer to form the pixel electrode and forming an overlapping portion located in the non-display area; wherein the overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through the fourth via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic diagram of a layout of an array substrate in a conventional ADS mode liquid crystal display panel;

[0045] FIG2 is a schematic diagram of the layout corresponding to a sub-pixel in FIG1 ;

[0046] FIG3 is a schematic cross-sectional view corresponding to FIG2 ;

[0047] FIG4 is a plan view of an array substrate provided in an embodiment of the present disclosure;

[0048] FIG5 is a schematic diagram of the layout corresponding to the display area in FIG4 ;

[0049] FIG6 is a schematic diagram of the layout corresponding to a sub-pixel in FIG5 ;

[0050] FIG7 is a schematic cross-sectional view corresponding to FIG6 ;

[0051] FIG8 is another cross-sectional schematic diagram corresponding to FIG6;

[0052] FIG9 is a plan view of the common electrode layer in FIG5 ;

[0053] FIG10 is a schematic diagram of a manufacturing process flow corresponding to the array substrate shown in FIG7 ;

[0054] FIG11 is a schematic diagram of a layout within the dotted box E in FIG4 ;

[0055] FIG12 is a cross-sectional view within the dotted frame F in FIG11 ;

[0056] FIG13 is a schematic diagram of a manufacturing process flow of the array substrate shown in FIG8 ;

[0057] FIG14 is a schematic diagram of another layout within the dotted box E in FIG4 ;

[0058] FIG15 is a schematic cross-sectional view within the dotted frame F in FIG14 ;

[0059] FIG16 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

[0060] FIG17 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0064] As shown in Figures 1 to 3, Figure 1 is a layout diagram of an array substrate in a conventional ADS mode liquid crystal display panel, Figure 2 is a layout diagram corresponding to a sub-pixel in Figure 1, and Figure 3 is a cross-sectional diagram corresponding to Figure 2. The array substrate includes: a base substrate 1, and a gate layer 2, a gate insulating layer 3, an active layer 4, a pixel electrode layer 5, a source-drain electrode layer 6, a first insulating layer 7, and a common electrode layer 8 stacked sequentially on the base substrate 1, wherein the gate layer 2 includes a gate 21 and gate lines (G1, G2...G2N), and the source-drain electrode layer 6 includes a source 61, a drain 62, and data lines (S1', S1, S2', S2...SN', SN), the gate lines (G1, G2...G2N) and the data lines (S1', S1, S2', S2...SN', SN) are insulated and cross-defined to form a plurality of sub-pixels P, the gate 21, the active layer 4, the source 61 and the drain 62 constitute a thin film transistor T arranged in each sub-pixel P, the pixel electrode layer 5 includes a pixel electrode 51 arranged in each sub-pixel P, the pixel electrode 51 and the drain 62 are located in the same plane and are in direct contact and electrically connected, the common electrode layer 8 is a planar electrode, and the common electrode layer 8 is a slit electrode with a slit 81 in the area corresponding to each pixel electrode 51, the source 61 is electrically connected to the corresponding data line, and the gate 21 is electrically connected to the corresponding gate line. Since the pixel electrode 51 and the drain electrode 62 are located in the same plane, there is a large coupling capacitance between the pixel electrode 51 and the data lines on both sides of it. In order to reduce the coupling capacitance in the related art, it is necessary to design the two sides of the pixel electrode 51 to be away from the data lines. Therefore, the size of the pixel electrode 51 is relatively reduced, and the number of slits 81 on the common electrode layer 8 corresponding to the pixel electrode 51 is also reduced. In this way, the electric field strength generated by the edge of the slit 81 in the same plane and the electric field strength generated between the pixel electrode 51 and the common electrode layer 8 will be reduced, so that the deflection degree of the liquid crystal molecules is reduced, thereby reducing the light transmittance efficiency of the liquid crystal display panel.

[0065] In view of this, in order to improve the transmittance of a liquid crystal display panel, an embodiment of the present disclosure provides an array substrate, as shown in Figures 4 to 8. Figure 4 is a plan view of the array substrate, Figure 5 is a layout view corresponding to the display area in Figure 4, Figure 6 is a layout view corresponding to a sub-pixel in Figure 5, Figure 7 is a cross-sectional view corresponding to Figure 6, and Figure 8 is another cross-sectional view corresponding to Figure 6. The array substrate includes:

[0066] The base substrate 1 has a display area AA and a non-display area BB surrounding the display area AA;

[0067] A plurality of gate lines (G1, G2...G2N) and a plurality of data lines (S1', S1, S2', S2...SN', SN) are located on a base substrate 1 and within a display area AA. The plurality of gate lines (G1, G2...G2N) and the plurality of data lines (S1', S1, S2', S2...SN', SN) are insulated and intersect with each other to define a plurality of sub-pixels P. The plurality of data lines (S1', S1, S2', S2...SN', SN) include a plurality of display data lines (S1, S2...SN) alternately arranged along a row direction and a plurality of dummy data lines (S1', S2'...SN'), and adjacent dummy data lines (e.g., S1') and display data lines (e.g., S1) are respectively arranged between different sub-pixels P.

[0068] A common electrode layer 8 is located on a side of the plurality of gate lines (G1, G2, ..., G2N) and the plurality of data lines (S1', S1, S2', S2, ..., SN', SN) facing away from the base substrate 1. The common electrode layer 8 is located at least in the display area AA.

[0069] A plurality of pixel electrodes 51 are located on a side of the common electrode layer 8 facing away from the base substrate 1 . Each pixel electrode 51 is disposed in a corresponding sub-pixel P. The pixel electrode 51 is a slit electrode having a plurality of slits 511 .

[0070] The array substrate provided in the embodiment of the present disclosure reduces coupling between the pixel electrode and the data line by disposing the pixel electrode on the side of the common electrode layer facing away from the base substrate. This reduces coupling between the pixel electrode and the data line, eliminating the need to dispose the pixel electrode near the data line. This allows for larger pixel electrodes within each sub-pixel. Compared to sub-pixels of the same size in related art, the pixel electrode within each sub-pixel in the present disclosure is larger. Consequently, with the same slit width, each sub-pixel in the present disclosure can have more slits. This increases the electric field strength generated by the slit edges and the electric field strength between the pixel electrode and the common electrode layer within the same plane, thereby increasing the degree of deflection of liquid crystal molecules and improving the transmittance of the liquid crystal display panel. Furthermore, the data lines in the present disclosure include display data lines and dummy data lines. The display data lines are used to provide data signals to the pixel electrodes. The dummy data lines, along with the display data lines and gate lines, define sub-pixels and can be connected to the common electrode layer to reduce the resistance of the common signal.

[0071] Optionally, the pixel electrodes provided in the embodiments of the present disclosure may be comb-shaped electrodes, strip-shaped electrodes, etc., as long as they are electrode structures with slits. Specifically, slits are provided in the pixel electrodes so that a horizontal electric field that drives the liquid crystal to rotate can be generated at the edges of the slit electrodes.

[0072] In a specific implementation, the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 5 to 8, also includes: a first insulating layer 7 located between the gate lines (G1, G2...G2N), the data lines (S1', S1, S2', S2...SN', SN) and the common electrode layer 8, a second insulating layer 9 located between the common electrode layer 8 and the pixel electrode 51, and a thin film transistor T located between the base substrate 1 and the first insulating layer 7 and arranged in each sub-pixel P; specifically, since there are the first insulating layer 7 and the second insulating layer 9 between the pixel electrode 51 and the data line, the coupling between the pixel electrode 51 and the data line is relatively small. Therefore, when manufacturing the pixel electrode 51, the present disclosure can make the size of the pixel electrode 51 larger than the size of the pixel electrode 51 in the related art, thereby improving the transmittance.

[0073] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, as shown in FIG5 to FIG8 , the thin film transistor T includes a gate 21, a gate insulating layer 3, an active layer 4, a source electrode 61, and a drain electrode 62, which are sequentially stacked between a base substrate 1 and a first insulating layer 7, wherein the gate 21 is close to the base substrate 1; gate lines (G1, G2, ..., G2N) are provided in the same layer as the gate 21 and are electrically connected thereto; data lines (S1', S1, S2', S2, ..., SN', SN) are provided in the same layer as the source electrode 61 and the drain electrode 62 and are electrically connected thereto; wherein the gate line and the gate 21 are located in the gate layer 2, and the source electrode 61, the drain electrode 62, and the data line are located in the source-drain electrode layer 6;

[0074] The pixel electrode 51 is electrically connected to the drain electrode 62 through a first via hole V1 penetrating the second insulating layer 9 and the first insulating layer 7 .

[0075] Optionally, the embodiment of the present disclosure takes the thin film transistor T as a bottom-gate structure as an example, but it can also be a top-gate structure.

[0076] In a specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figures 5 to 9, Figure 9 is a planar schematic diagram of the common electrode layer 8 in Figure 5. The common electrode layer 8 can be a planar electrode provided on the entire surface. The common electrode layer 8 has a plurality of second via holes V2. The second via holes V2 are provided in a one-to-one correspondence with the first via holes V1, and the orthographic projection of the first via holes V1 on the base substrate 1 is located within the orthographic projection range of the second via holes V2 on the base substrate 1. In this way, the pixel electrode 51 can be electrically connected to the drain electrode 62 through the first via holes V1 and the second via holes V2.

[0077] In a specific implementation, in order to further improve transmittance, in the above array substrate provided by the embodiment of the present disclosure, the material of the common electrode layer and the material of the pixel electrode can both be transparent conductive materials, such as ITO, but of course not limited thereto.

[0078] In a specific implementation, in the above array substrate provided in the embodiment of the present disclosure, as shown in FIG7 , the first insulating layer 7 and the second insulating layer 9 may both be inorganic insulating layers (eg PVX). The manufacturing process is shown in FIG10 , and the specific process steps include: (1) using a first mask to form a gate layer (represented by G) on the base substrate 2; (2) depositing a gate insulating layer (represented by GI) on the entire surface of the gate layer; (3) using a second mask to form an active layer (represented by Act) on the gate insulating layer; (4) using a third mask to form a source-drain electrode layer (represented by SD) on the active layer; (5) depositing a first insulating layer (represented by PVX1) on the entire surface of the source-drain electrode layer; (6) using a fourth mask to form a common electrode layer (represented by 1ITO) on the first insulating layer; (7) depositing a second insulating layer (represented by PVX2) on the entire surface of the common electrode layer, and using a fifth mask to simultaneously open holes in the first insulating layer and the second insulating layer to form a first via hole V1; (8) using a sixth mask to form a pixel electrode (represented by 2ITO) on the second insulating layer. Compared with the manufacturing process shown in FIG. 3 in the related art, the manufacturing process shown in FIG. 7 adds the deposition of the second insulating layer and changes the process sequence of 1ITO, so the present disclosure does not increase the manufacturing cost.

[0079] In a specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG4 , FIG11 and FIG12 , FIG11 is a layout schematic diagram within the dotted box E in FIG4 , and FIG12 is a cross-sectional schematic diagram within the dotted box F in FIG11 , the non-display area BB includes: a common electrode ring 10 provided on the same layer as the data lines (S1′, S1, S2′, S2 . . . SN′, SN) and surrounding the display area AA, and a lap portion 11 provided on the same layer as the pixel electrode 51; wherein,

[0080] Since the first insulating layer 7 and the second insulating layer 9 in the present disclosure use a mask, in order not to increase the mask, the common electrode ring 10 cannot be directly connected to the common electrode layer 8 through the via hole penetrating the first insulating layer 7, so two types of via holes are required for jump connection, that is, one end of the overlapping portion 11 is electrically connected to the common electrode ring 10 through the third via hole V3 penetrating the second insulating layer 9 and the first insulating layer 7, and the other end of the overlapping portion 11 is electrically connected to the part of the common electrode layer 8 extending to the non-display area BB through the fourth via hole V4 penetrating the second insulating layer 9. In this way, the first insulating layer 7 and the second insulating layer 9 can be opened at the same time through a mask to form a first via hole V1 in the display area AA, and a third via hole V3 and a fourth via hole V4 in the non-display area BB.

[0081] In a specific implementation, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG8 , the first insulating layer 7 may be an organic insulating layer (e.g., resin material, Resin), and the second insulating layer 9 may be an inorganic insulating layer (PVX). Specifically, since the thickness of the organic insulating layer is generally thicker than that of the inorganic insulating layer, for example, the thickness of the organic insulating layer is The thickness of the inorganic insulating layer is less than Therefore, the first insulating layer 7 disclosed in the present invention uses organic materials, which can further reduce parasitic capacitances such as Cgs, Cgc (parasitic capacitance between the gate and the common electrode ring), and Cdc (parasitic capacitance between the drain and the common electrode ring), thereby enhancing the overall optical reliability of the liquid crystal display panel. The manufacturing process flow of the array substrate shown in Figure 8 is shown in Figure 13, and the specific process steps include: (1) using a first mask to form a gate layer (represented by G) on the base substrate 2; (2) depositing a gate insulating layer (represented by GI) on the entire surface of the gate layer; (3) using a second mask to form an active layer (represented by Act) on the gate insulating layer; (4) using a third mask to form a source-drain electrode layer (represented by SD) on the active layer; (5) using a fourth mask to form a first insulating layer (represented by Res) on the source-drain electrode layer; (6) using a fifth mask to form a common electrode layer (represented by 1ITO) on the first insulating layer; (7) using a sixth mask to form a second insulating layer (represented by PVX2) on the common electrode layer; (8) using a seventh mask to form a pixel electrode (represented by 2ITO) on the second insulating layer.

[0082] In a specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG14 and FIG15 , FIG14 is another layout schematic diagram within the dotted box E in FIG4 , and FIG15 is a cross-sectional schematic diagram within the dotted box F in FIG14 , the non-display area BB includes: a common electrode ring 10 provided on the same layer as the data lines (S1′, S1, S2′, S2 . . . SN′, SN) and surrounding the display area AA, and a lap portion 10 provided on the same layer as the pixel electrode 51; wherein,

[0083] The overlapping portion 10 is electrically connected to the portion of the common electrode layer 8 extending into the non-display area BB via a fourth via V4 penetrating the second insulating layer 9. The portion of the common electrode layer 8 extending into the non-display area BB is electrically connected to the common electrode ring 10 via a fifth via V5 penetrating the first insulating layer 7. Specifically, since the bonding area pad of the non-display area BB is generally bonded to a material such as 2ITO and an FPC, the present disclosure allows the overlapping portion 10 to be fabricated simultaneously with the bonding area pad, thereby reducing resistance and improving signal transmission.

[0084] In specific implementation, in order to reduce the resistance of the common electrode signal, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figures 5, 10 and 13, the dummy data lines (S1', S2'...SN') extend to the non-display area BB and are electrically connected to the common electrode ring 10.

[0085] As market competition for consumer display products intensifies, the pursuit of both low cost and extreme performance is underway. Transmittance (Tr.) is a key indicator for evaluating display product performance. Currently, the PPI (pixel resolution) of LCD panels for wearables, scanners, and industrial control applications is concentrated between 200 and 330. To achieve low cost and minimized bezels, these panels generally utilize smaller driver ICs that support a dual-gate (each row of pixels is driven by two rows of scan lines) drive architecture. Therefore, in the array substrate provided in the present embodiment, as shown in FIG5 , multiple sub-pixels P are arranged in a multi-row, multi-column array. The source electrodes 61 of the two columns of thin-film transistors T on either side of each display data line (S1, S2, ..., SN) are electrically connected to the display data line (S1, S2, ..., SN).

[0086] Two gate lines are set on both sides of each row of sub-pixels P along the column direction, for example, gate lines G1 and G2 are set on both sides of the first row of sub-pixels P along the column direction, gate lines G3 and G4 are set on both sides of the second row of sub-pixels P along the column direction, and gate lines G5 and G6 are set on both sides of the third row of sub-pixels P along the column direction...; the gate electrodes 21 of each thin film transistor T of each row of sub-pixels P are alternately electrically connected to the two gate lines, for example, the gate electrodes 21 of each thin film transistor T of the first row of sub-pixels P are alternately electrically connected to the gate lines G1 and G2, the gate electrodes 21 of each thin film transistor T of the second row of sub-pixels P are alternately electrically connected to the gate lines G3 and G4, and the gate electrodes 21 of each thin film transistor T of the third row of sub-pixels P are alternately electrically connected to the gate lines G5 and G6... Specifically, while the aforementioned dual-gate drive architecture can reduce the space for routing the data lines in the lower frame's extension direction and reduce the number of driver ICs, it sacrifices the pixel's aperture ratio (AR). However, the present disclosure utilizes a pixel structure in which the pixel electrode 51 is above the common electrode layer 8, which can improve transmittance. Therefore, compared to the dual-gate drive architecture in related art, the present disclosure can reduce the number of driver ICs while still meeting transmittance requirements.

[0087] Optionally, the array substrate provided in the embodiment of the present disclosure may also be a single gate driving architecture or a triple gate driving architecture.

[0088] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, as shown in FIG5 , the sub-pixels P in the same column emit the same color, and the sub-pixels P in the same row include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 that are sequentially arranged in a row direction. The color of the first sub-pixel P1, the color of the second sub-pixel P2, and the color of the third sub-pixel P3 are different. Optionally, the color of the first sub-pixel P1 is red (R), the color of the second sub-pixel P2 is green (G), and the color of the third sub-pixel P3 is blue (B).

[0089] In current LCD products, to prevent liquid crystal polarization, the polarity of the pixel voltage undergoes periodic alternating positive and negative polarity around a common voltage during normal operation. However, when the gate voltage switches from the on-state high level VGH to the off-state low level VGL, the presence of parasitic capacitance causes the data line voltage ultimately applied to the pixel to shift from the initial voltage, i.e., the feed-through voltage (ΔVp). This ΔVp causes the positive and negative pixel voltages to shift in one direction, resulting in an asymmetric voltage difference between the two and the common voltage. This can cause severe flicker in LCD panels, which not only reduces product quality but also causes visual fatigue and even dizziness.

[0090] As shown in Figures 2, 3, 6-8, for example, the display product sizes corresponding to the related art and the present disclosure are 1.3 inches respectively, and the sub-pixel P sizes of the two are the same, but due to the coupling effect between the pixel electrode 51 and the data line in the related art, the size of the pixel electrode 51 in the related art is smaller than the size of the pixel electrode 51 in the present disclosure. When the slit widths in the two are the same and the branch electrode widths between adjacent slits are the same, for the pixel structure design in the related art shown in Figures 2 and 3, the number of branch electrodes of the common electrode layer 8 and the number of slits 81 are, for example, 3 and 4 respectively; for the pixel structure design in the present disclosure shown in Figures 6-8, since the size of the pixel electrode 51 is larger, for example, the number of branch electrodes of the pixel electrode 51 and the number of slits 511 can be, for example, 4 and 5 respectively. The pixel electrode 51 and the common electrode layer 8 form a storage capacitor Cst. According to the storage capacitor formula The only difference between the pixel designs in the related art and the present disclosure is the area S of the pixel electrode 51. As can be seen from the number of branch electrodes, the area S of the pixel electrode 51 corresponding to the pixel structure design of the present disclosure is larger. Therefore, the storage capacitor Cst in the present disclosure is larger than the storage capacitor Cst in the related art. Among them, VGH is the high-level signal of the gate, VGL is the low-level signal of the gate, Clc is the liquid crystal capacitor, Cst is the pixel storage capacitor, and Cgs is the coupling capacitor formed by the overlap of the gate and source. The degree of flicker is positively correlated with △Vp. The smaller △Vp is, the lower the flicker risk is. For the pixel structure designs shown in Figures 2 and 6, the Clc value is the same because of the same sub-pixel size and LC model; the pixel structure design shown in Figure 2 corresponds to Cgs = 5fF (dielectric layer thickness ), the thin film transistor design shown in FIG6 is compared with FIG2, because the pixel electrode 51 is connected to the drain 62 through the first via hole V1, FIG6 increases the overlap capacitance between the pixel electrode 51 and the gate 21 (the thickness of the dielectric layer in the middle ), the pixel structure design shown in Figure 6 corresponds to Cgs = 6fF. Since the increment of Cgs is much lower than the increment of Cst, the flicker risk corresponding to the pixel structure provided by the present disclosure is lower than the flicker risk corresponding to the pixel structure in the related art.

[0091] For product design, in addition to avoiding Flicker, there is also crosstalk avoidance. The crosstalk evaluation index can be based on the formula: Where Cpd is the total coupling capacitance between the pixel electrode and the data line, Cpd1 is the coupling capacitance between the pixel electrode and the most adjacent data line, Cpd2 is the coupling capacitance between the pixel electrode and the next-next-adjacent data line, Vd1*-Vd1 is the data voltage difference between the data line most adjacent to the pixel electrode in two adjacent frames, and Vd2*-Vd2 is the data voltage difference between the data line next-next-adjacent to the pixel electrode in two adjacent frames. ΔV represents the pull of the visual pixel signal by adjacent pixels. The smaller ΔV, the smaller the degree of crosstalk. Therefore, the ΔV formula shows that increasing Cst and decreasing Cpd in design are beneficial for reducing crosstalk. Since the storage capacitor Cst in the present disclosure is larger than the storage capacitor Cst in the related art, and as shown in Figures 3 and 7, the pixel electrode 51 and the data line in Figure 3 are located in the same plane (i.e., belong to the same layer), while the pixel electrode 51 and the data line in Figure 6 do not belong to the same layer, and the coupling between them is smaller, the Cpd formed by the pixel structure shown in Figure 3 is much larger than the Cpd formed by the pixel structure shown in Figure 6. In summary, the pixel structure design provided by the present disclosure is superior to the pixel structure design in the related art in preventing crosstalk.

[0092] It should be noted that the pixel structure design of the array substrate provided in the present disclosure is applicable to Single Gate, Dual Gate, and Triple Gate pixel architecture products, but is not limited to the product size, shape (round & R corner & square) and product type (wearable, industrial control, furniture medical, etc.).

[0093] In summary, the array substrate provided by the embodiment of the present disclosure has the same aperture ratio (AR) as conventional pixels (structure shown in FIG3 ), but the number of slits in the pixel electrode of the present disclosure is increased (for example, by one). Optical simulations have shown that, under the same conditions as color gamut and pixel resolution, the transmittance of the liquid crystal display panel in which the array substrate of the present disclosure is located can be increased from 4.2% in the related art to 5.1%. Furthermore, the pixel solution of the present disclosure not only does not increase the number of masks, but also optimizes the flicker and crosstalk reliability capabilities of liquid crystal display products compared to conventional pixels (structure shown in FIG3 ).

[0094] In specific implementation, the array substrate provided in the embodiment of the present disclosure may further include other functional structures well known to those skilled in the art, which will not be described in detail here.

[0095] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for manufacturing an array substrate, as shown in FIG16 , comprising:

[0096] S1601, providing a base substrate, wherein the base substrate has a display area and a non-display area surrounding the display area;

[0097] S1602, forming a plurality of gate lines and a plurality of data lines in a display area of ​​the base substrate, wherein the plurality of gate lines and the plurality of data lines are insulated and cross-linked to define a plurality of sub-pixels;

[0098] S1603, forming a common electrode layer at least located in the display area on a side of the plurality of gate lines and the plurality of data lines facing away from the base substrate;

[0099] S1604 , forming a pixel electrode disposed in each sub-pixel on a side of the common electrode layer facing away from the base substrate; wherein the pixel electrode is a slit electrode having a plurality of slits.

[0100] The manufacturing method of the above-mentioned array substrate provided by the embodiment of the present disclosure reduces the coupling between the pixel electrode and the data line by manufacturing the pixel electrode on the side of the common electrode layer facing away from the base substrate, so that the pixel electrode and the data line are not in the same plane. Therefore, the side of the pixel electrode close to the data line does not need to be arranged away from the data line. In this way, a pixel electrode with a larger size can be designed in each sub-pixel as much as possible. Compared with the sub-pixels of the same size in the related art, the size of the pixel electrode in each sub-pixel in the present disclosure is larger. In this way, when the slit width is consistent, the number of slits corresponding to each sub-pixel in the present disclosure can be greater. Therefore, the electric field strength generated by the slit edge in the same plane and the electric field strength generated between the pixel electrode and the common electrode layer will increase, so that the deflection degree of the liquid crystal molecules will increase, thereby improving the transmittance of the liquid crystal display panel.

[0101] In a specific implementation, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, when forming the array substrate shown in FIG7 , a plurality of gate lines and a plurality of data lines are formed in the display area of ​​the base substrate, specifically: a plurality of gate lines are formed on the base substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the base substrate;

[0102] The process also includes forming a source electrode and a drain electrode in each sub-pixel and forming a common electrode ring in a non-display area while forming a plurality of data lines;

[0103] After forming the plurality of data lines and before forming the common electrode layer, the method further includes depositing a first insulating layer on a side of the plurality of data lines facing away from the base substrate; wherein the first insulating layer is an inorganic insulating layer;

[0104] Forming the common electrode layer specifically includes: depositing a first transparent conductive layer on a side of the first insulating layer facing away from the base substrate, patterning the first transparent conductive layer to form a common electrode layer having a plurality of second via holes, wherein the second via holes are arranged corresponding to the drain electrodes;

[0105] After forming the common electrode layer and before forming the pixel electrode, the method further includes depositing a second insulating layer on a side of the common electrode layer facing away from the base substrate, wherein the second insulating layer is an inorganic insulating layer; and patterning the first insulating layer and the second insulating layer using a single patterning process to respectively form: a plurality of first via holes arranged in one-to-one correspondence with the drain electrodes, a third via hole arranged corresponding to the common electrode ring, and a fourth via hole arranged corresponding to a portion of the common electrode layer extending to the non-display area; the orthographic projections of the first via holes on the base substrate are within the range of the orthographic projections of the second via holes on the base substrate;

[0106] The formation of the pixel electrode specifically includes: depositing a second transparent conductive layer on the side of the second insulating layer facing away from the base substrate, patterning the second transparent conductive layer to form a pixel electrode and forming an overlapping portion located in the non-display area; wherein, one end of the overlapping portion is electrically connected to the common electrode ring through a third via hole, and the other end of the overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through a fourth via hole.

[0107] Specifically, the manufacturing process flow of forming the array substrate shown in FIG. 7 can be seen in FIG. 10 , which will not be described in detail here.

[0108] In a specific implementation, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, when forming the array substrate shown in FIG8 , a plurality of gate lines and a plurality of data lines are formed in the display area of ​​the base substrate, specifically: a plurality of gate lines are formed on the base substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the base substrate;

[0109] The process also includes forming a source electrode and a drain electrode in each sub-pixel and forming a common electrode ring in a non-display area while forming a plurality of data lines;

[0110] After forming the plurality of data lines and before forming the common electrode layer, the method further includes forming a first insulating layer on a side of the plurality of data lines facing away from the base substrate using a single patterning process; wherein the first insulating layer is an organic insulating layer and has first sub-via holes arranged in a one-to-one correspondence with the drain electrodes and fifth via holes arranged in a corresponding correspondence with the common electrode ring;

[0111] Forming the common electrode layer specifically includes: depositing a first transparent conductive layer on a side of the first insulating layer facing away from the base substrate, patterning the first transparent conductive layer to form a common electrode layer having a plurality of second via holes, wherein the second via holes are arranged corresponding to the drain electrodes; wherein a portion of the common electrode layer extending to the non-display area is electrically connected to the common electrode ring through a fifth via hole;

[0112] After forming the common electrode layer and before forming the pixel electrode, the method further includes forming a second insulating layer on a side of the common electrode layer facing away from the base substrate using a single patterning process; wherein the second insulating layer is an inorganic insulating layer, and has: a plurality of second sub-via holes arranged in a one-to-one correspondence with the first sub-via holes, and a fourth via hole arranged corresponding to a portion of the common electrode layer extending to the non-display area; the second sub-via holes and the first sub-via holes constitute a first via hole, and an orthographic projection of the first via hole on the base substrate is within the range of an orthographic projection of the second via hole on the base substrate;

[0113] The formation of the pixel electrode specifically includes: depositing a second transparent conductive layer on the side of the second insulating layer facing away from the base substrate, composing the second transparent conductive layer to form a pixel electrode and forming an overlapping portion located in the non-display area; wherein the overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through a fourth via hole.

[0114] Specifically, the manufacturing process flow for forming the array substrate shown in FIG8 can be referred to FIG13 , which will not be described in detail here.

[0115] It should be noted that in the above-mentioned array substrate manufacturing method provided in the embodiments of the present disclosure, the manufacturing process may include only photolithography, or may include photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern. Photolithography refers to a process that uses photoresist, a mask, an exposure machine, etc. to form a pattern, including film formation, exposure, and development processes. In specific implementations, the corresponding patterning process can be selected based on the structure formed in the present disclosure.

[0116] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising a display panel, the display panel comprising an array substrate and an opposing substrate disposed oppositely, and a liquid crystal layer interposed between the array substrate and the opposing substrate. The array substrate is the aforementioned array substrate provided in embodiments of the present disclosure. The principles underlying the problem solved by this display device are similar to those of the aforementioned array substrate. Therefore, the implementation of this display device can refer to the implementation of the aforementioned array substrate, and any overlaps will not be repeated here.

[0117] In a specific implementation, the opposite substrate is a color filter substrate (CF) having a color filter and a black matrix.

[0118] In specific implementation, the display device provided in the embodiment of the present disclosure also includes other functional structures such as a backlight module.

[0119] In specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a full-screen display device, or may be a flexible display device, etc., which is not limited here.

[0120] In a specific implementation, the display device provided in the embodiment of the present disclosure may be a full-screen mobile phone as shown in FIG17 . Of course, the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0121] The embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a display device. By arranging the pixel electrode on the side of the common electrode layer away from the base substrate, the pixel electrode and the data line are not in the same plane, so that the coupling between the pixel electrode and the data line can be reduced. Therefore, the side of the pixel electrode close to the data line does not need to be arranged away from the data line. In this way, a pixel electrode with a larger size can be designed in each sub-pixel. Compared with the sub-pixels of the same size in the related art, the pixel electrode in each sub-pixel in the present disclosure is larger. In this way, when the slit width is consistent, the number of slits corresponding to each sub-pixel in the present disclosure can be greater. Therefore, the electric field strength generated by the slit edge in the same plane and the electric field strength generated between the pixel electrode and the common electrode layer will increase, so that the deflection degree of the liquid crystal molecules is increased, thereby improving the transmittance of the liquid crystal display panel.

[0122] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0123] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: A base substrate having a display area and a non-display area surrounding the display area; A plurality of gate lines and a plurality of data lines are located on the substrate and in the display area, wherein the plurality of gate lines and the plurality of data lines are insulated and cross-define a plurality of sub-pixels; wherein the plurality of data lines include a plurality of display data lines and a plurality of dummy data lines alternately arranged along a row direction, and adjacent dummy data lines and display data lines are respectively arranged between different sub-pixels; A common electrode layer, located on a side of the plurality of gate lines and the plurality of data lines away from the base substrate, the common electrode layer being at least located in the display area; A plurality of pixel electrodes are located on a side of the common electrode layer away from the base substrate, and each of the pixel electrodes is arranged in a corresponding sub-pixel; wherein the pixel electrode is a slit electrode having a plurality of slits.

2. The array substrate according to claim 1, wherein: Also includes: a first insulating layer located between the gate line, the data line and the common electrode layer, a second insulating layer located between the common electrode layer and the pixel electrode, and a thin film transistor located between the base substrate and the first insulating layer and arranged in each sub-pixel; wherein, The thin film transistor comprises a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are sequentially stacked between the base substrate and the first insulating layer, wherein the gate electrode is close to the base substrate; the gate line is arranged in the same layer as the gate electrode and is electrically connected to the gate electrode, and the data line is arranged in the same layer as the source electrode and the drain electrode and is electrically connected to the source electrode; The pixel electrode is electrically connected to the drain electrode through a first via hole penetrating the second insulating layer and the first insulating layer.

3. The array substrate according to claim 2, wherein: The common electrode layer is a planar electrode disposed on the entire surface, and has a plurality of second via holes, the second via holes are disposed in one-to-one correspondence with the first via holes, and the orthographic projection of the first via holes on the base substrate is located within the orthographic projection range of the second via holes on the base substrate.

4. The array substrate according to claim 3, wherein: The first insulating layer and the second insulating layer are both inorganic insulating layers.

5. The array substrate according to claim 4, wherein: The non-display area includes: a common electrode ring arranged in the same layer as the data line and surrounding the display area, and an overlap portion arranged in the same layer as the pixel electrode; wherein, One end of the overlap portion is electrically connected to the common electrode ring through a third via hole penetrating the second insulating layer and the first insulating layer, and the other end of the overlap portion is electrically connected to a portion of the common electrode layer extending to the non-display area through a fourth via hole penetrating the second insulating layer.

6. The array substrate according to claim 3, wherein: The first insulating layer is an organic insulating layer, and the second insulating layer is an inorganic insulating layer.

7. The array substrate according to claim 6, wherein: The non-display area includes: a common electrode ring arranged in the same layer as the data line and surrounding the display area, and an overlap portion arranged in the same layer as the pixel electrode; wherein, The overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through a fourth via hole penetrating the second insulating layer, and the portion of the common electrode layer extending to the non-display area is electrically connected to the common electrode ring through a fifth via hole penetrating the first insulating layer.

8. The array substrate according to claim 5 or 7, wherein: The dummy data line extends to the non-display area and is electrically connected to the common electrode ring.

9. The array substrate according to any one of claims 2 to 8, wherein: The plurality of sub-pixels are arranged in a multi-row and multi-column array, and the sources of the two columns of thin film transistors on both sides of each display data line are electrically connected to the display data line; Two gate lines are arranged on both sides of each row of sub-pixels along the column direction, and the gates of the thin film transistors of each row of sub-pixels are electrically connected to the two gate lines alternately.

10. The array substrate according to claim 9, wherein: The sub-pixels in the same column have the same luminous color, and the sub-pixels in the same row include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a cycle in the row direction, and the luminous color of the first sub-pixel, the luminous color of the second sub-pixel, and the luminous color of the third sub-pixel are different.

11. The array substrate according to any one of claims 1 to 10, wherein: The material of the common electrode layer and the material of the pixel electrode are both transparent conductive materials.

12. A display device, wherein: The invention comprises a display panel, wherein the display panel comprises an array substrate and an opposite substrate which are arranged opposite to each other, and a liquid crystal layer sandwiched between the array substrate and the opposite substrate, and the array substrate is the array substrate according to any one of claims 1 to 11.

13. A method for manufacturing an array substrate, wherein: include: Providing a base substrate, the base substrate having a display area and a non-display area surrounding the display area; A plurality of gate lines and a plurality of data lines are formed in a display area of ​​the base substrate, wherein the plurality of gate lines and the plurality of data lines are insulated and cross-define a plurality of sub-pixels; forming a common electrode layer at least located in the display area on a side of the plurality of gate lines and the plurality of data lines away from the base substrate; A pixel electrode is formed in each of the sub-pixels on a side of the common electrode layer away from the base substrate; wherein the pixel electrode is a slit electrode having a plurality of slits.

14. The method of claim 13, wherein: Forming a plurality of gate lines and a plurality of data lines in the display area of ​​the base substrate, specifically: forming a plurality of gate lines on the base substrate, and forming a plurality of data lines on a side of the plurality of gate lines away from the base substrate; While forming the plurality of data lines, it also includes forming a source electrode and a drain electrode in each of the sub-pixels and forming a common electrode ring in the non-display area; After forming the plurality of data lines and before forming the common electrode layer, the method further includes depositing a first insulating layer on a side of the plurality of data lines away from the base substrate; wherein the first insulating layer is an inorganic insulating layer; Forming the common electrode layer specifically includes: depositing a first transparent conductive layer on a side of the first insulating layer away from the base substrate, patterning the first transparent conductive layer to form the common electrode layer having a plurality of second via holes, wherein the second via holes are arranged corresponding to the drain electrodes; After forming the common electrode layer and before forming the pixel electrode, the method further includes depositing a second insulating layer on a side of the common electrode layer away from the base substrate, wherein the second insulating layer is The first insulating layer and the second insulating layer are patterned by a single patterning process to form: a plurality of first via holes corresponding to the drain electrodes, a third via hole corresponding to the common electrode ring, and a fourth via hole corresponding to the portion of the common electrode layer extending to the non-display area; the orthographic projection of the first via hole on the base substrate is within the orthographic projection range of the second via hole on the base substrate; The formation of the pixel electrode specifically includes: depositing a second transparent conductive layer on the side of the second insulating layer facing away from the base substrate, composing the second transparent conductive layer to form the pixel electrode and forming an overlapping portion located in the non-display area; wherein one end of the overlapping portion is electrically connected to the common electrode ring through the third via hole, and the other end of the overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through the fourth via hole.

15. The method of claim 13, wherein: Forming a plurality of gate lines and a plurality of data lines in the display area of ​​the base substrate, specifically: forming a plurality of gate lines on the base substrate, and forming a plurality of data lines on a side of the plurality of gate lines away from the base substrate; While forming the plurality of data lines, it also includes forming a source electrode and a drain electrode in each of the sub-pixels and forming a common electrode ring in the non-display area; After forming the plurality of data lines and before forming the common electrode layer, the method further comprises forming a first insulating layer on a side of the plurality of data lines away from the base substrate by a single patterning process; wherein the first insulating layer is an organic insulating layer, and the first insulating layer has first sub-via holes arranged in one-to-one correspondence with the drain electrodes and fifth via holes arranged in correspondence with the common electrode ring; Forming the common electrode layer specifically includes: depositing a first transparent conductive layer on a side of the first insulating layer away from the base substrate, patterning the first transparent conductive layer to form the common electrode layer having a plurality of second via holes, wherein the second via holes are arranged corresponding to the drain electrodes; wherein a portion of the common electrode layer extending to the non-display area is electrically connected to the common electrode ring through the fifth via hole; After forming the common electrode layer and before forming the pixel electrode, the method further comprises forming a second insulating layer on the side of the common electrode layer away from the base substrate by a single patterning process; wherein the second insulating layer is an inorganic insulating layer, and the second insulating layer has: a plurality of second sub-via holes arranged in one-to-one correspondence with the common electrode layer, and a fourth via hole arranged corresponding to the portion of the common electrode layer extending to the non-display area; the second sub-via holes and the first sub-via holes constitute a first via hole, and the orthographic projection of the first via hole on the base substrate is within the orthographic projection range of the second via hole on the base substrate; The formation of the pixel electrode specifically includes: depositing a second transparent conductive layer on the side of the second insulating layer facing away from the base substrate, composing the second transparent conductive layer to form the pixel electrode and forming an overlapping portion located in the non-display area; wherein the overlapping portion is electrically connected to the portion of the common electrode layer extending to the non-display area through the fourth via hole.

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