Array substrate, display panel and display device

Abstract

The array substrate comprises a substrate; a display area and a non-display area are arranged on the substrate, the non-display area comprises a lead area and a grooving area, the grooving area is located on the side, away from the display area, of the lead area, the grooving area comprises a binding area and a spacer area, and the spacer area is located between the binding area and the lead area; wherein each of the lead area and the grooving area comprises a lead layer arranged on the substrate, the lead area further comprises a plurality of protective film layers which are arranged in a stacked mode, and the protective film layers are located on the sides, away from the substrate, of the lead layers; wherein at least two kinds of protective film layers in the lead area extend to the spacer area; and / or, the size of the spacer region in a target direction is greater than or equal to 20 [mu] m and less than or equal to 30 [mu] m, and the target direction is a direction in which the binding region points to the lead region.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of display technology, various types of display devices have emerged. However, no matter what type of display device, it usually includes an array substrate. The array substrate includes a display area and a non-display area. A plurality of pixel areas are arrayed in the display area. Each pixel area includes a driving circuit for driving the pixel to emit light. The driving circuit generally leads to scan lines and data lines. The scan lines and data lines (hereinafter referred to as leads) are routed on the array substrate and eventually converge to the non-display area. A binding area is set in the non-display area. Packaging technology is used in the binding area to connect these leads to peripheral devices, such as a driver chip, so as to control the working state of the driver circuit in the display area based on the output signal of the driver chip to achieve display control.

[0003] In related technologies, when peripheral devices are connected to leads in the binding area using a packaging process, the surface of the non-display area is cleaned first. However, during the cleaning process, the leads in the non-display area are easily damaged, resulting in problems with poor vertical lines and grids on the display panel.

[0004] Overview

[0005] A first aspect of the present disclosure provides an array substrate, comprising: a substrate;

[0006] The substrate is provided with a display area and a non-display area, wherein the non-display area includes a lead area and a groove area, wherein the groove area is located on a side of the lead area away from the display area, and the groove area includes a binding area and a spacer area, wherein the spacer area is located between the binding area and the lead area;

[0007] Wherein, both the lead area and the trench area include a lead layer provided on the substrate, and the lead area also includes a plurality of protective film layers stacked and provided, and the plurality of protective film layers are located on a side of the lead layer away from the substrate;

[0008] At least two of the protective film layers in the lead area extend to the spacer area; and / or the size of the spacer area in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm, and the target direction is the direction from the binding area to the lead area.

[0009] Exemplarily, the size of the spacer region in the target direction increases as the number of protective film layers extending into the spacer region increases.

[0010] Exemplarily, in the case where at least three types of the protective film layers extend to the spacer, a size of the spacer in the target direction is greater than or equal to 200 μm and less than or equal to 250 μm;

[0011] In the case where the two protective film layers extend to the spacer, a size of the spacer in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

[0012] Exemplarily, the plurality of protective film layers include:

[0013] a first passivation layer, located on a side of the lead layer facing away from the substrate;

[0014] an organic film layer, located on a side of the first passivation layer facing away from the substrate;

[0015] a second passivation layer, located on a side of the organic film layer facing away from the substrate;

[0016] a first thin film layer, located on a side of the second passivation layer facing away from the substrate;

[0017] The second passivation layer and the first thin film layer extend to the spacer area, and the second passivation layer covers the spacer area. There is a gap between the first thin film layer and the binding area.

[0018] Exemplarily, the first passivation layer further extends to the spacer region, and the first passivation layer covers the spacer region.

[0019] Exemplarily, a size of the spacer in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

[0020] Exemplarily, the distance between the binding area and the first film layer is greater than or equal to 10 μm and less than or equal to 20 μm.

[0021] Exemplarily, the plurality of protective film layers further include: a second thin film layer, the second thin film layer being located on a side of the organic film layer facing away from the substrate, and the second passivation layer being located on a side of the second thin film layer facing away from the substrate;

[0022] The second film layer further extends to the spacer area, and there is a gap between the second film layer and the binding area.

[0023] Exemplarily, the first passivation layer further extends to the spacer region, and the first passivation layer covers the spacer region.

[0024] Exemplarily, a size of the spacer in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

[0025] Exemplarily, the spacing between the second film layer and the binding area is greater than or equal to 10 μm and less than or equal to 20 μm; and the spacing between the first film layer and the binding area is greater than or equal to 10 μm and less than or equal to 20 μm.

[0026] Exemplarily, the distance between the first film layer and the binding area is smaller than the distance between the second film layer and the binding area.

[0027] Exemplarily, the display area includes: a plurality of pixel units arranged in an array, wherein the pixel units include a pixel electrode, a common electrode, and a thin film transistor;

[0028] The pixel electrode is electrically connected to the source and drain of the thin film transistor, and the common electrode is further away from the substrate than the pixel electrode;

[0029] The first thin film layer is provided in the same layer as the common electrode, and the second thin film layer is provided in the same layer as the pixel electrode.

[0030] Exemplarily, the display area includes: a plurality of pixel units arranged in an array, wherein the pixel units include a pixel electrode, a common electrode, and a thin film transistor;

[0031] The pixel electrode is electrically connected to the source and drain of the thin film transistor, and the common electrode is closer to the substrate than the pixel electrode;

[0032] The first thin film layer is provided on the same layer as the pixel electrode, and the second thin film layer is provided on the same layer as the common electrode.

[0033] Exemplarily, the thickness of the first passivation layer is greater than the thickness of the first thin film layer, and / or the thickness of the second passivation layer is greater than the thickness of the first thin film layer.

[0034] In a second aspect, a display panel is also disclosed, comprising the array substrate and a cell-matching substrate arranged to be matched with the array substrate, wherein a liquid crystal layer is filled between the cell-matching substrate and the array substrate.

[0035] Exemplarily, there is a gap between the binding area in the array substrate and the orthographic projection of the aligning substrate on the array substrate, and the spacing is greater than or equal to 10 μm and less than or equal to 20 μm.

[0036] In a third aspect, a display device is also disclosed, comprising a control chip and the display panel;

[0037] The array substrate in the display panel includes a binding area, the binding area includes a lead-out electrode overlapped with the lead layer, and the pins of the control chip overlap with the lead-out electrode.

[0038] Exemplarily, the array substrate in the display device includes a groove area and a lead area, and further includes:

[0039] A conductive film, wherein the orthographic projection of the conductive film on the substrate covers part or all of the orthographic projection of the trench area on the substrate.

[0040] Exemplarily, the trench area includes a spacer area adjacent to the lead area and a binding area adjacent to the spacer area, wherein a size of the spacer area in a target direction is greater than or equal to 20 μm and less than or equal to 30 μm; wherein a size of the conductive film in the target direction is greater than or equal to 70 μm and less than or equal to 110 μm;

[0041] The target direction is that the binding area points to the lead area.

[0042] The present disclosure provides an array substrate, which includes a substrate, on which a display area and a non-display area are arranged, wherein the non-display area includes a lead area and a groove area, the groove area is located on the side of the lead area away from the display area, and the groove area includes a binding area and a spacing area, and the spacing area is located between the binding area and the lead area; wherein both the lead area and the groove area include a lead layer arranged on the substrate, and the lead area also includes a plurality of stacked protective film layers, and the plurality of protective film layers are located on the side of the lead layer away from the substrate; wherein at least two protective film layers in the lead area extend to the spacing area; and / or a size of the spacing area in a target direction is greater than or equal to 20 μm and less than or equal to 30 μm, and the target direction is the direction from the binding area to the lead area.

[0043] The array substrate disclosed in the present invention has a spacer area near the binding area, wherein, when there are two protective film layers on the lead layer in the spacer area, when the surface of the non-display area is cleaned, the lead layer in the spacer area can be protected by at least two protective film layers to prevent water vapor from entering the lead layer and corroding the lead. Wherein, when the size of the spacer area in the direction from the binding area to the lead area is greater than or equal to 20μm and less than or equal to 30μm, the area of ​​the spacer area can be made very small, so that the risk area of ​​the lead area in the spacer area being corroded is greatly reduced, thereby reducing the risk of the lead layer being corroded and broken. Wherein, when the size of the spacer area is reduced to less than 30μm and the spacer area has at least two protective film layers, the protection of the lead layer in the spacer area is stronger, thereby greatly reducing the risk of lead breakage during packaging and reliability processes, thereby avoiding the problems of poor grid and poor vertical lines when testing the display panel.

[0044] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0045] BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0047] FIG1 shows a top view of wiring in a non-display area of ​​an array substrate in the related art;

[0048] FIG2 shows a cross-sectional view of the non-display area along the AA′ direction in FIG1 ;

[0049] FIG3 shows the position range of the lead wires damaged in the non-display area under a microscope;

[0050] FIG4 is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0051] FIG5 is a schematic top view of an array substrate in a grooved area according to an embodiment of the present disclosure;

[0052] FIG6 shows a cross-sectional view of the array substrate in the non-display area along the AA′ direction according to an embodiment of the present disclosure;

[0053] FIG7 shows a schematic cross-sectional structure diagram of an array substrate in the AA′ direction according to an embodiment of the present disclosure;

[0054] FIG8 shows a case where the array substrate includes three types of protective film layers in the spacer region in an embodiment of the present disclosure;

[0055] FIG9 shows a cross-sectional view of the array substrate in the AA′ direction in the case where the spacer region includes two protective film layers in an embodiment of the present disclosure;

[0056] FIG10 shows a schematic cross-sectional structure diagram of a display area of ​​an array substrate A in an embodiment of the present disclosure;

[0057] FIG11 shows a schematic cross-sectional structure diagram of an array substrate A in the AA′ direction according to an embodiment of the present disclosure;

[0058] FIG12 shows a schematic cross-sectional structure diagram of another array substrate A in the AA′ direction according to an embodiment of the present disclosure;

[0059] FIG13 shows a schematic cross-sectional structure diagram of another array substrate B in the display area according to an embodiment of the present disclosure;

[0060] FIG14 shows a schematic cross-sectional structure diagram of an array substrate B in the AA′ direction according to an embodiment of the present disclosure;

[0061] FIG15 shows a schematic cross-sectional structure diagram of another array substrate B in the AA′ direction according to an embodiment of the present disclosure;

[0062] FIG16 shows a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure;

[0063] FIG17 shows a schematic cross-sectional structure diagram of another array substrate A in the display area according to an embodiment of the present disclosure;

[0064] FIG18 a shows a schematic top plan view of a display device in a non-display area according to an embodiment of the present disclosure;

[0065] FIG18 b is a schematic top plan view of another display device in a non-display area according to an embodiment of the present disclosure;

[0066] FIG19 a is a schematic diagram of the cross-sectional structure of the display device shown in FIG18 a taken along the AA′ direction;

[0067] FIG19 b is a schematic diagram of the cross-sectional structure of the display device shown in FIG18 b along the AA′ direction.

[0068] Reference numerals:

[0069] 100, array substrate; 101, display area; 102, non-display area; 1021, lead area; 1022, groove area; 221, spacer area; 222, bonding area; 103, gate line; 104, data line; 11, substrate; 12, lead layer; 13, protective film layer; 14, gate insulation layer; 15, conductive film; 131, first passivation layer; 132, organic film layer; 133, pixel electrode; 134, second passivation layer; 135, common electrode; 122, gate; 1 22a, drain; 122b, source; 122c, active layer; 2211, lead-out electrode; 2212, via; 130a, first thin film layer; 130b, second thin film layer; 100A, array substrate A; 100B, array substrate B; 200, matching substrate; 300, liquid crystal layer; 400, control chip; h1, size of the spacer area in the target direction; h2, spacing between the first thin film layer and the binding area; h3, size of the conductive film in the target direction starting from the binding area.

[0070] Detailed description

[0071] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0072] As mentioned in the background art, when connecting peripheral devices to leads using the packaging process, the surface of the non-display area is first cleaned. During the cleaning process, the leads in the non-display area are easily damaged, resulting in defective vertical lines and grids on the display panel. Specifically, taking a thin film transistor liquid crystal display (TFT-LCD) as an example, the problems in the related art are explained:

[0073] Referring to Figures 1 to 3, Figure 1 shows a top view of the wiring of the array substrate in the non-display area in the related art, Figure 2 shows a cross-sectional view in the AA' direction of the non-display area in Figure 1, and Figure 3 shows a diagram of the position range of the lead damage in the non-display area under a microscope. As shown in Figure 1, the array substrate of the thin film transistor liquid crystal display includes a plurality of scan lines (gate 122 leads in Figure 1) and a plurality of data lines (source and drain leads in Figure 1) arranged in an array in the display area. The area defined by the intersection of the scan lines and the data lines in the display area is the pixel area, wherein the data lines will be routed on the array substrate, and extend in the non-display area and finally converge to the binding area, where they are connected to the driver chip through packaging technology to achieve circuit connection. The driver chip is used to provide digital signals to the data lines according to the image to be displayed, and the data lines are connected to the source and drain in the thin film transistor. Of course, in some displays with touch functions, the display area also includes touch signal lines. The touch signal lines can also be routed on the array substrate, extended in the non-display area, and finally converged to the binding area, so that the touch chip can also be used to receive the routing of the touch signal lines and realize the touch function.

[0074] The structure of the array substrate in the display area can refer to the structure of a conventional IPS display panel or a VA panel. As shown in Figure 2, taking the data line as an example, the size of the organic film removal area is 250μm. Since the organic film and PVX1 layer above the source and drain layers are removed during the manufacturing process of the array substrate, only the PVX2 layer is retained above the leads in the bonding area and its surrounding areas. Since the PVX2 layer is thin, its protection effect on the underlying leads is poor, which can easily lead to the following problems:

[0075] Problem 1: When cutting the array substrate from the motherboard along the cutting line, the area near the cutting line is easily crushed by debris during cutting. If the leads are arranged in a double-layer manner in the non-display area, the pressure of the debris can easily cause a short circuit between the upper and lower layers of leads.

[0076] Issue 2: When using COG packaging technology, plasma cleaning is required on the surface of the non-display area. This cleaning process can easily damage the leads. Furthermore, subsequent exposure to high temperature and humidity for extended periods of time can easily lead to moisture intrusion and corrosion, potentially causing lead breakage. As shown in Figure 3, lead breakage occurred in the non-display area, where the organic film and PVX1 layer have been removed, within a 250μm area surrounding the bonding zone.

[0077] Among them, since the lead is the data line lead or the scan line lead, no matter which lead it is, based on the above two problems, there is a situation where the lead is corroded and broken due to the binding process in the non-display area, resulting in problems of poor vertical lines and grids on the display panel.

[0078] In view of this, the present disclosure provides an array substrate, which reduces the size of the area where the organic film and PVX1 layer are removed around the binding area on the array substrate, so that the area where the lead is covered only by the PVX2 layer is greatly reduced, such as reduced to 30μm or less. When the size is reduced, the risk area corroded by water vapor during the packaging process can be reduced, thereby avoiding the problem of lead breakage; and, by adding a protective film layer around the binding area, the thickness and number of the film layer protecting the lower lead can be increased to avoid erosion by water vapor, thereby greatly reducing the risk of lead breakage.

[0079] 4 to 6 , FIG4 shows a schematic top plan view of an array substrate, FIG5 shows a schematic top plan view of an array substrate in a grooved area according to an embodiment of the present disclosure, and FIG6 shows a cross-sectional view of the array substrate in the AA′ direction of the non-display area 102 . As shown in FIG4 to 6 , the array substrate mainly includes:

[0080] substrate 11;

[0081] A display area 101 and a non-display area 102 are provided on a substrate 11. The non-display area 102 includes a lead area 1021 and a groove area 1022. The groove area 1022 is located on a side of the lead area 1021 away from the display area 101. The groove area 1022 includes a binding area 222 and a spacer area 221. The spacer area 221 is located between the binding area 222 and the lead area 1021.

[0082] The lead area 1021 and the groove area 1022 both include a lead layer 12 disposed on the substrate 11. The lead area 1021 also includes multiple protective film layers 13 stacked and located on a side of the lead layer 12 facing away from the substrate 11.

[0083] In which, at least two protective film layers 13 in the lead area 1021 extend to the spacer area 221; and / or, the size of the spacer area 221 in the target direction is greater than or equal to 20μm and less than or equal to 30μm, and the target direction is the direction from the binding area 222 to the lead area 1021.

[0084] In this embodiment, the substrate 11 can be a glass substrate 11, the array substrate can be an array substrate used for an LCD display, the array substrate can be an array substrate in an ADS (Adwanced Dimens In Switch) panel or an IPS panel, or it can be an array substrate of the HADS (High-Adwanced Dimens In Switch) type, or it can be an array substrate in a TN panel or a VA panel, and no special restrictions are made here.

[0085] As shown in FIG4 , a display area 101 and a non-display area 102 are provided on a substrate 11. The non-display area 102 includes a lead area 1021 and a trench area 1022. The trench area 1022 further includes a spacer area 221 and a bonding area 222. The spacer area 221 is used to separate the lead area 1021 from the bonding area 222. As shown in FIG5 , the lead area 1021 includes a plurality of leads, each made of a metal material, such as a metal or alloy material, to ensure good electrical conductivity. The display area 101 of the array substrate generally includes a plurality of thin film transistors. For an array substrate of an LCD display, the display area 101 includes a plurality of pixel areas, each of which includes a thin film transistor. The gate electrode 122 of the thin film transistor is connected to the gate line 103, i.e., the scan line 103, and the source and drain electrodes are connected to the data line 104. The source or drain electrode is connected to the data line 104.

[0086] The display area 101, the lead area 1021, and the trench area 1022 on the array substrate all have lead layers 12. In some cases, the data lines 104 and the scan lines 103 can be arranged on the same layer in the display area 101, but on different layers in the lead area 1021. In this way, two layers of lead layers 12 are retained in both the trench area 1022 and the lead area 1021. Different layers of lead layers 12 can have different leads, such as one layer having leads for the data lines 104 and another layer having leads for the scan lines 103. The leads are spaced and insulated from each other. In this way, the data lines 104 and the scan lines 103 can be transferred from being arranged on the same layer in the display area 101 to being arranged on different layers in the lead area 1021.

[0087] In some cases, after the data lines 104 are led out of the display area 101, they can be routed through multiple layers in the lead area. For example, they can be routed alternately in two lead layers in the lead area, thereby shortening the wiring spacing and saving space. This double-layer routing approach allows more leads to be routed within the limited lead area 1021, facilitating the design of an array substrate with a narrow frame.

[0088] Exemplarily, the leads in the lead layer can be electrically connected to the data lines in the display area and can be regarded as lead lines of the data lines, that is, data lines connected to the source and drain electrodes. Specifically, the leads in the lead layer can be wired in alternating film layers using the same metal layer as the gate or data line.

[0089] For example, the leads in the lead layer may also include leads connected to touch signal lines in the display area. These touch signal lines may also be routed using the same metal layer as the data lines. Both the data line leads and the touch signal line leads may be protected by at least two protective film layers above the lead layer where they are located, and / or the size of the spacer in the target direction may be shortened.

[0090] Among them, above the lead layer 12 of the lead area 1021, that is, on the side of the lead layer 12 facing away from the substrate 11, multiple protective film layers 13 are included, and the multiple protective film layers 13 can be regarded as extensions of part of the film layer in the display area 101 of the array substrate. The extended part of the film layer will be described in detail in subsequent embodiments.

[0091] The trench area 1022 may be understood as an area formed after removing part of the protective film layer 13 in the lead area 1021 , such as an area formed after removing the organic film layer 132 in the lead area 1021 .

[0092] For example, the corresponding film structures of the trench region 1022, the lead region 1021, and the display region 101 can all be formed simultaneously in the same manufacturing process. Thus, the trench region 1022 and the lead region 1021 are formed simultaneously with the display region 101. Because different types of array substrates have different film layer structures in the display region 101, the manufacturing process steps for the array substrates also differ. The specific differences are described in subsequent embodiments. Thus, different types of array substrates may have different film layers removed when forming the trench region 1022 due to differences in the manufacturing process. Consequently, the film layers retained in the trench region 1022 may differ.

[0093] The binding area 222 may be a portion of the trench area 1022, and its size may be determined based on the peripheral device being bound and the binding method. The spacer area 221 may be the area of ​​the trench area excluding the binding area 222. If the peripheral device is a driver chip, when the binding method is top-surface binding, the driver chip needs to be bound on the side of the binding area 222 facing away from the substrate 11. In this case, the size of the binding area 222 may be adapted to the driver chip. When the binding method is side-surface binding, the driver chip needs to be bound on the side of the binding area 222, that is, on the cross-section of the array substrate. In this case, the size of the binding area 222 may be smaller than that of the top-surface binding method.

[0094] Among them, in the embodiment of the present disclosure, no matter which preparation process is adopted for the array substrate, when part of the protective film layer 13 above the lead layer 12 is removed, at least two film layers above the lead layer 12 can be retained as much as possible, so that the lead layer 12 of the spacer area 221 is protected by at least two protective film layers 13, and / or, the size of the removed area of ​​the protective film layer 13 can be as small as possible, so that the size of the spacer area 221 in the target direction is greater than or equal to 20μm and less than or equal to 30μm.

[0095] Therefore, at least two protective film layers 13 are stacked on the side of the lead layer 12 of the spacer area 221 facing away from the substrate 11. When the spacer area 221 includes two lead layers 12, at least two protective film layers 13 are arranged on the side of the topmost lead layer 12 facing away from the substrate 11.

[0096] As shown in FIG6 , the array substrate needs to have the following three configurations:

[0097] The first configuration includes: at least two protective film layers 13 in the lead region 1021 extend to the spacer region 221; the second configuration includes: the size of the spacer region 221 in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm; and the third configuration includes: at least two protective film layers 13 in the lead region 1021 extend to the spacer region 221, and the size of the spacer region 221 in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm. The first and third configurations increase the thickness of the protective film above the lead layer 12 in the spacer region 221. With this increased thickness, high-temperature, high-humidity, and long-term reliability make it less likely for water vapor to enter and corrode the metal of the lead layer 12. The second and third configurations reduce the size of the spacer region 221, thereby reducing the size of the lead layer 12 with less protection from the protective film layer 13 and the area at risk of water vapor corrosion. This reduces the risk of water vapor corrosion of the lead layer 12 and the probability of corrosion and fracture of the leads in the lead layer 12.

[0098] Exemplarily, at least one protective film layer 13 in the lead region 1021 extends to the spacer region 221 and fully covers the spacer region 221. If only one protective film layer 13 in the lead region 1021 extends to the spacer region 221, the size of the spacer region 221 in the target direction is 20 μm to 30 μm. If two protective film layers 13 in the lead region 1021 extend to the spacer region 221 and fully cover the spacer region 221, the size of the spacer region 221 in the target direction may be greater than 30 μm, such as 200 μm to 250 μm. If two protective film layers 13 in the lead region 1021 extend to the spacer region 221, and one protective film layer 13 does not fully cover the spacer region 221, the size of the spacer region 221 in the target direction may be 20 μm to 30 μm. If more than two protective film layers 13 in the lead region 1021 extend to the spacer region 221, the size of the spacer region 221 in the target direction may be greater than 30 μm.

[0099] Illustratively, regardless of which of the above settings is used, the protective film layer 13 retained in the spacer area 221 may include a protective film layer 13 made of an inorganic material, such as SiNx, SiOx and other inorganic materials, wherein the thickness and hardness of the protective film layer 13 of the inorganic material are better, and its protection and waterproof effects are better; of course, in addition to including the protective film layer 13 made of inorganic material, it may also include a protective film layer 13 of metal material. The metal material has good ductility, and can realize a flexible design of the lead area 1021 and the spacer area 221, such as the design of a curved lead area 1021 and the spacer area 221.

[0100] The protective film layer of the metal material may not be made of pure metal material, but may be made of materials such as indium tin oxide.

[0101] In some optional examples, the film layer structures of the binding area 222 and the spacer area 221 may be consistent or inconsistent. In the case of inconsistency, the binding area 222 may only include the lead layer 12 to expose the leads; or, the binding area 222 may include at least one protective film layer 13 above the lead layer 12, and a lead electrode 2211 may be provided on the side of the protective film layer 13 facing away from the substrate 11. Referring to FIG7 , a schematic diagram of the cross-sectional structure of an array substrate in the AA' direction is shown. As shown in FIG7 , the lead electrode 2211 is overlapped with the lead in the underlying lead layer 12 through a through hole 2212 provided in the protective film layer 13, so that the peripheral device can achieve circuit connection with the array substrate through the overlap with the lead electrode 2211. In this case, the protective film layer 13 in the binding area 222 may be an extension of at least one protective film layer 13 in the spacer area 221, or may be a protective film layer 13 grown independently in the binding area 222, which is not limited here.

[0102] Among them, when using the array substrate of this embodiment, during the packaging process, the surface of the groove area 1022 is first cleaned. After cleaning, the peripheral devices are bound to the binding area 222, such as the driver chip is bound to the binding area 222. In the binding area 222, the pins of the driver chip are overlapped with the leads in the lead layer 12 in the binding area 222, thereby realizing the circuit connection between the driver chip and the array substrate.

[0103] Because two protective film layers 13 are formed on the lead layer 12 within the spacer region 221, when the surface of the grooved area 1022 is cleaned, the lead layer 12 within the spacer region 221 can be protected by at least two protective film layers 13, preventing moisture from entering the lead layer 12 and corroding the leads. When the dimension of the spacer region 221 in the direction from the binding area 222 to the lead region 1021 is greater than or equal to 20 μm and less than or equal to 30 μm, the area of ​​the spacer region 221 can be very small. This greatly reduces the risk of corrosion of the lead region 1021 within the spacer region 221, thereby reducing the risk of corrosion and breakage of the lead layer 12. Among them, when the size of the spacer area 221 is reduced to less than 30μm and the spacer area 221 has at least two protective film layers 13, the protection of the lead layer 12 in the spacer area 221 is stronger, thereby greatly reducing the risk of lead breakage during the packaging process, thereby avoiding the problems of poor grid and poor vertical lines when testing the display panel.

[0104] In one embodiment, the size of the spacer 221 in the target direction may be related to the number of protective film layers 13 extending into the spacer 221. For example, the size of the spacer 221 in the target direction may increase as the number of protective film layers 13 extending into the spacer 221 increases. For example, the more protective film layers 13 extending from the lead region 1021 to the spacer 221, the larger the size of the spacer 221 in the target direction. This is because the more protective film layers 13 there are, the greater the protection provided to the lead layer 12 in the spacer 221. In this case, the size of the spacer 221 in the target direction may be increased to avoid the formation of close steps around the bonding region 222 when peripheral devices are packaged in the bonding region 222.

[0105] For another example, the fewer protective film layers 13 extending from the lead area 1021 to the spacer area 221, the smaller the size of the spacer area 221 in the target direction. This is because the fewer protective film layers 13, the weaker the protection of the lead layer 12 in the spacer area 221. In this case, the size of the spacer area 221 in the target direction can be reduced to reduce the risk area of ​​the lead layer 12 being corroded by water vapor, thereby reducing the probability of the lead layer 12 being corroded.

[0106] In an optional example of this embodiment, the size of the spacer 221 in the target direction may be in the range of 20μm to 250μm, and increase as the number of protective film layers 13 extending to the spacer 221 increases. In an optional example, the size of the spacer 221 in the target direction may also be in the range of 20μm to 25μm, and increase as the number of protective film layers 13 extending to the spacer 221 increases. When the size is changed within the first range of 20μm to 250μm, a variety of flexible settings can be made for the size of the spacer 221 in the target direction to meet the diverse protection requirements for the lead layer 12. When the size is changed within the second range of 20μm to 250μm, the corrosion risk area can be reduced to maximize the guarantee that the leads in the lead layer 12 cannot be corroded.

[0107] In another optional example of this embodiment, when the number of protective film layers 13 extending from the lead area 1021 to the spacer area 221 is greater than or equal to three, the protection of the lead layer 12 is already good. In this case, the size of the spacer area 221 in the target direction may not be limited to less than 30μm, and may be greater than 30μm. When it is greater than 30μm, there may be a larger spacer area 221 around the binding area 222. When the binding area 222 is used to bind peripheral devices, it is possible to avoid large steps in the surrounding area close to the binding area 222.

[0108] In practice, when at least three protective film layers 13 extend to the spacer 221 , the size of the spacer 221 in the target direction may be greater than or equal to 200 μm and less than or equal to 250 μm.

[0109] In the case where the two protective film layers 13 extend to the spacer region 221 , the size of the spacer region 221 in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

[0110] For example, referring to Figures 8 and 9, Figure 8 shows a cross-sectional view of the array substrate along the AA' direction when the spacer 221 includes three types of protective film layers 13, and Figure 9 shows a cross-sectional view of the array substrate along the AA' direction when the spacer 221 includes two types of protective film layers 13. As shown in Figure 8, when three types of protective film layers 13 are included, three types of protective film layers 13 are present above the lead layer 12 in the spacer 221. Thus, the presence of three types of protective film layers 13 blocks the ingress of water vapor. Even when exposed to water vapor for a long time, the lead layer 12 below can still be protected from water vapor corrosion. Under this setting, the size of the spacer area 221 in the target direction is greater than or equal to 200μm and less than or equal to 250μm. When the peripheral device is bound to the binding area 222, such as the driver chip is bound to the binding area 222, there can be a larger area around the binding area 222 with a height not much different from the binding area 222, so as to avoid the generation of large steps near the binding area 222, so that the peripheral device will not crush the lead area 1021 device due to the close step, thereby improving the binding quality.

[0111] As shown in FIG9 , the two protective film layers 13 of the lead region 1021 extend to the spacer region 221 . In this arrangement, only two protective film layers 13 are present above the lead layer 12 in the spacer region. Thus, the barrier effect against water vapor is weaker than that of three protective film layers 13, and its barrier against long-term water vapor infiltration is weaker. The risk of water vapor corrosion of the lead layer 12 can be reduced by reducing the size of the spacer region 221 . For example, the size of the spacer region 221 in the target direction can be set to be greater than or equal to 20 μm and less than or equal to 30 μm. Thus, since the lead layer 12 with only two protective film layers 13 is reduced in size, the risk area affected by water vapor corrosion is reduced, thereby reducing the risk of water vapor corrosion of the lead layer 12. For example, the size of the spacer region 221 in the target direction can be 25 μm. This 25 μm size can avoid the generation of large steps when bonding peripheral devices in the bonding region 222 , thus meeting the most basic bonding requirements.

[0112] In one example of this embodiment, at least three protective film layers 13 in the lead region 1021 extend into the spacer region 221. The at least three film layers may not include the organic film layer 132. The size of the spacer region 221 in the target direction may be 250 μm, 200 μm, or 225 μm. The at least three film layers may not include the organic film layer 132. Specifically, the protective film layer 13 extending into the spacer region 221 includes at least a thin film layer and an inorganic film layer. Depending on the actual situation, the protective film layer 13 may include two thin film layers, two inorganic film layers, or both thin film layers and inorganic film layers.

[0113] The thin film layer may be made of indium tin oxide material.

[0114] In another example, only two protective film layers 13 in the lead area 1021 extend to the spacer area 221, and the two film layers may not include the organic film layer 132, wherein the two film layers may include a thin film layer and an inorganic film layer made of indium tin oxide material, and the size of the spacer area 221 in the target direction can be 30μm or 20μm, or, it can be 25μm; of course, preferably, it can be 25μm.

[0115] Below, each array substrate under the above three settings is introduced and explained respectively:

[0116] First, the lead area 1021 of the array substrate includes a variety of protective film layers 13 . In practice, the structure of the protective film layer 13 in the lead area 1021 may be slightly different depending on the film layer structure of the display area 101 of the array substrate.

[0117] 10 shows a schematic cross-sectional structure diagram of a display area 101 of an array substrate A. As shown in FIG10 , the display area 101 includes:

[0118] substrate 11;

[0119] a gate 122 located on the substrate 11 , a gate insulating layer 14 located on a side of the gate 122 facing away from the substrate 11 , and an active layer 122 c located on a side of the gate insulating layer 14 facing away from the substrate 11 ;

[0120] a source electrode 122 b and a drain electrode 122 a located on a side of the active layer 122 c facing away from the substrate 11 and overlapping the doped region of the active layer 122 c ;

[0121] A first passivation layer 131 located on a side of the source / drain electrode 122 a facing away from the substrate 11 ;

[0122] a pixel electrode 133 located on a side of the first passivation layer 131 facing away from the substrate 11;

[0123] an organic film layer 132 located on a side of the pixel electrode 133 facing away from the substrate 11;

[0124] A second passivation layer 134 located on a side of the organic film layer 132 facing away from the substrate 11;

[0125] a common electrode 135 located on a side of the second passivation layer 134 facing away from the substrate 11;

[0126] The pixel electrode 133 may be a plate electrode, and the common electrode 135 may be a slit electrode. The common electrode 135 may be formed after the pixel electrode 133 is formed. This type of array substrate may be referred to as a Top com design.

[0127] Among them, the pixel electrode 133 and the common electrode 135 can both be made of transparent metal materials, such as indium tin oxide ITO material; the pixel electrode 133 is overlapped with the drain electrode 122a through a through hole opened on the first passivation layer 131; among them, the thickness of the first passivation layer 131 and the second passivation layer 134 can be 1000~5000A (angstroms), and the thickness of the organic film layer 132 is generally thicker, which can be 20000A~25000A.

[0128] The organic film layer 132 acts as a buffer between the pixel electrode 133 and the second passivation layer 134, primarily protecting the pixel electrode 133. In the fabrication of this type of array substrate, since the pixel electrode 133 needs to be connected to the drain electrode 122a below through a through-hole in the first passivation layer 131, a hole needs to be drilled in the first passivation layer 131. Therefore, when the organic film is removed in the trench area 1022, the first passivation layer 131 is also removed for the sake of process simplicity. Consequently, the first passivation layer 131 is removed at the corresponding location simultaneously with the organic film. Consequently, the first passivation layer 131 is no longer present in the trench area 1022.

[0129] In the exemplary array substrate A shown in Figure 10, the display area 101 of the array substrate may include a plurality of pixel units arranged in an array, and the pixel unit includes a pixel electrode 133, a common electrode 135 and a thin film transistor; wherein the pixel electrode 133 is electrically connected to the source and drain of the thin film transistor, and the common electrode 135 is located on the side of the pixel electrode 133 facing away from the substrate 11; wherein the first thin film layer 130a and the common electrode 135 are arranged on the same layer.

[0130] Therefore, the protective film layer 13 above the lead layer 12 in the lead region 1021 can be part or all of the film layers in the display region 101 except for the gate 122 and the source-drain electrode 122a. Referring to Figures 11 and 12, Figure 11 shows a schematic cross-sectional structure diagram of an array substrate A along the AA' direction, and Figure 12 shows a schematic cross-sectional structure diagram of the array substrate A along the AA' direction. The array substrates shown in Figures 11 and 12 have different numbers of protective film layers 13 in the lead region 1021, and accordingly, the film layer structures formed by the protective film layers 13 are also slightly different.

[0131] As shown in FIG11 , the various protective film layers 13 of the lead area 1021 include the following film layers:

[0132] A first passivation layer 131 is located on the side of the lead layer 12 facing away from the substrate 11;

[0133] The organic film layer 132 is located on the side of the first passivation layer 131 facing away from the substrate 11;

[0134] The second passivation layer 134 is located on the side of the organic film layer 132 facing away from the substrate 11;

[0135] The first thin film layer 130 a is located on a side of the second passivation layer 134 facing away from the substrate 11 .

[0136] In which, the array substrate may include a gate insulation layer in addition to the substrate 11 in the lead area 1021. The gate insulation layer of the lead area 1021 and the gate insulation layer of the display area 101 may be arranged on the same layer, that is, formed in one film forming process; the lead layer 12 in the lead area 1021 is insulated from the gate insulation layer.

[0137] The plurality of leads provided in the lead layer 12 in the lead region 1021 include a lead connected to the drain electrode 122 a and a lead connected to the gate 122 . The two leads may be provided in the same layer and spaced apart from each other. The lead and the electrodes to which they are connected (the drain electrode 122 a and the gate 122 ) may be made of the same material.

[0138] The first passivation layer 131 in the lead area 1021 can be formed in the same layer and made of the same material as the first passivation layer 131 in the display area 101 . The organic film layer 132 can be formed in the same layer and made of the same material as the organic film layer 132 in the display area 101 . The second passivation layer 134 can be formed in the same layer and made of the same material as the second passivation layer 134 in the display area 101 .

[0139] The first thin film layer 130 a may be provided in the same layer as the common electrode 135 , and the material of the first thin film layer 130 a may be the material of the common electrode 135 , so that the first thin film layer 130 a may be formed in one film forming process.

[0140] Therefore, four types of protective film layers 13 are formed above the lead layer 12 in the lead area 1021 .

[0141] In another exemplary array substrate shown in FIG. 11 , the thickness of the first passivation layer 131 is greater than the thickness of the first thin film layer 130 a , and / or the thickness of the second passivation layer 134 is greater than the thickness of the first thin film layer 130 a .

[0142] In this optional example, the thickness of the first passivation layer 131 in the lead area 1021 may be greater than the thickness of the first film layer 130a, or the thickness of the second passivation layer 134 in the lead area 1021 may be greater than the thickness of the first film layer 130a; or the thickness of the first passivation layer 131 in the lead area 1021 is greater than the thickness of the first film layer 130a, and the thickness of the second passivation layer 134 in the lead area 1021 may be greater than the thickness of the first film layer 130a.

[0143] FIG12 shows a cross-sectional structure of another lead region 1021 in the array substrate A shown in FIG10 . The lead region 1021 of this array substrate includes the following film layers:

[0144] A first passivation layer 131 is located on the side of the lead layer 12 facing away from the substrate 11;

[0145] The organic film layer 132 is located on the side of the first passivation layer 131 facing away from the substrate 11;

[0146] The second thin film layer 130b is located on the side of the organic film layer 132 facing away from the substrate 11;

[0147] The second passivation layer 134 is located on the side of the second thin film layer 130b facing away from the substrate 11;

[0148] The first thin film layer 130 a is located on a side of the second passivation layer 134 facing away from the substrate 11 .

[0149] In the array substrate A shown in FIG10 , the display area 101 may include a plurality of pixel units arranged in an array. The pixel units include a pixel electrode 133, a common electrode 135, and a thin film transistor. The pixel electrode 133 is electrically connected to the source and drain of the thin film transistor, and the common electrode 135 is located on a side of the pixel electrode 133 close to the substrate 11.

[0150] The first film layer 130a and the second film layer 130b can both be made of indium tin oxide material, which can ensure that the spacer region has a certain ductility and prevent corrosion of the film layer during the trust process.

[0151] Compared with the lead area 1021 shown in Figure 11, the lead area 1021 in Figure 12 also includes a second thin film layer 130b, wherein the second thin film layer 130b can be set in the same layer as the pixel electrode 133 in the display area 101 shown in Figure 10, and the material of the second thin film layer 130b can be the material of the pixel electrode 133, thereby forming the pixel electrode 133 and the second thin film layer 130b in one film forming process.

[0152] Among them, whether it is the lead area 1021 shown in Figure 11 or the lead area 1021 shown in Figure 12, the material of the first passivation layer 131 and the second passivation layer 134 can be SiNx or SiOx; the organic film layer 132 can be a high molecular polymer material, for example: cellulose derivatives, polyimides, silicon-containing polymers, etc.; among them, the thickness of the organic film layer 132 can be 20000~30000A, the thickness of the first thin film layer 130a and the second thin film layer 130b can be 500~1000A, and the thickness of the pixel electrode 133 and the common electrode 135 can also be 500~1000A.

[0153] As shown in Figures 11 and 12, since the number and structure of the protective film layer 13 in the lead area 1021 of the array substrate can be slightly different, the protective film layer 13 extending from the lead area 1021 to the spacer area 221, and the size of the spacer area 221 in the target direction can also be set in multiple ways to increase the protection of the lead layer 12.

[0154] As shown in FIG11 , the multiple protective film layers 13 in the lead region 1021 may include four types of protective film layers 13 , namely, the multiple protective film layers 13 in the lead region 1021 include the following film layers: a first passivation layer 131, an organic film layer 132, a second passivation layer 134, and a first thin film layer 130 a. The two protective film layers 13 in the lead region 1021 extend to the spacer region 221. Specifically, the second passivation layer 134 and the first thin film layer 130 a extend to the spacer region 221, and the second passivation layer 134 covers the spacer region 221. A gap exists between the first thin film layer 130 a and the bonding region 222.

[0155] As shown in Figure 11, there is a gap between the first film layer 130a and the binding area 222. In this way, electrical connection between the binding area 222 and the first film layer 130a can be avoided, thereby preventing a short circuit problem. For example, when the first film layer 130a overlaps with the lead layer 12 below, if the first film layer 130a also overlaps with the binding area 222, a short circuit will occur between the two.

[0156] In which case, when the second passivation layer 134 and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 can be greater than or equal to 25μm and less than or equal to 30μm; or can be greater than 30μm and within the range of 200μm to 250μm.

[0157] In an alternative embodiment of this embodiment, regardless of which size range the spacer region 221 falls within, due to the spacing between the first film layer 130a and the binding region 222, the spacing between the binding region 222 and the first film layer 130a can be greater than or equal to 10 μm and less than or equal to 20 μm. As shown in FIG11 , although there is a spacing between the first film layer 130a and the binding region 222, the spacing is between 10 μm and 20 μm. This improves the protection of the lead layer 12, reduces the risk area above the lead layer 12 where there is less coverage of the protective film layer 13, and enhances the protection of the lead layer 12.

[0158] In an alternative embodiment of this embodiment, as described above, when the two protective film layers 13 of the lead region 1021 extend to the spacer region 221, the size of the spacer region 221 in the target direction can be greater than or equal to 20 μm and less than or equal to 30 μm. As shown in Figure 11, in this case, the size of the spacer region 221 is sufficiently small, so the risk area of ​​corrosion of the lead layer 12 caused by water vapor infiltration is reduced. When the risk area is reduced, the possibility of corrosion of the lead layer 12 is reduced, thereby effectively preventing the problem of lead layer 12 being corroded and breaking due to corrosion.

[0159] In another embodiment, as shown in Figure 12, the lead region 1021 includes five protective film layers 13: a first passivation layer 131, an organic film layer 132, a second thin film layer 130b, a second passivation layer 134, and a first thin film layer 130a. In this array substrate, in addition to the second passivation layer 134 and the first thin film layer 130a extending into the spacer region 221, the second thin film layer 130b also extends into the spacer region 221, with a gap between the second thin film layer 130b and the bonding region 222.

[0160] As described above, as the number of film layers extending into the spacer 221 increases, the target size of the spacer 221 may also gradually increase. For example, when the second passivation layer 134 and the first thin film layer 130a extend into the spacer 221, the size of the spacer 221 in the target direction may also be greater than or equal to 20 μm and less than or equal to 30 μm. When the second passivation layer 134, the first thin film layer 130a, and the second thin film layer 130b extend into the spacer 221, the size of the spacer 221 in the target direction may also be greater than or equal to 200 μm and less than or equal to 250 μm.

[0161] Alternatively, the size of the spacer 221 in the target direction can be changed within 20μm-30μm. For example, when the second passivation layer 134 and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 20μm; when the second passivation layer 134, the first thin film layer 130a and the second thin film layer 130b extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 30μm.

[0162] Alternatively, as another example, in the case where the second passivation layer 134 and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 20 μm, and in the case where the second passivation layer 134, the second thin film layer 130b and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 25 μm.

[0163] Alternatively, as another example, in the case where the second passivation layer 134 and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 25 μm, and in the case where the second passivation layer 134, the second thin film layer 130b and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 30 μm.

[0164] In another optional example of this embodiment, since the size of the spacer 221 in the target direction can increase with the increase of the protective film layer 13 in the spacer 221, when the spacer 221 includes the first film layer 130a and the second film layer 130b, the spacing between the first film layer 130a and the second film layer 130b and the binding area 222 can be related to the size of the spacer 221 in the target direction.

[0165] For example, if the size of the spacer 221 in the target direction is 200 μm to 250 μm, the distance between the second film layer 130 b and the binding area 222 may be 45 μm to 80 μm, such as 45 μm or 80 μm.

[0166] In another exemplary embodiment, the distance between the second film layer 130b and the binding area 222 is greater than or equal to 10 μm and less than or equal to 20 μm; and the distance between the first film layer 130a and the binding area 222 is greater than or equal to 10 μm and less than or equal to 20 μm.

[0167] Among them, the distances between the first film layer 130a and the second film layer 130b and the binding area 222 can be different or the same. In different cases, the distance between the first film layer 130a and the binding area 222 can be greater than the distance between the second film layer 130b and the binding area 222. In this case, when cleaning the surface of the groove area 1022, the area of ​​the second passivation layer 134 in direct contact with the cleaning liquid can be reduced, thereby reducing the risk area of ​​corrosion to the lead layer 12 below.

[0168] Alternatively, for example, the distance between the first film layer 130a and the bonding area 222 can be smaller than the distance between the second film layer 130b and the bonding area 222. In this case, when cleaning the surface of the grooved area 1022, the area of ​​the first film layer 130a in direct contact with the cleaning solution can be reduced, thereby preventing a large area of ​​the first film layer 130a from being corroded during the cleaning process, thereby preventing residue from forming. Furthermore, since the second film layer 130b is closer to the bonding area 222, the risk area of ​​corrosion to the underlying lead layer 12 can be reduced. Furthermore, since the second film layer 130b is protected by the second passivation layer 134 above it, the risk of corrosion to the second film layer 130b can be reduced.

[0169] 13 shows a schematic cross-sectional structure diagram of another array substrate B in the display area 101. In this array substrate, the pixel electrode 133 in the display area 101 is electrically connected to the source and drain of the thin film transistor, and the common electrode 135 is closer to the substrate 11 than the pixel electrode 133.

[0170] As shown in FIG13 , the display area 101 may include:

[0171] substrate 11;

[0172] a gate 122 located on the substrate 11;

[0173] a gate insulating layer 14 located on a side of the gate 122 facing away from the substrate 11;

[0174] an active layer 122 c located on a side of the gate insulating layer 14 facing away from the substrate 11 ;

[0175] a source electrode 122 b and a drain electrode 122 a located on a side of the active layer 122 c facing away from the substrate 11 and overlapping the doped region of the active layer 122 c ;

[0176] A first passivation layer 131 located on a side of the source / drain electrode 122 a facing away from the substrate 11 ;

[0177] an organic film layer 132 located on a side of the first passivation layer 131 facing away from the substrate 11;

[0178] a common electrode 135 located on a side of the organic film layer 132 facing away from the substrate 11;

[0179] a second passivation layer 134 located on a side of the common electrode 135 facing away from the substrate 11;

[0180] a pixel electrode 133 located on a side of the second passivation layer 134 facing away from the substrate 11;

[0181] Among them, the pixel electrode 133 is overlapped with the drain electrode 122a below by opening a through hole on the first passivation layer 131, the second passivation layer 134 and the organic film layer 132. In this way, when manufacturing this type of array substrate, when digging holes in the organic film layer 132, the first passivation layer 131 and the second passivation layer 134, it is necessary to avoid the common electrode 135. In practice, a single mask plate can be used to etch the organic film, and the first passivation layer 131 and the second passivation layer 134 can be etched using the same mask plate. Therefore, when the organic film is removed, the structure of the first passivation layer 131 and the structure of the second passivation layer 134 can be the same, that is, the first passivation layer 131 can also extend to the spacer area 221.

[0182] In an alternative example of the array substrate B shown in FIG13 , as shown in FIG14 , the various protective film layers 13 in the lead region 1021 may include, in sequence: a first passivation layer 131, an organic film layer 132, a second passivation layer 134, and a first thin film layer 130a. In yet another alternative example of the array substrate B shown in FIG13 , as shown in FIG15 , the various protective film layers 13 in the lead region 1021 may include: a first passivation layer 131, an organic film layer 132, a second thin film layer 130b, a second passivation layer 134, and a first thin film layer 130a.

[0183] It should be noted that, unlike the array substrate A shown in FIG10 , in this array substrate B, the first thin film layer 130a in the lead region 1021 is provided on the same layer as the pixel electrode 133, and the second thin film layer 130b is provided on the same layer as the common electrode 135. The thicknesses and materials of the first passivation layer 131, the second thin film layer 130b, the organic film layer 132, the second passivation layer 134, and the first thin film layer 130a in the array substrate B shown in FIG13 can refer to the thicknesses and materials of the relevant film layers in the array substrate A shown in FIG10 , and are not further described here.

[0184] In an optional example of the array substrate B shown in Figure 13, referring to Figure 14, a schematic diagram of the cross-sectional structure of the array substrate B in the AA' direction is shown. As shown in Figure 14, the array substrate may further include a gate insulating layer 14 in the lead area 1021 in addition to the substrate 11 and the lead layer 12. The gate insulating layer 14 of the lead area 1021 and the gate insulating layer 14 of the display area 101 may be arranged in the same layer, that is, formed in a single film forming process; wherein, in addition to the second passivation layer 134 and the first thin film layer 130a extending to the spacer area 221, the first passivation layer 131 in the lead area 1021 also extends to the spacer area 221, and the first passivation layer 131 covers the spacer area 221; wherein, there is also a gap between the first thin film layer 130a and the binding area 222.

[0185] In a further optional example of this optional example, when the spacer 221 includes the first passivation layer 131, the second passivation layer 134 and the first thin film layer 130a, the size of the spacer 221 in the target direction can also be reduced. For example, the size of the spacer 221 in the target direction can also be greater than or equal to 20μm and less than or equal to 30μm. Optionally, it can be 25μm or 30μm.

[0186] Among them, the spacing distance between the first film layer 130a and the binding area 222 can be determined according to the size of the spacer area 221 in the target direction. If the size of the spacer area 221 in the target direction is between 20μm and 30μm, the spacing between the first film layer 130a and the binding area 222 can be 10μm to 20μm; if the size of the spacer area 221 in the target direction is between 200μm and 250μm, the spacing between the first film layer 130a and the binding area 222 can be 45μm to 80μm, such as 45μm, or 80μm.

[0187] In the array substrate in this example, as the number of protective film layers 13 in the lead area 1021 increases, the number of protective film layers 13 extending to the spacer area 221 can also increase, so that there can be three or more protective film layers 13 in the spacer area 221. This can increase the protection of the lead layer 12 and prevent water vapor from corroding the leads in the lead layer 12.

[0188] As shown in Figure 15, a schematic diagram of the cross-sectional structure of the array substrate B shown in Figure 13 in the AA' direction is shown. As shown in Figure 15, in an optional example of this embodiment, in addition to the first passivation layer 131, the second passivation layer 134 and the first thin film layer 130a extending into the spacer area 221, the second thin film layer 130b also extends into the spacer area 221; wherein, the second thin film layer 130b, like the first thin film layer 130a, has a gap with the binding area 222.

[0189] Among them, the spacing distance between the second film layer 130b and the binding area 222 can be determined according to the size of the spacer area 221 in the target direction. If the size of the spacer area 221 in the target direction is between 20μm and 30μm, the spacing between the second film layer 130b and the binding area 222 can be 10μm to 20μm; if the size of the spacer area 221 in the target direction is between 200μm and 250μm, the spacing between the second film layer 130b and the binding area 222 can be 45μm to 80μm, such as 45μm, or 80μm.

[0190] In some other examples, the spacing between the first film layer 130a and the binding area 222 can be the same as or different from the spacing between the second film layers 130b. The specific setting method can refer to the introduction of the first film layer 130a and the second film layer 130b in Figure 12 above, and is not limited here.

[0191] In the array substrate B in this example, the number of protective film layers 13 in the lead area 1021 increases to five, and correspondingly, the number of protective film layers 13 in the spacer area 221 increases to four. This can increase the protection of the lead layer 12 and prevent water vapor from corroding the leads in the lead layer 12.

[0192] As described above, as the number of film layers extending into the spacer 221 increases, the target size of the spacer 221 may also gradually increase. For example, the size of the spacer 221 in the target direction may vary within a range of 200 μm to 250 μm. For example, when the spacer 221 includes the second passivation layer 134 and the first thin film layer 130a, the size of the spacer 221 in the target direction may also be greater than or equal to 200 μm. When the second passivation layer 134, the first passivation layer 131, and the first thin film layer 130a extend into the spacer 221, the size of the spacer 221 in the target direction may also be greater than or equal to 225 μm and less than or equal to 250 μm. When the second passivation layer 134, the first passivation layer 131, the first thin film layer 130a, and the second thin film layer 130b extend into the spacer 221, the size of the spacer 221 in the target direction may also be equal to 250 μm.

[0193] As described above, when the spacer area 221 has three or more protective film layers 13 to protect the lead layer 12, the size of the spacer area 221 in the target direction can also be reduced. As shown in Figures 14 and 15, the size of the spacer area 221 in the target direction can also be greater than or equal to 20μm and less than or equal to 30μm. Optionally, it can be 25μm or 30μm.

[0194] Exemplarily, the size of the spacer 221 in the target direction can vary within 20μm-30μm, so as to increase with the increase of the protective film layer 13. For example, in the case where the spacer 221 includes the second passivation layer 134 and the first thin film layer 130a, in this case, the second passivation layer 134 will not be removed when the groove area is formed, wherein the size of the spacer 221 in the target direction may also be greater than or equal to 20μm. In the case where the second passivation layer 134, the first passivation layer 131 and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction may also be greater than or equal to 25μm and less than or equal to 30μm; in the case where the second passivation layer 134, the first passivation layer 131, the first thin film layer 130a and the second thin film layer 130b extend to the spacer 221, the size of the spacer 221 in the target direction may also be equal to 30μm.

[0195] Alternatively, when the second passivation layer 134 and the first thin film layer 130a extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 20μm; when the second passivation layer 134, the first passivation layer 131, the first thin film layer 130a and the second thin film layer 130b extend to the spacer 221, the size of the spacer 221 in the target direction can be equal to 25μm, and when the second passivation layer 134, the first passivation layer 131, the first thin film layer 130a and the second thin film layer 130b extend to the spacer 221, the size of the spacer 221 in the target direction can also be equal to 30μm.

[0196] Among them, for LCD display devices, they include various types of display devices. The above-mentioned array substrate A and array substrate B are the cases where the common electrode 135 and the pixel electrode 133 are both arranged on the array substrate, that is, the common electrode 135 and the pixel electrode 133 are both located on the same side of the liquid crystal layer; in practice, there are also other types of LCD display devices, in which the common electrode 135 and the pixel electrode 133 are respectively located on opposite sides of the liquid crystal layer. Generally speaking, the pixel electrode 133 is located on the array substrate, and the common electrode 135 is located on the counter substrate. This type of array substrate can be called an array substrate C, wherein the structure of the array substrate C in the display area 101 can refer to the structure of the array substrate in the display area 101 in the related art, for example, including a substrate 11, a gate 122 located on the substrate 11, and a gate insulating layer 14 located on the gate 122, an active layer 122c located on the gate insulating layer 14, a source and drain layer located on the active layer 122c, and a passivation layer located on the source and drain layer, an organic film layer 132 located on the passivation layer, and a pixel electrode 133 located on the organic film layer 132.

[0197] In this array substrate C, the lead area 1021 still includes a lead layer 12, and the lead layer 12 includes a lead connected to the gate 122 and a lead connected to the source and drain. The various protective film layers 13 in the lead layer 12 can still have the film layer structure described in any of Figures 11, 12, 14 and 15 above, wherein the arrangement of the various protective film layers 13 in the inter-isolation area can also refer to the film layer structure described in any of Figures 11, 12, 14 and 15; specifically, the first thin film layer 130a or the second thin film layer 130b in the lead area 1021 can be arranged in the same layer as the pixel electrode 133, and the first passivation layer 131 or the second passivation layer 134 can be arranged in the same layer as the passivation layer in the display area 101. As for the additional protective film layer 13 in the lead area 1021 compared to the display area 101, it can be specifically manufactured when manufacturing the array substrate, such as using a mask plate to add a passivation layer and a thin film layer made of indium tin oxide material.

[0198] For example, the present disclosure provides a preferred array substrate D, which may include, in the display area 101: a substrate 11; a gate electrode 122 located on the substrate 11; a gate insulating layer 14 located on a side of the gate electrode 122 facing away from the substrate 11; an active layer 122c located on a side of the gate insulating layer 14 facing away from the substrate 11; a source electrode 122b and a drain electrode 122a located on a side of the active layer 122c facing away from the substrate 11 and overlapping with the doped region of the active layer 122c; and a gate electrode 122b located on a side of the source-drain electrode 122a facing away from the substrate 11. a first passivation layer 131 on the side of the first passivation layer 131 facing away from the substrate 11; an organic film layer 132 located on the side of the first passivation layer 131 facing away from the substrate 11; a common electrode 135 located on the side of the organic film layer 132 facing away from the substrate 11; a second passivation layer 134 located on the side of the common electrode 135 facing away from the substrate 11; and a pixel electrode 133 located on the side of the second passivation layer 134 facing away from the substrate 11; wherein the pixel electrode 133 is connected to the drain electrode 122a below via a through hole provided in the first passivation layer 131, the second passivation layer 134, and the organic film layer 132;

[0199] The array substrate D may include, in the lead region 1021, a substrate 11, a gate insulating layer 14 located on the substrate 11, a lead layer 12 located on the gate insulating layer 14; a first passivation layer 131 located on the side of the lead layer 12 facing away from the substrate 11; an organic film layer 132 located on the side of the first passivation layer 131 facing away from the substrate 11; a second thin film layer 130b located on the side of the organic film layer 132 facing away from the substrate 11; a second passivation layer 134 located on the side of the second thin film layer 130b facing away from the substrate 11; and a first thin film layer 130a located on the side of the second passivation layer 134 facing away from the substrate 11. The second thin film layer 130b is provided on the same layer as the common electrode 135, and the first thin film layer 130a is provided on the same layer as the pixel electrode 133.

[0200] The array substrate D may include, in the spacer region 221: a first passivation layer 131 located above the lead layer 12; a second thin film layer 130b located above the first passivation layer 131; a second passivation layer 134 located above the second thin film layer 130b; and a first thin film layer 130a located above the second passivation layer 134; wherein the first passivation layer 131 and the second passivation layer 134 both fully cover the spacer region 221;

[0201] The array substrate D may include, in the binding area 222: a first passivation layer 131 located above the lead layer 12, and an extraction electrode 2211 located above the first passivation layer 131, wherein the extraction electrode 2211 is connected to the lead in the lead layer 12 through a hole opened in the first passivation layer 131;

[0202] Among them, the size of the spacer area 221 in the target direction can be 20μm-30μm, for example, 25μm; there is a gap between the first film layer 130a and the second film layer 130b and the binding area 222, and the size of the gap in the target manner, that is, the spacing can be 10μm-20μm, for example, 10μm.

[0203] Based on the same inventive concept, a display panel is provided. Referring to FIG. 16 , FIG. 16 shows a schematic diagram of the cross-sectional structure of the display panel. As shown in FIG. 16 , the display panel may include the array substrate 100 described in the above embodiment, and a matching substrate 200 that is matched with the array substrate, wherein a liquid crystal layer 300 is filled between the matching substrate and the array substrate.

[0204] In one optional example, a color filter layer can be set on the array substrate, so that filtering can be achieved on the path of the backlight source incident on the liquid crystal layer. In another optional example, a color filter layer can be set on the box substrate, so that the light emitted by the liquid crystal layer can be filtered.

[0205] Among them, when a color filter layer is set on the array substrate, the color filter layer can be set to the organic film layer 132 set in the display area 101 in the above embodiment, that is, the organic film layer 132 can achieve the function of filtering. In this case, the film layer set in the above display area 101 can be a transparent film layer.

[0206] In this optional example, for the groove area 1022 of the array substrate, its binding area 222 and part of the spacing area 221 can be understood as the area grown by the array substrate on the cutting line of the box substrate. For the spacing area 221, its topmost protective film layer 13 can be a film layer made of indium tin oxide ITO, such as the first film layer 130a. There is a gap between the first film layer 130a and the binding area 222, then a boundary of the orthographic projection of the box substrate on the array substrate can be aligned with the boundary of the first film layer 130a on the side of the binding area 222, that is, the orthographic projection of the box substrate 200 on the array substrate 100 has a gap with the binding area 222 in the array substrate. In one example, the spacing of the gap is greater than or equal to 10μm and less than or equal to 20μm; in another example, the size of the gap in the target direction can be 45μm-80μm.

[0207] Based on the same inventive concept, a display device is provided, as shown in Figures 17 and 18. Figure 17 shows a schematic diagram of the cross-sectional structure of the display device. As shown in Figure 17, the display device may include the display panel shown in Figure 16 above; wherein, the array substrate 100 in the display panel includes a binding area 222, the binding area 222 includes a lead-out electrode 2211 overlapped with the lead layer 12, and the pins of the control chip 400 are overlapped with the lead-out electrode 2211.

[0208] The control chip 400 can be either a driver chip or a touch chip, depending on whether the display device has touch capabilities. If so, the bonding area can include both the touch chip and the driver chip. If not, the bonding area can include the driver chip. Both the touch chip and the driver chip are bonded to the leads in the lead layer in the bonding area. The touch chip is specifically bonded to the leads connected to the touch signal lines, and the driver chip is specifically bonded to the leads connected to the data lines.

[0209] In some optional examples of this embodiment, the array substrate in the display device includes a groove area 1022 and a lead area 1021, and the groove area 1022 includes a spacer area 221 and a binding area 222, wherein a conductive film 15 is also applied in the groove area 1022, and the conductive film 15 covers part or all of the protective film layer 13 extending from the lead area 1021 to the spacer area 221.

[0210] 18a and 18b , taking the array substrate D as an example, two display devices are shown in plan view schematically in the non-display area 102 . Referring to FIG. 19a and FIG. 19b , FIG. 19a is a schematic diagram of the cross-sectional structure of the display device shown in FIG. 18a in the AA' direction, and FIG. 19b is a schematic diagram of the cross-sectional structure of the display device shown in FIG. 18b in the AA' direction.

[0211] As shown in Figures 18a and 19a, in some embodiments, the size of the conductive film 15 can be smaller than the size of the recessed area 1022. Thus, the conductive film 15 can cover a portion of the recessed area 1022, that is, the portion of the protective film layer 13 extending from the lead area 1021 to the spacer area 221. In this way, the orthographic projection of the conductive film 15 on the substrate 11 can be located within the orthographic projection of the recessed area 1022 on the substrate 11, that is, the orthographic projection of the conductive film 15 on the substrate 11 can cover a portion of the orthographic projection of the recessed area 1022 on the substrate 11. For example, the dimension h1 of the spacer area 221 on the array substrate in the target direction is greater than or equal to 200 μm and less than or equal to 250 μm; the dimension h3 of the conductive film 15 in the target direction can be greater than or equal to 70 μm and less than or equal to 110 μm; and the distance h2 between the topmost first film layer 130a in the spacer area 221 and the binding area 222 is 80 μm.

[0212] As shown in Figures 18b and 19b , in some embodiments, the size of the conductive film 15 can be larger than the size of the recessed area 1022. Thus, the conductive film 15 can cover the entire recessed area 1022, that is, fully cover the protective film layer 13 extending from the lead area 1021 to the spacer area 221. Thus, the orthographic projection of the conductive film 15 on the substrate 11 can cover the orthographic projection of the recessed area 1022 on the substrate 11. For example, in a display device, the dimension h1 of the spacer area 221 in the target direction on the array substrate is greater than or equal to 20 μm and less than or equal to 30 μm; wherein, the dimension h3 of the conductive film 15 in the target direction is greater than or equal to 70 μm and less than or equal to 110 μm, and the distance h2 between the topmost first film layer 130a in the spacer area 221 and the binding area 222 is 10 μm to 20 μm.

[0213] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0214] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, commodity, or device that includes the element.

[0215] The above is a detailed introduction to an array substrate, display panel and display device provided by the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, for those skilled in the art, according to the ideas of the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0216] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0217] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0218] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0219] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0220] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0221] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. An array substrate, wherein: include: substrate; The substrate is provided with a display area and a non-display area, the non-display area includes a lead area and a groove area, the groove area is located at a side of the lead area away from the display area, the groove area includes a binding area and a spacing area, the spacing area is located between the binding area and the lead area; Wherein, both the lead area and the trench area include a lead layer disposed on the substrate, and the lead area also includes a plurality of protective film layers stacked and disposed, and the plurality of protective film layers are located on a side of the lead layer away from the substrate; At least two of the protective film layers in the lead area extend to the spacing area; and / or a size of the spacing area in a target direction is greater than or equal to 20 μm and less than or equal to 30 μm, and the target direction is the direction from the binding area to the lead area.

2. The array substrate according to claim 1, wherein: The size of the spacer in the target direction increases as the number of protective film layers extending to the spacer increases.

3. The array substrate according to claim 2, wherein: In the case where at least three of the protective film layers extend to the spacer, a size of the spacer in the target direction is greater than or equal to 200 μm and less than or equal to 250 μm; In the case where the two protective film layers extend to the spacer region, a size of the spacer region in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

4. The array substrate according to any one of claims 1 to 3, wherein: The various protective film layers include: A first passivation layer, located on a side of the lead layer away from the substrate; an organic film layer, located on a side of the first passivation layer away from the substrate; A second passivation layer is located on a side of the organic film layer away from the substrate; A first thin film layer, located on a side of the second passivation layer away from the substrate; The second passivation layer and the first thin film layer extend to the spacing area, and the second passivation layer covers the spacing area, and there is a spacing between the first thin film layer and the binding area.

5. The array substrate according to claim 4, wherein: The first passivation layer further extends to the spacer region, and the first passivation layer covers the spacer region.

6. The array substrate according to claim 4, wherein: A size of the spacer in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

7. The array substrate according to claim 4, wherein: The distance between the binding area and the first film layer is greater than or equal to 10 μm and less than or equal to 20 μm.

8. The array substrate according to claim 4, wherein: The plurality of protective film layers further include: a second thin film layer, the second thin film layer is located on a side of the organic film layer away from the substrate, and the second passivation layer is located on a side of the second thin film layer away from the substrate; The second film layer further extends to the spacing area, and there is a spacing between the second film layer and the binding area.

9. The array substrate according to claim 8, wherein: The first passivation layer also extends to the spacer region, and the first passivation layer covers the spacer region.

10. The array substrate according to claim 8 or 9, wherein: A size of the spacer in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm.

11. The array substrate according to claim 10, wherein: The spacing between the second film layer and the binding area is greater than or equal to 10 μm and less than or equal to 20 μm; and the spacing between the first film layer and the binding area is greater than or equal to 10 μm and less than or equal to 20 μm.

12. The array substrate according to claim 8 or 9, wherein: The distance between the first film layer and the binding area is smaller than the distance between the second film layer and the binding area.

13. The array substrate according to claim 8, wherein: The display area includes: a plurality of pixel units arranged in an array, wherein the pixel units include a pixel electrode, a common electrode and a thin film transistor; The pixel electrode is electrically connected to the source and drain of the thin film transistor, and the common electrode is further away from the substrate than the pixel electrode; Wherein, the first thin film layer is disposed in the same layer as the common electrode, and the second thin film layer is disposed in the same layer as the pixel electrode.

14. The array substrate according to claim 5 or 9, wherein: The display area includes: a plurality of pixel units arranged in an array, wherein the pixel units include a pixel electrode, a common electrode and a thin film transistor; The pixel electrode is electrically connected to the source and drain of the thin film transistor, and the common electrode is closer to the substrate than the pixel electrode; Wherein, the first thin film layer is disposed in the same layer as the pixel electrode, and the second thin film layer is disposed in the same layer as the common electrode.

15. The array substrate according to claim 5 or 9, wherein: The thickness of the first passivation layer is greater than the thickness of the first thin film layer, and / or the thickness of the second passivation layer is greater than the thickness of the first thin film layer.

16. A display panel, wherein: It comprises the array substrate according to any one of claims 1 to 15, and a box-matching substrate arranged in a box with the array substrate, wherein a liquid crystal layer is filled between the box-matching substrate and the array substrate.

17. The display panel according to claim 16, wherein: There is a gap between the binding area in the array substrate and the orthographic projection of the aligning substrate on the array substrate, and the spacing is greater than or equal to 10 μm and less than or equal to 20 μm.

18. A display device, wherein: Comprising a control chip, and the display panel and the control chip according to any one of claims 16-17; Wherein, the array substrate in the display panel comprises a binding area, and the control chip is electrically connected to the lead layer in the binding area.

19. The display device according to claim 18, wherein: The array substrate in the display device includes a groove area and a lead area, and also includes: A conductive film, wherein the orthographic projection of the conductive film on the substrate covers part or all of the orthographic projection of the groove area on the substrate.

20. The driving substrate according to claim 19, wherein: The groove area includes a spacing area adjacent to the lead area and a binding area adjacent to the spacing area, wherein the size of the spacing area in the target direction is greater than or equal to 20 μm and less than or equal to 30 μm; wherein the size of the conductive film in the target direction is greater than or equal to 70 μm and less than or equal to 110 μm; The target mode is a direction in which the binding area points to the lead area.

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