Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises: a first substrate; a plurality of scanning lines; a plurality of first electrodes; a plurality of first signal lines and a plurality of second signal lines; each of the first signal line and the second signal line comprises a plurality of first parts and a plurality of second parts, and the first parts and the second parts are alternately arranged and electrically connected in the extension direction of the first signal line or the plurality of second signal lines; the orthographic projection of part of the first parts on the first substrate is located in a wiring area between two adjacent sub-pixel areas in the first direction, the orthographic projection of the second parts on the first substrate is located in a wiring area between two adjacent sub-pixel areas in the second direction, and the two first parts connected with the second parts are located in different columns in the second direction; in the second direction, the orthographic projection of the second part on the first substrate is located on the side, away from the orthographic projection of the adjacent first electrode on the first substrate, of the orthographic projection of the scanning line on the first substrate.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] With the continuous development and application of display technology, users have increasingly higher requirements for the display effects of electronic display products.

[0003] Currently, LCD products use a dual-gate design to reduce costs and increase screen-to-body ratio. This means a single data line can drive subpixels in two adjacent columns. To improve voltage polarity uniformity among the same subpixels, a bow-shaped data line is often used. However, capacitance exists between the horizontally extending portion of the bow-shaped data line and the pixel electrode, affecting display quality.

[0004] Summary of the Invention

[0005] An embodiment of the present disclosure provides an array substrate, the array substrate comprising:

[0006] The first substrate comprises a plurality of sub-pixel regions arrayed along a first direction and a second direction and a wiring region outside the sub-pixel regions; the first direction intersects the second direction;

[0007] Multiple scan lines, located in the wiring area;

[0008] A plurality of first electrodes; the orthographic projections of the first electrodes on the first substrate are at least partially located in the sub-pixel region;

[0009] A plurality of first signal lines and a plurality of second signal lines are located in a wiring area; the first signal line and the second signal line both include: a plurality of first portions and a plurality of second portions, in the extension direction of the first signal line or the plurality of second signal lines, the first portions and the second portions are alternately arranged and electrically connected, and the extension direction of the first portion intersects with the extension direction of the second portion; the orthographic projection of some of the first portions on the first substrate is located in the wiring area between two adjacent sub-pixel areas in the first direction, the orthographic projection of the second portion on the first substrate is located in the wiring area between two adjacent sub-pixel areas in the second direction, and the two first portions connected by the second portion are located in different columns in the second direction; in the second direction, the orthographic projection of the second portion on the first substrate is located on the side of the orthographic projection of the scanning line on the first substrate that is away from the orthographic projection of the first electrode adjacent to it on the first substrate.

[0010] In some embodiments, an orthographic projection of the first signal line on the first substrate and an orthographic projection of the second signal line on the first substrate do not overlap with each other;

[0011] The first signal line and the plurality of second signal lines are alternately arranged in a first direction;

[0012] A sub-pixel region is spaced between the first portion of at least partially adjacent first signal lines and the first portion of the second signal line, which are projected onto the first base substrate.

[0013] In some embodiments, in the second direction, two scan lines are provided in the wiring area between two adjacent sub-pixel areas;

[0014] The orthographic projection of the second portion on the first base substrate falls within a region between two adjacent scan lines in the wiring region and is within the orthographic projection of the first base substrate.

[0015] In some embodiments, the second portion of the first signal line includes: n first sub-portions, and n-1 second sub-portions; wherein n is an integer greater than 1;

[0016] The second portion of the second signal line includes: n third sub-portions, and n-1 fourth sub-portions;

[0017] The first sub-section and the third sub-section extend along the first direction, the extension direction of the second sub-section intersects both the first direction and the second direction, and the extension direction of the fourth sub-section intersects both the first direction and the second direction;

[0018] The second subsection connects the two first subsections, and the fourth subsection connects the two third subsections;

[0019] The sub-pixel area and the wiring area are divided into: a plurality of sub-pixel rows and wiring area rows arranged along the second direction and extending along the first direction; the sub-pixel rows and the wiring area rows are arranged alternately, and the wiring area rows include sub-areas corresponding to the sub-pixel areas one by one;

[0020] The two first portions connected by the second portion are separated by n sub-pixel regions in the first direction;

[0021] The orthographic projection of the second portion on the first substrate falls into the wiring area; the orthographic projections of the first sub-portion and the third sub-portion on the first substrate are located in the sub-area, and the orthographic projections of the second sub-portion and the fourth sub-portion on the first substrate pass between two adjacent sub-areas.

[0022] In some embodiments, the second portion of the first signal line includes n first sub-portions located on different straight lines in the first direction;

[0023] The second portion of the first signal line includes n first sub-portions located on different straight lines in the first direction, and the second portion of the second signal line includes n third sub-portions located on different straight lines in the first direction;

[0024] In the second direction, the first subsection is adjacent to the third subsection.

[0025] In some embodiments, the region between two adjacent sub-pixel regions in the second direction and between two adjacent scan lines in the wiring region includes only one first sub-portion and one third sub-portion.

[0026] In some embodiments, in the wiring area row, in the second direction, two third subportions adjacent to the second subportion of the first signal line and respectively located on both sides of the second subportion of the first signal line are located on different second signal lines;

[0027] In the area between two adjacent scan lines in the wiring region, in the second direction, two first subparts adjacent to the second subpart of the second signal line and located on both sides of the second subpart of the second signal line are located on different first signal lines.

[0028] In some embodiments, the first signal line further includes a third portion; the third portion connects the first portion and the first sub-portion, and an extension direction of the third portion intersects both the first direction and the second direction;

[0029] The second signal line further includes a fourth portion; the fourth portion connects the first portion and the third sub-portion, and an extending direction of the fourth portion intersects both the first direction and the second direction;

[0030] The third portion is adjacent to the fourth sub-portion, and the adjacent third portion and fourth sub-portion extend in the same direction;

[0031] The fourth portion is adjacent to the second sub-portion, and the adjacent second sub-portion and the fourth portion extend in the same direction.

[0032] In some embodiments, at least part of the fourth sub-portion is adjacent to two third portions located on different first signal lines;

[0033] At least part of the second sub-portion is adjacent to two fourth portions located on different second signal lines.

[0034] In some embodiments, in the i-th row of the wiring area, the second sub-portion, part of the fourth sub-portion, the third portion, and the fourth portion extend along the third direction, and the remaining fourth sub-portions extend along the fourth direction; wherein i is a positive integer;

[0035] In the (i+1)th row of the wiring area, part of the second sub-portion, part of the fourth sub-portion, the third portion, and the fourth portion extend along the fourth direction, and the remaining fourth sub-portion extends along the third direction;

[0036] In each common electrode line, an extension direction of the fourth sub-portion in the i-th wiring area is different from an extension direction of the fourth sub-portion in the i+1-th wiring area;

[0037] An included angle between the third direction and the positive direction of the first direction is greater than 0° and less than 90°, and an included angle between the fourth direction and the positive direction of the first direction is greater than 90° and less than 180°.

[0038] In some embodiments, the array substrate includes a plurality of second signal lines, and every three second signal lines form a group; in each group of second signal lines, in the i-th row wiring area, the fourth sub-portions of two adjacent second signal lines extend along the fourth direction, and the fourth sub-portion of another second signal line extends along the third direction.

[0039] In some embodiments, the array substrate further comprises: a plurality of thin film transistors; the thin film transistors comprise a first electrode, a second electrode, and a third electrode; the first electrode is electrically connected to the scan line, and the third electrode is electrically connected to the first signal line;

[0040] The scanning line includes a plurality of strip electrode lines; the plurality of strip electrode lines are alternately arranged and electrically connected with a plurality of first electrodes corresponding to the scanning line; in the second direction, the width of the first electrode is greater than the width of the strip electrode line.

[0041] In some embodiments, the strip electrode line and the edge of the first electrode facing the first electrode are located on the same straight line;

[0042] In the second direction, the first pole is adjacent to the third subsection.

[0043] In some embodiments, the patterns of the second pole and the third pole whose orthographic projections on the first substrate overlap with the orthographic projection of the first pole on the first substrate both include strips extending along the first direction;

[0044] In the second direction, the second pole is adjacent to the third subsection, and part of the first subsection is reused as the second pole;

[0045] The orthographic projection of the first sub-portion multiplexed as the second pole on the first substrate overlaps with the orthographic projection of the first pole on the first substrate; the orthographic projection of the first sub-portion not multiplexed as the second pole on the first substrate does not overlap with the orthographic projection of the first pole on the first substrate;

[0046] In the i-th row of the wiring area, the fourth sub-portion of the second signal line adjacent to the first sub-portion multiplexed as the second pole extends along the third direction, and the fourth sub-portion of the second signal line not adjacent to the first sub-portion multiplexed as the second pole extends along the fourth direction;

[0047] In the i+1th row of wiring area, the fourth subportion included in the second signal line adjacent to the first subportion multiplexed as the second pole extends along the fourth direction, and the fourth subportion included in the second signal line not adjacent to the first subportion multiplexed as the second pole extends along the third direction.

[0048] In some embodiments, the array substrate further includes: a second electrode located on a side of the first electrode facing away from the first base substrate; and an insulating film layer located between the second electrode and the second signal line; the second electrode being electrically connected to the second signal line via a first via hole penetrating the insulating film layer.

[0049] The third sub-portion includes a first strip portion and a first protrusion located on one side of the first strip portion in the second direction; the orthographic projection of the first via hole on the first base substrate falls within the orthographic projection of the third sub-portion on the first base substrate, and the orthographic projection of the first via hole on the first base substrate overlaps with the orthographic projection of the first protrusion on the first base substrate;

[0050] The orthographic projection of the first protrusion on the first base substrate is located on a side of the orthographic projection of the first strip portion on the first base substrate away from the orthographic projection of the first sub-portion reused as the second pole on the first base substrate.

[0051] In some embodiments, the plurality of strip electrode lines include a plurality of first strip electrode lines and a plurality of second strip electrode lines, and in a first direction, one end of the first electrode is electrically connected to the first strip electrode line, and the other end of the first electrode is electrically connected to the second strip electrode line; in the first direction, the first strip electrode line and the second strip electrode line are located on different straight lines;

[0052] In the second direction, the first pole is adjacent to the first subsection or the third subsection.

[0053] In some embodiments, an orthographic projection of the second portion on the first substrate and an orthographic projection of the first pole on the first substrate do not overlap with each other;

[0054] The pattern of the second pole having an overlapping portion with the orthographic projection of the first pole on the first substrate is a U-shaped pattern having a groove area; the pattern of the third pole having an overlapping portion with the orthographic projection of the first pole on the first substrate is a stripe-shaped pattern; the second pole and the third pole are arranged along the first direction;

[0055] The second pole electrically connected to the first portion and the first sub-portion are respectively located on both sides of the first portion in the first direction.

[0056] In some embodiments, in the i-th row of wiring regions, the second sub-portion, the fourth sub-portion, the third portion, and the fourth portion extend along a third direction; wherein i is a positive integer;

[0057] In the (i+1)th row of the wiring area, the second sub-portion, the fourth sub-portion, the third portion, and the fourth portion extend along a fourth direction;

[0058] An included angle between the third direction and the positive direction of the first direction is greater than 0° and less than 90°, and an included angle between the fourth direction and the positive direction of the first direction is greater than 90° and less than 180°.

[0059] In some embodiments, the array substrate further comprises: a plurality of thin film transistors; the thin film transistors comprise a first electrode, a second electrode, and a third electrode; the first electrode is electrically connected to the scan line, and the third electrode is electrically connected to the first signal line;

[0060] The scanning line includes a plurality of strip electrode lines; the plurality of strip electrode lines are alternately arranged and electrically connected to a plurality of first electrodes corresponding to the scanning line; in the second direction, the width of the first electrode is greater than the width of the strip electrode line;

[0061] The strip electrode line and the edge of the first electrode on a side facing away from the first electrode are located in the same straight line;

[0062] The orthographic projection of the first electrode on the first base substrate overlaps with a wiring area between two adjacent sub-pixel areas in the first direction.

[0063] In some embodiments, an orthographic projection of the second portion on the first substrate and an orthographic projection of the first pole on the first substrate do not overlap with each other;

[0064] The pattern of the portion where the orthographic projection of the second pole on the first substrate overlaps with the orthographic projection of the first pole on the first substrate has a groove area; the pattern of the portion where the orthographic projection of the third pole on the first substrate overlaps with the orthographic projection of the first pole on the first substrate is a stripe; the second pole and the third pole are arranged along the first direction;

[0065] A partial area of ​​the first portion of the first signal line is reused as a second pole.

[0066] In some embodiments, the array substrate further includes: a second electrode located on a side of the first electrode facing away from the first base substrate; and an insulating film layer located between the second electrode and the second signal line; the second electrode being electrically connected to the second signal line via a first via hole penetrating the insulating film layer.

[0067] The orthographic projection of the first via hole on the first substrate falls within the orthographic projection of the fourth sub-portion on the first substrate;

[0068] In the second portion of the second signal line, a line width of a fourth subportion electrically connected to the second electrode through the first via hole is greater than a line width of the third subportion.

[0069] In some embodiments, n=2.

[0070] In some embodiments, a line width of the second signal line is greater than a line width of the first signal line.

[0071] An embodiment of the present disclosure provides a display panel, comprising:

[0072] The array substrate provided by the embodiment of the present disclosure;

[0073] an opposite substrate, arranged opposite to the array substrate;

[0074] The liquid crystal layer is located between the array substrate and the opposite substrate.

[0075] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0077] FIG1 is a schematic structural diagram of an array substrate provided by related art;

[0078] FIG2 is a cross-sectional view along line AA′ in FIG1 ;

[0079] FIG3 is a cross-sectional view along line BB′ in FIG1 ;

[0080] FIG4 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0081] FIG5 is a cross-sectional view taken along CC' in FIG4;

[0082] FIG6 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0083] FIG7 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0084] FIG8 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0085] FIG9 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0086] FIG10 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0088] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0089] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0090] In related technologies, one method of driving subpixels to emit light using a dual-gate structure involves using a single data line to drive two adjacent columns of subpixels. However, because the data signals received by two columns of subpixels connected to the same data line in the dual-gate structure have the same polarity, the data signals received by subpixels connected to adjacent data lines have different polarities. For the same subpixel in each row of pixels, the probability of the voltage polarity between any two adjacent subpixels being the same is nearly 50%. Furthermore, for each column of subpixels, the voltage polarity of each subpixel is the same, making it impossible to spatially average the voltage polarity of the same subpixel in the same frame of an image. This results in the visual appearance of alternating light and dark stripes, also known as "shaking head wrinkles." Another method of driving subpixels to emit light is bow-shaped wiring, where the data lines are bow-shaped, and the common voltage line between the data lines is also bow-shaped, which can improve the uniformity of the subpixel polarity distribution. However, as shown in FIG1 , since the bow-shaped wiring has a transverse portion a1, both the data line 24 and the common voltage signal line 25 have a transverse portion a1, which is located on the side of the scanning line 1 facing the pixel electrode P1. The cross-sectional view of AA' in FIG1 is shown in FIG2 , and the cross-sectional view of BB' in FIG1 is shown in FIG3 . The distance h1 between the transverse portion a1 and the pixel electrode P1 is relatively close. Both the transverse portion a1 of the data line 24 and the transverse portion a1 of the common voltage signal line 25 generate capacitance with the pixel electrode P1, which affects the charging of the sub-pixel and thus affects the display effect.

[0091] An embodiment of the present disclosure provides an array substrate, as shown in FIG4 and FIG5 , the array substrate includes:

[0092] The first base substrate 1 includes a plurality of sub-pixel regions 101 arranged in an array along a first direction X and a second direction Y, and a wiring region 102 located outside the sub-pixel regions 101; the first direction X intersects the second direction Y;

[0093] A plurality of scan lines 4 are located in the wiring area 102;

[0094] A plurality of first electrodes 5 are located in the sub-pixel area 101;

[0095] A plurality of first signal lines 2 and a plurality of second signal lines 3 are located in a wiring area 102; the first signal lines 2 and the second signal lines 3 each include: a plurality of first portions 6 and a plurality of second portions 7, the first portions 6 and the second portions 7 being alternately arranged and electrically connected, and the extension direction of the first portions 6 intersects with the extension direction of the second portions 7; the orthographic projection of part of the first portions 6 on the first substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the first direction X, the orthographic projection of the second portions 7 on the first substrate 1 is located in the wiring area 102 between two adjacent sub-pixel areas 101 in the second direction Y, and the two first portions 6 connected by the second portion 7 are located in different columns in the second direction Y; in the second direction Y, the orthographic projection of the second portion 7 on the first substrate 1 is located on the side of the orthographic projection of the scan line 4 on the first substrate 1 that is away from the orthographic projection of the first electrode 5 adjacent to it on the first substrate 1.

[0096] In the array substrate provided by the embodiments of the present disclosure, both the first and second signal lines include alternating and electrically connected first and second portions, with the first and second portions extending in intersecting directions. This means that both the first and second signal lines extend in an "arch" shape, which can improve sub-pixel polarity uniformity. Furthermore, in the second direction, the orthographic projection of the second portion of the first or second signal line on the first substrate is located on the side of the orthographic projection of the scan line on the first substrate facing away from the adjacent first electrode. This increases the distance between the second portion and the first electrode, thereby preventing the formation of capacitance between the second portion and the first electrode that affects the charging of the first electrode, thereby improving display quality.

[0097] It should be noted that FIG5 is a cross-sectional view along CC' in FIG4 .

[0098] It should be noted that, as shown in FIG4 , the first portion 6 extends generally along the second direction Y, and the second portion 7 extends generally along the first direction X. The first portion 6 extending generally along the second direction Y means that at least a portion of the first portion 6 extends along the first direction, or that the angle between the actual extension direction of at least a portion of the first portion 6 and the first direction X is relatively small. The second portion 7 extending generally along the first direction X means that at least a portion of the second portion 7 extends along the first direction X, or that the angle between the actual extension direction of at least a portion of the second portion 7 and the first direction X is relatively small.

[0099] It should be noted that the multiple sub-pixel areas correspond to the areas divided by the multiple scan lines, the multiple first signal lines, and the multiple second signal lines. When the array substrate is applied to a display product, as shown in FIG4 , the array substrate is divided into a display area AA and a peripheral area NA surrounding the display area AA. The sub-pixel area 101 is only located in the display area AA, and the display area AA and the peripheral area NA both include a wiring area 102. The sub-pixel area corresponds to the sub-pixel opening area of ​​the display area of ​​the display product. The wiring area corresponds to the sub-pixel non-opening area and the peripheral area of ​​the display area of ​​the display product. The area between any two adjacent sub-pixel areas is the wiring area.

[0100] In a specific implementation, as shown in FIG5 , the distance h2 between the second portion 7 and the first electrode 5 is greater than the distance h1 between the horizontal portion a1 and the pixel electrode P1 in the related art.

[0101] In some embodiments, as shown in Figure 4, the array substrate further includes: a plurality of thin film transistors TFT; the thin film transistor TFT includes a first electrode, a second electrode and a third electrode; the first electrode is electrically connected to the scan line 4, the second electrode is electrically connected to the first signal line 2, and the third electrode is electrically connected to the first electrode 5.

[0102] In some embodiments, the second electrode, the third electrode, the first signal line, and the second signal line are disposed in the same layer. The scan line and the first electrode are disposed in the same layer. The second electrode, the third electrode, the first signal line, and the second signal line are located on a side of the scan line and the first electrode facing away from the first substrate. The first electrode is located on a side of the second electrode, the third electrode, the first signal line, and the second signal line facing away from the first substrate.

[0103] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0104] In some embodiments, as shown in FIG5 , the array substrate further includes:

[0105] The second electrode 16 is located on a side of the first electrode 5 facing away from the first substrate 1 .

[0106] In a specific implementation, the second electrode can be provided on the entire surface, for example. The second electrode is electrically connected to a plurality of second signal lines.

[0107] That is, in the disclosed embodiment, the first electrode is a pixel electrode, and the second electrode is a common electrode. Both the first electrode and the second electrode are transparent electrodes. The first electrode and the second electrode are made of the same material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0108] Of course, in specific implementation, if the array substrate is applied to a touch display product, in the touch stage, the second electrode can also serve as a touch electrode, and the second signal line can also serve as a touch signal line for transmitting a touch signal.

[0109] In some embodiments, as shown in FIG4 , the orthographic projection of the first signal line 2 on the first substrate 1 and the orthographic projection of the second signal line 3 on the first substrate 1 do not overlap with each other, thereby avoiding interference between the first signal line and the second signal line.

[0110] In some embodiments, as shown in FIG4 , the first signal lines 2 and the second signal lines 3 are alternately arranged in the first direction X;

[0111] A sub-pixel region 101 is spaced between the orthographic projections of at least partially adjacent first portions 6 of the first signal lines 2 and first portions 6 of the second signal lines 3 on the first base substrate 1 .

[0112] In some embodiments, as shown in FIG. 4 , in the display area AA, a sub-pixel area 101 is spaced between the orthographic projections of any adjacent first portion 6 of the first signal line 2 and the first portion 6 of the second signal line 3 on the first base substrate 1 .

[0113] In some embodiments, the lengths of the plurality of first signal lines are all equal, and the lengths of the plurality of second signal lines are all equal. This ensures that the resistances of the plurality of first signal lines are consistent and that of the plurality of second signal lines are consistent, which is beneficial to the uniformity of signal transmission. Accordingly, the first portion of the outermost first signal line or the second signal line is located in the peripheral area NA, and part of the second portion of the outermost first signal line or the second signal line also extends to the peripheral area. As shown in FIG4 , the first portion 6 of part of the first signal line 2 or the second signal line 3 extends to the peripheral area NA, that is, the first portion 6 marked as 6-1 in FIG4 . In FIG4 , there is no sub-pixel area between the first portion 6 marked as 6-1 and the first portion 6 adjacent thereto. However, the distance between the first portion 6 located in the peripheral area and the first portion 6 adjacent thereto is equal to the distance between the two adjacent first portions in the display area AA.

[0114] In some embodiments, in the first direction X, the distances between any two adjacent first portions are equal.

[0115] Alternatively, in some embodiments, the distance between a first portion in the peripheral area and an adjacent first portion is smaller than the distance between two adjacent first portions in the display area, thereby reducing the size of the peripheral area and facilitating narrow-frame display.

[0116] In some embodiments, as shown in FIG4 , two scan lines 4 are provided in the wiring area 102 between any two adjacent sub-pixel areas 101 in the second direction Y. Specifically, the plurality of scan lines 4 include a plurality of first scan lines 4 - 1 and a plurality of second scan lines 4 - 2 ; the first scan lines 4 - 1 and the second scan lines 4 - 2 are alternately arranged; and one first scan line 4 - 1 and one second scan line 4 - 2 are provided between any two adjacent sub-pixel areas 101 in the second direction Y.

[0117] In a specific implementation, a row of sub-pixel regions arranged along the first direction corresponds to a first scan line and a second scan line. That is, in the second direction, a first scan line and a second scan line are located on either side of a row of sub-pixel regions. In other words, the scan lines of the array substrate provided in the embodiment of the present disclosure adopt a dual-gate design.

[0118] In some embodiments, as shown in FIG4 , the orthographic projection of the second portion 7 on the first substrate 1 falls within the orthographic projection of the first substrate 1 in the region between two adjacent scan lines 4 in the wiring region 102. That is, the orthographic projection of the second portion 7 on the first substrate 1 falls within the orthographic projection of the first substrate 1 in the region between the first scan line 4-1 and the second scan line 4-2.

[0119] In some embodiments, as shown in FIG. 4 , the orthographic projection of the second portion 7 on the first base substrate 1 and the orthographic projection of the scan line 4 on the first base substrate 1 do not overlap with each other.

[0120] In some embodiments, as shown in FIG. 4 , the two first portions 6 connected to the second portion 7 are spaced apart by n sub-pixel regions 101 in the first direction X; wherein n is an integer greater than 1.

[0121] In some embodiments, n=2. FIG4 takes n=2 as an example for illustration.

[0122] 4 , the second portions 7 of adjacent first signal lines 2 and second signal lines 3 are staggered in the first direction X. That is, in the adjacent first signal lines 2 and second signal lines 3 , in the second direction Y, the second portions 7 of the two are adjacent only in a partial area.

[0123] In some embodiments, as shown in FIG. 4 , the second portion 7 of some first signal lines 2 is adjacent to the second portions 7 of two different second signal lines 3 , and the second portion 7 of some second signal lines 3 is adjacent to the second portions 7 of two different first signal lines 2 .

[0124] In some embodiments, as shown in FIG4 , the second portion 7 of the first signal line 2 includes: n first sub-portions 701 , and n−1 second sub-portions 702 ;

[0125] The second portion 7 of the second signal line 3 includes: n third sub-portions 703 , and n-1 fourth sub-portions 704 ;

[0126] The first sub-portion 701 and the third sub-portion 703 extend along the first direction X, the extension direction of the second sub-portion 702 intersects both the first direction X and the second direction Y, and the extension direction of the fourth sub-portion 704 intersects both the first direction X and the second direction Y.

[0127] The second sub-portion 702 connects the two first sub-portions 701 , and the second portion 7 of the first signal line 2 includes n first sub-portions 701 located on different straight lines in the first direction X;

[0128] The fourth sub-portion 704 connects the two third sub-portions 703 . The n first sub-portions 701 included in the second portion 7 of the first signal line 2 are located on different straight lines in the first direction X. The n third sub-portions 703 included in the second portion 7 of the second signal line 3 are located on different straight lines in the first direction X.

[0129] In the second direction Y, the first sub-portion 701 is adjacent to the third sub-portion 703 .

[0130] In an array substrate provided by an embodiment of the present disclosure, the second portion of a first signal line includes n first sub-portions and n-1 second sub-portions, the second sub-portions extending in a direction intersecting the first sub-portions. Thus, the n first sub-portions included in the second portion of the first signal line are located on different straight lines in a first direction X, i.e., the second portion of the first signal line has a zigzag shape. The second portion of a second signal line includes n third sub-portions and n-1 fourth sub-portions, the fourth sub-portions extending in a direction intersecting the third sub-portions. Thus, the n third sub-portions included in the second portion of the second signal line are located on different straight lines in the first direction X, i.e., the second portion of the second signal line has a zigzag shape. In situations where the second portions of adjacent first and second signal lines are staggered in the first direction, the second portions of some first signal lines are adjacent to the second portions of two different second signal lines, and the second portions of some second signal lines are adjacent to the second portions of two different first signal lines, compared to situations where the second portion is straight, the zigzag shape of the second portion is more conducive to rationally utilizing the wiring space between two scan lines and helps avoid excessively increasing the space occupied by the second portions of the first and second signal lines in the second direction.

[0131] It should be noted that the positions of the first signal lines, scan lines, second signal lines, and first electrodes of the array substrate are schematically illustrated in Figure 4. The patterns of the first signal lines, scan lines, second signal lines, and first electrodes are described below using Figures 6 to 8 as examples.

[0132] In some embodiments, as shown in FIG6 to FIG8 , the sub-pixel region 101 and the wiring region 102 are divided into: a plurality of sub-pixel rows 11 and wiring region rows 10 arranged along the second direction Y and extending along the first direction X, and a plurality of sub-pixel columns 26 and a plurality of wiring region columns 27 extending along the second direction Y and arranged along the first direction X; the sub-pixel rows 11 and the wiring region rows 10 are arranged alternately; the sub-pixel columns 26 and the wiring region columns 27 are arranged alternately;

[0133] The two first portions 6 connected to the second portion 7 are separated by n sub-pixel areas 101 in the first direction X;

[0134] The orthographic projection of the second portion 7 on the first substrate 1 falls into the wiring area row 10; and the orthographic projections of the first sub-portion 701 and the third sub-portion 703 on the first substrate 1 overlap with the sub-pixel column 26, and the orthographic projections of the second sub-portion 702 and the fourth sub-portion 704 on the first substrate 1 overlap with the wiring area column 27.

[0135] In the array substrate provided by the embodiment of the present disclosure, the first sub-portion and the third sub-portion extend along the first direction X, which helps to avoid excessive increase in the space occupied by the second portion in the second direction and excessive increase in the width of the wiring area to reduce the aperture ratio.

[0136] In a specific implementation, each first subsection and each third subsection corresponds to only one subpixel column, and each second subsection and each fourth subsection corresponds to one wiring area column. The first subsections corresponding to two subpixel columns are connected via the second subsection, such that the second portion of the first signal line extends in a zigzag pattern. The third subsections corresponding to two subpixel columns are connected via the fourth subsection, such that the second portion of the second signal line extends in a zigzag pattern.

[0137] In some embodiments, in the first direction, the width of the first subsection is greater than the width of the second subsection, and the width of the third subsection is greater than the width of the fourth subsection.

[0138] In a specific implementation, since the extension directions of the third sub-part and the fourth sub-part intersect with the first direction and the second direction, in the first direction, the width of the first sub-part is greater than the width of the second sub-part, and the width of the third sub-part is greater than the width of the fourth sub-part, the width of the corresponding second sub-part and the fourth sub-part in the second direction can also be set smaller to avoid excessively increasing the space occupied by the second part in the second direction, and to avoid excessively increasing the width of the wiring area and resulting in a reduction in the aperture ratio.

[0139] In some embodiments, as shown in Figures 6 to 8 , the area between two adjacent sub-pixel areas 101 in the second direction Y and between two adjacent scan lines 4 in the wiring area 102 includes only one first sub-portion 701 and one third sub-portion 703. This allows for reasonable utilization of the wiring space between the two scan lines, avoiding an increase in the width of the wiring area due to a large number of first sub-portions and third sub-portions disposed in the second direction between the two scan lines, thereby preventing a reduction in the aperture ratio.

[0140] In some embodiments, as shown in FIG6 to FIG8 , in the wiring area row 10 , in the second direction Y, two third sub-portions 703 adjacent to the second sub-portion 702 of the first signal line 2 and located on both sides of the second sub-portion 702 of the first signal line 2 are located on different second signal lines 3 ;

[0141] In the area between two adjacent scan lines 4 in the wiring area 102 , in the second direction Y, two first sub-portions 701 adjacent to the second sub-portion 702 of the second signal line 3 and located on both sides of the second sub-portion 702 of the second signal line 3 are located on different first signal lines 2 .

[0142] In some embodiments, taking n=2 as an example, as shown in Figures 6 to 8, in the second direction Y, a first sub-portion 701 of the second portion 7 of a portion of the first signal line 2 is adjacent to the third sub-portion 703 of a second signal line 3, another first sub-portion 701 of the second portion 7 of the first signal line 2 is adjacent to the third sub-portion 703 of another second signal line 3, and the third sub-portions 703 of the two second signal lines 3 are respectively located on both sides of the second portion 7 of the first signal line 2 in the second direction Y; a third sub-portion 703 of the second portion 7 of a portion of the second signal line 3 is adjacent to the first sub-portion 701 of a first signal line 2, and another third sub-portion 703 of the second portion 7 of the second signal line 3 is adjacent to the first sub-portion 701 of another first signal line 2.

[0143] In some embodiments, as shown in FIG6 to FIG8 , the first signal line 2 further includes a third portion 8 ; the third portion 8 connects the first portion 6 and the first sub-portion 701 , and the extension direction of the third portion 8 intersects both the first direction X and the second direction Y;

[0144] The second signal line 3 further includes a fourth portion 9; the fourth portion 9 connects the first portion 6 and the third sub-portion 703, and the extension direction of the fourth portion 9 intersects both the first direction X and the second direction Y;

[0145] The third portion 8 is adjacent to the fourth sub-portion 704 , and the adjacent third portion 8 and the fourth sub-portion 704 extend in the same direction;

[0146] The fourth portion 9 is adjacent to the second sub-portion 702 , and the adjacent second sub-portion 702 and the fourth portion 9 extend in the same direction.

[0147] It should be noted that the second and fourth sub-portions correspond to the area between two adjacent columns of sub-pixel areas, and this area also corresponds to the region where the first portion and the second portion are electrically connected. When the second and fourth sub-portions extend in directions that intersect both the first and second directions, providing a third portion parallel to the fourth sub-portion to connect the first and second portions of the first signal line, and providing a fourth portion parallel to the second sub-portion to connect the first and second portions of the second signal line, facilitates the efficient use of the wiring space between the two scan lines.

[0148] In a specific implementation, as shown in Figure 7 , the first portion 6 and the first sub-portion 701 need to be connected via the third portion 8 . Alternatively, as shown in Figures 6 and 8 , the third portion 8 may be used to connect the first portion 6 and the first sub-portion 701 only in some areas, while the first portion 6 and the first sub-portion 701 are directly connected in the remaining areas. Whether the third portion is required to connect the first portion and the first sub-portion can be determined based on the actual wiring space.

[0149] In some embodiments, as shown in FIG6 to FIG8 , at least part of the fourth sub-portion 704 is adjacent to two third portions 8 located on different first signal lines 2 ;

[0150] At least part of the second sub-portion 702 is adjacent to two fourth portions 9 located on different second signal lines 3 .

[0151] In some embodiments, as shown in Figures 6 to 8, the array substrate includes three second signal lines 3 in the plurality of second signal lines 3 as a group; specifically, every three second signal lines 3 in the plurality of second signal lines 3 as a group, that is, the plurality of second signal lines 3 are divided into a plurality of second signal line groups 17, and the pattern of the second signal line group 17 is a repeating unit; each second signal line group 17 includes a first second signal line 3-1, a second second signal line 3-2, and a third second signal line 3-3 arranged in sequence in the first direction X.

[0152] In a specific implementation, as shown in Figures 6 to 8 , every three first signal lines 2 in the plurality of first signal lines 2 form a first signal line group 28, i.e., the pattern of the first signal line group 28 forms a repeating unit. Thus, for the entire array substrate, the three first signal lines 2 in the first signal line group 28 and the three second signal lines 3 in the second signal line group 17 are alternately arranged as a repeating unit. The first signal line group 28 includes: a first first signal line 2-1, a second first signal line 2-2, and a third first signal line 22-3.

[0153] In some embodiments, as shown in FIG6 and FIG7 , in the i-th wiring area row 10 , the second sub-portion 702 , part of the fourth sub-portion 704 , the third portion 8 , and the fourth portion 9 extend along the third direction X1 , and the remaining fourth sub-portion 704 extends along the fourth direction X2 ; wherein i is a positive integer;

[0154] In the (i+1)th wiring area row 10, at least part of the second sub-portion 702, part of the fourth sub-portion 704, the third portion 8, and the fourth portion 9 extend along the fourth direction X2, and the remaining fourth sub-portion 704 extends along the third direction X1;

[0155] In each second signal line, the extension direction of the fourth sub-portion 704 in the i-th wiring area row 10 is different from the extension direction of the fourth sub-portion 704 in the (i+1)-th wiring area row 10;

[0156] The angle between the third direction X1 and the positive direction X+ of the first direction X is greater than 0° and less than 90°. The angle between the fourth direction X2 and the positive direction X+ of the first direction X is greater than 90° and less than 180°.

[0157] It should be noted that the angle between the portion of the extension direction located in the positive direction Y+ of the first direction X and the positive direction X+ of the first direction X is greater than 0° and less than 90°, which means that when the extension direction passes through the origin of the coordinate system formed by the first direction X and the second direction Y, the angle between the portion of the extension direction located in the positive direction Y+ of the second direction Y and the positive direction X+ of the first direction X is greater than 0° and less than 90°, that is, the extension direction extends along the first and third quadrants of the coordinate system formed by the first direction X and the second direction Y. The angle between the portion of the extension direction located in the positive direction Y+ of the first direction X and the positive direction X+ of the first direction X is greater than 90° and less than 180°, which means that when the extension direction passes through the origin of the coordinate system formed by the first direction X and the second direction Y, the angle between the portion of the extension direction located in the positive direction Y+ of the second direction Y and the positive direction X+ of the first direction X is greater than 90° and less than 180°, that is, the extension direction extends along the second and fourth quadrants of the coordinate system formed by the first direction X and the second direction Y.

[0158] In a specific implementation, for example, in the odd-numbered wiring area rows, the second subportion, part of the fourth subportion, the third portion, and the fourth portion extend along the third direction X1, and the remaining fourth subportion extends along the fourth direction X2; in the even-numbered wiring area rows, at least part of the second subportion, part of the fourth subportion, the third portion, and the fourth portion extend along the fourth direction X2, and the remaining fourth subportion extends along the third direction X1. Alternatively, in the even-numbered wiring area rows, the second subportion, part of the fourth subportion, the third portion, and the fourth portion extend along the third direction X1, and the remaining fourth subportion extends along the fourth direction X2; in the odd-numbered wiring area rows, at least part of the second subportion, part of the fourth subportion, the third portion, and the fourth portion extend along the fourth direction X2, and the remaining fourth subportion extends along the third direction X1.

[0159] In some embodiments, as shown in Figures 6 and 7 , the array substrate includes a plurality of second signal lines 3, wherein each group of three second signal lines 3 is formed. In each group of second signal lines 3, in the i-th row wiring area 10, the fourth subportions 704 of two adjacent second signal lines 3 extend along the fourth direction X2, and the fourth subportion 704 of another second signal line 3 extends along the third direction X1. Accordingly, in the group of second signal lines 3, in the i+1-th row wiring area 10, the fourth subportions 704 of two adjacent second signal lines 3 extend along the third direction X1, and the fourth subportion 704 of another second signal line 3 extends along the fourth direction X2.

[0160] Specifically, as shown in Figures 6 and 7, every three second signal lines 3 in the multiple second signal lines 3 are grouped as a group, that is, the multiple second signal lines 3 are divided into multiple second signal line groups 17, and the pattern of the second signal line group 17 is a repeating unit; each second signal line group 17 includes a first second signal line 3-1, a second second signal line 3-2, and a third second signal line 3-3 arranged in sequence in the first direction X; in the i-th row wiring area 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the fourth direction X2, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the third direction X1; in the i+1-th row wiring area 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the third direction X1, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the fourth direction X2.

[0161] In a specific implementation, the i-th row of wiring area is an odd row, and the i+1-th row of wiring area is an even row. Alternatively, the i-th row of wiring area is an even row, and the i+th row of wiring area is an odd row.

[0162] In some embodiments, as shown in Figures 6 and 7, the scan line 4 includes a plurality of strip electrode lines 401; the plurality of strip electrode lines 401 are alternately arranged and electrically connected to a plurality of first electrodes G corresponding to the scan line 4; in the second direction Y, the width of the first electrode G is greater than the width of the strip electrode line 401.

[0163] In the array substrate provided by the embodiment of the present disclosure, the fourth part, the third sub-part and the fourth sub-part are connected in sequence. When the extension directions of the fourth part and the fourth sub-part intersect, the fourth part, the third sub-part and the fourth sub-part connected in sequence form a groove area for accommodating the first pole.

[0164] In some embodiments, as shown in FIG6 , the strip electrode line 401 and the edge of the first electrode G facing the first electrode 5 are located on the same straight line;

[0165] In the second direction Y, the first pole G is adjacent to the third sub-portion 703 .

[0166] In the array substrate provided by the embodiment of the present disclosure, as shown in FIG6 , the edges of the strip electrode lines 401 and the first electrodes G facing the first electrode 5 are located on the same straight line. In the second direction Y, the width of the first electrodes G is greater than the width of the strip electrode lines 401. That is, the pattern composed of the scan lines 4 and the plurality of first electrodes G has a protrusion at the first electrodes G that faces away from the first electrode 5 adjacent to the two. The protrusion of the first electrodes facing the side of the first electrode can increase the area of ​​the sub-pixel region, thereby increasing the sub-pixel aperture ratio.

[0167] In some embodiments, as shown in FIG6 , the patterns of the second pole S and the third pole D whose orthographic projections on the first substrate 1 overlap with the orthographic projections of the first pole G on the first substrate 1 both include strips extending along the first direction X;

[0168] In the second direction Y, the second pole S is adjacent to the third sub-portion 8, and part of the first sub-portion 701 is reused as the second pole S;

[0169] The orthographic projection of the first sub-portion 701 multiplexed as the second pole S on the first substrate substrate 1 overlaps with the orthographic projection of the first pole G on the first substrate substrate 1; the orthographic projection of the first sub-portion 701 not multiplexed as the second pole S on the first substrate substrate 1 does not overlap with the orthographic projection of the first pole G on the first substrate substrate 1.

[0170] In some embodiments, as shown in FIG6 , the plurality of thin-film transistors TFT include a plurality of first thin-film transistors TFT1 and a plurality of second thin-film transistors TFT2 . The first sub-portion 701 electrically connected to the first thin-film transistor TFT1 is not reused as the second electrode S. The second electrode S of the first thin-film transistor TFT1 and the first sub-portion 701 electrically connected thereto are located on either side of the first portion 6 in the first direction X. The first sub-portion 701 electrically connected to the second thin-film transistor TFT2 is reused as the second electrode S.

[0171] In some embodiments, as shown in FIG6 , in the i-th wiring area row 10 , the second sub-portion 702 , part of the fourth sub-portion 704 , the third portion 8 , and the fourth portion 9 extend along the third direction X1 , and the remaining fourth sub-portion 704 extends along the fourth direction X2 ; wherein i is a positive integer;

[0172] In the (i+1)th wiring area row 10, the second subportion 702, part of the fourth subportion 704, the third portion 8, and the fourth portion 9 extend along the fourth direction X2, and the remaining fourth subportion 704 extends along the third direction X1.

[0173] In some embodiments, as shown in FIG6 , in the i-th wiring area row 10 , the fourth sub-portion 704 of the second signal line 3 adjacent to the first sub-portion 701 multiplexed as the second pole S extends along the third direction X1, and the fourth sub-portion 704 of the second signal line 3 not adjacent to the first sub-portion 701 multiplexed as the second pole S extends along the fourth direction X2;

[0174] In the i+1th row wiring area row 10, the fourth sub-portion 704 included in the second signal line 3 adjacent to the first sub-portion 701 multiplexed as the second pole S extends along the fourth direction X2, and the fourth sub-portion 704 included in the second signal line 3 not adjacent to the first sub-portion 701 multiplexed as the second pole S extends along the third direction X1.

[0175] In the array substrate provided by the embodiment of the present disclosure, as shown in FIG6 , in the second signal line 3 not adjacent to the first sub-portion 701 multiplexed as the second pole S, the fourth portion 9, the third sub-portion 703, and the fourth sub-portion 704, which are connected in sequence, form a first groove area E1. The first pole G is provided in the first groove area E1. This facilitates maximum utilization of the space between the two scan lines.

[0176] In some embodiments, as shown in FIG. 6 , the third sub-portion 703 that is not adjacent to the first sub-portion 701 multiplexed as the second electrode S is adjacent to the second electrode S of the first thin film transistor TFT1 on a side away from the first sub-portion 701 .

[0177] In some embodiments, as shown in FIG6 , the third electrode D includes a first sub-electrode D1, a second sub-electrode D2, and a third sub-electrode D3. The second sub-electrode D2 connects the first sub-electrode D1 and the third sub-electrode D3. The orthographic projections of the first sub-electrode D1 and the third sub-electrode D3 on the first substrate 1 are strips extending along the first direction X. The orthographic projection of the first sub-electrode D1 on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1. The orthographic projection of the third sub-electrode D3 on the first substrate 1 overlaps with the orthographic projection of the first electrode 5 on the first substrate 1. The first electrode 5 is electrically connected to the third sub-electrode D3. In the first direction X, the width of the second sub-electrode D2 is less than the length of the first sub-electrode D1 and the third sub-electrode D3.

[0178] In the array substrate provided by the embodiment of the present disclosure, the third electrode D includes a first sub-electrode D1, a second sub-electrode D2, and a third sub-electrode D3, which are approximately in the shape of an "I". The first sub-electrode D1 and the third sub-electrode D3 are in the shape of a bar, and the second sub-electrode D2 is smaller in size, thereby ensuring the electrical connection area between the third electrode and the first electrode and reducing the overlapping capacitance between the third electrode and the first electrode, thereby reducing the pixel voltage jump caused by the overlapping capacitance between the third electrode and the first electrode and improving the operating stability of the thin film transistor.

[0179] In some embodiments, as shown in FIG6 , the second electrode S of the first thin-film transistor TFT1 includes a fourth sub-electrode S1 and a fifth sub-electrode S2. The fourth sub-electrode S1 is a strip extending along the first direction X. The fifth sub-electrode S2 is adjacent to the fourth sub-portion 704, and the adjacent fifth sub-electrode S2 and the fourth sub-portion 704 extend in the same direction. Furthermore, in the i-th wiring area 10, the fifth sub-electrode S2 extends along the fourth direction X2; in the i+1-th wiring area 10, the fifth sub-electrode S2 extends along the third direction X1.

[0180] In some embodiments, as shown in FIG6 , the plurality of thin film transistors TFT corresponding to the wiring area row 10 are divided into a plurality of first repeating unit groups 24 - 1 or a plurality of second repeating unit groups 24 - 2 ;

[0181] The first repeating unit group 24-1 includes m first units 2401 and k second units 2402, and the second repeating unit group 24-2 includes k first units 2401 and m second units 2402; wherein m and k are both positive integers and are not equal to each other;

[0182] The first unit 2401 includes one or two first thin film transistors TFT1, and the second unit 2402 includes one or two second thin film transistors TFT2;

[0183] In the second direction, the first units 2401 and the second units 2402 are arranged alternately.

[0184] That is, in a specific implementation, as shown in FIG6 , in the second direction Y, one side of each sub-pixel row 11 corresponds to a plurality of first repeating unit groups 24 - 1 , and the other side corresponds to a second repeating unit group 24 - 2 .

[0185] In a specific implementation, as shown in FIG6 , for example, the i-th wiring area row 10 includes a plurality of first repeating unit groups 24 - 1 , and the (i+1)-th wiring area row 10 includes a plurality of second repeating unit groups 24 - 2 .

[0186] In a specific implementation, the i-th wiring area row is an odd-numbered wiring area row, and the i+1-th wiring area row is an even-numbered wiring area row, that is, the multiple thin film transistors corresponding to the odd-numbered wiring area row are divided into multiple first repeating unit groups, and the multiple thin film transistors corresponding to the even-numbered wiring area row are divided into multiple second repeating unit groups. Alternatively, the i-th wiring area row is an even-numbered wiring area row, and the i+1-th wiring area row is an odd-numbered wiring area row, that is, the multiple thin film transistors corresponding to the even-numbered wiring area row are divided into multiple first repeating unit groups, and the multiple thin film transistors corresponding to the odd-numbered wiring area row are divided into multiple second repeating unit groups.

[0187] In a specific implementation, the first row of the wiring area includes a first scan line but does not include a second scan line, the first unit includes a first thin film transistor electrically connected to the first scan line, and the second unit includes a second thin film transistor electrically connected to the first scan line. The last row of the wiring area includes the second scan line but does not include the first scan line, the first unit includes a first thin film transistor electrically connected to the second scan line, and the second unit includes a second thin film transistor electrically connected to the second scan line.

[0188] In a specific implementation, in the remaining wiring area rows except the first row wiring area row 10 and the last row wiring area row 10, as shown in Figure 6, the first unit 2401 includes two first thin film transistors TFT1 corresponding to different sub-pixel rows 11 and corresponding to different sub-pixel columns 26, and the two first thin film transistors TFT1 are electrically connected to the first scan line 4-1 and the second scan line 4-2, respectively. The second unit 2402 includes two second thin film transistors TFT2 corresponding to different sub-pixel rows 11 and corresponding to different sub-pixel columns 26, and the two second thin film transistors TFT2 are electrically connected to the first scan line 4-1 and the second scan line 4-2, respectively.

[0189] In some embodiments, as shown in FIG6 , m=1, k=2.

[0190] In some embodiments, as shown in FIG6 , in the first direction X, in the remaining wiring area rows 11 except the first wiring area row 11 and the last wiring area row 11, in adjacent first units 2401 and second units 2402, the first thin film transistor TFT1 and the second thin film transistor TFT2 located in adjacent sub-pixel columns 26 correspond to the same sub-pixel row 11; in two adjacent second units 2402, the second thin film transistor TFT2 located in adjacent sub-pixel columns 26 correspond to different sub-pixel rows 11;

[0191] In the i-th wiring area row 11, among the plurality of thin film transistors TFT electrically connected to the second scan line 4-2, two adjacent second thin film transistors TFT2 are separated by one sub-pixel column 26, a first thin film transistor TFT1 and an adjacent second thin film transistor TFT2 in the positive direction X+ of the first direction X are located in adjacent sub-pixel columns 26, and the first thin film transistor TFT1 and an adjacent second thin film transistor TFT2 in the negative direction X- of the first direction X are separated by two sub-pixel columns 26;

[0192] In the i-th wiring area row 11, among the plurality of thin film transistors TFT electrically connected to the first scan line 4-1, two adjacent second thin film transistors TFT2 are separated by one sub-pixel column 26, a first thin film transistor TFT1 and a second thin film transistor TFT2 adjacent thereto in the negative direction X- of the first direction X are located in adjacent sub-pixel columns 26, and the first thin film transistor TFT1 and a second thin film transistor TFT2 adjacent thereto in the positive direction X+ of the first direction X are separated by two sub-pixel columns 26;

[0193] In the (i+1)th row 11 of the wiring region, among the plurality of thin-film transistors TFT electrically connected to the second scan line 4-2, one sub-pixel column 26 is spaced between two adjacent first thin-film transistors TFT1, a second thin-film transistor TFT2 is located in an adjacent sub-pixel column 26 to the first thin-film transistor TFT1 adjacent thereto in the positive direction X+ of the first direction X, and two sub-pixel columns 26 are spaced between the second thin-film transistor TFT2 and the first thin-film transistor TFT1 adjacent thereto in the negative direction X− of the first direction X;

[0194] In the (i+1)th row 11 of the wiring area, among the multiple thin-film transistors TFT electrically connected to the first scan line 4-1, one sub-pixel column 26 is spaced between two adjacent first thin-film transistors TFT1, the second thin-film transistor TFT2 and the first thin-film transistor TFT1 adjacent to it in the negative direction X- of the first direction X are located in the adjacent sub-pixel column 26, and the second thin-film transistor TFT2 and the first thin-film transistor TFT1 adjacent to it in the positive direction X+ of the first direction X are spaced two sub-pixel columns 26 apart.

[0195] It should be noted that, in FIG6 , the rightward extending direction is taken as the positive direction X+ of the first direction X, and the leftward extending direction is taken as the negative direction X− of the first direction X. As shown in FIG6 , FIG6 is a block diagram of a first direction X+.

[0196] In some embodiments, as shown in FIG6 , for the remaining wiring area rows 10 except the first row of wiring area rows 10 and the last row of wiring area rows 10, in the second repeating unit group 24-2, the two first thin film transistors TFT1 of one first unit 2401 are electrically connected to the first first signal line 2-1 and the third first signal line 2-3, respectively, the two first thin film transistors TFT1 of another first unit 2401 are electrically connected to the first first signal line 2-1 and the second first signal line 2-2, respectively, and the two second thin film transistors TFT2 of the second unit 2402 are electrically connected to the second first signal line 2-1 and the second first signal line 2-2, respectively. The first signal line 2-2 is electrically connected to the third first signal line 2-3; in the first repeating unit group 24-1, the two first thin film transistors TFT1 of the first unit 2401 are electrically connected to the second first signal line 2-2 and the third first signal line 2-3, respectively, the two second thin film transistors TFT2 of one second unit 2402 are electrically connected to the first first signal line 2-1 and the second first signal line 2-2, respectively, and the two second thin film transistors TFT2 of the other second unit 2402 are electrically connected to the first first signal line 2-1 and the third first signal line 2-3, respectively.

[0197] In some embodiments, as shown in FIG6 , in the i-th wiring area row 11, in adjacent first units 2401 and second units 2402, the first thin film transistor TFT1 electrically connected to the same first signal line 2 and the second thin film transistor TFT are separated by one sub-pixel column 26; in two adjacent second units 2402, the two second thin film transistors TFT2 electrically connected to the same first signal line 2 are located in adjacent sub-pixel columns 26;

[0198] In the i+1th row wiring area 11, in adjacent first units 2401 and second units 2402, there is one sub-pixel column 26 between the first thin-film transistor TFT1 and the second thin-film transistor TFT2 electrically connected to the same first signal line 2; in two adjacent first units 2401, there are two sub-pixel columns 26 between the two first thin-film transistors TFT1 electrically connected to the same first signal line 2.

[0199] In some embodiments, as shown in Figure 6, in each second signal line group 17, in the i-th row wiring area row 10, the thin film transistor TFT adjacent to the first second signal line 3-1 and the second second signal line 3-2 is the second thin film transistor TFT2, and the thin film transistor TFT adjacent to the third second signal line 3-3 is the first thin film transistor TFT1; in the i+1-th row wiring area row 10, the thin film transistor TFT adjacent to the first second signal line 3-1 and the second second signal line 3-2 is the first thin film transistor TFT1, and the thin film transistor TFT adjacent to the third second signal line 3-3 is the second thin film transistor TFT2.

[0200] In some embodiments, as shown in Figure 5, the array substrate further includes: an insulating film layer 18 located between the second electrode 16 and the second signal line 3; as shown in Figure 6, the second electrode (not shown in Figure 6) is electrically connected to the second signal line 3 through a first via 1801 that passes through the insulating film layer (not shown in Figure 6).

[0201] In some embodiments, as shown in FIG6 , part of the third sub-portion 703 includes a first strip portion 7032 and a first protrusion 7031 located on one side of the first strip portion 7032 in the second direction Y; the orthographic projection of the first via hole 1801 on the first base substrate 1 falls within the orthographic projection of the third sub-portion 703 on the first base substrate 1, and the orthographic projection of the first via hole 1801 on the first base substrate 1 overlaps with the orthographic projection of the first protrusion 7031 on the first base substrate 1;

[0202] The orthographic projection of the first protrusion 7031 on the first base substrate 1 is located on a side of the orthographic projection of the first strip portion 7032 on the first base substrate 1 away from the orthographic projection of the first sub-portion 701 reused as the second pole S on the first base substrate 1 .

[0203] Specifically, as shown in Figure 6, the first strip portion 7032 includes a first sub-strip portion 70321 adjacent to the first protruding portion 7031, and the orthographic projection of the first via 1801 on the first base substrate 1 falls within the pattern composed of the first protruding portion 7031 and the first sub-strip portion 70321, that is, the F area is within the orthographic projection of the first base substrate 1.

[0204] In some embodiments, as shown in Figure 6, in each second signal line group 17, in the i-th row wiring area row 10, the first second signal line 3-1 and the second second signal line 3-2 include the first protrusion 7031, and the third second signal line 3-3 does not include the first protrusion 7031; in the i+1-th row wiring area row 10, the first second signal line 3-1 and the second second signal line 3-2 do not include the first protrusion 7031, and the third second signal line 3-3 includes the first protrusion 7031.

[0205] In some embodiments, the width of the pattern composed of the first protrusion and the first sub-strip portion in the first direction is greater than the width of the first via in the first direction, and the width of the pattern composed of the first protrusion and the first sub-strip portion in the second direction is greater than the width of the first via in the second direction.

[0206] In some embodiments, the width of the orthographic projection of the first via hole on the first substrate in the first direction and the width of the orthographic projection of the first via hole in the second direction are both approximately 8 microns. Therefore, the width of the pattern formed by the first protrusion and the first sub-strip portion in the first direction and the width of the pattern formed by the first protrusion and the first sub-strip portion in the second direction are approximately 14 microns. In a specific implementation, the orthographic projection of the first via hole on the first substrate is circular or rectangular. The width of the orthographic projection of the first via hole on the first substrate in the first direction and the width of the pattern formed by the first protrusion and the first sub-strip portion in the first direction and the width of the pattern formed by the first protrusion and the first sub-strip portion in the first direction and the width of the pattern formed by the first protrusion and the first sub-strip portion in the second direction can be specifically set based on actual process capabilities, etc.

[0207] In some embodiments, as shown in FIG5 , the array substrate further includes: a buffer layer 12 located between the first base substrate 1 and the scan line 4; an interlayer insulating layer 13 located between the scan line 4 and the first signal line 2; a planarization layer 14 located between the first signal line 2 and the first electrode 5; and a protective layer 15 located between the first electrode 5 and the second electrode 16. The insulating film layer 18 located between the second electrode 16 and the second signal line 3 includes the protective layer 15 and the planarization layer 14.

[0208] In some embodiments, as shown in Figures 6 to 8 , the second electrode 16 includes slit portions 1601 corresponding one-to-one to the sub-pixel regions 101, and each slit portion 1601 includes a plurality of slits 16011. In a specific implementation, the second electrode 16 can be provided on the entire surface, for example. As shown in Figure 6 , the entire second electrode 16 also includes a plurality of opening regions 1602, and the opening regions 1602 are located in the wiring region row 10.

[0209] Of course, in a specific implementation, the scan lines, the first signal lines, the second signal lines, and the thin film transistors may also be other patterns.

[0210] In some embodiments, as shown in FIG7 , the plurality of strip electrode lines 401 include a plurality of first strip electrode lines 401 - 1 and a plurality of second strip electrode lines 401 - 2 . In the first direction X, one end of the first electrode G is electrically connected to the first strip electrode line 401 - 1 , and the other end of the first electrode G is electrically connected to the second strip electrode line 401 - 2 . In the first direction X, the first strip electrode line 401 - 1 and the second strip electrode line 401 - 2 are located on different straight lines.

[0211] In the second direction Y, the first pole G is adjacent to the first sub-portion 701 or the third sub-portion 703 .

[0212] In the array substrate provided by the embodiments of the present disclosure, in a first direction X, the first and second strip electrode lines are located on different straight lines, and the two ends of the first electrode are connected to the first and second strip electrode lines, respectively. Thus, as shown in FIG7 , the pattern of the first electrode G and the scan line 4 has a recessed region Q. The third electrode D includes a sixth sub-electrode D4 and a seventh sub-electrode D5 connected to the sixth sub-electrode D4. The seventh sub-electrode D5 is electrically connected to the first electrode 5. The orthographic projection of the sixth sub-electrode D4 on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1. The orthographic projection of the seventh sub-electrode D5 on the first substrate 1 does not overlap with the orthographic projection of the first electrode G on the first substrate 1. The orthographic projection of the seventh sub-electrode D5 on the first substrate 1 is located in the recessed region Q. The seventh sub-electrode D5 is electrically connected to the first electrode 5 via a via whose orthographic projection falls into the recessed region Q. The recessed region Q is located in the wiring area 102. Specifically, the seventh sub-electrode D5 is electrically connected to the first electrode 5 in the wiring region 102. This connection between the seventh sub-electrode D5 and the first electrode 5 does not occupy space in the sub-pixel region 101, further improving the sub-pixel aperture ratio. In a specific implementation, the width of the seventh sub-electrode D5 in the second direction Y is greater than the width of the sixth sub-electrode D4. This increases the contact area between the seventh sub-electrode D5 and the first electrode 5, improving electrical connection performance.

[0213] In some embodiments, as shown in FIG. 7 , the number of thin film transistors corresponding to the remaining wiring area rows 10 except the first wiring area row 10 and the last wiring area row 10 is equal to the number of sub-pixel columns.

[0214] In some embodiments, as shown in FIG7 , the plurality of thin film transistors TFT include a plurality of third thin film transistors TFT3 and a plurality of fourth thin film transistors TFT4 ;

[0215] The first electrode G of the third thin film transistor TFT3 is adjacent to the first sub-portion 701 , and the first electrode G of the fourth thin film transistor TFT4 is adjacent to the third sub-portion 703 .

[0216] In some embodiments, as shown in FIG. 7 , the plurality of thin film transistors TFT corresponding to the wiring area row 10 are divided into a plurality of third repeating unit groups 24 - 3 or fourth repeating unit groups 24 - 4 ;

[0217] The third repeating unit group 24-3 includes: p third units 2403 and q fourth units 2404; wherein p and q are both positive integers and p and q are not equal;

[0218] The third unit 2403 includes one or two third thin film transistors TFT3, and the fourth unit 2404 includes one or two fourth thin film transistors TFT4;

[0219] In the second direction, the third units 2403 and the fourth units 2404 are arranged alternately.

[0220] That is, in a specific implementation, as shown in FIG. 7 , in the second direction Y, one side of each sub-pixel row 11 corresponds to a plurality of third repeating unit groups 24 - 3 , and the other side corresponds to a fourth repeating unit group 24 - 4 .

[0221] In a specific implementation, as shown in FIG. 7 , for example, the i-th wiring area row 10 includes a plurality of third repeating unit groups 24 - 3 , and the (i+1)-th wiring area row 10 includes a plurality of fourth repeating unit groups 24 - 4 .

[0222] In a specific implementation, the i-th wiring area row is an odd-numbered wiring area row, and the i+1-th wiring area row is an even-numbered wiring area row, that is, the multiple thin film transistors corresponding to the odd-numbered wiring area row are divided into multiple third repeating unit groups, and the multiple thin film transistors corresponding to the even-numbered wiring area row are divided into multiple fourth repeating unit groups. Alternatively, the i-th wiring area row is an even-numbered wiring area row, and the i+1-th wiring area row is an odd-numbered wiring area row, that is, the multiple thin film transistors corresponding to the even-numbered wiring area row are divided into multiple third repeating unit groups, and the multiple thin film transistors corresponding to the odd-numbered wiring area row are divided into multiple fourth repeating unit groups.

[0223] In a specific implementation, the first row of the wiring area includes a first scan line but does not include a second scan line, the third unit includes a third thin-film transistor electrically connected to the first scan line, and the fourth unit includes a fourth thin-film transistor electrically connected to the first scan line. The last row of the wiring area includes the second scan line but does not include the first scan line, the third unit includes a third thin-film transistor electrically connected to the second scan line, and the fourth unit includes a fourth thin-film transistor electrically connected to the second scan line.

[0224] In a specific implementation, in the remaining wiring area rows except the first row wiring area row 10 and the last row wiring area row 10, as shown in Figure 7, the third unit 2403 includes two third thin-film transistors TFT3 corresponding to different sub-pixel rows 11 and corresponding to different sub-pixel columns 26, and the two third thin-film transistors TFT3 are electrically connected to the first scan line 4-1 and the second scan line 4-2, respectively. The fourth unit 2404 includes two fourth thin-film transistors TFT4 corresponding to different sub-pixel rows 11 and corresponding to different sub-pixel columns 26, and the two fourth thin-film transistors TFT4 are electrically connected to the first scan line 4-1 and the second scan line 4-2, respectively.

[0225] In some embodiments, as shown in FIG7 , p=1, q=2.

[0226] In some embodiments, as shown in FIG7 , in the first direction X, in the remaining wiring area rows 11 except the first wiring area row 11 and the last wiring area row 11, in adjacent third units 2403 and fourth units 2404, the third thin film transistor TFT3 and the fourth thin film transistor TFT4 located in adjacent sub-pixel columns 26 correspond to the same sub-pixel row 11; in two adjacent fourth units 2404, the fourth thin film transistor TFT4 located in adjacent sub-pixel columns 26 correspond to different sub-pixel rows 11;

[0227] In the i-th wiring area row 11, among the plurality of thin film transistors TFT electrically connected to the second scan line 4-2, two adjacent fourth thin film transistors TFT4 are separated by one sub-pixel column 26, the third thin film transistor TFT3 and the fourth thin film transistor TFT4 adjacent thereto in the negative direction X- of the first direction X are located in adjacent sub-pixel columns 26, and the third thin film transistor TFT3 and the fourth thin film transistor TFT4 adjacent thereto in the positive direction X+ of the first direction X are separated by two sub-pixel columns 26;

[0228] In the i-th wiring area row 11, among the plurality of thin film transistors TFT electrically connected to the first scan line 4-1, two adjacent fourth thin film transistors TFT4 are separated by one sub-pixel column 26, the third thin film transistor TFT3 and the adjacent fourth thin film transistor TFT4 in the positive direction X+ of the first direction X are located in adjacent sub-pixel columns 26, and the third thin film transistor TFT3 and the adjacent fourth thin film transistor TFT4 in the negative direction X- of the first direction X are separated by two sub-pixel columns 26;

[0229] In the (i+1)th row 11 of the wiring region, among the plurality of thin-film transistors TFT electrically connected to the second scan line 4-2, two adjacent third thin-film transistors TFT3 are separated by one sub-pixel column 26, the fourth thin-film transistor TFT4 is located in an adjacent sub-pixel column 26 to the third thin-film transistor TFT3 adjacent thereto in the negative direction X− of the first direction X, and the fourth thin-film transistor TFT4 is located in an adjacent sub-pixel column 26 to the third thin-film transistor TFT3 adjacent thereto in the positive direction X+ of the first direction X.

[0230] In the (i+1)th row 11 of the wiring area, among the multiple thin-film transistors TFT electrically connected to the first scan line 4-1, one sub-pixel column 26 is spaced between two adjacent third thin-film transistors TFT3, the fourth thin-film transistor TFT4 and the third thin-film transistor TFT3 adjacent to it in the positive direction X+ of the first direction X are located in adjacent sub-pixel columns 26, and the fourth thin-film transistor TFT4 and the third thin-film transistor TFT3 adjacent to it in the negative direction X- of the first direction X are spaced two sub-pixel columns 26 apart.

[0231] It should be noted that, in FIG. 7 , the rightward extending direction is taken as the positive direction X+ of the first direction X, and the leftward extending direction is taken as the negative direction X− of the first direction X. As shown in FIG.

[0232] In some embodiments, as shown in FIG7 , for the remaining wiring area rows 10 except the first row of wiring area rows 10 and the last row of wiring area rows 10, in the fourth repeating unit group 24-4, the two third thin film transistors TFT3 of one third unit 2403 are electrically connected to the first first signal line 2-1 and the third first signal line 2-3, respectively, the two third thin film transistors TFT3 of another third unit 2403 are electrically connected to the first first signal line 2-1 and the second first signal line 2-2, respectively, and the two fourth thin film transistors TFT4 of the fourth unit 2404 are electrically connected to the second first signal line 2-1 and the second first signal line 2-2, respectively. The first signal line 2-2 is electrically connected to the third first signal line 2-3; in the third repeating unit group 24-3, the two third thin-film transistors TFT3 of the third unit 2403 are electrically connected to the second first signal line 2-2 and the third first signal line 2-3, respectively; the two fourth thin-film transistors TFT4 of one fourth unit 2404 are electrically connected to the first first signal line 2-1 and the second first signal line 2-2, respectively; and the two fourth thin-film transistors TFT4 of the other fourth unit 2404 are electrically connected to the first first signal line 2-1 and the third first signal line 2-3, respectively.

[0233] In some embodiments, as shown in FIG7 , in the i-th wiring area row 11, in adjacent third units 2403 and fourth units 2404, a sub-pixel column 26 is spaced between the third thin-film transistor TFT3 and the second thin-film transistor TFT electrically connected to the same first signal line 2; and in two adjacent fourth units 2404, two sub-pixel columns 26 are spaced between the two fourth thin-film transistors TFT4 electrically connected to the same first signal line 2.

[0234] In the i+1th row wiring area 11, in the adjacent third unit 2403 and the fourth unit 2404, the third thin-film transistor TFT3 and the fourth thin-film transistor TFT4 electrically connected to the same first signal line 2 are separated by one sub-pixel column 26; in two adjacent third units 2403, the two third thin-film transistors TFT3 electrically connected to the same first signal line 2 are located in adjacent sub-pixel columns 26.

[0235] In some embodiments, as shown in FIG. 7 , in the i-th wiring area row 10 , the second sub-portion 702 , part of the fourth sub-portion 704 , the third portion 8 , and the fourth portion 9 extend along the third direction X1 , and the remaining fourth sub-portion 704 extends along the fourth direction X2 ; wherein i is a positive integer;

[0236] In the (i+1)th wiring area row 10, part of the second subportion 702, part of the fourth subportion 704, the third portion 8, and the fourth portion 9 extend along the fourth direction X2, and the remaining fourth subportion 704 and the remaining second subportion 702 extend along the third direction X1.

[0237] In some embodiments, as shown in Figure 7, the scan line 4 also includes a third strip electrode line 401-3; the third strip electrode line 401-3 connects the first strip electrode line 401-1 and the second strip electrode line 401-2; the third strip electrode line 401-3 crosses both the first direction X and the second direction Y; part of the third strip electrode line 401-3 is adjacent to the fourth portion 9, and part of the third strip electrode line 401-3 is adjacent to the second sub-portion 702; and the adjacent third strip electrode lines 401-3 have the same extension direction as the fourth portion 9, and the adjacent third strip electrode lines 401-3 have the same extension direction as the second sub-portion 702.

[0238] In a specific implementation, the third strip electrode line is connected to the first strip electrode line and the second strip electrode line, so that the scanning line and the first electrode pattern in the area corresponding to the third strip electrode line also have a recessed area Q. At least a portion of the third strip electrode line is located in the wiring area column, that is, between adjacent sub-pixel columns. The third strip electrode line is adjacent to the fourth portion or the second sub-portion and extends in the same direction, which is conducive to the rational use of the wiring space in the wiring area row.

[0239] In some embodiments, as shown in FIG. 7 , the third strip electrode line 401 - 3 extends along a third direction X1 .

[0240] In some embodiments, as shown in Figure 7, in the i-th wiring area row 10, the third strip electrode line 401-3 is adjacent to the fourth portion 9; in the i+1-th wiring area row 10, the third strip electrode line 401-3 is adjacent to the second sub-portion 702, that is, in the i+1-th wiring area row 10, the second sub-portion 702 adjacent to the third strip electrode line 401-3 extends along the third direction X1, and the remaining second sub-portions 702 extend along the fourth direction X2.

[0241] In some embodiments, as shown in Figure 7, in each second signal line group 17, in the i-th row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the fourth direction X2, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the third direction X1; in the i+1-th row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the third direction X1, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the fourth direction X2.

[0242] In a specific implementation, the i-th row is an odd row, and the i+1-th row is an even row, that is, in each second signal line group 17, in the odd-numbered row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the fourth direction X2, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the third direction X1; in the even-numbered row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the third direction X1, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the fourth direction X2. Alternatively, the i+1th row is an odd row, and the ith row is an even row, that is, in each second signal line group 17, in the even-numbered row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the fourth direction X2, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the third direction X1; in the odd-numbered row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 extends along the third direction X1, and the fourth sub-portion 704 of the third second signal line 3-3 extends along the fourth direction X2.

[0243] In some embodiments, as shown in FIG7 , in each second signal line group 17, in the i-th wiring area row 10, the third sub-portion 703 of the first second signal line 3-1 and the second second signal line 3-2 is adjacent to the first pole G, and the third sub-portion 703 of the third second signal line 3-3 is not adjacent to the first pole G; in the i+1-th wiring area row 10, the third sub-portion 703 of the first second signal line 3-1 and the second second signal line 3-2 is not adjacent to the first pole G, and the third sub-portion 703 of the third second signal line 3-3 is adjacent to the first pole G; correspondingly, in the i-th wiring area row 10, the third second signal line 3-3 is adjacent to the second second signal line 3-3. The first subportion 701 of the first signal line 2 between the first second signal line 3-2 and the first subportion 701 of the first signal line 2 between the third second signal line 3-3 and the first second signal line 3-1 are both adjacent to the first pole G; in the i+1-th row wiring area row 10, the first subportion 701 of the first signal line 2 between the first second signal line 3-1 and the second second signal line 3-2, the first subportion 701 of the first signal line 2 between the third second signal line 3-3 and the second second signal line 3-2, and the first subportion 701 of the first signal line 2 between the third second signal line 3-3 and the first second signal line 3-1 are all adjacent to the first pole G.

[0244] In some embodiments, as shown in Figure 7 , when the extension direction of the fourth portion 9 intersects that of the fourth sub-portion 704, the sequentially connected fourth portion 9, third sub-portion 703, and fourth sub-portion 704 form a second recessed region E2, where a first electrode G is disposed. This facilitates maximum utilization of the space between rows of wiring areas. When the extension direction of the third portion 8 intersects that of the second sub-portion 702, the sequentially connected first sub-portion 701 and second sub-portion 702 of the third portion 8 form a third recessed region E3, where a first electrode G is disposed. This facilitates maximum utilization of the space between rows of wiring areas.

[0245] In some embodiments, as shown in FIG7 , the orthographic projection of the second portion 7 on the first substrate 1 and the orthographic projection of the first pole G on the first substrate 1 do not overlap with each other;

[0246] The pattern of the overlapping portion of the orthographic projection of the second electrode S on the first substrate 1 and the orthographic projection of the first electrode G on the first substrate 1 has a groove area. FIG7 illustrates the U-shaped pattern in which the overlapping portion of the orthographic projection of the second electrode S on the first substrate 1 and the orthographic projection of the first electrode G on the first substrate 1 is used as an example. The pattern of the overlapping portion of the orthographic projection of the third electrode D on the first substrate 1 and the orthographic projection of the first electrode G on the first substrate 1 is a stripe; that is, the orthographic projection pattern of the sixth sub-electrode D4 on the first substrate 1 is a stripe. The second electrode S and the third electrode D are arranged along the first direction X.

[0247] The second pole S electrically connected to the first portion 6 and the first sub-portion 701 are located on both sides of the first portion 6 in the first direction X, respectively.

[0248] In the array substrate provided by the present disclosure, as shown in FIG7 , the groove region of the pattern where the orthographic projection of the second electrode S on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1 opens toward the first direction X, i.e., the U-shaped opening faces the first direction X. Furthermore, the pattern where the orthographic projection of the third electrode D on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1 is strip-shaped, and the strip extends deep into the groove region of the pattern where the orthographic projection of the second electrode S on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1. This can increase the length of the channel region of the thin-film transistor (TFT).

[0249] It should be noted that in the array substrate described in FIG6 , since the second electrode S and the third electrode D are arranged along the second direction and both include strip patterns extending along the first direction X, if one wishes to improve the performance of the thin-film transistor (TFT) by increasing the length of the channel region, it is necessary to increase the distance between the second electrode S and the third electrode D in the second direction Y. While the dimensions of the second portion, the width of the scan line, and the spacing between the conductive structures remain unchanged, this will result in an increase in the width of the wiring area in the second direction, which in turn will result in a decrease in the width of the sub-pixel area in the second direction, affecting the sub-pixel aperture ratio. In contrast, the array substrate provided in the embodiment of the present disclosure, as shown in FIG7 , designs the patterns of the second and third electrodes to increase the channel size without increasing the size of the wiring area in the second direction, thereby improving the performance of the thin-film transistor while avoiding affecting the sub-pixel aperture ratio.

[0250] In some embodiments, as shown in FIG7 , the orthographic projection of the first via hole 1801 on the first substrate 1 falls within the orthographic projection of the fourth sub-portion 704 on the first substrate 1 ;

[0251] In the second portion 7 of the second signal line 3 , the line width of the fourth sub-portion 704 electrically connected to the second electrode 16 through the first via 1801 is greater than the line width of the third sub-portion 703 .

[0252] It should be noted that the line width involved in this disclosure refers to the width of the trace perpendicular to its extension direction.

[0253] The array substrate provided by the embodiment of the present disclosure ensures the contact area between the second electrode and the second signal line by increasing the line width at the fourth sub-portion, thereby improving the electrical connection effect.

[0254] It should be noted that the line width of the fourth sub-portion is increased. Accordingly, the width of the fourth sub-portion electrically connected to the second electrode through the first via in the first direction is greater than the width of the remaining fourth sub-portions in the first direction.

[0255] In some embodiments, the width of the fourth subsection electrically connected to the second electrode through the first via in the first direction is , and the width of the fourth subsection electrically connected to the second electrode through the first via in the second direction is .

[0256] It should be noted that the first vias and the fourth sub-portions do not correspond one-to-one, that is, some areas corresponding to the fourth sub-portions do not need to be electrically connected to the second electrode through the first vias. In some embodiments, as shown in FIG7 , the width of the fourth sub-portion 704 electrically connected to the second electrode 16 through the first via 1801 in the first direction X is greater than the width of the fourth sub-portion 704 not electrically connected to the second electrode 16 through the first via 1801 in the first direction X.

[0257] In some embodiments, as shown in FIG7 , in each second signal line group 17, in the i-th row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 is electrically connected to the second electrode 16 through the first via 1801, the fourth sub-portion 704 of the third second signal line 3-3 is not electrically connected to the second electrode 16 through the first via 1801, and the width of the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 in the first direction X is greater than the fourth sub-portion 704 of the third second signal line 3-3. 4 in the first direction X; in the (i+1)th wiring area row 10, the fourth subportion 704 of the first second signal line 3-1 and the second second signal line 3-2 is not electrically connected to the second electrode 16 through the first via 1801, the fourth subportion 704 of the third second signal line 3-3 is electrically connected to the second electrode 16 through the first via 1801, and the width of the fourth subportion 704 of the first second signal line 3-1 and the second second signal line 3-2 in the first direction X is smaller than the width of the fourth subportion 704 of the third second signal line 3-3 in the first direction X.

[0258] Alternatively, in some embodiments, as shown in FIG8 , in the i-th wiring area row 10 , the second sub-portion 702 , the fourth sub-portion 704 , the third portion 8 , and the fourth portion 9 extend along the third direction X1 ; wherein i is a positive integer;

[0259] In the (i+1)th wiring area row 10, the second sub-portion 702, the fourth sub-portion 704, the third portion 8, and the fourth portion 9 extend along the fourth direction X2;

[0260] The angle between the third direction X1 and the positive direction X+ of the first direction X is greater than 0° and less than 90°. The angle between the fourth direction X2 and the positive direction X+ of the first direction X is greater than 90° and less than 180°.

[0261] In some embodiments, as shown in FIG8 , the strip electrode line 401 and the edge of the first electrode G facing away from the first electrode 5 are located on the same straight line;

[0262] The orthographic projection of the first electrode G on the first base substrate 1 overlaps with the wiring region 102 between two adjacent sub-pixel regions 101 in the first direction X.

[0263] In some embodiments, as shown in FIG8 , the orthographic projection of the second portion 7 on the first substrate 1 and the orthographic projection of the first pole G on the first substrate 1 do not overlap with each other;

[0264] The pattern in which the orthographic projection of the second pole S on the first substrate 1 overlaps with the orthographic projection of the first pole G on the first substrate 1 has a groove region. FIG8 illustrates an example in which the orthographic projection of the second pole S on the first substrate 1 overlaps with the orthographic projection of the first pole G on the first substrate 1 and is U-shaped. The pattern in which the orthographic projection of the third pole D on the first substrate 1 overlaps with the orthographic projection of the first pole G on the first substrate 1 is a stripe. The second pole S and the third pole D are arranged along the first direction X.

[0265] Part of the first portion 6 of the first signal line 2 is reused as the second electrode S.

[0266] In the array substrate provided by the present disclosure, as shown in FIG8 , the groove region of the pattern where the orthographic projection of the second electrode S on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1 opens toward the first direction X, i.e., the U-shaped opening faces the first direction X. Furthermore, the pattern where the orthographic projection of the third electrode D on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1 is strip-shaped, and this strip extends deep into the groove region where the orthographic projection of the second electrode S on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1. The second electrode S and the third electrode D are arranged along the first direction X, thereby increasing the length of the thin-film transistor (TFT) channel region without increasing the size of the wiring area in the second direction. This improves thin-film transistor performance while avoiding compromising the sub-pixel aperture ratio.

[0267] In some embodiments, the first electrode may be directly connected to the third electrode, that is, no insulating layer is required between the first electrode and the third electrode, and no electrical connection is required through a via.

[0268] In some embodiments, as shown in Figure 8, the third electrode D includes a sixth sub-electrode D4 and a seventh sub-electrode D5 connected to the sixth sub-electrode D4; the seventh sub-electrode D5 is electrically connected to the first electrode 5; the orthographic projection of the sixth sub-electrode D4 on the first substrate 1 overlaps with the orthographic projection of the first electrode G on the first substrate 1, the orthographic projection of the seventh sub-electrode D5 on the first substrate 1 does not overlap with the orthographic projection of the first electrode G on the first substrate 1, and the orthographic projection of the seventh sub-electrode D5 on the first substrate 1 overlaps with the orthographic projection of the first electrode 5 on the first substrate 1; the sixth sub-electrode D4 and the seventh sub-electrode D5 both extend along the first direction X, and in the second direction Y, the width of the seventh sub-electrode D5 is greater than the width of the sixth sub-electrode D4, thereby increasing the contact area between the seventh sub-electrode D5 and the first electrode 5, thereby improving the electrical connection performance between the seventh sub-electrode D5 and the first electrode 5.

[0269] In some embodiments, as shown in Figure 8, the multiple thin film transistors TFT include multiple fifth thin film transistors TFT5 and multiple thin film transistors TFT6; in the fifth thin film transistor TFT5, the third electrode D is located on one side of the second electrode S in the negative direction X- of the first direction X, and in the thin film transistor TFT6, the third electrode D is located on one side of the second electrode S in the positive direction X+ of the first direction X.

[0270] In some embodiments, as shown in Figure 8, partial areas at both ends of the extension direction of each first portion 6 of the first signal line 2 are reused as the second pole S, that is, the first portion 6 of each first signal line 2 includes two portions reused as the second pole S; the two thin film transistors TFT6 electrically connected to each first portion 6 of the first signal line 2 are respectively the fifth thin film transistor TFT5 and the sixth thin film transistor TFT6.

[0271] In some embodiments, as shown in FIG. 8 , in the second direction Y, the fifth thin film transistor TFT5 and the thin film transistor TFT6 are alternately arranged.

[0272] In some embodiments, as shown in FIG8 , a plurality of thin film transistors TFT electrically connected to one scan line 4 are divided into a plurality of fifth repeating unit groups 24 - 5 or a plurality of sixth repeating unit groups 24 - 6 ; the fifth repeating unit group 24 - 5 includes t fifth thin film transistors TFT5 and w sixth thin film transistors TFT6 ; the sixth repeating unit group 24 - 6 includes w fifth thin film transistors TFT5 and t sixth thin film transistors TFT6 ; wherein t and w are positive integers and t and w are not equal;

[0273] In the second direction Y, the fifth repeating unit group 24 - 5 and the sixth repeating unit group 24 - 6 are alternately arranged.

[0274] In a specific implementation, one of the first row of wiring area rows and the last row of wiring area rows only includes multiple fifth repeating unit groups 24-5, and the other of the first row of wiring area rows and the last row of wiring area rows only includes multiple sixth repeating unit groups 24-6; the remaining wiring area rows except the first row of wiring area rows and the last row of wiring area rows, as shown in Figure 8, include the fifth repeating unit group 24-5 and the sixth repeating unit group 24-6.

[0275] In some embodiments, as shown in FIG8 , t=2 and w=1.

[0276] In some embodiments, as shown in FIG7 and FIG8 , the orthographic projection of the first via hole 1801 on the first substrate 1 falls within the orthographic projection of the fourth sub-portion 704 on the first substrate 1 ;

[0277] In the second portion 7 of the second signal line 3 , the line width of the fourth sub-portion 704 electrically connected to the second electrode 16 through the first via 1801 is greater than the line width of the third sub-portion 703 .

[0278] The array substrate provided by the embodiment of the present disclosure ensures the contact area between the second electrode and the second signal line by increasing the line width at the fourth sub-portion, thereby improving the electrical connection effect.

[0279] It should be noted that the line width of the fourth sub-portion is increased. Accordingly, the width of the fourth sub-portion electrically connected to the second electrode through the first via in the first direction is greater than the width of the remaining fourth sub-portions in the first direction.

[0280] In some embodiments, when the width of the orthographic projection of the first via in the first direction and the width of the second direction of the first substrate are both 8 microns, the width of the fourth subsection electrically connected to the second electrode through the first via in the first direction is 14 microns, and the width of the fourth subsection electrically connected to the second electrode through the first via in the second direction is 14 microns. The width of the orthographic projection of the first via in the first direction and the width of the second direction of the first substrate, and the width of the fourth subsection electrically connected to the second electrode through the first via in the first direction and the width of the second direction can be specifically set based on actual process capabilities, etc.

[0281] It should be noted that the first vias and the fourth sub-portions do not correspond one-to-one, that is, some areas corresponding to the fourth sub-portions do not need to be electrically connected to the second electrode 16 through the first vias. In some embodiments, as shown in Figures 7 and 8, the width of the fourth sub-portion 704 electrically connected to the second electrode 16 through the first via 1801 in the first direction X is greater than the width of the fourth sub-portion 704 not electrically connected to the second electrode 16 through the first via 1801 in the first direction X.

[0282] In some embodiments, as shown in FIG7 , in each second signal line group 17, in the i-th row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 is electrically connected to the second electrode 16 through the first via 1801, the fourth sub-portion 704 of the third second signal line 3-3 is not electrically connected to the second electrode 16 through the first via 1801, and the width of the fourth sub-portion 704 of the first second signal line 3-1 and the second second signal line 3-2 in the first direction X is greater than the fourth sub-portion 704 of the third second signal line 3-3. 4 in the first direction X; in the (i+1)th wiring area row 10, the fourth subportion 704 of the first second signal line 3-1 and the second second signal line 3-2 is not electrically connected to the second electrode 16 through the first via 1801, the fourth subportion 704 of the third second signal line 3-3 is electrically connected to the second electrode 16 through the first via 1801, and the width of the fourth subportion 704 of the first second signal line 3-1 and the second second signal line 3-2 in the first direction X is smaller than the width of the fourth subportion 704 of the third second signal line 3-3 in the first direction X.

[0283] In some embodiments, as shown in FIG8 , in each second signal line group 17, in the i-th row wiring area row 10, the fourth sub-portion 704 of the first second signal line 3-1 is electrically connected to the second electrode 16 through the first via 1801, the fourth sub-portion 704 of the second second signal line 3-2 and the third second signal line 3-3 are not electrically connected to the second electrode 16 through the first via 1801, and the width of the fourth sub-portion 704 of the first second signal line 3-1 in the first direction X is greater than the fourth sub-portion 704 of the second second signal line 3-2 and the third second signal line 3-3. 4 in the first direction X; in the (i+1)th wiring area row 10, the fourth subportion 704 of the first second signal line 3-1 is not electrically connected to the second electrode 16 through the first via 1801, and the fourth subportions 704 of the second second signal line 3-2 and the third second signal line 3-3 are electrically connected to the second electrode 16 through the first via 1801, and the width of the fourth subportion 704 of the first second signal line 3-1 in the first direction X is smaller than the widths of the fourth subportions 704 of the second second signal line 3-2 and the third second signal line 3-3 in the first direction X.

[0284] In a specific implementation, the i-th row is an odd row, and the i+1-th row is an even row; or, the i-th row is an even row, and the i+1-th row is an odd row.

[0285] In some embodiments, the line width of the second signal line is greater than the line width of the first signal line. Specifically, the line width of the first portion of the second signal line is greater than the line width of the first portion of the first signal line, the line width of the third sub-portion is greater than the line width of the first sub-portion, the line width of the fourth sub-portion is greater than the line width of the second sub-portion, and the line width of the fourth portion is greater than the line width of the third portion.

[0286] The wiring substrate provided by the embodiments of the present disclosure increases the line width of the second signal line, thereby reducing the resistance and impedance of the second signal line, alleviating or even avoiding voltage drops during signal transmission. When the second electrode functions as a touch electrode, it can also improve touch accuracy.

[0287] In specific implementations, the line widths of the same first signal line or second signal line at different locations may be different. The line widths of various portions of the first signal line or second signal line may be designed based on resistance requirements and actual wiring space.

[0288] In a specific implementation, the first substrate is, for example, a glass substrate. The active layer may be made of amorphous silicon (a-Si), polycrystalline silicon (poly), or an oxide (e.g., indium gallium zinc oxide (IGZO)). The first electrode, second electrode, third electrode, scan line, first signal line, and second signal line may be made of a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), or nickel (Ni). The structure may be a single layer or a stacked layer, for example, a stacked layer consisting of a titanium metal layer, an aluminum metal layer, and a titanium metal layer.

[0289] A display panel provided by an embodiment of the present disclosure, as shown in FIG9 , includes:

[0290] The array substrate 19 provided in the embodiment of the present disclosure;

[0291] The opposite substrate 20 is arranged opposite to the array substrate 19;

[0292] The liquid crystal layer 21 is located between the array substrate 19 and the opposite substrate 20 .

[0293] In the display panel provided by the embodiment of the present disclosure, in the second direction, the second part included in the first signal line or the second signal line is located on the side of the scanning line's orthographic projection on the first substrate substrate that is away from the first electrode adjacent to it, thereby increasing the distance between the second part and the first electrode to avoid the formation of a capacitance between the second part and the first electrode that affects the charging of the first electrode, thereby improving the display effect.

[0294] In some embodiments, the opposing substrate comprises:

[0295] a second substrate;

[0296] A plurality of spacers are located on a side of the second base substrate facing the liquid crystal layer.

[0297] In a specific implementation, an alignment layer is further provided on a side of the array substrate close to the liquid crystal layer and a side of the opposite substrate close to the liquid crystal layer.

[0298] In some embodiments, the counter substrate further includes a black matrix and color resists on the side of the second base substrate facing the liquid crystal layer. The black matrix has an opening area, and the color resists are located in the opening area; and the spacers are located on the side of the black matrix facing the liquid crystal layer.

[0299] In a specific implementation, the orthographic projection of the black matrix on the array substrate falls within the wiring area. The color resists correspond one-to-one with the sub-pixel areas, and the orthographic projection of the color resists on the array substrate falls within the sub-pixel areas. The display panel includes sub-pixels corresponding one-to-one with the sub-pixel areas, and the sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels. Accordingly, the color resists include red color resists corresponding to the red sub-pixels, blue color resists corresponding to the blue sub-pixels, and green color resists corresponding to the green sub-pixels.

[0300] In some embodiments, the orthographic projection of the spacer on the first substrate falls into the wiring area. For example, the orthographic projection of the spacer on the first substrate overlaps with the orthographic projection of the first pole on the first substrate. Alternatively, the spacer may correspond to the first via. If the orthographic projection of the first via on the first substrate falls into the orthographic projection of the first protrusion of the third sub-part and the first sub-strip on the first substrate, the orthographic projection of the spacer on the first substrate may also fall into the orthographic projection of the first protrusion and the first sub-strip on the first substrate. If the orthographic projection of the first via on the first substrate falls into the orthographic projection of the fourth sub-part on the first substrate, the orthographic projection of the spacer on the first substrate may also fall into the orthographic projection of the fourth sub-part on the first substrate.

[0301] An embodiment of the present disclosure provides a display device, as shown in FIG10 , which includes a display panel 22 provided in an embodiment of the present disclosure.

[0302] In some embodiments, the display device provided in the embodiments of the present disclosure may further include a backlight module 23 located on the light incident side of the array substrate 19, as shown in FIG10 . The backlight module may be a direct-lit backlight module or an edge-lit backlight module.

[0303] In a specific implementation, the side-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightening film, etc. The reflective sheet includes an opening arranged directly opposite the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter or even micron-scale micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. Moreover, when micro-light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0304] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the display panel and array substrate, and any repetitive details will be omitted.

[0305] To sum up, in the array substrate, display panel and display device provided by the embodiments of the present disclosure, in the second direction, the second part included in the first signal line or the second signal line is located on the side of the scanning line's positive projection on the first base substrate away from the first electrode adjacent to it, thereby increasing the distance between the second part and the first electrode to avoid the formation of a capacitance between the second part and the first electrode that affects the charging of the first electrode, thereby improving the display effect.

[0306] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0307] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: The array substrate comprises: A first substrate, comprising a plurality of sub-pixel regions arrayed along a first direction and a second direction and a wiring region outside the sub-pixel regions; the first direction intersects the second direction; A plurality of scan lines are located in the wiring area; A plurality of first electrodes; the orthographic projections of the first electrodes on the first substrate are at least partially located in the sub-pixel region; A plurality of first signal lines and a plurality of second signal lines are located in the wiring area; the first signal line and the second signal line each include: a plurality of first portions and a plurality of second portions, in the extension direction of the first signal line or the plurality of second signal lines, the first portions and the second portions are alternately arranged and electrically connected, and the extension direction of the first portion intersects with the extension direction of the second portion; the orthographic projection of some of the first portions on the first substrate is located in the wiring area between two adjacent sub-pixel areas in the first direction, the orthographic projection of the second portion on the first substrate is located in the wiring area between two adjacent sub-pixel areas in the second direction, and the two first portions connected by the second portion are located in different columns in the second direction; in the second direction, the orthographic projection of the second portion on the first substrate is located on the side of the orthographic projection of the scanning line on the first substrate away from the orthographic projection of the first electrode adjacent to it on the first substrate.

2. The array substrate according to claim 1, wherein: The orthographic projection of the first signal line on the first substrate and the orthographic projection of the second signal line on the first substrate do not overlap each other; The first signal lines and the plurality of second signal lines are alternately arranged in the first direction; At least part of the first portion of the first signal line and the first portion of the second signal line that are adjacent to each other are separated by one sub-pixel region between their orthographic projections on the first substrate.

3. The array substrate according to claim 2, wherein: In the second direction, the wiring area between two adjacent sub-pixel areas is provided with two scanning lines; An orthographic projection of the second portion on the first substrate falls within an area between two adjacent scanning lines in the wiring region and is within the orthographic projection of the first substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: The second portion of the first signal line includes: n first sub-portions, and n-1 second sub-portions; wherein n is an integer greater than 1; The second portion of the second signal line includes: n third sub-portions, and n-1 fourth sub-portions; The first sub-portion and the third sub-portion extend along the first direction, the extension direction of the second sub-portion intersects both the first direction and the second direction, and the extension direction of the fourth sub-portion intersects both the first direction and the second direction; The second sub-portion connects the two first sub-portions, and the fourth sub-portion connects the two third sub-portions; The sub-pixel area and the wiring area are divided into: a plurality of sub-pixel rows and wiring area rows arranged along the second direction and extending along the first direction; the sub-pixel rows and the wiring area rows are arranged alternately, and the wiring area rows include sub-areas corresponding to the sub-pixel areas one by one; Two of the first portions connected by the second portion are separated by n sub-pixel regions in a first direction; The orthographic projection of the second portion on the first substrate falls into the wiring area; and the orthographic projections of the first sub-portion and the third sub-portion on the first substrate are located within the sub-area, and the orthographic projections of the second sub-portion and the fourth sub-portion on the first substrate pass between two adjacent sub-areas.

5. The array substrate according to claim 4, wherein: The n first sub-portions included in the second portion of the first signal line are located on different straight lines in the first direction; The n first sub-portions included in the second portion of the first signal line are located on different straight lines in the first direction, and the n third sub-portions included in the second portion of the second signal line are located on different straight lines in the first direction; In the second direction, the first subsection is adjacent to the third subsection.

6. The array substrate according to claim 4 or 5, wherein: The area between two adjacent sub-pixel areas in the second direction and between two adjacent scan lines in the wiring area includes only one first sub-portion and one third sub-portion.

7. The array substrate according to claim 6, wherein: In the wiring area row, in the second direction, two third sub-portions adjacent to the second sub-portion of the first signal line and respectively located on both sides of the second sub-portion of the first signal line are located on different second signal lines; In the area between two adjacent scan lines in the wiring region, two first sub-portions adjacent to the second sub-portion of the second signal line and located on both sides of the second sub-portion of the second signal line in the second direction are located on different first signal lines.

8. The array substrate according to any one of claims 4 to 7, wherein: The first signal line further includes a third portion; the third portion connects the first portion and the first sub-portion, and an extension direction of the third portion intersects both the first direction and the second direction; The second signal line further includes a fourth portion; the fourth portion connects the first portion and the third sub-portion, and an extending direction of the fourth portion intersects both the first direction and the second direction; The third portion is adjacent to the fourth sub-portion, and the adjacent third portion and the fourth sub-portion extend in the same direction; The fourth portion is adjacent to the second sub-portion, and the adjacent second sub-portion and the fourth portion extend in the same direction.

9. The array substrate according to claim 8, wherein: At least part of the fourth sub-portion is adjacent to two third portions located on different first signal lines; At least part of the second sub-portion is adjacent to two of the fourth portions located on different second signal lines.

10. The array substrate according to claim 8 or 9, wherein: In the i-th row of the wiring area, the second sub-portion, part of the fourth sub-portion, the third portion, and the fourth portion extend along the third direction, and the rest of the fourth sub-portion extends along the fourth direction; wherein i is a positive integer; In the row of the wiring areas in the (i+1)th row, part of the second sub-portion, part of the fourth sub-portion, the third portion, and the fourth portion extend along the fourth direction, and the rest of the fourth sub-portion extends along the third direction; In each of the common electrode lines, the extension of the fourth sub-portion in the i-th row of the wiring area is The direction is different from the extension direction of the fourth sub-portion in the wiring area row of the i+1th row; An angle between the third direction and the positive direction of the first direction is greater than 0° and less than 90°, and an angle between the fourth direction and the positive direction of the first direction is greater than 90° and less than 180°.

11. The array substrate according to claim 10, wherein: The array substrate includes a plurality of second signal lines, and every three second signal lines form a group; in each group of second signal lines, in the i-th row of the wiring area, the fourth sub-portions of two adjacent second signal lines extend along the fourth direction, and the fourth sub-portion of another second signal line extends along the third direction.

12. The array substrate according to claim 11, wherein: The array substrate further comprises: a plurality of thin film transistors; the thin film transistors comprise a first electrode, a second electrode and a third electrode; the first electrode is electrically connected to the scan line, and the third electrode is electrically connected to the first signal line; The scanning line includes a plurality of strip electrode lines; the plurality of strip electrode lines are alternately arranged and electrically connected with a plurality of first electrodes corresponding to the scanning line; in the second direction, the width of the first electrode is greater than the width of the strip electrode line.

13. The array substrate according to claim 12, wherein: The strip electrode line and the edge of the first electrode facing the first electrode are located in the same straight line; In the second direction, the first pole is adjacent to the third subsection.

14. The array substrate according to claim 13, wherein: The patterns of the overlapped portions of the orthographic projections of the second pole and the third pole on the first substrate and the orthographic projection of the first pole on the first substrate both include strips extending along the first direction; In the second direction, the second pole is adjacent to the third sub-portion, and part of the first sub-portion is reused as the second pole; The orthographic projection of the first sub-portion of the second pole multiplexed on the first substrate overlaps with the orthographic projection of the first pole on the first substrate; An orthographic projection of the first sub-portion that is not multiplexed into the second pole on the first substrate does not overlap with an orthographic projection of the first pole on the first substrate; In the i-th row of the wiring area, the fourth sub-portion of the second signal line adjacent to the first sub-portion multiplexed as the second pole extends along the third direction and does not overlap with the first sub-portion multiplexed as the second pole. The fourth sub-portion included in the second signal line adjacent to the first sub-portion of the second pole extends along the fourth direction; In the i+1th row of the wiring area, the fourth subportion included in the second signal line adjacent to the first subportion multiplexed as the second pole extends along the fourth direction, and the fourth subportion included in the second signal line not adjacent to the first subportion multiplexed as the second pole extends along the third direction.

15. The array substrate according to claim 13 or 14, wherein: The array substrate further comprises: a second electrode located at a side of the first electrode away from the first base substrate, and an insulating film layer located between the second electrode and the second signal line; the second electrode is electrically connected to the second signal line through a first via hole penetrating the insulating film layer; Part of the third sub-portion includes a first strip portion and a first protruding portion located on one side of the first strip portion in the second direction; an orthographic projection of the first via hole on the first substrate falls within an orthographic projection of the third sub-portion on the first substrate, and an orthographic projection of the first via hole on the first substrate overlaps an orthographic projection of the first protruding portion on the first substrate; The orthographic projection of the first protruding portion on the first substrate is located on a side of the orthographic projection of the first strip portion on the first substrate away from the orthographic projection of the first sub-portion multiplexed as the second pole on the first substrate.

16. The array substrate according to claim 12, wherein: The plurality of strip electrode lines include a plurality of first strip electrode lines and a plurality of second strip electrode lines, in the first direction, one end of the first electrode is electrically connected to the first strip electrode line, and the other end of the first electrode is electrically connected to the second strip electrode line; in the first direction, the first strip electrode line and the second strip electrode line are located on different straight lines; In the second direction, the first pole is adjacent to the first subsection or the third subsection.

17. The array substrate according to claim 16, wherein: The orthographic projection of the second portion on the first substrate and the orthographic projection of the first pole on the first substrate do not overlap each other; The pattern of the overlapping portion of the orthographic projection of the second pole on the first substrate and the orthographic projection of the first pole on the first substrate has a groove area; the pattern of the overlapping portion of the orthographic projection of the third pole on the first substrate and the orthographic projection of the first pole on the first substrate is a strip; the second pole and the third pole are arranged along the first direction; The second pole electrically connected to the first portion and the first sub-portion are respectively located at two sides of the first portion in the first direction.

18. The array substrate according to claim 8 or 9, wherein: In the i-th row of the wiring area, the second sub-portion, the fourth sub-portion, the third portion, and the fourth portion extend along a third direction; wherein i is a positive integer; In the row of the wiring areas in the (i+1)th row, the second sub-portion, the fourth sub-portion, the third portion, and the fourth portion extend along a fourth direction; An angle between the third direction and the positive direction of the first direction is greater than 0° and less than 90°, and an angle between the fourth direction and the positive direction of the first direction is greater than 90° and less than 180°.

19. The array substrate according to claim 18, wherein: The array substrate further comprises: a plurality of thin film transistors; the thin film transistors comprise a first electrode, a second electrode and a third electrode; the first electrode is electrically connected to the scan line, and the third electrode is electrically connected to the first signal line; The scanning line comprises a plurality of strip electrode lines; the plurality of strip electrode lines are alternately arranged and electrically connected with a plurality of first electrodes corresponding to the scanning line; in the second direction, the width of the first electrode is greater than the width of the strip electrode line; The strip electrode line and the edge of the first electrode on a side away from the first electrode are located in the same straight line; An orthographic projection of the first electrode on the first substrate overlaps with the wiring area between two adjacent sub-pixel areas in the first direction.

20. The array substrate according to claim 19, wherein: The orthographic projection of the second portion on the first substrate and the orthographic projection of the first pole on the first substrate do not overlap each other; The pattern of the part where the orthographic projection of the second pole on the first substrate overlaps with the orthographic projection of the first pole on the first substrate has a groove area; the third pole is formed on the first substrate. The pattern of the overlapping portion of the orthographic projection of the bottom substrate and the orthographic projection of the first pole on the first base substrate is in the shape of a strip; the second pole and the third pole are arranged along the first direction; A partial area of ​​the first portion of the first signal line is reused as the second electrode.

21. The array substrate according to any one of claims 16 to 20, wherein: The array substrate further comprises: a second electrode located at a side of the first electrode away from the first base substrate, and an insulating film layer located between the second electrode and the second signal line; the second electrode is electrically connected to the second signal line through a first via hole penetrating the insulating film layer; The orthographic projection of the first via hole on the first substrate falls within the orthographic projection of the fourth sub-portion on the first substrate; In the second portion of the second signal line, the line width of the fourth sub-portion electrically connected to the second electrode through the first via hole is greater than the line width of the third sub-portion.

22. The array substrate according to any one of claims 4 to 21, wherein: n＝2。 23. The array substrate according to any one of claims 1 to 22, wherein: The line width of the second signal line is greater than the line width of the first signal line.

24. A display panel, wherein: include: The array substrate according to any one of claims 1 to 23 an opposite substrate, arranged opposite to the array substrate; The liquid crystal layer is located between the array substrate and the opposite substrate.

25. A display device, wherein: The display device comprises the display panel according to claim 24.

Images