Driving circuit, driving method and display device

Abstract

The invention discloses a driving circuit, a driving method and a display device. The driving circuit comprises a first output node control circuit (11), an output reset circuit (12), a second output node control circuit (52), an output circuit (53), a first energy storage circuit (13), a second energy storage circuit (10) and a driving signal output end (GT). The output reset circuit (12) controls the connection between the driving signal output end (GT) and the first voltage line (V1) under the control of the potential of the first output node (NO1); the output circuit (53) controls the connection between the driving signal output end (GT) and the second voltage line (V2) under the control of the potential of the second output node (NO2); the first energy storage circuit (13) is electrically connected with the first output node (NO1) and the driving signal output end (GT), the second energy storage circuit (10) is electrically connected with the second output node (NO1) and the second voltage line (V2), and the first energy storage circuit (13) and the second energy storage circuit (10) are used for storing electric energy. According to the driving circuit and the driving method thereof, the negative influence caused by two times of pull-down of switching of the potential of the driving signal from a high level to a low level can be reduced.

Description

Driving circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, and a display device. Background Art

[0002] Low-temperature polysilicon and oxide hybrid drivers are widely used in high-end OLED (organic light-emitting diode) display panels. These driver circuits experience a two-step pull-down problem when reducing the potential of the drive signal from a high voltage to a low voltage. This creates a pull-down step, preventing the drive signal from reaching the low voltage level quickly enough, resulting in bright horizontal stripes.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a first output node control circuit, an output reset circuit, a second output node control circuit, an output circuit, a first energy storage circuit, a second energy storage circuit, and a driving signal output terminal;

[0005] The first output node control circuit is electrically connected to the first output node and is used to control the potential of the first output node;

[0006] The second output node control circuit is electrically connected to the second output node and is used to control the potential of the second output node; the output reset circuit is electrically connected to the first output node, the drive signal output terminal and the first voltage line respectively, and is used to control the connection between the drive signal output terminal and the first voltage line under the control of the potential of the first output node;

[0007] The output circuit is electrically connected to the second output node, the drive signal output terminal and the second voltage line respectively, and is used to control the connection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0008] The first energy storage circuit is electrically connected to the first output node and the drive signal output terminal respectively, and the second energy storage circuit is electrically connected to the second output node and the second voltage line respectively; the first energy storage circuit and the second energy storage circuit are used to store electrical energy.

[0009] Optionally, the first energy storage circuit includes a first capacitor;

[0010] The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0011] The second energy storage circuit includes a sixth capacitor;

[0012] The first plate of the sixth capacitor is electrically connected to the second output node, and the second plate of the sixth capacitor is electrically connected to the second voltage line.

[0013] Optionally, the first energy storage circuit includes a second capacitor and a third capacitor;

[0014] The first plate of the second capacitor is electrically connected to the first output node, and the second plate of the second capacitor is electrically connected to the connection node;

[0015] The first plate of the third capacitor is electrically connected to the connection node, and the second plate of the third capacitor is electrically connected to the driving signal output terminal.

[0016] Optionally, the first energy storage circuit includes a first capacitor, a second capacitor and a third capacitor;

[0017] The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0018] The first plate of the second capacitor is electrically connected to the first output node, and the second plate of the second capacitor is electrically connected to the connection node;

[0019] The first plate of the third capacitor is electrically connected to the connection node, and the second plate of the third capacitor is electrically connected to the driving signal output terminal.

[0020] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a connection node control circuit;

[0021] The connecting node control circuit is electrically connected to the first node, the second voltage line, the first node of the adjacent previous level, the connecting node, the second node, the first clock signal line, the second output node and the first output node, respectively, and is used to control the connection or disconnection between the connecting node and the second voltage line under the control of the potential of the first node and the potential of the first node of the adjacent previous level, control the connection or disconnection between the connecting node and the second node under the control of the first clock signal provided by the first clock signal line, control the connection or disconnection between the connecting node and the second node under the control of the potential of the second output node, and control the connection or disconnection between the second node and the first clock signal line under the control of the potential of the first output node.

[0022] Optionally, the connection node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;

[0023] The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0024] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the first clock signal line;

[0025] The gate of the third transistor is electrically connected to the first node of the adjacent previous stage, and the second electrode of the third transistor is electrically connected to the connection node;

[0026] The gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the connection node, and the second electrode of the fourth transistor is electrically connected to the second node;

[0027] The gate of the fifth transistor is electrically connected to the second output node, the first electrode of the fifth transistor is electrically connected to the connection node, and the second electrode of the fifth transistor is electrically connected to the second node;

[0028] The first output node control circuit includes a sixth transistor;

[0029] A gate of the sixth transistor is electrically connected to the second clock signal line, a first electrode of the sixth transistor is electrically connected to the input terminal, and a second electrode of the sixth transistor is electrically connected to the first output node.

[0030] Optionally, the first output node control circuit is also electrically connected to the first node, the second voltage line, the third node, the first clock signal line, the fourth node, the input end and the second clock signal line, respectively, and is used to control the connection or disconnection between the third node and the second voltage line under the control of the potential of the first node, control the connection or disconnection between the third node and the first clock signal line under the control of the potential of the fourth node, control the potential of the fourth node according to the potential of the third node, and control the connection or disconnection between the input end and the first output node under the control of the second clock signal provided by the second clock signal line, control the connection or disconnection between the input end and the fourth node under the control of the second clock signal, and control the potential of the first output node under the control of the potential of the fourth node.

[0031] Optionally, the first output node control circuit includes a first transistor, a second transistor, a fourth capacitor, a sixth transistor, a seventh transistor and an eighth transistor;

[0032] The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the third node;

[0033] The gate of the second transistor is electrically connected to the fourth node, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first clock signal line;

[0034] The first plate of the fourth capacitor is electrically connected to the third node, and the second plate of the fourth capacitor is electrically connected to the fourth node;

[0035] The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the first output node;

[0036] The gate of the seventh transistor is electrically connected to the second clock signal line, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node;

[0037] A gate of the eighth transistor and a first electrode of the eighth transistor are electrically connected to the fourth node, and a second electrode of the eighth transistor is electrically connected to the first output node.

[0038] Optionally, the first output node control circuit further includes a ninth transistor;

[0039] The second electrode of the seventh transistor is electrically connected to the fourth node through the ninth transistor;

[0040] A gate of the ninth transistor is electrically connected to the third voltage line, a first electrode of the ninth transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the ninth transistor is electrically connected to the fourth node.

[0041] Optionally, the first output node control circuit further includes a tenth transistor;

[0042] The second electrode of the sixth transistor is electrically connected to the first output node through the tenth transistor;

[0043] The gate of the tenth transistor is electrically connected to the third voltage line, the first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the first output node;

[0044] A second electrode of the sixth transistor is electrically connected to the fifth node.

[0045] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit;

[0046] The first node control circuit electrically connects the first node to the second clock signal line, the first voltage line and the first output node respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the second clock signal provided by the second clock signal line, and to control the connection or disconnection between the first node and the second clock signal line under the control of the first output node.

[0047] Optionally, the first node control circuit includes an eleventh transistor and a twelfth transistor;

[0048] The gate of the eleventh transistor is electrically connected to the second clock signal line, the first electrode of the eleventh transistor is electrically connected to the first voltage line, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0049] A gate of the twelfth transistor is electrically connected to the first output node, a first electrode of the twelfth transistor is electrically connected to the second clock signal line, and a second electrode of the twelfth transistor is electrically connected to the first node.

[0050] Optionally, the second output node control circuit is further electrically connected to the first node, the first clock signal line, the sixth node, the second voltage line, and the first output node, respectively, and is configured to control the connection or disconnection between the sixth node and the first clock signal line under the control of the potential of the first node, control the potential of the sixth node based on the potential of the first node, control the connection between the sixth node and the second output node under the control of the first clock signal provided by the first clock signal line, maintain the potential of the second output node, and control the connection or disconnection between the second output node and the second voltage line under the control of the potential of the first output node. Optionally, the second output node control circuit includes a thirteenth transistor, a fourteenth transistor, a fifth capacitor, and a fifteenth transistor.

[0051] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the sixth node;

[0052] The gate of the fourteenth transistor is electrically connected to the first clock signal line, the first electrode of the fourteenth transistor is electrically connected to the sixth node, and the second electrode of the fourteenth transistor is electrically connected to the second output node;

[0053] A first plate of the fifth capacitor is electrically connected to the gate of the thirteenth transistor, and a second plate of the fifth capacitor is electrically connected to the sixth node;

[0054] A gate of the fifteenth transistor is electrically connected to the first output node, a first electrode of the fifteenth transistor is electrically connected to the second output node, and a second electrode of the fifteenth transistor is electrically connected to the second voltage line.

[0055] Optionally, the first output node control circuit includes a sixteenth transistor;

[0056] A gate of the sixteenth transistor is electrically connected to the control signal line, a first electrode of the sixteenth transistor is electrically connected to the second voltage line, and a second electrode of the sixteenth transistor is electrically connected to the first output node.

[0057] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a seventeenth transistor;

[0058] The first node is electrically connected to the gate of the thirteenth transistor through the seventeenth transistor;

[0059] A gate of the seventeenth transistor is electrically connected to the third voltage line, a first electrode of the seventeenth transistor is electrically connected to the first node, and a second electrode of the seventeenth transistor is electrically connected to the gate of the thirteenth transistor.

[0060] Optionally, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0061] The gate of the output transistor is electrically connected to the second output node, the first electrode of the output transistor is electrically connected to the second voltage line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0062] A gate of the output reset transistor is electrically connected to the first output node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the first voltage line.

[0063] Optionally, the first capacitor includes a first plate and a second plate;

[0064] The first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other;

[0065] The first electrode portion is formed on a first metal layer, the second electrode portion is formed on a second metal layer, the second electrode portion is formed on a third metal layer, and the second metal layer is disposed between the first metal layer and the third metal layer;

[0066] The sixth capacitor includes a first plate and a second plate;

[0067] The first electrode plate of the sixth capacitor is formed on the first metal layer, and the second electrode plate of the sixth capacitor is formed on the fifth metal layer.

[0068] Optionally, the first metal layer is a first gate metal layer, the second metal layer is a first source / drain metal layer, the third metal layer is a second source / drain metal layer, and the fifth metal layer is a second gate metal layer.

[0069] Optionally, the first capacitor includes a first plate and a second plate; the sixth capacitor includes a first plate and a second plate;

[0070] The first electrode plate of the first capacitor is formed on the fourth metal layer, and the second electrode plate of the first capacitor is formed on the fifth metal layer;

[0071] The first electrode plate of the sixth capacitor is formed on the fourth metal layer, and the second electrode plate of the sixth capacitor is formed on the fifth metal layer.

[0072] Optionally, the fourth metal layer is a first gate metal layer, and the fifth metal layer is a second gate metal layer.

[0073] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0074] The first output node control circuit controls the potential of the first output node;

[0075] The second output node control circuit controls the potential of the second output node;

[0076] The output reset circuit controls the connection between the drive signal output terminal and the first voltage line under the control of the potential of the first output node;

[0077] The output circuit controls the connection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0078] The first energy storage circuit controls the potential of the first output node according to the driving signal provided by the driving signal output terminal; the second energy storage circuit maintains the potential of the second output node.

[0079] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0081] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0082] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0083] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0084] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0085] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0086] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0087] FIG8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0088] FIG9 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG8 ;

[0089] FIG10A is a first layout diagram of at least one embodiment of the driving circuit shown in FIG8 ;

[0090] FIG10B is a layout diagram of the semiconductor layer in FIG10A;

[0091] FIG10C is a layout diagram of the first gate metal layer in FIG10A ;

[0092] FIG10D is a layout diagram of the second gate metal layer in FIG10A;

[0093] FIG10E is a layout diagram of the first source / drain metal layer in FIG10A ;

[0094] FIG10F is a layout diagram of the second source / drain metal layer in FIG10A ;

[0095] FIG11 is a schematic diagram of a stack of the first capacitor in FIG10A;

[0096] FIG12A is a second layout diagram of at least one embodiment of the driving circuit shown in FIG8;

[0097] FIG12B is a layout diagram of the semiconductor layer in FIG12A;

[0098] FIG12C is a layout diagram of the first gate metal layer in FIG12A;

[0099] FIG12D is a layout diagram of the second gate metal layer in FIG12A;

[0100] FIG12E is a layout diagram of the first source / drain metal layer in FIG12A ;

[0101] FIG12F is a layout diagram of the second source / drain metal layer in FIG12A;

[0102] FIG13 is a schematic diagram of a stack of the first capacitor in FIG12A;

[0103] FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0104] FIG15 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG14 of the present disclosure;

[0105] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0106] FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0107] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0108] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0109] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0110] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0111] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a first output node control circuit 11 , an output reset circuit 12 , a second output node control circuit 52 , an output circuit 53 , a first energy storage circuit 13 , a second energy storage circuit 10 , and a driving signal output terminal GT;

[0112] The first output node control circuit 11 is electrically connected to the first output node NO1 and is used to control the potential of the first output node NO1;

[0113] The second output node control circuit 52 is electrically connected to the second output node NO2 and is used to control the potential of the second output node NO2;

[0114] The output reset circuit 12 is electrically connected to the first output node NO1, the drive signal output terminal GT and the first voltage line V1 respectively, and is used to control the connection between the drive signal output terminal GT and the first voltage line V1 under the control of the potential of the first output node NO1;

[0115] The output circuit 53 is electrically connected to the second output node NO2, the drive signal output terminal GT and the second voltage line V2, respectively, and is used to control the connection between the drive signal output terminal GT and the second voltage line V2 under the control of the potential of the second output node NO2;

[0116] The first energy storage circuit 13 is electrically connected to the first output node NO1 and the drive signal output terminal GT respectively, and is used to store electrical energy;

[0117] The second energy storage circuit 10 is electrically connected to the second output node NO2 and the second voltage line V2, respectively, for storing electrical energy.

[0118] The driving circuit described in the embodiment of the present disclosure strengthens the pull-down capability of the output reset transistor included in the output reset circuit 12 by adding a first energy storage circuit 13 between the first output node NO1 and the driving signal output terminal GT, thereby achieving the purpose of more thoroughly pulling down the potential of the driving signal provided by the driving signal output terminal GT, so that the first pull-down of the potential of the driving signal is closer to the low level, thereby enabling the transistor in the pixel circuit whose gate is electrically connected to the driving signal output terminal GT to be turned off more quickly, thereby reducing the negative impact caused by the double pull-down of the potential of the driving signal from a high level to a low level.

[0119] In at least one embodiment of the present disclosure, the first voltage line may be a low voltage line.

[0120] Optionally, the first energy storage circuit includes a first capacitor;

[0121] The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0122] The second energy storage circuit includes a sixth capacitor;

[0123] The first plate of the sixth capacitor is electrically connected to the second output node, and the second plate of the sixth capacitor is electrically connected to the second voltage line.

[0124] In a specific implementation, the first energy storage circuit may include a first capacitor connected between the first output node and the driving signal output terminal.

[0125] Optionally, the first energy storage circuit includes a second capacitor and a third capacitor;

[0126] The first plate of the second capacitor is electrically connected to the first output node, and the second plate of the second capacitor is electrically connected to the connection node;

[0127] The first plate of the third capacitor is electrically connected to the connection node, and the second plate of the third capacitor is electrically connected to the driving signal output terminal.

[0128] In a specific implementation, the first energy storage circuit may include a second capacitor and a third capacitor, the second capacitor and the third capacitor are connected in series with each other, the second capacitor and the third capacitor are arranged between the first output node and the drive signal output end, and the node between the second capacitor and the third capacitor is a connection node.

[0129] Optionally, the first energy storage circuit includes a first capacitor, a second capacitor and a third capacitor;

[0130] The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0131] The first plate of the second capacitor is electrically connected to the first output node, and the second plate of the second capacitor is electrically connected to the connection node;

[0132] The first plate of the third capacitor is electrically connected to the connection node, and the second plate of the third capacitor is electrically connected to the driving signal output terminal.

[0133] In a specific implementation, the first energy storage circuit may include a first capacitor, a second capacitor and a third capacitor, the first capacitor is connected between the first output node and the drive signal output end, the second capacitor and the third capacitor are connected in series with each other, the second capacitor and the third capacitor are arranged between the first output node and the drive signal output end, and the node between the second capacitor and the third capacitor is a connection node.

[0134] The driving circuit according to at least one embodiment of the present disclosure further includes a connection node control circuit;

[0135] The connecting node control circuit is electrically connected to the first node, the second voltage line, the first node of the adjacent previous level, the connecting node, the second node, the first clock signal line, the second output node and the first output node, respectively, and is used to control the connection or disconnection between the connecting node and the second voltage line under the control of the potential of the first node and the potential of the first node of the adjacent previous level, control the connection or disconnection between the connecting node and the second node under the control of the first clock signal provided by the first clock signal line, control the connection or disconnection between the connecting node and the second node under the control of the potential of the second output node, and control the connection or disconnection between the second node and the first clock signal line under the control of the potential of the first output node.

[0136] In a specific implementation, the driving circuit may also include a connection node control circuit for controlling the potential of the connection node. The connection node control circuit controls the connection or disconnection between the connection node and the second voltage line under the control of the potential of the first node and the potential of the first node of the adjacent previous level, controls the connection or disconnection between the connection node and the second node under the control of the first clock signal, controls the connection or disconnection between the connection node and the second node under the control of the potential of the second output node, and controls the connection or disconnection between the second node and the first clock signal line under the control of the potential of the first output node.

[0137] Optionally, the second voltage line may be a high voltage line.

[0138] As shown in FIG2 , based on at least one embodiment of the driving circuit shown in FIG1 ,

[0139] The first energy storage circuit includes a second capacitor C2 and a third capacitor C3;

[0140] The first plate of the second capacitor C2 is electrically connected to the first output node NO1, and the second plate of the second capacitor C2 is electrically connected to the connection node NJ;

[0141] The first plate of the third capacitor C3 is electrically connected to the connection node NJ, and the second plate of the third capacitor C3 is electrically connected to the drive signal output terminal GT;

[0142] The driving circuit according to at least one embodiment of the present disclosure further includes a connection node control circuit 21;

[0143] The connection node control circuit 21 is electrically connected to the first node N1, the second voltage line V2, the adjacent previous level first node N1(n-1), the connection node NJ, the second node N2, the first clock signal line CB, the second output node NO2 and the first output node NO1, respectively, and is used to control the connection or disconnection between the connection node NJ and the second voltage line V2 under the control of the potential of the first node N1 and the potential of the adjacent previous level first node N1(n-1), control the connection or disconnection between the connection node NJ and the second node N2 under the control of the first clock signal provided by the first clock signal line CB, control the connection or disconnection between the connection node NJ and the second node N2 under the control of the potential of the second output node NO2, and control the connection or disconnection between the second node N2 and the first clock signal line CB under the control of the potential of the first output node NO1.

[0144] In a specific implementation, when the first energy storage circuit 13 includes a second capacitor C2 and a third capacitor C3, the driving circuit described in at least one embodiment of the present disclosure further includes a connection node control circuit 21. The connection node control circuit 21 can, during the time period when the potential of the driving signal is pulled down, cause the second voltage signal provided by the second voltage line to not be written to the connection node NJ, and cause the first clock signal provided by the first clock signal line to not be written to the connection node NJ, so that during the time period when the potential of the driving signal is pulled down, the connection node NJ is in a floating state, and by adopting the third capacitor C3 and utilizing the capacitance characteristics, during the time period when the potential of the driving signal is pulled down, the potential of the connection node NJ is lowered, thereby eliminating the falling edge step of the driving signal.

[0145] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the first energy storage circuit may further include a first capacitor C1;

[0146] The first plate of the first capacitor C1 is electrically connected to the first output node NO1 , and the second plate of the first capacitor C1 is electrically connected to the driving signal output terminal GT.

[0147] Optionally, the connection node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;

[0148] The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0149] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the first clock signal line;

[0150] The gate of the third transistor is electrically connected to the first node of the adjacent previous stage, and the second electrode of the third transistor is electrically connected to the connection node;

[0151] The gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the connection node, and the second electrode of the fourth transistor is electrically connected to the second node;

[0152] The gate of the fifth transistor is electrically connected to the second output node, the first electrode of the fifth transistor is electrically connected to the connection node, and the second electrode of the fifth transistor is electrically connected to the second node;

[0153] The first output node control circuit includes a sixth transistor;

[0154] A gate of the sixth transistor is electrically connected to the second clock signal line, a first electrode of the sixth transistor is electrically connected to the input terminal, and a second electrode of the sixth transistor is electrically connected to the first output node.

[0155] In at least one embodiment of the present disclosure, the first output node control circuit is also electrically connected to the first node, the second voltage line, the third node, the first clock signal line, the fourth node, the input end and the second clock signal line, respectively, and is used to control the connection or disconnection between the third node and the second voltage line under the control of the potential of the first node, control the connection or disconnection between the third node and the first clock signal line under the control of the potential of the fourth node, control the potential of the fourth node according to the potential of the third node, and control the connection or disconnection between the input end and the first output node under the control of the second clock signal provided by the second clock signal line, control the connection or disconnection between the input end and the fourth node under the control of the second clock signal, and control the potential of the first output node under the control of the potential of the fourth node.

[0156] In a specific implementation, the first output node control circuit can control the connection or disconnection between the third node and the second voltage line under the control of the potential of the first node, control the connection or disconnection between the third node and the first clock signal line under the control of the potential of the fourth node, control the potential of the fourth node according to the potential of the third node, and control the connection or disconnection between the input end and the first output node under the control of the second clock signal, control the connection or disconnection between the input end and the fourth node under the control of the second clock signal, and control the potential of the first output node under the control of the potential of the fourth node.

[0157] Optionally, the second voltage line may be a high voltage line.

[0158] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG1 ,

[0159] The first output node control circuit 11 is also electrically connected to the first node N1, the second voltage line V2, the third node N3, the first clock signal line CB, the fourth node N4, the input terminal I1 and the second clock signal line CK, respectively, and is used to control the connection or disconnection between the third node N3 and the second voltage line V2 under the control of the potential of the first node N1, and control the connection or disconnection between the third node N3 and the first clock signal line CB under the control of the potential of the fourth node N4, control the potential of the fourth node N4 according to the potential of the third node N3, and control the connection or disconnection between the input terminal I1 and the first output node NO1 under the control of the second clock signal provided by the second clock signal line CK, control the connection or disconnection between the input terminal I1 and the fourth node N4 under the control of the second clock signal, and control the potential of the first output node NO1 under the control of the potential of the fourth node N4.

[0160] Optionally, the first output node control circuit includes a first transistor, a second transistor, a fourth capacitor, a sixth transistor, a seventh transistor and an eighth transistor;

[0161] The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the third node;

[0162] The gate of the second transistor is electrically connected to the fourth node, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first clock signal line;

[0163] The first plate of the fourth capacitor is electrically connected to the third node, and the second plate of the fourth capacitor is electrically connected to the fourth node;

[0164] The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the first output node;

[0165] The gate of the seventh transistor is electrically connected to the second clock signal line, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node;

[0166] A gate of the eighth transistor and a first electrode of the eighth transistor are electrically connected to the fourth node, and a second electrode of the eighth transistor is electrically connected to the first output node.

[0167] In the driving circuit described in at least one embodiment of the present disclosure, the first output node control circuit further includes a ninth transistor;

[0168] The second electrode of the seventh transistor is electrically connected to the fourth node through the ninth transistor;

[0169] A gate of the ninth transistor is electrically connected to the third voltage line, a first electrode of the ninth transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the ninth transistor is electrically connected to the fourth node.

[0170] In at least one embodiment of the present disclosure, when the ninth transistor is a p-type transistor, the third voltage line is a low voltage line.

[0171] In the driving circuit described in at least one embodiment of the present disclosure, the first output node control circuit further includes a tenth transistor;

[0172] The second electrode of the sixth transistor is electrically connected to the first output node through the tenth transistor;

[0173] The gate of the tenth transistor is electrically connected to the third voltage line, the first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the first output node;

[0174] A second electrode of the sixth transistor is electrically connected to the fifth node.

[0175] In at least one embodiment of the present disclosure, when the tenth transistor is a p-type transistor, the third voltage line is a low voltage line.

[0176] In a specific implementation, the first output node control circuit may include a first transistor, a second transistor, a fourth capacitor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0177] After the potential of the input signal provided at the input end changes from high to low, the potential of the second clock signal jumps from a high voltage to a low voltage, and the input signal is written to the first output node and the fourth node. Since the low voltage value of the second clock signal is -7V, after passing through the sixth transistor, due to the threshold voltage loss, the potential of the first output node is -4.5V, and due to the threshold voltage loss after passing through the seventh transistor and the ninth transistor, the potential of the fourth node is -2.5V. At this time, a high voltage signal is written to the second output node, and the output transistor included in the output circuit is turned off; since the tenth transistor is a normally open transistor and the eighth transistor is a transistor with a diode connection structure, as the potential of the first output node gradually becomes negative, a low voltage signal is output through the output reset transistor included in the output reset circuit. Since the channel width-to-length ratio of the output reset transistor is relatively large, the potential of the first output node will gradually be lowered through the bootstrap effect. The bootstrap effect is enhanced by increasing the capacitance between the gate and the drain of the output reset transistor, so that at this stage, the potential of the first output node reaches a lower potential.

[0178] Optionally, the channel width of the output reset transistor may be greater than or equal to 30 μm, and the channel length of the output reset transistor may be less than or equal to 6 μm, but is not limited thereto.

[0179] The driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit;

[0180] The first node control circuit electrically connects the first node to the second clock signal line, the first voltage line and the first output node respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the second clock signal provided by the second clock signal line, and to control the connection or disconnection between the first node and the second clock signal line under the control of the first output node.

[0181] In a specific implementation, the driving circuit may further include a first node control circuit, which controls the connection or disconnection between the first node and the first voltage line under the control of the second clock signal, and controls the connection or disconnection between the first node and the second clock signal line under the control of the first output node.

[0182] Optionally, the first node control circuit includes an eleventh transistor and a twelfth transistor;

[0183] The gate of the eleventh transistor is electrically connected to the second clock signal line, the first electrode of the eleventh transistor is electrically connected to the first voltage line, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0184] A gate of the twelfth transistor is electrically connected to the first output node, a first electrode of the twelfth transistor is electrically connected to the second clock signal line, and a second electrode of the twelfth transistor is electrically connected to the first node.

[0185] In the driving circuit described in at least one embodiment of the present disclosure,

[0186] The second output node control circuit is also electrically connected to the first node, the first clock signal line, the sixth node, the second voltage line and the first output node, respectively, and is used to control the connection or disconnection between the sixth node and the first clock signal line under the control of the potential of the first node, control the potential of the sixth node according to the potential of the first node, control the connection between the sixth node and the second output node under the control of the first clock signal provided by the first clock signal line, and maintain the potential of the second output node, and control the connection or disconnection between the second output node and the second voltage line under the control of the potential of the first output node.

[0187] Optionally, the second voltage line may be a high voltage line.

[0188] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure may further include a first node control circuit 51. The first node control circuit 51 electrically connects the first node N1 to the second clock signal line CK, the first voltage line V1, and the first output node NO1, respectively, and is configured to control the connection or disconnection between the first node N1 and the first voltage line V1 under the control of the second clock signal provided by the second clock signal line CK, and to control the connection or disconnection between the first node N1 and the second clock signal line CK under the control of the first output node NO1.

[0189] The second output node control circuit 52 is also electrically connected to the first node N1, the first clock signal line CB, the sixth node N6, the second voltage line V2 and the first output node NO1, respectively, and is used to control the connection or disconnection between the sixth node N6 and the first clock signal line CB under the control of the potential of the first node N1, control the potential of the sixth node N6 according to the potential of the first node N1, control the connection between the sixth node N6 and the second output node NO2 under the control of the first clock signal provided by the first clock signal line CB, and maintain the potential of the second output node NO2, and control the connection or disconnection between the second output node NO2 and the second voltage line V2 under the control of the potential of the first output node NO1.

[0190] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure may further include a first node control circuit 51 ;

[0191] The first node control circuit 51 electrically connects the first node N1 to the second clock signal line CK, the first voltage line V1, and the first output node NO1, respectively, and is configured to control the connection or disconnection between the first node N1 and the first voltage line V1 under the control of the second clock signal provided by the second clock signal line CK, and to control the connection or disconnection between the first node N1 and the second clock signal line CK under the control of the first output node NO1;

[0192] The second output node control circuit 52 is also electrically connected to the first node N1, the first clock signal line CB, the sixth node N6, the second voltage line V2 and the first output node NO1, respectively, and is used to control the connection or disconnection between the sixth node N6 and the first clock signal line CB under the control of the potential of the first node N1, control the potential of the sixth node N6 according to the potential of the first node N1, control the connection between the sixth node N6 and the second output node NO2 under the control of the first clock signal provided by the first clock signal line CB, and maintain the potential of the second output node NO2, and control the connection or disconnection between the second output node NO2 and the second voltage line V2 under the control of the potential of the first output node NO1.

[0193] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG4 , the driving circuit according to at least one embodiment of the present disclosure may further include a first node control circuit 51 ;

[0194] The first node control circuit 51 electrically connects the first node N1 to the second clock signal line CK, the first voltage line V1, and the first output node NO1, respectively, and is configured to control the connection or disconnection between the first node N1 and the first voltage line V1 under the control of the second clock signal provided by the second clock signal line CK, and to control the connection or disconnection between the first node N1 and the second clock signal line CK under the control of the first output node NO1;

[0195] The second output node control circuit 52 is also electrically connected to the first node N1, the first clock signal line CB, the sixth node N6, the second voltage line V2 and the first output node NO1, respectively, and is used to control the connection or disconnection between the sixth node N6 and the first clock signal line CB under the control of the potential of the first node N1, control the potential of the sixth node N6 according to the potential of the first node N1, control the connection between the sixth node N6 and the second output node NO2 under the control of the first clock signal provided by the first clock signal line CB, and maintain the potential of the second output node NO2, and control the connection or disconnection between the second output node NO2 and the second voltage line V2 under the control of the potential of the first output node NO1.

[0196] Optionally, the second output node control circuit includes a thirteenth transistor, a fourteenth transistor, a fifth capacitor and a fifteenth transistor;

[0197] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the sixth node;

[0198] The gate of the fourteenth transistor is electrically connected to the first clock signal line, the first electrode of the fourteenth transistor is electrically connected to the sixth node, and the second electrode of the fourteenth transistor is electrically connected to the second output node;

[0199] The first plate of the fifth capacitor is electrically connected to the gate of the thirteenth transistor, and the second plate of the fifth capacitor is electrically connected to the sixth node;

[0200] A gate of the fifteenth transistor is electrically connected to the first output node, a first electrode of the fifteenth transistor is electrically connected to the second output node, and a second electrode of the fifteenth transistor is electrically connected to the second voltage line.

[0201] Optionally, the first output node control circuit includes a sixteenth transistor;

[0202] A gate of the sixteenth transistor is electrically connected to the control signal line, a first electrode of the sixteenth transistor is electrically connected to the second voltage line, and a second electrode of the sixteenth transistor is electrically connected to the first output node.

[0203] The driving circuit according to at least one embodiment of the present disclosure further includes a seventeenth transistor;

[0204] The first node is electrically connected to the gate of the thirteenth transistor through the seventeenth transistor;

[0205] A gate of the seventeenth transistor is electrically connected to the third voltage line, a first electrode of the seventeenth transistor is electrically connected to the first node, and a second electrode of the seventeenth transistor is electrically connected to the gate of the thirteenth transistor.

[0206] In a specific implementation, when the seventeenth transistor is a p-type transistor, the third voltage line may be a low voltage line.

[0207] Optionally, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0208] The gate of the output transistor is electrically connected to the second output node, the first electrode of the output transistor is electrically connected to the second voltage line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0209] A gate of the output reset transistor is electrically connected to the first output node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the first voltage line.

[0210] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG7 ,

[0211] The first energy storage circuit includes a first capacitor C1; the second energy storage circuit includes a sixth capacitor C6;

[0212] The first plate of the first capacitor C1 is electrically connected to the first output node NO1, and the second plate of the first capacitor C1 is electrically connected to the driving signal output terminal GT;

[0213] A first end of the sixth capacitor C6 is electrically connected to the second output node NO2, and a second end of the sixth capacitor C6 is electrically connected to the high voltage line VGH;

[0214] The first output node control circuit includes a first transistor T1, a second transistor T2, a fourth capacitor C4, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10;

[0215] The gate of the first transistor T1 is electrically connected to the first node N1, the drain of the first transistor T1 is electrically connected to the high voltage line VGH, and the source of the first transistor T1 is electrically connected to the third node N3;

[0216] The gate of the second transistor T2 is electrically connected to the fourth node N4, the drain of the second transistor T2 is electrically connected to the third node N3, and the source of the second transistor T2 is electrically connected to the first clock signal line CB;

[0217] The first plate of the fourth capacitor C4 is electrically connected to the third node N3, and the second plate of the fourth capacitor C4 is electrically connected to the fourth node N4;

[0218] The gate of the sixth transistor T6 is electrically connected to the second clock signal line CK, the drain of the sixth transistor T6 is electrically connected to the input terminal I1, and the source of the sixth transistor T6 is electrically connected to the fifth node N5;

[0219] The gate of the tenth transistor T10 is electrically connected to the low voltage line VGL, the drain of the tenth transistor T10 is electrically connected to the fifth node N5, and the source of the tenth transistor T10 is electrically connected to the first output node NO1;

[0220] The gate of the seventh transistor T7 is electrically connected to the second clock signal line CK, the drain of the seventh transistor T7 is electrically connected to the input terminal I1, and the source of the seventh transistor T7 is electrically connected to the drain of the ninth transistor T9;

[0221] The gate of the ninth transistor T9 is electrically connected to the low voltage line VGL, and the source of the ninth transistor T9 is electrically connected to the fourth node N4;

[0222] The gate of the eighth transistor T8 and the drain of the eighth transistor T8 are electrically connected to the fourth node N4, and the source of the eighth transistor T8 is electrically connected to the first output node NO1;

[0223] The first node control circuit includes an eleventh transistor T11 and a twelfth transistor T12;

[0224] The gate of the eleventh transistor T11 is electrically connected to the second clock signal line CK, the drain of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and the source of the eleventh transistor T11 is electrically connected to the first node N1;

[0225] The gate of the twelfth transistor T12 is electrically connected to the fifth node N5, the drain of the twelfth transistor T12 is electrically connected to the second clock signal line CK, and the source of the twelfth transistor T12 is electrically connected to the first node N1;

[0226] The second output node control circuit includes a seventeenth transistor T17, a thirteenth transistor T13, a fourteenth transistor T14, a fifth capacitor C5 and a fifteenth transistor T15;

[0227] The gate of the seventeenth transistor T17 is electrically connected to the low voltage line VGL, the drain of the seventeenth transistor T17 is electrically connected to the first node N1, and the source of the seventeenth transistor T17 is electrically connected to the gate of the thirteenth transistor T13;

[0228] A drain of the thirteenth transistor T13 is electrically connected to the first clock signal line CB, and a source of the thirteenth transistor T13 is electrically connected to the sixth node N6;

[0229] The gate of the fourteenth transistor T14 is electrically connected to the first clock signal line CB, the drain of the fourteenth transistor T14 is electrically connected to the sixth node N6, and the source of the fourteenth transistor T14 is electrically connected to the second output node NO2;

[0230] A first plate of the fifth capacitor C5 is electrically connected to the gate of the thirteenth transistor T13, and a second plate of the fifth capacitor C5 is electrically connected to the sixth node N6;

[0231] A gate of the fifteenth transistor T15 is electrically connected to the fifth node N5, a drain of the fifteenth transistor T15 is electrically connected to the second output node NO2, and a source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH;

[0232] The first output node control circuit includes a sixteenth transistor T16;

[0233] The gate of the sixteenth transistor T16 is electrically connected to the control signal line NCX, the drain of the sixteenth transistor T16 is electrically connected to the high voltage line VGH, and the source of the sixteenth transistor T16 is electrically connected to the fifth node N5;

[0234] The output circuit includes an output transistor T0, and the output reset circuit includes an output reset transistor Tf;

[0235] The gate of the output transistor T0 is electrically connected to the second output node NO2, the drain of the output transistor T0 is electrically connected to the high voltage line VGH, and the source of the output transistor T0 is electrically connected to the drive signal output terminal GT;

[0236] The gate of the output reset transistor Tf is electrically connected to the first output node NO1 , the drain of the output reset transistor Tf is electrically connected to the driving signal output terminal GT, and the source of the output reset transistor Tf is electrically connected to the low voltage line VGL.

[0237] In at least one embodiment of the driving circuit shown in FIG. 8 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0238] At least one embodiment of the driving circuit shown in FIG8 of the present disclosure adds a first capacitor C1 between the gate of Tf and the drain of Tf to enhance the pull-down capability of Tf, thereby achieving a more thorough pull-down of the potential of the driving signal provided by the driving signal output terminal GT, and enabling the transistor in the pixel circuit whose gate is connected to the driving signal to be turned off more quickly, thereby reducing the negative impact caused by the two pull-downs of the potential of the driving signal from a high level to a low level.

[0239] In related technologies, low-temperature polysilicon and oxide hybrid drives have been widely used in high-end OLED (organic light-emitting diode) display panels. At least one embodiment of the driving circuit shown in Figure 8 of the present disclosure is used to drive the oxide TFT (thin-film transistor) in the display area. The driving circuit has a stronger pull-down capability for the potential of the driving signal, which can effectively reduce the step height of the driving signal during the switching process from high level to low level, so that the high and low switching of the potential of the driving signal is smoother, thereby achieving the purpose of improving the screen display effect of the display panel.

[0240] In at least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure, T10 , T9 , and T17 are normally-on transistors.

[0241] During operation of at least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure, after the potential of the input signal provided by the input terminal I1 changes from a high voltage to a low voltage, the potential of the second clock signal provided by CK changes from a high voltage to a low voltage. The low voltage signal provided by I1 is written into N5, N4, and NO2. Since the low voltage value of the second clock signal is -7V, after T6, the potential of N5 is -4.5V due to threshold voltage loss. After T7 and T9, the potential of N4 is -2.5V due to threshold voltage loss. At this time, T15 is turned on, NO2 is connected to VGH, and T0 is turned off. Since T10 is a normally open transistor and T8 is a diode-connected transistor, as the potential of NO1 gradually becomes negative, the low voltage signal provided by VGL is output through Tf. Since Tf is a buffer transistor with a large channel width-to-length ratio, the potential of NO1 is gradually lowered through the bootstrap effect. The bootstrap effect is enhanced by increasing the voltage between the gate and drain of Tf, so that the potential of NO1 reaches a lower potential during this stage.

[0242] FIG. 9 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 8 .

[0243] As shown in FIG9 , when at least one embodiment of the driving circuit shown in FIG8 is in operation, the falling edge of the driving signal output by GT has no step.

[0244] In a specific implementation, when at least one embodiment of the driving circuit shown in FIG8 is operating, a simulation scan is performed with the capacitance value of C1 ranging from 0fF to 100fF, with a gradient of 10fF. It can be seen that as the capacitance value of C1 increases, the pull-down step of the potential of NO1 gradually decreases after the input signal potential jumps from a high voltage to a low voltage. After the capacitance value of C4 increases to a certain value, the position of the pull-down step of the potential of NO1 becomes increasingly close to the output voltage of -7V. However, in actual layouts, increasing the capacitance value of C1 will increase the layout area, affecting the overall width of the driving circuit and further affecting the size of the display panel frame. Therefore, it is more reasonable to set the capacitance value of C1 between 5fF and 50fF.

[0245] In at least one embodiment of the present disclosure, the first capacitor includes a first electrode plate and a second electrode plate;

[0246] The first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other;

[0247] The first electrode portion is formed on a first metal layer, the second electrode portion is formed on a second metal layer, the second electrode portion is formed on a third metal layer, and the second metal layer is disposed between the first metal layer and the third metal layer;

[0248] The sixth capacitor includes a first plate and a second plate;

[0249] The first electrode plate of the sixth capacitor is formed on the first metal layer, and the second electrode plate of the sixth capacitor is formed on the fifth metal layer.

[0250] Optionally, the first metal layer is a first gate metal layer, the second metal layer is a first source / drain metal layer, the third metal layer is a second source / drain metal layer, and the fifth metal layer may be a second gate metal layer.

[0251] FIG. 10A is a first layout diagram of at least one embodiment of the driving circuit shown in FIG. 8 .

[0252] In FIG. 10A , VGH1 is a first high voltage line, VH2 is a second high voltage line, VGH3 is a third high voltage line, VGL1 is a first low voltage line, and VGL2 is a second low voltage line.

[0253] Fig. 10B is a layout diagram of the semiconductor layer in Fig. 10A. In Fig. 10B, A0 is an active pattern of T0, and Af is an active pattern of Tf.

[0254] 10C is a layout diagram of the first gate metal layer in FIG10A . In FIG10C , C1a is the first electrode portion of C1 , C41 is the first electrode portion of C4 , C51 is the first electrode portion of C5 , and C61 is the first electrode portion of C6 .

[0255] Figure 10D is a layout diagram of the second gate metal layer in Figure 10A. In Figure 10D, C42 is the second electrode plate of C4, C52 is the second electrode plate of C5, and C62 is the second electrode plate of C6.

[0256] Figure 10E is a layout diagram of the first source / drain metal layer in Figure 10A. In Figure 10E, the element labeled C1b is the second electrode plate of C1.

[0257] FIG. 10F is a layout diagram of the second source / drain metal layer in FIG. 10A .

[0258] As shown in Figure 10A, in order not to occupy too much Layout space and to ensure the stability of the increased capacitance value of C1, a sandwich structure of a first gate metal layer, a first source-drain metal layer and a second source-drain metal layer is adopted in the design. The first capacitor includes a first electrode and a second electrode. The first electrode includes a first electrode portion and a second electrode portion electrically connected to each other. The first electrode portion is formed on the first gate metal layer, the second electrode is formed on the first source-drain metal layer, and the second electrode portion is formed on the second source-drain metal layer. A stable capacitance value is formed through the sandwich design.

[0259] As shown in FIG11 , reference numeral 111 is a first gate metal layer, reference numeral 112 is an interlayer dielectric layer, reference numeral 113 is a first source / drain metal layer, reference numeral 114 is a passivation layer, reference numeral 115 is a planarization layer, and reference numeral 116 is a second source / drain metal layer;

[0260] A driving signal output terminal is formed on the first source / drain metal layer 113 , and the driving signal output terminal is electrically connected to the second electrode plate;

[0261] In the first gate metal layer 111 , the gate of Tf and the first plate portion of C1 are formed, and the first plate portion of C1 , the gate of Tf, and the second plate portion of C1 are electrically connected to each other.

[0262] In at least one embodiment of the present disclosure, the first capacitor includes a first plate and a second plate; the sixth capacitor includes a first plate and a second plate;

[0263] The first electrode plate of the first capacitor is formed on the fourth metal layer, and the second electrode plate of the first capacitor is formed on the fifth metal layer;

[0264] The first electrode plate of the sixth capacitor is formed on the fourth metal layer, and the second electrode plate of the sixth capacitor is formed on the fifth metal layer.

[0265] Optionally, the fourth metal layer is a first gate metal layer, and the fifth metal layer is a second gate metal layer.

[0266] FIG. 12A is a second layout diagram of at least one embodiment of the driving circuit shown in FIG. 8 .

[0267] In FIG12A , VGH1 is a first high voltage line, VH2 is a second high voltage line, VGH3 is a third high voltage line, VGL1 is a first low voltage line, and VGL2 is a second low voltage line.

[0268] Fig. 12B is a layout diagram of the semiconductor layer in Fig. 12 A. In Fig. 12B, A0 is an active pattern of T0, and Af is an active pattern of Tf.

[0269] Fig. 12C is a layout diagram of the first gate metal layer in Fig. 12A. In Fig. 12C, C11 is the first electrode plate of C1, and C61 is the first electrode plate of C6.

[0270] Fig. 12D is a layout diagram of the second gate metal layer in Fig. 12A. In Fig. 12D, C1b is the second electrode plate of C1, and C62 is the second electrode plate of C6.

[0271] FIG12E is a layout diagram of the first source / drain metal layer in FIG12A .

[0272] FIG12F is a layout diagram of the second source / drain metal layer in FIG12A .

[0273] As shown in FIG13 , reference numeral 111 denotes a first gate metal layer, reference numeral 117 denotes a second gate metal layer, and reference numeral 118 denotes a gate insulating layer. The gate insulating layer 118 is disposed between the first gate metal layer 111 and the second gate metal layer 117 .

[0274] The first plate of the first capacitor is formed on the first gate metal layer 111 , and the second plate of the first capacitor is formed on the second gate metal layer 117 ;

[0275] The gate of Tf is formed on the first gate metal layer 111, and the gate of Tf is electrically connected to the first plate of the first capacitor;

[0276] The driving signal output terminal is formed in the second gate metal layer 117 , and the driving signal output terminal is electrically connected to the second plate of the first capacitor.

[0277] In at least one embodiment of the present disclosure, a first gate metal layer and a second gate metal layer may be used to form a first capacitor. Since the dielectric constant of the first gate metal layer and the dielectric constant of the second gate metal layer are larger, a smaller overlapping area can form a larger capacitance value.

[0278] In a specific implementation, the film layer forming the electrode plate of the first capacitor may be any metal film layer, and may be designed according to the dielectric constants between different metal film layers.

[0279] At least one embodiment of the present disclosure, by providing a first capacitor between the gate and drain of Tf, can be applied not only to 16T drive circuits but also to shift registers such as 13T drive circuits and 12T drive circuits that output low-voltage and high-voltage signals by using the bootstrap effect of buffer transistors, thereby reducing the falling step of Tf during the output reset phase.

[0280] As shown in FIG14 , based on at least one embodiment of the driving circuit shown in FIG5 ,

[0281] The first energy storage circuit includes a second capacitor C2 and a third capacitor C3; the second energy storage circuit includes a sixth capacitor C6;

[0282] The first plate of the second capacitor C2 is electrically connected to the first output node NO1, and the second plate of the second capacitor C2 is electrically connected to the connection node NJ;

[0283] The first plate of the third capacitor C3 is electrically connected to the connection node NJ, and the second plate of the third capacitor C3 is electrically connected to the drive signal output terminal GT;

[0284] A first end of the sixth capacitor C6 is electrically connected to the second output node NO2, and a second end of the sixth capacitor C6 is electrically connected to the high voltage line VGH;

[0285] The connection node control circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5;

[0286] The gate of the first transistor T1 is electrically connected to the first node N1, the drain of the first transistor T1 is electrically connected to the high voltage line VGH, and the source of the first transistor T1 is electrically connected to the drain of the third transistor T3;

[0287] The gate of the second transistor T2 is electrically connected to the first output node NO1, the drain of the second transistor T2 is electrically connected to the second node N2, and the source of the second transistor T2 is electrically connected to the first clock signal line CB;

[0288] The gate of the third transistor T3 is electrically connected to the first node N1(n-1) of the adjacent previous stage, and the source of the third transistor T3 is electrically connected to the connection node NJ;

[0289] The gate of the fourth transistor T4 is electrically connected to the first clock signal line CB, the drain of the fourth transistor T4 is electrically connected to the connection node NJ, and the source of the fourth transistor T4 is electrically connected to the second node N2;

[0290] The gate of the fifth transistor T5 is electrically connected to the second output node NO2, the drain of the fifth transistor T5 is electrically connected to the connection node NJ, and the source of the fifth transistor T5 is electrically connected to the second node N2;

[0291] The first output node control circuit includes a sixth transistor T6 and a tenth transistor T10;

[0292] The gate of the sixth transistor T6 is electrically connected to the second clock signal line CK, the drain of the sixth transistor T6 is electrically connected to the input terminal I1, and the source of the sixth transistor T6 is electrically connected to the fifth node N5;

[0293] The gate of the tenth transistor T10 is electrically connected to the low voltage line VGL, the drain of the tenth transistor T10 is electrically connected to the fifth node N5, and the source of the tenth transistor T10 is electrically connected to the first output node NO1;

[0294] The first node control circuit includes an eleventh transistor T11 and a twelfth transistor T12;

[0295] The gate of the eleventh transistor T11 is electrically connected to the second clock signal line CK, the drain of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and the source of the eleventh transistor T11 is electrically connected to the first node N1;

[0296] The gate of the twelfth transistor T12 is electrically connected to the fifth node N5, the drain of the twelfth transistor T12 is electrically connected to the second clock signal line CK, and the source of the twelfth transistor T12 is electrically connected to the first node N1;

[0297] The second output node control circuit includes a seventeenth transistor T17, a thirteenth transistor T13, a fourteenth transistor T14, a fifth capacitor C5 and a fifteenth transistor T15;

[0298] The gate of the seventeenth transistor T17 is electrically connected to the low voltage line VGL, the drain of the seventeenth transistor T17 is electrically connected to the first node N1, and the source of the seventeenth transistor T17 is electrically connected to the gate of the thirteenth transistor T13;

[0299] A drain of the thirteenth transistor T13 is electrically connected to the first clock signal line CB, and a source of the thirteenth transistor T13 is electrically connected to the sixth node N6;

[0300] The gate of the fourteenth transistor T14 is electrically connected to the first clock signal line CB, the drain of the fourteenth transistor T14 is electrically connected to the sixth node N6, and the source of the fourteenth transistor T14 is electrically connected to the second output node NO2;

[0301] A first plate of the fifth capacitor C5 is electrically connected to the gate of the thirteenth transistor T13, and a second plate of the fifth capacitor C5 is electrically connected to the sixth node N6;

[0302] A gate of the fifteenth transistor T15 is electrically connected to the fifth node N5, a drain of the fifteenth transistor T15 is electrically connected to the second output node NO2, and a source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH;

[0303] The first output node control circuit includes a sixteenth transistor T16;

[0304] The gate of the sixteenth transistor T16 is electrically connected to the control signal line NCX, the drain of the sixteenth transistor T16 is electrically connected to the high voltage line VGH, and the source of the sixteenth transistor T16 is electrically connected to the fifth node N5;

[0305] The output circuit includes an output transistor T0, and the output reset circuit includes an output reset transistor Tf;

[0306] The gate of the output transistor T0 is electrically connected to the second output node NO2, the drain of the output transistor T0 is electrically connected to the high voltage line VGH, and the source of the output transistor T0 is electrically connected to the drive signal output terminal GT;

[0307] The gate of the output reset transistor Tf is electrically connected to the first output node NO1 , the drain of the output reset transistor Tf is electrically connected to the driving signal output terminal GT, and the source of the output reset transistor Tf is electrically connected to the low voltage line VGL.

[0308] At least one embodiment of the drive circuit shown in FIG. 14 of the present disclosure adds T3, T4, T5, and C3 during operation. The gate of T3 is electrically connected to the first node in the adjacent upper-level drive circuit. T1 and T3 are utilized to prevent the high voltage signal provided by VGH from being written to the connection node NJ during the time period when the potential of the drive signal output by the drive circuit decreases. T4 and T5 are connected in parallel. The gate of T4 is electrically connected to the first clock signal line CB, and the gate of T5 is electrically connected to the second output node NO2. During the time period when the potential of the drive signal decreases, the high voltage signal provided by CB cannot be written to the connection node NJ. Due to the effects of T3, T4, and T5, the connection node NJ is in a floating state during the time period when the potential of the drive signal decreases. By adding C3, the capacitance characteristics are utilized to pull down the potential of NJ during the time period when the potential of the drive signal decreases, thereby eliminating the falling edge step of the drive signal.

[0309] FIG15 is a timing diagram of the operation of at least one embodiment of the driving circuit shown in FIG14 of the present disclosure. As shown in FIG14 , the falling edge of the driving signal provided by the driving signal output terminal GT has no steps.

[0310] The difference between at least one embodiment of the driving circuit shown in FIG16 of the present disclosure and at least one embodiment of the driving circuit shown in FIG14 of the present disclosure is that: it further includes a first capacitor C1;

[0311] The first plate of the first capacitor C1 is electrically connected to the first output node NO1 , and the second plate of the first capacitor C1 is electrically connected to the driving signal output terminal GT.

[0312] At least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure increases the ability to pull down the potential of the first output node NO1 during the period when the potential of the driving signal decreases by adding a first capacitor C1, thereby further reducing the falling time of the driving signal.

[0313] The difference between at least one embodiment of the driving circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure is that:

[0314] The first output node control circuit includes a sixth transistor T6;

[0315] The gate of the sixth transistor T6 is electrically connected to the second clock signal line CK, the drain of the sixth transistor T6 is electrically connected to the input terminal I1, and the source of the sixth transistor T6 is electrically connected to the first output node NO1;

[0316] The second output node control circuit includes a thirteenth transistor T13, a fourteenth transistor T14, a fifth capacitor C5 and a fifteenth transistor T15;

[0317] A drain of the thirteenth transistor T13 is electrically connected to the first clock signal line CB, and a source of the thirteenth transistor T13 is electrically connected to the sixth node N6;

[0318] The gate of the fourteenth transistor T14 is electrically connected to the first clock signal line CB, the drain of the fourteenth transistor T14 is electrically connected to the sixth node N6, and the source of the fourteenth transistor T14 is electrically connected to the second output node NO2;

[0319] A first plate of the fifth capacitor C5 is electrically connected to the gate of the thirteenth transistor T13, and a second plate of the fifth capacitor C5 is electrically connected to the sixth node N6;

[0320] A gate of the fifteenth transistor T15 is electrically connected to the first output node NO1 , a drain of the fifteenth transistor T15 is electrically connected to the second output node NO2 , and a source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH.

[0321] The difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 17 of the present disclosure is that:

[0322] The second output node control circuit further includes a seventeenth transistor T17;

[0323] The first node N1 is electrically connected to the gate of the thirteenth transistor T13 through the seventeenth transistor T17;

[0324] The twelfth transistor T12 is a dual-gate transistor;

[0325] The first output node control circuit includes a sixth transistor T6 and a tenth transistor T10;

[0326] The gate of the sixth transistor T6 is electrically connected to the second clock signal line CK, the drain of the sixth transistor T6 is electrically connected to the input terminal I1, and the source of the sixth transistor T6 is electrically connected to the fifth node N5;

[0327] A gate of the tenth transistor T10 is electrically connected to the low voltage line VGL, a drain of the tenth transistor T10 is electrically connected to the fifth node N5, and a source of the tenth transistor T10 is electrically connected to the first output node NO1.

[0328] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:

[0329] The first output node control circuit controls the potential of the first output node;

[0330] The second output node control circuit controls the potential of the second output node;

[0331] The output reset circuit controls the connection between the drive signal output terminal and the first voltage line under the control of the potential of the first output node;

[0332] The output circuit controls the connection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node;

[0333] The first energy storage circuit controls the potential of the first output node according to the driving signal provided by the driving signal output terminal; the second energy storage circuit maintains the potential of the second output node.

[0334] The display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0335] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising a first output node control circuit, an output reset circuit, a second output node control circuit, an output circuit, a first energy storage circuit, a second energy storage circuit and a driving signal output terminal; The first output node control circuit is electrically connected to the first output node and is used to control the potential of the first output node; The second output node control circuit is electrically connected to the second output node and is used to control the potential of the second output node; The output reset circuit is electrically connected to the first output node, the drive signal output terminal and the first voltage line respectively, and is used to control the connection between the drive signal output terminal and the first voltage line under the control of the potential of the first output node; The output circuit is electrically connected to the second output node, the drive signal output terminal and the second voltage line respectively, and is used to control the connection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node; The first energy storage circuit is electrically connected to the first output node and the drive signal output terminal respectively, and the second energy storage circuit is electrically connected to the second output node and the second voltage line respectively; the first energy storage circuit and the second energy storage circuit are used to store electrical energy.

2. The driving circuit according to claim 1, wherein: The first energy storage circuit includes a first capacitor; The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal; The second energy storage circuit includes a sixth capacitor; The first plate of the sixth capacitor is electrically connected to the second output node, and the second plate of the sixth capacitor is electrically connected to the second voltage line.

3. The driving circuit according to claim 1, wherein: The first energy storage circuit includes a second capacitor and a third capacitor; The first plate of the second capacitor is electrically connected to the first output node, and the second plate of the second capacitor is electrically connected to the connection node; The first plate of the third capacitor is electrically connected to the connection node, and the second plate of the third capacitor is electrically connected to the drive signal output terminal.

4. The driving circuit according to claim 1, wherein: The first energy storage circuit includes a first capacitor, a second capacitor and a third capacitor; The first plate of the first capacitor is electrically connected to the first output node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal; The first plate of the second capacitor is electrically connected to the first output node, and the second plate of the second capacitor is electrically connected to the connection node; The first plate of the third capacitor is electrically connected to the connection node, and the second plate of the third capacitor is electrically connected to the drive signal output terminal.

5. The driving circuit according to claim 3 or 4, wherein: Also included is a connection node control circuit; The connecting node control circuit is electrically connected to the first node, the second voltage line, the first node of the adjacent previous level, the connecting node, the second node, the first clock signal line, the second output node and the first output node, respectively, and is used to control the connection or disconnection between the connecting node and the second voltage line under the control of the potential of the first node and the potential of the first node of the adjacent previous level, control the connection or disconnection between the connecting node and the second node under the control of the first clock signal provided by the first clock signal line, control the connection or disconnection between the connecting node and the second node under the control of the potential of the second output node, and control the connection or disconnection between the second node and the first clock signal line under the control of the potential of the first output node.

6. The driving circuit according to claim 5, wherein: The connection node control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor; The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the first clock signal line; The gate of the third transistor is electrically connected to the first node of the adjacent previous stage, and the second electrode of the third transistor is electrically connected to the connection node; The gate of the fourth transistor is electrically connected to the first clock signal line, the first electrode of the fourth transistor is electrically connected to the connection node, and the second electrode of the fourth transistor is electrically connected to the second node; The gate of the fifth transistor is electrically connected to the second output node, the first electrode of the fifth transistor is electrically connected to the connection node, and the second electrode of the fifth transistor is electrically connected to the second node; The first output node control circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected to the second clock signal line, a first electrode of the sixth transistor is electrically connected to the input terminal, and a second electrode of the sixth transistor is electrically connected to the first output node.

7. The driving circuit according to claim 1, wherein: The first output node control circuit is also electrically connected to the first node, the second voltage line, the third node, the first clock signal line, the fourth node, the input end and the second clock signal line, respectively, and is used to control the connection or disconnection between the third node and the second voltage line under the control of the potential of the first node, control the connection or disconnection between the third node and the first clock signal line under the control of the potential of the fourth node, control the potential of the fourth node according to the potential of the third node, and control the connection or disconnection between the input end and the first output node under the control of the second clock signal provided by the second clock signal line, control the connection or disconnection between the input end and the fourth node under the control of the second clock signal, and control the potential of the first output node under the control of the potential of the fourth node.

8. The driving circuit according to claim 7, wherein: The first output node control circuit includes a first transistor, a second transistor, a fourth capacitor, a sixth transistor, a seventh transistor and an eighth transistor; The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the third node; The gate of the second transistor is electrically connected to the fourth node, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first clock signal line; The first electrode plate of the fourth capacitor is electrically connected to the third node, and the second electrode plate of the fourth capacitor is electrically connected to the fourth node; The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the input terminal, and the second electrode of the sixth transistor is electrically connected to the first output node; The gate of the seventh transistor is electrically connected to the second clock signal line, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node; A gate of the eighth transistor and a first electrode of the eighth transistor are electrically connected to the fourth node, and a second electrode of the eighth transistor is electrically connected to the first output node.

9. The driving circuit according to claim 8, wherein: The first output node control circuit further includes a ninth transistor; The second electrode of the seventh transistor is electrically connected to the fourth node through the ninth transistor; A gate of the ninth transistor is electrically connected to the third voltage line, a first electrode of the ninth transistor is electrically connected to a second electrode of the seventh transistor, and a second electrode of the ninth transistor is electrically connected to the fourth node.

10. The driving circuit according to claim 8 or 9, wherein: The first output node control circuit further includes a tenth transistor; The second electrode of the sixth transistor is electrically connected to the first output node through the tenth transistor; The gate of the tenth transistor is electrically connected to the third voltage line, the first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the first output node; A second electrode of the sixth transistor is electrically connected to the fifth node.

11. The driving circuit according to claim 1, 2, 3, 4, 7, 8 or 9, wherein: Also included is a first node control circuit; The first node control circuit electrically connects the first node to the second clock signal line, the first voltage line and the first output node, respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the second clock signal provided by the second clock signal line, and to control the connection or disconnection between the first node and the second clock signal line under the control of the first output node.

12. The driving circuit according to claim 11, wherein: The first node control circuit includes an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor is electrically connected to the second clock signal line, the first electrode of the eleventh transistor is electrically connected to the first voltage line, and the second electrode of the eleventh transistor is electrically connected to the first node; A gate of the twelfth transistor is electrically connected to the first output node, a first electrode of the twelfth transistor is electrically connected to the second clock signal line, and a second electrode of the twelfth transistor is electrically connected to the first node.

13. The driving circuit according to claim 11, wherein: The second output node control circuit is also electrically connected to the first node, the first clock signal line, the sixth node, the second voltage line and the first output node, respectively, and is used to control the connection or disconnection between the sixth node and the first clock signal line under the control of the potential of the first node, control the potential of the sixth node according to the potential of the first node, and control the connection between the sixth node and the first clock signal line under the control of the first clock signal provided by the first clock signal line. The second output nodes are connected and used to maintain the potential of the second output node. Under the control of the potential of the first output node, the second output node and the second voltage line are controlled to be connected or disconnected.

14. The driving circuit according to claim 13, wherein: The second output node control circuit includes a thirteenth transistor, a fourteenth transistor, a fifth capacitor and a fifteenth transistor; The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the sixth node; The gate of the fourteenth transistor is electrically connected to the first clock signal line, the first electrode of the fourteenth transistor is electrically connected to the sixth node, and the second electrode of the fourteenth transistor is electrically connected to the second output node; The first plate of the fifth capacitor is electrically connected to the gate of the thirteenth transistor, and the second plate of the fifth capacitor is electrically connected to the sixth node; A gate of the fifteenth transistor is electrically connected to the first output node, a first electrode of the fifteenth transistor is electrically connected to the second output node, and a second electrode of the fifteenth transistor is electrically connected to the second voltage line.

15. The driving circuit according to claim 14, wherein: The first output node control circuit includes a sixteenth transistor; A gate of the sixteenth transistor is electrically connected to the control signal line, a first electrode of the sixteenth transistor is electrically connected to the second voltage line, and a second electrode of the sixteenth transistor is electrically connected to the first output node.

16. The driving circuit according to claim 14, wherein: Also included is a seventeenth transistor; The first node is electrically connected to the gate of the thirteenth transistor through the seventeenth transistor; A gate of the seventeenth transistor is electrically connected to the third voltage line, a first electrode of the seventeenth transistor is electrically connected to the first node, and a second electrode of the seventeenth transistor is electrically connected to the gate of the thirteenth transistor.

17. The driving circuit according to claim 13, wherein: The output circuit includes an output transistor, and the output reset circuit includes an output reset transistor; The gate of the output transistor is electrically connected to the second output node, the first electrode of the output transistor is electrically connected to the second voltage line, and the second electrode of the output transistor is electrically connected to the drive signal output terminal; A gate of the output reset transistor is electrically connected to the first output node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the first voltage line.

18. The driving circuit according to claim 2, wherein: The first capacitor includes a first plate and a second plate; The first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other; The first electrode portion is formed on a first metal layer, the second electrode portion is formed on a second metal layer, the second electrode portion is formed on a third metal layer, and the second metal layer is disposed between the first metal layer and the third metal layer; The sixth capacitor includes a first plate and a second plate; The first electrode plate of the sixth capacitor is formed on the first metal layer, and the second electrode plate of the sixth capacitor is formed on the fifth metal layer.

19. The driving circuit according to claim 18, wherein: The first metal layer is a first gate metal layer, the second metal layer is a first source-drain metal layer, the third metal layer is a second source-drain metal layer, and the fifth metal layer is a second gate metal layer.

20. The driving circuit according to claim 2, wherein: The first capacitor includes a first plate and a second plate; the sixth capacitor includes a first plate and a second plate; The first electrode plate of the first capacitor is formed on the fourth metal layer, and the second electrode plate of the first capacitor is formed on the fifth metal layer; The first electrode plate of the sixth capacitor is formed on the fourth metal layer, and the second electrode plate of the sixth capacitor is formed on the fifth metal layer.

21. The driving circuit according to claim 20, wherein: The fourth metal layer is a first gate metal layer, and the fifth metal layer is a second gate metal layer.

22. A driving method, applied to the driving circuit according to any one of claims 1 to 21, the driving method comprising: The first output node control circuit controls the potential of the first output node; The second output node control circuit controls the potential of the second output node; The output reset circuit controls the driving signal output terminal to be connected to the first voltage line under the control of the potential of the first output node; The output circuit controls the connection between the drive signal output terminal and the second voltage line under the control of the potential of the second output node; The first energy storage circuit controls the potential of the first output node according to the driving signal provided by the driving signal output terminal; The second energy storage circuit maintains the potential of the second output node.

23. A display device comprising the driving circuit according to any one of claims 1 to 21.

Images