Array substrate, manufacturing method thereof and display panel

Abstract

The invention discloses an array substrate (100), a manufacturing method thereof and a display panel, and belongs to the technical field of display. The array substrate (100) comprises a substrate (101), a reflective pattern (102), a plurality of first gate signal lines (103) and a plurality of data signal lines (104). The light reflecting pattern (102) comprises a plurality of reflecting parts (1021), and an opening area is arranged between every two adjacent reflecting parts (1021). Since the first gate signal line (103) and the data signal line (104) are film layers with low light transmittance, the reflective pattern (102) can be at least partially overlapped with the first gate signal line (103) and the data signal line (104), and when light of a light source irradiates the reflective pattern (102), the reflective pattern (102) can reflect the light of the light source to other film layers, so that the light of the light source can be reflected by the reflective pattern (102). The other film layers reflect at least part of the light of the light source to the side, away from the substrate (101), of the reflective pattern (102), so that the backlight utilization rate of the display panel comprising the array substrate (100) can be improved through the reflective pattern (102), and the influence of the first gate signal line (103) and the data signal line (104) with low light transmittance on the light transmittance of the array substrate (100) is reduced.

Description

Array substrate and manufacturing method thereof, and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] A display panel generally includes an array substrate, which is a device used to control the display panel.

[0003] A display panel includes a stacked backlight structure, an array substrate, and a color filter substrate, and a liquid crystal layer located between the array and color filter substrates. The array substrate includes a substrate and multiple thin-film transistors (TFTs) located on the substrate. It also includes pixel electrodes electrically connected to the TFTs in a one-to-one correspondence, as well as gate signal lines and data signal lines.

[0004] However, the light transmittance of the above array substrate is relatively low, resulting in a poor display effect of a display panel using the array substrate.

[0005] Summary of the Invention

[0006] The present invention provides an array substrate and a manufacturing method thereof, and a display panel. The technical solution is as follows:

[0007] According to one aspect of the present application, an array substrate is provided, comprising:

[0008] substrate;

[0009] a reflective pattern located on the substrate, the reflective pattern comprising a plurality of reflective portions, with an opening area between two adjacent reflective portions;

[0010] a plurality of first gate signal lines located on a side of the reflective pattern facing away from the substrate;

[0011] a plurality of data signal lines located on a side of the plurality of first gate signal lines facing away from the substrate;

[0012] The orthographic projection of the first gate signal line on the substrate and the orthographic projection of the data signal line on the substrate have a first overlapping region, and at least one of the plurality of first overlapping regions is located in the orthographic projection of the reflective portion on the substrate.

[0013] Optionally, the array substrate further comprises a buffer layer, a second active layer pattern, a first gate insulating layer, a plurality of second gate signal lines, a first interlayer dielectric layer and a first active layer pattern located between the plurality of first gate signal lines and the reflective pattern;

[0014] The buffer layer, the second active layer pattern, the first gate insulating layer, the plurality of second gate signal lines, the first interlayer dielectric layer, and the first active layer pattern are stacked and arranged in a direction away from the substrate.

[0015] Optionally, the array substrate further includes a light shielding pattern located between the light reflecting pattern and the first active layer pattern;

[0016] The first active layer pattern includes a plurality of first active layers, each of the first active layers having a channel region, and an orthographic projection of the channel region on the substrate is located within an orthographic projection of the light shielding pattern on the substrate;

[0017] An orthographic projection of the light-shielding pattern on the substrate overlaps with an orthographic projection of the light-reflecting pattern on the substrate.

[0018] Optionally, the material of the reflective pattern includes at least one of molybdenum, aluminum, titanium and silver, and the thickness of the reflective pattern ranges from 50 angstroms to 2000 angstroms.

[0019] Optionally, the array substrate further comprises a buffer layer, a second active layer pattern, a first gate insulating layer, a plurality of second gate signal lines, a first interlayer dielectric layer, and a first active layer pattern located on a side of the plurality of first gate signal lines close to the substrate;

[0020] The buffer layer, the second active layer pattern, the first gate insulating layer, the plurality of second gate signal lines, the first interlayer dielectric layer and the first active layer pattern are stacked and arranged in a direction away from the substrate;

[0021] The reflective pattern and the plurality of second gate signal lines are in the same layer structure.

[0022] Optionally, the material of the reflective pattern includes at least one of molybdenum, aluminum and titanium, and the thickness of the reflective pattern ranges from 1500 angstroms to 6000 angstroms.

[0023] Optionally, the plurality of reflective portions are arranged in an array, the data signal line extends along a first direction, and the plurality of data signal lines are arranged along a second direction, the first gate signal line extends along the second direction, and the plurality of first gate signal lines are arranged along the first direction;

[0024] The plurality of reflective portions satisfy the following formulas: L1 = n × H; L2 = 3n × W;

[0025] Wherein, L1 is the distance between the centers of two adjacent reflective portions along the first direction, H is the shortest distance between the centers of two adjacent first gate signal lines in the first direction, and n is a positive integer greater than or equal to 1;

[0026] The L2 is the distance between the centers of two adjacent reflective portions along the second direction, and the W is the shortest distance between the centers of two adjacent data signal lines along the second direction.

[0027] Optionally, the plurality of first gate signal lines and the plurality of data signal lines satisfy the following formula: D1 / D2≥1.3;

[0028] Wherein, D1 is the distance between two adjacent first gate signal lines, and D2 is the distance between two adjacent data signal lines.

[0029] Optionally, the plurality of reflective portions are arranged in a plurality of rows, the plurality of rows of reflective portions are arranged along a first direction, and the plurality of reflective portions in a row of reflective portions are arranged along a second direction, the first direction is an extension direction of the data signal line, and the second direction is an extension direction of the first gate signal line;

[0030] The multiple reflective portions in two adjacent rows of reflective portions are arranged in a staggered manner.

[0031] Optionally, the plurality of reflective portions are arranged in a plurality of rows, the plurality of rows of reflective portions are arranged along a first direction, and the plurality of reflective portions in a row of reflective portions are arranged along a second direction, the first direction is an extension direction of the data signal line, and the second direction is an extension direction of the first gate signal line;

[0032] A row of the reflecting parts includes a plurality of first reflecting parts and a plurality of second reflecting parts, and the first reflecting parts and the second reflecting parts are alternately arranged along the second direction;

[0033] The first overlapping region has a first side and a second side opposite to each other along the first direction, the center of the orthographic projection of the first reflecting portion on the substrate is located on the first side of the center of the first overlapping region, and the center of the orthographic projection of the second reflecting portion on the substrate is located on the second side of the center of the first overlapping region.

[0034] Optionally, a shape of an orthographic projection of the reflective portion on the substrate includes at least one of a circle, an ellipse, a square and a regular hexagon.

[0035] Optionally, the orthographic projection of the reflective portion on the substrate is rectangular, the multiple reflective portions correspond one-to-one to the multiple first overlapping regions, and the first overlapping regions are located in the orthographic projection of the corresponding reflective portion on the substrate;

[0036] The difference between the width of the reflective portion in the first direction and the width of the first overlapping region in the first direction is in a range of 1 micron to 8 microns, and the difference between the width of the reflective portion in the second direction and the width of the first overlapping region in the second direction is in a range of 1 micron to 6 microns;

[0037] The first direction is an extending direction of the data signal line, and the second direction is an extending direction of the first gate signal line.

[0038] Optionally, the plurality of reflective portions are arranged in a plurality of rows, the reflective portions in the plurality of rows are arranged along the first direction, and the plurality of reflective portions in a row of reflective portions are arranged along the second direction;

[0039] The reflective pattern further includes a plurality of connecting portions, each of which is located between two adjacent reflective portions in a row of the reflective portions and is connected to the two adjacent reflective portions;

[0040] An orthographic projection of the connection portion on the substrate is located in an orthographic projection of the first gate signal line on the substrate.

[0041] Optionally, the reflective portion comprises a reflective portion main body and two first protruding structures, the two first protruding structures are respectively located on both sides of the reflective portion main body in the second direction, and an opening area is provided between two adjacent first protruding structures of the reflective portion along the second direction;

[0042] The orthographic projection of the first protruding structure on the substrate is located in the orthographic projection of the first gate signal line on the substrate.

[0043] Optionally, the plurality of reflective portions are arranged in a plurality of rows, the reflective portions in the plurality of rows are arranged along the first direction, and the plurality of reflective portions in a row of reflective portions are arranged along the second direction;

[0044] A row of the reflecting parts includes a plurality of reflecting part units, and one reflecting part unit includes a plurality of reflecting parts;

[0045] In two adjacent reflection unit units, the length of the reflection part in one reflection unit in the first direction is a first length, and the length of the reflection part in the other reflection unit in the first direction is a second length, and the first length is greater than the second length.

[0046] Optionally, the multiple reflecting portions include multiple reflecting portion groups, one reflecting portion group includes two rows of reflecting portions, the multiple reflecting portion groups are arranged along a first direction, the two rows of reflecting portions in one reflecting portion group are arranged along the first direction, and the multiple reflecting portions in one row of reflecting portions are arranged along a second direction, the first direction is an extension direction of the data signal line, and the second direction is an extension direction of the first gate signal line;

[0047] The orthographic projections of the multiple reflecting parts in one row of reflecting parts in one reflecting part group on the substrate are circular, and the orthographic projections of the multiple reflecting parts in another row of reflecting parts on the substrate are rectangular.

[0048] According to another aspect of the present application, a method for manufacturing an array substrate is provided, the method comprising:

[0049] forming a reflective pattern on a substrate, wherein the reflective pattern comprises a plurality of reflective portions, and an opening area is provided between two adjacent reflective portions;

[0050] forming a plurality of first gate signal lines on the substrate having the light-reflecting pattern formed thereon;

[0051] forming a plurality of first data signal lines on a substrate on which a plurality of first gate signal lines are formed;

[0052] The orthographic projection of the first gate signal line on the substrate and the orthographic projection of the data signal line on the substrate have a first overlapping area, and the orthographic projection of the reflective portion on the substrate overlaps with the first overlapping area.

[0053] According to another aspect of the present application, a display panel is provided, comprising: an array substrate and a color filter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is the above-mentioned array substrate.

[0054] Optionally, the display panel further includes a plurality of supporting portions located between the array substrate and the color filter substrate, and an orthographic projection of at least one of the plurality of supporting portions on the substrate is located within an orthographic projection of the reflective portion on the substrate.

[0055] Optionally, the color filter substrate includes a plurality of red color resist blocks, a plurality of blue color resist blocks and a plurality of green color resist blocks;

[0056] The orthographic projection of the reflecting portion on the substrate overlaps with the orthographic projection of at least one red color resist block among the multiple red color resist blocks on the substrate, the orthographic projection of the reflecting portion on the substrate overlaps with the orthographic projection of at least one blue color resist block among the multiple blue color resist blocks on the substrate, and the orthographic projection of the reflecting portion on the substrate is staggered with the orthographic projection of the green color resist block on the substrate.

[0057] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0058] Provided is an array substrate comprising a substrate, a reflective pattern, a plurality of first gate signal lines, and a plurality of data signal lines. The reflective pattern comprises a plurality of reflective portions, with an opening region between two adjacent reflective portions. Since both the first gate signal lines and the data signal lines are film layers with low light transmittance, the reflective pattern can overlap at least partially with the first gate signal lines and the data signal lines. When light from a light source is irradiated on the reflective pattern, the reflective pattern can reflect the light from the light source to other film layers, which in turn reflect at least part of the light from the light source toward a side of the reflective pattern away from the substrate. Therefore, the reflective pattern can improve the backlight utilization rate of a display panel comprising the array substrate, reduce the influence of the first gate signal lines and data signal lines with low light transmittance on the transmittance of the array substrate, solve the problem of poor display effect of a display panel using the array substrate in the related art, and improve the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0061] FIG2 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG1 along position A1-A2;

[0062] FIG3 is a schematic diagram of a portion of the film layers of the array substrate shown in FIG1 ;

[0063] FIG4 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0064] FIG5 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG4 along position B1-B2;

[0065] FIG6 is a schematic diagram of another cross-sectional structure of the array substrate shown in FIG4 along the B1-B2 position;

[0066] FIG7 is a schematic diagram of another cross-sectional structure of the array substrate shown in FIG4 along the B1-B2 position;

[0067] FIG8 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0068] FIG9 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0069] FIG10 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0070] FIG11 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0071] FIG12 is a schematic diagram of shapes of various reflective portions provided in an embodiment of the present application;

[0072] FIG13 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0073] FIG14 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0074] FIG15 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0075] FIG16 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0076] FIG17 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0077] FIG18 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0078] FIG19 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0079] FIG20 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0080] FIG21 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG20 along the position C1-C2;

[0081] FIG22 is a schematic diagram of a partial film layer of the array substrate shown in FIG20 ;

[0082] FIG23 is a schematic diagram of another cross-sectional structure of the array substrate shown in FIG20 along the position C1-C2;

[0083] FIG24 is a schematic diagram of another cross-sectional structure of the array substrate shown in FIG20 along the position C1-C2;

[0084] FIG25 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0085] FIG26 is a flow chart of another method for manufacturing a substrate provided in an embodiment of the present application;

[0086] FIG27 is a schematic diagram of a film structure of a reflective pattern formed on a substrate according to an embodiment of the present application;

[0087] FIG28 is a schematic diagram of a partial film layer structure of a display area corresponding to FIG27;

[0088] FIG29 is a schematic diagram of a film structure for forming a buffer layer and a second active layer pattern provided in an embodiment of the present application;

[0089] FIG30 is a schematic diagram of a film structure for forming a first gate insulating layer, a plurality of second gate signal lines and a light shielding pattern provided in an embodiment of the present application;

[0090] FIG31 is a schematic diagram of a partial film layer structure of a display area corresponding to FIG30;

[0091] FIG32 is a schematic diagram of a film structure for forming a first interlayer dielectric layer and a first active layer pattern according to an embodiment of the present application;

[0092] FIG33 is a schematic diagram of the film structure of the display area corresponding to FIG32;

[0093] FIG34 is a schematic diagram of a film structure for forming a second gate insulating layer and a first gate signal line provided in an embodiment of the present application;

[0094] FIG35 is a schematic diagram of a partial film layer structure of a display area corresponding to FIG34;

[0095] FIG36 is a schematic diagram of a film structure for forming a second interlayer dielectric layer and a plurality of data signal lines provided in an embodiment of the present application;

[0096] FIG37 is a schematic diagram of a partial film layer structure of a display area corresponding to FIG36;

[0097] FIG38 is a schematic diagram of a film structure for forming a first passivation layer and a transfer electrode provided in an embodiment of the present application;

[0098] FIG39 is a schematic diagram of a partial film layer structure of a display area corresponding to FIG38;

[0099] FIG40 is a schematic diagram of a film structure for forming a planar layer and a pixel electrode provided in an embodiment of the present application;

[0100] FIG41 is a schematic diagram of a partial film layer structure of a display area corresponding to FIG40;

[0101] FIG42 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0102] FIG43 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0103] Figure 44 is a schematic structural diagram of another display panel provided in an embodiment of the present application.

[0104] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0105] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0106] FIG1 is a schematic structural diagram of an array substrate 100 provided in an embodiment of the present application. FIG2 is a schematic cross-sectional structural diagram of the array substrate 100 shown in FIG1 along the A1-A2 position. FIG3 is a schematic diagram of a portion of the film layers of the array substrate 100 shown in FIG1. ​​Referring to FIG1, FIG2 and FIG3, the array substrate 100 may include: a substrate 101, a reflective pattern 102, a plurality of first gate signal lines 103, and a plurality of data signal lines 104. FIG3 shows three film layers in the array substrate 100 stacked and arranged in a direction away from the substrate 101. These three film layers include: a reflective pattern 102, a plurality of first gate signal lines (Gate1) 103, and a plurality of data signal lines (Data) 104.

[0107] The reflective pattern 102 may be located on the substrate 101 and may include a plurality of reflective portions 1021. An opening region may be defined between two adjacent reflective portions 1021, and the opening region may be a light-transmitting region. Multiple first gate signal lines 103 may be located on a side of the reflective pattern 102 facing away from the substrate 101, and multiple data signal lines 104 may be located on a side of the multiple first gate signal lines 103 facing away from the substrate 101.

[0108] In which, the orthographic projection of the first gate signal line 103 on the substrate 101 and the orthographic projection of the data signal line 104 on the substrate 101 may have a first overlapping area c1, the first overlapping area c1 may overlap with the orthographic projection of the reflective portion 1021 on the substrate 101, and at least one of the multiple first overlapping areas c1 may be located in the orthographic projection of the reflective portion 1021 on the substrate 101.

[0109] During the use of the array substrate 100, the backlight source in the display panel can be located on the side of the substrate 101 away from the reflective pattern 102. Since the first gate signal line 103 and the data signal line 104 are both film layers with low light transmittance, the first gate signal line 103 and the data signal line 104 will affect the transmittance of the display panel. Therefore, a reflective pattern 102 can be set on the side of the first gate signal line 103 and the data signal line 104 close to the substrate 101. The reflective pattern 102 can overlap with at least part of the first gate signal line 103 and the data signal line 104. When the light source illuminates When the light is incident on the reflective pattern 102, the reflective pattern 102 can reflect the light from the light source to other film layers (such as a backlight light source), and the other film layers can reflect the light from the light source reflected by the reflective pattern 102, and the other film layers reflect at least part of the light from the light source through the opening area between adjacent reflective portions 1021 toward the side of the reflective pattern 102 away from the substrate 101. Therefore, the reflective pattern 102 can improve the backlight utilization rate of the display panel including the array substrate 100, and reduce the influence of the first gate signal line 103 and the data signal line 104 with lower transmittance on the transmittance of the array substrate 100.

[0110] Moreover, since the first overlapping area c1 is located in the orthographic projection of the reflective portion 1021, the transmittance of the first gate signal line 103 and the data signal line 104 corresponding to the first overlapping area c1 is lower than the transmittance of the single-layer first gate signal line 103 and the transmittance of the single-layer data signal line 104, which can further reduce the influence of the reflective pattern 102 on the transmittance of the array substrate 100, and thus reduce the influence of the reflective pattern 102 on the aperture ratio of the display panel.

[0111] In summary, an embodiment of the present application provides an array substrate comprising a substrate, a reflective pattern, a plurality of first gate signal lines, and a plurality of data signal lines. The reflective pattern comprises a plurality of reflective portions, with an opening area between two adjacent reflective portions. Since the first gate signal lines and the data signal lines are both film layers with low transmittance, the reflective pattern can overlap at least partially with the first gate signal lines and the data signal lines. When light from a light source is irradiated onto the reflective pattern, the reflective pattern can reflect the light from the light source to other film layers, and the other film layers reflect at least part of the light from the light source toward the side of the reflective pattern away from the substrate. Therefore, the reflective pattern can improve the backlight utilization rate of the display panel including the array substrate, reduce the influence of the first gate signal lines and data signal lines with low transmittance on the transmittance of the array substrate, solve the problem of poor display effect of the display panel using the array substrate in the related art, and improve the display effect of the display panel.

[0112] FIG4 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application, and FIG5 is a schematic cross-sectional structural diagram of the array substrate 100 shown in FIG4 along the line B1-B2. Referring to FIG4 and FIG5 , the array substrate 100 may optionally further include a buffer layer 105 ("Buffer") located between the plurality of first gate signal lines 103 and the reflective pattern 102, a second active layer pattern 106, a first gate insulating layer 107 ("Gate Insulator 1"; abbreviated as GI1), a plurality of second gate signal lines 108 ("Gate2"), a first interlayer dielectric layer 109 ("Inter Layer Dielectric 1"; abbreviated as ILD1), and a first active layer pattern 110. The buffer layer 105, the second active layer pattern 106, the first gate insulating layer 107, the plurality of second gate signal lines 108, the first interlayer dielectric layer 109, and the first active layer pattern 110 are stacked and arranged in a direction away from the substrate 101.

[0113] The reflective pattern 102 may be located closer to the substrate 101 , that is, the reflective pattern 102 may be closer to the backlight source on the other side of the substrate 101 away from the reflective pattern 102 . This may improve the reflective efficiency of the reflective pattern 102 .

[0114] The array substrate 100 may have a plurality of thin film transistors, which may include low temperature polycrystalline silicon thin film transistors (LTPS) and / or oxide thin film transistors (O-TFT). The thin film transistor may be located on the substrate 101, and the thin film transistor may include an active layer, a source electrode and a drain electrode. The source electrode and the drain electrode may be located in the same layer and may be prepared using the same patterning process. It should be noted that in the embodiment of the present application, when using thin film transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged. The embodiment of the present application does not limit this.

[0115] In an embodiment of the present application, the array substrate 100 may include a display area and a non-display area. The display area and the non-display area are areas divided based on the layout of the display panel. The display area can be referred to as an active area (AA area) or a pixel circuit area. The non-display area is the area on the array substrate 100 other than the display area. The non-display area can be arranged around or encircle the display area. Figure 4 shows the division of the display area and the non-display area on the array substrate 100 in an embodiment of the present application. The non-display area may include areas such as a flexible circuit board pad area and an array gate drive area (GOA). The array gate drive area may have two sub-areas, which may be located on either side of the display area.

[0116] It should be noted that the enlarged structural diagram of a portion of the film layers on the array substrate 100 shown in FIG4 is only an enlarged structural diagram of the portion of the film layers in the display area, and does not show an enlarged structural diagram of the film layers in the non-display area. Furthermore, the area AA in the cross-sectional structural diagram shown in FIG5 corresponds to the cross-sectional structural diagram at the B11-B12 position shown in the enlarged structural diagram of the portion of the film layers in FIG4 . FIG5 does not show the overlapping position of the first gate signal line 103 and the data signal line 104 to more clearly illustrate the positional relationship of the film layers of the various structures on the array substrate 100.

[0117] Since the display area has high requirements for the uniformity of the characteristics of the thin film lens tube, the thin film transistors in the display area can be oxide thin film transistors. The mobility of the thin film transistors in the array gate drive area is required to be high, and the thin film transistors in the array gate drive area can be low-temperature polysilicon thin film transistors.

[0118] The second active layer pattern 106 in FIG5 may include multiple second active layers, which may be low-temperature polysilicon layers. The second active layers may serve as active layers for low-temperature polysilicon thin-film transistors located in the array gate drive region. The first active layer pattern 110 may include multiple first active layers, which may be metal oxide semiconductor layers. The first active layers may serve as active layers for oxide thin-film transistors located in the display region. The metal oxide semiconductor layer may include materials such as indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), or a single or multiple metal oxide composed of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), tungsten (W), zirconium (Zr), hafnium (Hf), and silicon (Si).

[0119] Optionally, a buffer layer 105 may be provided between the reflective pattern 102 and the second active layer pattern 106. The buffer layer 105 may include at least one of an inorganic insulating layer and an organic insulating layer. Exemplarily, the buffer layer 105 may be a composite film layer including an inorganic insulating layer and an organic insulating layer, and the organic insulating layer may be located on a side of the inorganic insulating layer away from the substrate 101. In this manner, the buffer layer 105 may protect the reflective pattern 102 via the inorganic insulating layer to prevent corrosion of the reflective pattern 102 by external moisture, which may damage the reflective pattern 102. The buffer layer 105 may also improve the flatness of the second active layer pattern 106 on the side of the buffer layer 105 away from the substrate 101 via the organic insulating layer, thereby improving the film quality of the second active layer pattern 106.

[0120] In an alternative embodiment, the material of the reflective pattern 102 may include at least one of molybdenum (Mo), aluminum, titanium (Ti), and silver (Ag), and the thickness of the reflective pattern 102 may range from 50 angstroms to 2000 angstroms. For example, the material of the reflective pattern 102 may be silver, so that the reflective pattern 102 has better reflective efficiency. Alternatively, the material of the reflective pattern 102 may include aluminum alloy. Because aluminum alloy materials can have good film quality and good reflective effect, the reflective pattern 102 can be configured as a single-layer structure to simplify the manufacturing process of the reflective pattern 102.

[0121] FIG6 is another schematic diagram of a cross-sectional structure of the array substrate 100 shown in FIG4 along the line B1-B2. Referring to FIG6 , in an alternative embodiment, the array substrate 100 may further include a light-shielding pattern 111 located between the light-reflecting pattern 102 and the first active layer pattern 110. The first active layer pattern 110 may include a plurality of first active layers, each of which includes a channel region. The orthographic projection of the channel region on the substrate 101 may be located within the orthographic projection of the light-shielding pattern 111 on the substrate 101. The orthographic projection of the light-shielding pattern 111 on the substrate 101 may overlap with the orthographic projection of the light-reflecting pattern 102 on the substrate 101.

[0122] The shading pattern 111 can be located on the side of the first active layer close to the substrate 101. The orthographic projection of the light-shielding pattern 111 on the substrate 101 overlaps with the orthographic projection of the first active layer on the substrate 101. The light-shielding pattern 111 can be used to block light (such as light emitted by the backlight source on the display panel) from entering the first active layer, thereby preventing the light from affecting the stability of the channel region of the first active layer; the light-shielding pattern 111 can also be used to shield the influence of the film layer on the side of the light-shielding pattern 111 away from the first active layer on the electrical properties of the first active layer under the action of the electric field.

[0123] Optionally, the light-shielding pattern 111 may be a co-layer structure with the second gate signal line 108. A second gate insulating layer 109 may be provided between the light-shielding pattern 111 and the first active layer, wherein the second gate insulating layer 109 may include at least one of an inorganic insulating layer and an organic insulating layer. Exemplarily, the first gate insulating layer 107 may be a composite film layer including an inorganic insulating layer and an organic insulating layer, and the organic insulating layer may be located on the side of the inorganic insulating layer away from the substrate 101. In this way, the second gate insulating layer 109 may protect the light-shielding pattern 111 through the inorganic insulating layer to prevent external moisture from corroding the light-shielding pattern 111 and causing damage to the light-shielding pattern 111. The second gate insulating layer 109 may also improve the flatness of the first active layer on the side of the first gate insulating layer 107 away from the substrate 101 through the organic insulating layer to improve the film quality of the first active layer.

[0124] FIG7 is a schematic diagram of another cross-sectional structure of the array substrate 100 shown in FIG4 along the line B1-B2. Referring to FIG7 , in an alternative embodiment, the array substrate 100 may further include a buffer layer 105, a second active layer pattern 106, a first gate insulating layer 107, a plurality of second gate signal lines 108, a first interlayer dielectric layer 109, and a first active layer pattern 110, located on the side of the plurality of first gate signal lines 103 closer to the substrate 101. The buffer layer 105, the second active layer pattern 106, the first gate insulating layer 107, the plurality of second gate signal lines 108, the first interlayer dielectric layer 109, and the first active layer pattern 110 may be stacked and arranged in a direction away from the substrate 101. The reflective pattern 102 may be co-layered with the plurality of second gate signal lines 108. In this manner, the second gate signal lines 108 and the reflective pattern 102 can be formed through a single patterning process, simplifying the manufacturing process of the array substrate 100.

[0125] Optionally, the material of the reflective pattern 102 includes at least one of molybdenum, aluminum, and titanium, and the thickness of the reflective pattern 102 may range from 1500 angstroms to 6000 angstroms. The thickness of the reflective pattern 102 may be the same as that of the second gate signal line 108. In this case, the preparation temperature of the reflective pattern 102 may be 25° C. to 300° C.

[0126] Please refer to Figure 1. In an optional embodiment, multiple reflective portions 1021 can be arranged in an array, the data signal line 104 can extend along the first direction f1, and multiple data signal lines 104 can be arranged along the second direction f2, the first gate signal line 103 can extend along the second direction f2, and multiple first gate signal lines 103 can be arranged along the first direction f1.

[0127] The plurality of reflective portions 1021 may satisfy the following formula: L1 = n × H; L2 = 3n × W;

[0128] Wherein, L1 is the distance between the centers of two adjacent reflective portions 1021 along the first direction f1, H is the shortest distance between the centers of two adjacent first gate signal lines 103 in the first direction f1, and n is a positive integer greater than or equal to 1. L2 is the distance between the centers of two adjacent reflective portions 1021 along the second direction f2, and W is the shortest distance between the centers of two adjacent data signal lines 104 in the second direction f2.

[0129] Multiple first overlapping regions c1 can be arranged in rows and columns. When n is 1, in the second direction f2, the arrangement density of the first overlapping regions c1 can be three times the arrangement density of the reflecting portion 1021, that is, in the second direction f2, every three first overlapping regions c1 can correspond to one reflecting portion 1021, and the 3rd first overlapping region c1, the 6th first overlapping region c1, the 9th first overlapping region c1, etc. of the multiple first overlapping regions c1 in a row of first overlapping regions c1 can be located in the orthographic projection of the corresponding reflecting portion 1021 on the substrate 101.

[0130] In the first direction f1 , the arrangement density of the first overlapping regions c1 may be the same as the arrangement density of the reflective portions 1021 , that is, in the first direction f1 , the plurality of first overlapping regions c1 and the plurality of reflective portions 1021 may correspond one to one.

[0131] Because the arrangement density of the multiple reflective portions 1021 in the reflective pattern is too high, the opening area between two adjacent reflective portions 1021 will be small. This makes it difficult for the light emitted by the backlight source and the light reflected by the reflective portions 1021 to pass through the opening area and exit to the side of the reflective portion 1021 facing away from the substrate 101, thereby resulting in a low light transmittance of the array substrate 100. In the embodiment of the present application, by arranging the multiple reflective portions 1021 according to the above formula, the arrangement density of the multiple reflective portions 1021 in the reflective pattern can be avoided to be too high, thereby improving the light transmittance of the array substrate 100.

[0132] FIG8 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG8 , in an exemplary embodiment, the value of n can range from 2 to 5. As shown in FIG8 , n can be 2. When n is 2, the size of the opening area between two adjacent reflective portions 1021 can be increased so that light emitted by the backlight source and light reflected by the reflective portion 1021 can be emitted from the opening area.

[0133] Referring to FIG. 8 , optionally, the plurality of first gate signal lines 103 and the plurality of data signal lines 104 satisfy the following formula: D1 / D2≥1.3;

[0134] Where D1 is the distance between two adjacent first gate signal lines 103, and D2 is the distance between two adjacent data signal lines 104. The extension direction of the first gate signal line 103 can be perpendicular to the extension direction of the data signal line 104. In this way, two adjacent first gate signal lines 103 and two adjacent data signal lines 104 can enclose a pixel area p1, and a pixel electrode 112 can be distributed within this pixel area p1. The pixel area p1 in the array substrate 100 in Figure 8 can be rectangular in shape. For example, the ratio of the long side to the short side of the pixel area p1 can be 3.

[0135] FIG9 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG9 , in an alternative embodiment, multiple reflective portions 1021 may be arranged in multiple rows, with the multiple rows of reflective portions 1021 arranged along a first direction f1. The multiple reflective portions 1021 in a row of reflective portions 1021 are arranged along a second direction f2. The first direction f1 is the extension direction of the data signal lines 104, and the second direction f2 is the extension direction of the first gate signal lines 103. The multiple reflective portions 1021 in two adjacent rows of reflective portions 1021 are arranged in a staggered manner. Because the light transmission of the reflective portions 1021 is lower than that of the opening areas, the staggered arrangement of the reflective portions 1021 in two adjacent rows of reflective portions 1021 can avoid poor light efficiency at the location of a particular row of reflective portions 1021, thereby preventing the appearance of alternating light and dark stripes on the display panel. In other words, it can reduce display defects caused by large differences in light transmittance between the regions corresponding to the two adjacent rows of reflective portions 1021, thereby improving the uniformity of light efficiency across the display panel.

[0136] FIG10 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG10 , in an alternative embodiment, a plurality of reflective portions 1021 may be arranged in multiple rows, with the multiple rows of reflective portions 1021 arranged along a first direction f1. The plurality of reflective portions 1021 in a row of reflective portions 1021 are arranged along a second direction f2. The first direction f1 is the extension direction of the data signal lines 104, and the second direction f2 is the extension direction of the first gate signal lines 103. A row of reflective portions 1021 may include multiple first reflective portions 10211 and multiple second reflective portions 10212, and the first reflective portions 10211 and the second reflective portions 10212 may be arranged alternately along the second direction f2. The first overlapping area c1 may have a first side and a second side opposite to each other along the first direction f1, the center of the orthographic projection of the first reflecting portion 10211 on the substrate 101 may be located on the first side of the center of the first overlapping area c1, and the center of the orthographic projection of the second reflecting portion 10212 on the substrate 101 may be located on the second side of the center of the first overlapping area c1.

[0137] In this way, the uniformity of the light from the light source transmitted in the opening areas on both sides of a row of reflective parts 1021 can be improved, the influence of the reflective parts 1021 arranged in multiple rows on the transmittance of the display panel at the position where a row of reflective parts 1021 is located can be reduced, and the uniformity of the light effect of the display panel can be improved.

[0138] Exemplarily, in the first direction f1, the distance between the centers of two adjacent first reflecting portions 10211 and the second reflecting portion 10212 ranges from 1 micrometer (um) to 5um. In this way, the reflecting portion 1021 can be avoided from being staggered with the first overlapping area c1, so as to reduce the influence of the reflecting portion 1021 on the transmittance of the array substrate 100.

[0139] FIG11 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG10 , in an optional embodiment, when the ratio of the long side to the short side of the pixel region p1 is less than 1.3, the multiple reflective portions 1021 and the multiple first overlapping regions c1 may correspond one to one. For example, the ratio of the long side to the short side of the pixel region p1 may be 1, i.e., the shape of the pixel region p1 may be square, and the multiple reflective portions 1021 in the array substrate 100 and the multiple first overlapping regions c1 may correspond one to one.

[0140] FIG12 is a schematic diagram of various shapes of the reflective portion 1021 provided in an embodiment of the present application. Referring to FIG12 , in an optional embodiment, the orthographic projection of the reflective portion 1021 on the substrate 101 may include at least one of a circle, an ellipse, a square, and a regular hexagon. When the orthographic projection of the reflective portion 1021 on the substrate 101 is an ellipse, the ratio of the length of the major axis to the length of the minor axis of the ellipse may be less than 3.

[0141] For example, referring to FIG11 , the difference between the width of the reflective portion 1021 in the first direction f1 and the width of the first overlapping region c1 in the first direction f1 can be in the range of 2 μm to 20 μm, and the difference between the width of the reflective portion 1021 in the second direction f2 and the width of the first overlapping region c1 in the second direction f2 can be in the range of 2 μm to 10 μm. Furthermore, the center of the orthographic projection of the reflective portion 1021 on the substrate 101 can coincide with the center of the first overlapping region c1 located in the orthographic projection of the reflective portion 1021 on the substrate 101.

[0142] FIG13 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG13 , in an alternative embodiment, the orthographic projection of the reflective portion 1021 on the substrate 101 may be rectangular. Multiple reflective portions 1021 may correspond one-to-one to multiple first overlapping regions c1, and the first overlapping regions c1 may be located within the orthographic projection of the corresponding reflective portion 1021 on the substrate 101. The difference between the width of the reflective portion 1021 in the first direction f1 and the width of the first overlapping regions c1 in the first direction f1 may be in a range of 1 to 8 microns. The difference between the width of the reflective portion 1021 in the second direction f2 and the width of the first overlapping regions c1 in the second direction f2 may be in a range of 1 to 6 microns. Furthermore, the center of the orthographic projection of the reflective portion 1021 on the substrate 101 may coincide with the center of the first overlapping regions c1 located within the orthographic projection of the reflective portion 1021 on the substrate 101.

[0143] Since the shape of the reflective portion 1021 and the shape of the first overlapping region c1 can be relatively similar when the orthographic projection of the reflective portion 1021 on the substrate 101 is rectangular, and the difference in size between the reflective portion 1021 and the first overlapping region c1 is relatively small, the effect of the reflective portion 1021 on the transmittance of the array substrate 100 can be reduced. By providing a plurality of reflective portions 1021 in a one-to-one correspondence with the plurality of first overlapping regions c1, the reflective size of the reflective pattern 102 including the plurality of reflective portions 1021 can be increased while the effect of the reflective portions 1021 on the transmittance of the array substrate 100 is relatively low, thereby improving the reflective efficiency of the reflective pattern 102.

[0144] FIG14 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG14 , in an optional embodiment, a plurality of reflective portions 1021 may be arranged in multiple rows, the multiple rows of reflective portions 1021 may be arranged along a first direction f1, and the plurality of reflective portions 1021 in a row of reflective portions 1021 may be arranged along a second direction f2. The reflective pattern 102 may further include a plurality of connecting portions 1022. The connecting portions 1022 may be located between and connected to adjacent two reflective portions 1021 in a row of reflective portions 1021. The orthographic projection of the connecting portions 1022 on the substrate may be located within the orthographic projection of the first gate signal line 103 on the substrate.

[0145] Two adjacent reflecting portions 1021 can be respectively located on both sides of the connecting portion 1022, wherein one end of the two reflecting portions 1021 is respectively connected to both sides of the connecting portion 1022. The reflecting portion 1021 and the connecting portion 1022 can be a same-layer structure and can be manufactured by a single patterning process. The multiple reflecting portions 1021 in a row of reflecting portions 1021 can be arranged along the second direction f2, and the two adjacent connecting portions 1022 can be located on both sides of the reflecting portion 1021 in the second direction f2. Because the connecting portion 1022 has a film layer with low light transmittance (such as the first gate signal line 103) on the side away from the substrate 101, and the first gate signal line 103 overlaps with the reflecting portion 1021. In this way, by providing a reflective portion 1021 and a connecting portion 1022 connecting the reflective portion 1021 in the reflective pattern 102, the reflective area of ​​the reflective pattern 102 can be increased without affecting the transmittance of the array substrate 100, thereby improving the backlight utilization rate of the display panel and further improving the aperture ratio of the display panel.

[0146] FIG15 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG15 , in an optional embodiment, the reflective portion 1021 may include a reflective portion main body 10213 and two first protruding structures 10214. The two first protruding structures 10214 may be located on either side of the reflective portion main body 10213 in the second direction f2, and an opening region may be provided between the first protruding structures 10214 of two adjacent reflective portions 1021 along the second direction f2. The orthographic projection of the first protruding structure 10214 on the substrate may be located within the orthographic projection of the first gate signal line 103 on the substrate. The reflective portion main body 10213 and the first protruding structures 10214 may be co-layer structures and may be manufactured through a single patterning process.

[0147] The first protruding structures 10214 located on both sides of the reflective portion main body 10213 can be used to increase the reflective area of ​​the reflective portion 1021. Because the reflective portion main body 10213 and the first protruding structures 10214 have a film layer with low light transmittance (e.g., the first gate signal line 103) on the side away from the substrate 101, and the first gate signal line 103 overlaps with the reflective portion main body 10213 and the first protruding structures 10214, the reflective portion 1021 is provided with the reflective portion main body 10213 and the first protruding structures 10214. Thus, the reflective area of ​​the reflective portion 1021 can be increased without affecting the transmittance of the array substrate 100, thereby improving the backlight utilization of the display panel and, in turn, the aperture ratio of the display panel. Furthermore, an opening area is provided between the first protruding structures 10214 of two adjacent reflective portions 1021 along the second direction f2 , which can increase the light-transmitting area between adjacent reflective portions 1021 and reduce the influence of the reflective portions 1021 on the transmittance of the array substrate 100 .

[0148] FIG16 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Referring to FIG16 , in an optional embodiment, a plurality of reflective portions 1021 may be arranged in multiple rows, with the multiple rows of reflective portions 1021 arranged along a first direction f1, and the multiple reflective portions 1021 in a row of reflective portions 1021 arranged along a second direction f2. A row of reflective portions 1021 may include multiple reflective portion units 102a, and a reflective portion unit 102a may include multiple reflective portions 1021. Of two adjacent reflective portion units 102a, the reflective portion 1021 in one reflective portion unit 102a has a first length in the first direction f1, and the reflective portion 1021 in the other reflective portion unit 102a has a second length in the first direction f1, where the first length may be greater than the second length.

[0149] Because the light transmission effect at the reflective portion 1021 is poorer than that at the opening area, by setting the lengths of the reflective portions 1021 in two adjacent reflective portion units 102a to be different, the sizes of the opening areas on both sides of the reflective portions 1021 in the two reflective portion units 102a can be made different. This can improve the problem of obvious abnormal display on the display panel (e.g., the appearance of light and dark stripes) caused by the same length of multiple reflective portions 1021 in a row of reflective portions 1021, reduce the impact of the reflective portions 1021 on the display effect of the display panel, and improve the uniformity of the light effect of the display panel. For example, a reflective portion unit 102a can include four reflective portions 1021, or a reflective portion unit 102a can include three reflective portions 1021, five reflective portions 1021, or more reflective portions 1021, which is not limited in this embodiment of the present application.

[0150] FIG17 is a schematic diagram of the structure of another array substrate 100 provided in an embodiment of the present application, and FIG18 is a schematic diagram of the structure of another array substrate 100 provided in an embodiment of the present application. Referring to FIG17 and FIG18 , in an alternative embodiment, the plurality of reflective portions 1021 include a plurality of reflective portion groups 102b, each reflective portion group 102b including two rows of reflective portions 1021. The plurality of reflective portion groups 102b are arranged along a first direction f1, the two rows of reflective portions 1021 in a reflective portion group 102b are arranged along the first direction f1, and the plurality of reflective portions 1021 in a row of reflective portions 1021 are arranged along a second direction f2. The first direction f1 is the direction in which the data signal lines 104 extend, and the second direction f2 is the direction in which the first gate signal lines 103 extend. The orthographic projection of the plurality of reflective portions 1021 in a row of reflective portions 1021 in a reflective portion group 102b onto the substrate 101 is circular, while the orthographic projection of the plurality of reflective portions 1021 in another row of reflective portions 1021 onto the substrate 101 is rectangular.

[0151] Since the light transmission effect at the reflective portion 1021 is poorer than that at the opening area, the shapes of two adjacent rows of reflective portions 1021 in a reflective portion group 102b can be set to be different to reduce the regularity of the arrangement of the multiple reflective portions 1021 in the reflective pattern 102, thereby improving the uniformity of the light effect of the display panel.

[0152] For example, the aperture ratio of the display panel using the array substrate 100 in the embodiment of the present application may be in the range of 20% to 45%.

[0153] Figure 19 is a structural schematic diagram of another array substrate 100 provided in an embodiment of the present application. Please refer to Figure 19. In an exemplary embodiment, the multiple reflective portions 1021 in a row of reflective portions 1021 may include reflective portions 1021 that are circular when projected onto the substrate 101, or may include reflective portions 1021 that are rectangular when projected onto the substrate 101, thereby increasing the flexibility of the combination of the reflective portions 1021 in the reflective pattern 102.

[0154] Figure 20 is a schematic structural diagram of another array substrate 100 provided in an embodiment of the present application. Figure 21 is a schematic cross-sectional structural diagram of the array substrate 100 shown in Figure 20 along the C1-C2 position. Figure 22 is a schematic partial film layer diagram of a portion 20A of the array substrate 100 shown in Figure 20. Please refer to Figures 20, 21, and 22. Optionally, the array substrate 100 may further include a pixel electrode 112 located on a side of the first active layer facing away from the substrate 101. The material of the pixel electrode 112 may include a light-transmitting conductive material, which can increase the light transmittance of the array substrate 100 and, in turn, increase the aperture ratio of the display panel including the array substrate 100. Exemplarily, the material of the pixel electrode 112 includes a light-transmitting conductive material, and the light-transmitting conductive material may include indium tin oxide (ITO).

[0155] The first active layer may include a source contact portion, a drain contact portion, and a middle portion located between the source contact portion and the drain contact portion. The dimensions of the source contact portion and the drain contact portion in the second direction f2 are larger than the dimension of the middle portion in the second direction f2. The orthographic projection of the first active layer on the substrate 101 may have a shape that is wider at both ends and narrower in the middle, so as to facilitate electrical connection between the two ends of the first active layer and other structures on the array substrate 100.

[0156] Optionally, the array substrate 100 may further include a transfer electrode 113. The transfer electrode 113 may be located on a side of the first gate signal line 103 away from the substrate 101. One end of the transfer electrode 113 may be electrically connected to the first drain electrode, and the other end of the transfer electrode 113 may be electrically connected to the pixel electrode 112. The material of the transfer electrode 113 may include a light-transmitting conductive material, which may increase the light transmittance of the array substrate 100 and, in turn, increase the aperture ratio of a display panel including the array substrate 100. Exemplarily, the light-transmitting conductive material of the transfer electrode 113 may include indium tin oxide (ITO).

[0157] As shown in FIG7 , the extension direction of the first active layer may form an acute angle with the extension direction of the data line, so that one end of the first active layer can be electrically connected to the data line, and the other end of the first active layer can be electrically connected to the switching electrode 113 .

[0158] Optionally, the array substrate 100 may further include a common electrode pattern 114, which may be located on a side of the pixel electrode 112 away from the substrate 101. The pixel electrode 112 and the common electrode pattern 114 may jointly drive liquid crystals in the liquid crystal layer of the display panel.

[0159] The common electrode pattern 114 may include a first electrode portion, the material of which may include metal, and the first electrode portion includes a plurality of first strip electrodes m1. Because the pixel structures in high pixel density (PI) display panels are small in size and the spacing between adjacent pixel structures is close, the light emitted by each pixel is more likely to exhibit cross-color, which in turn affects the display quality of the display panel. The first electrode portion can prevent light from the area containing pixel structures of different colors from being emitted from the area containing adjacent pixel structures, and can be used to improve the cross-color problem of the display panel.

[0160] The common electrode pattern 114 may also include a transparent electrode layer m2, and the first electrode portion may be located on a side of the transparent electrode layer m2 that is close to the substrate 101. The transparent electrode layer m2 may be a whole-layer structure, and the common electrode pattern 114 may be a slit electrode by stacking the whole-layer transparent electrode layer m2 and the multiple first strip electrodes m1 of the first electrode portion. By setting slits in different directions and changing the pattern of the slit electrodes, the liquid crystals on the display panel can be arranged in multiple directions in the horizontal direction of the pixel area, thereby improving the uniformity of the brightness of the image displayed by the display panel and reducing the color cast problem of the display panel. In other words, a multi-dimensional electric field can be formed by the electric field generated by the slit electrodes in the same plane and the electric field generated between the entire transparent electrode layer, so that all liquid crystals between the slit electrodes and directly above the slit electrodes can rotate, which can improve the working efficiency of the liquid crystals in the display panel and increase the transmittance of the liquid crystals in the display panel.

[0161] Alternatively, a plurality of openings may be formed in the transparent electrode layer m2 to form a slit electrode, which is not limited in this embodiment of the present application.

[0162] In addition, the transparent electrode layer can protect the first electrode portion, preventing external moisture from corroding the first electrode portion and causing damage to the first electrode portion. The material of the transparent electrode layer can include indium tin oxide.

[0163] Optionally, referring to Figure 21, the array substrate 100 may further include a second source electrode 115 and a second drain electrode 116 located on the side of the second active layer facing away from the substrate 101. The material of the second source electrode 115 and the second drain electrode 116 may include metal, and the second source electrode 115 and the second drain electrode 116 may be electrically connected to the second active layer. This embodiment of the present application will not be elaborated on this.

[0164] Figure 23 is another schematic diagram of the cross-sectional structure of the array substrate 100 shown in Figure 20 along the C1-C2 position. Please refer to Figure 23. The array substrate 100 may also include a light-blocking pattern 117 located on the side of the second active layer close to the substrate 101. The second active layer has a channel region, and the orthographic projection of the channel region on the substrate 101 may be located in the orthographic projection of the light-blocking pattern 117 on the substrate 101. The light-blocking pattern 117 can be used to block light (such as light emitted by the backlight source on the display panel) from being incident on the second active layer, thereby preventing the light from affecting the stability of the channel region of the second active layer. The light-blocking pattern 117 may also be a co-layer structure with the reflective pattern 102. The difference between the width of the orthographic projection of the light-blocking pattern 117 on the substrate 101 and the width of the second gate signal line 108 ranges from 1 micron to 5 microns.

[0165] Figure 24 is another schematic diagram of the cross-sectional structure of the array substrate 100 shown in Figure 20 along the C1-C2 position. Please refer to Figure 24. The light-blocking pattern 117 can also be electrically connected to the second gate signal line 108, so that the thin film transistor in the GOA area can include a dual-gate structure thin film transistor. In this way, the light-blocking pattern 117 can not only have a light-shielding effect, but also improve the output capacity of the thin film transistor in the GOA area.

[0166] The array substrate 100 provided in the embodiment of the present application can be applied to small-sized mobile devices (Mobile), notebook computers (NB), tablet computers, small and medium-sized monitors (Monitor, MNT), medium and large-sized televisions (Television, TV) and medium and large-sized MNT products.

[0167] The array substrate 100 provided in the embodiment of the present application can be used in the display field or the chip field. The display field can be a liquid crystal display (LCD) display panel, an organic light-emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode display panel (Micro LED) and a sensing field.

[0168] In summary, an embodiment of the present application provides an array substrate comprising a substrate, a reflective pattern, a plurality of first gate signal lines, and a plurality of data signal lines. The reflective pattern comprises a plurality of reflective portions, with an opening area between two adjacent reflective portions. Since the first gate signal lines and the data signal lines are both film layers with low transmittance, the reflective pattern can overlap at least partially with the first gate signal lines and the data signal lines. When light from a light source is irradiated onto the reflective pattern, the reflective pattern can reflect the light from the light source to other film layers, and the other film layers reflect at least part of the light from the light source toward the side of the reflective pattern away from the substrate. Therefore, the reflective pattern can improve the backlight utilization rate of the display panel including the array substrate, reduce the influence of the first gate signal lines and data signal lines with low transmittance on the transmittance of the array substrate, solve the problem of poor display effect of the display panel using the array substrate in the related art, and improve the display effect of the display panel.

[0169] FIG25 is a flow chart of a method for manufacturing an array substrate 100 provided in an embodiment of the present application. The method can be used with the array substrate 100 provided in the above embodiment, for example, to manufacture the array substrate 100 in any of the above embodiments. Referring to FIG25 , the method may include:

[0170] Step 201: Obtain a substrate.

[0171] Step 202: forming a reflective pattern on a substrate, wherein the reflective pattern includes a plurality of reflective portions, and an opening area is provided between two adjacent reflective portions.

[0172] Step 203: forming a plurality of first gate signal lines on the substrate having the reflective pattern formed thereon.

[0173] Step 204 : forming a plurality of first data signal lines on the substrate on which the plurality of first gate signal lines are formed.

[0174] The orthographic projection of the first gate signal line on the substrate and the orthographic projection of the data signal line on the substrate have a first overlapping area, and the orthographic projection of the reflective portion on the substrate overlaps with the first overlapping area.

[0175] In summary, an embodiment of the present application provides a method for manufacturing an array substrate, wherein the array substrate includes a substrate, a reflective pattern, and an array substrate having a plurality of first gate signal lines and a plurality of data signal lines. The reflective pattern includes a plurality of reflective portions, with an opening area between two adjacent reflective portions. Since the first gate signal lines and the data signal lines are both film layers with low light transmittance, the reflective pattern can overlap at least partially with the first gate signal lines and the data signal lines. When light from a light source is irradiated on the reflective pattern, the reflective pattern can reflect the light from the light source to other film layers, and the other film layers reflect at least part of the light from the light source toward the side of the reflective pattern away from the substrate. Therefore, the reflective pattern can improve the backlight utilization rate of a display panel including the array substrate, reduce the influence of the first gate signal lines and data signal lines with low light transmittance on the transmittance of the array substrate, solve the problem of poor display effect of the display panel using the array substrate in the related art, and improve the display effect of the display panel.

[0176] FIG26 is a flow chart of another method for manufacturing a substrate provided in an embodiment of the present application. The method can be used to prepare the substrate provided in the above embodiment, for example, the substrate shown in FIG21. Referring to FIG26, the method may include:

[0177] Step 301: Obtain a substrate.

[0178] The substrate 101 may be a flexible substrate, which may be made of a flexible material (eg, polyimide PI material). Alternatively, the substrate 101 may be a glass substrate.

[0179] Step 302: forming a reflective pattern on the substrate.

[0180] The reflective pattern 102 may include a plurality of reflective portions 1021, and an opening may be provided between two adjacent reflective portions 1021. The reflective pattern 102 may be made of at least one of molybdenum, aluminum, titanium, and silver, and may have a thickness ranging from 50 angstroms to 2000 angstroms.

[0181] For example, please refer to Figures 27 and 28. Figure 27 is a schematic diagram of the film structure of a reflective pattern 102 formed on a substrate 101 according to an embodiment of the present application, and Figure 28 is a schematic diagram of the film structure of a portion of the display area corresponding to Figure 27. A metal film can be formed on one side of the substrate 101 by any of a variety of methods, such as deposition, coating, and sputtering. Then, a patterning process (including exposure and etching processes) is performed on the metal film to form the reflective pattern 102. The etching process may include a dry etching process, and the slope angle of the formed reflective pattern 102 can range from 45° to 90°.

[0182] Step 303 : forming a buffer layer and a second active layer pattern in sequence on the side of the reflective pattern facing away from the substrate.

[0183] The material of the buffer layer 105 may include an organic insulating material or an inorganic insulating material. The material of the second active layer pattern 106 may be low temperature polysilicon. The thickness range of the second active layer pattern 106 may be The second active layer pattern 106 may be located in a GOA region of the array substrate 100 .

[0184] For example, please refer to Figure 29, which is a schematic diagram of a film structure for forming a buffer layer 105 and a second active layer pattern 106, provided in an embodiment of the present application. The buffer layer 105 can be formed on the side of the reflective pattern 102 facing away from the substrate 101 by any of a variety of methods, such as deposition, coating, or sputtering. The second active layer thin film can also be formed on the side of the buffer layer 105 facing away from the substrate 101 by any of a variety of methods, such as deposition, coating, or sputtering. Subsequently, a single patterning process can be performed on this second active layer thin film to form a plurality of second active layer patterns 106.

[0185] Step 304 : forming a first gate insulating layer, a plurality of second gate signal lines and a light shielding pattern in sequence on a side of the second active layer pattern facing away from the substrate.

[0186] Optionally, the material of the first gate insulating layer 107 may include silicon oxide. This prevents the second active layer pattern 106 from being directly conductive. The material of the second gate signal line 108 may be a metal material. For example, the material of the second gate signal line 108 may be at least one of copper, titanium, molybdenum, and titanium. The second gate signal line 108 may have a stacked structure of titanium / aluminum / titanium. The light shielding pattern 111 may be co-layered with the second gate signal line 108 and made of the same material.

[0187] For example, please refer to Figures 30 and 31. Figure 30 is a schematic diagram of a film structure for forming a first gate insulating layer 107, a plurality of second gate signal lines 108, and a light-shielding pattern 111, according to an embodiment of the present application. Figure 31 is a schematic diagram of a portion of the film structure of the display area corresponding to Figure 30. The first gate insulating layer 107 can be formed on the side of the second active layer pattern 106 facing away from the substrate 101 by any of a variety of methods, such as deposition, coating, and sputtering.

[0188] A metal film may be formed on the first gate insulating layer 107 and then patterned once to form a plurality of second gate signal lines 108 and a light shielding pattern 111. Here, the plurality of second gate signal lines 108 may be insulated from the second active layer pattern 106 by the first gate insulating layer 107.

[0189] Step 305 : forming a first interlayer dielectric layer and a first active layer pattern in sequence on a side of the second gate signal line and the light shielding pattern facing away from the substrate.

[0190] The material of the first interlayer dielectric layer 109 may include silicon oxide. The material of the first active layer pattern 110 may be a transparent oxide semiconductor material. For example, the material of the first active layer pattern 110 may be IGZO.

[0191] For example, please refer to Figures 32 and 33. Figure 32 is a schematic diagram of a film layer structure for forming a first interlayer dielectric layer 109 and a first active layer pattern 110 provided in an embodiment of the present application, and Figure 33 is a schematic diagram of the film layer structure of the display area corresponding to Figure 32.

[0192] The first interlayer dielectric layer 109 can be formed on the side of the second gate signal line 108 and the light shielding pattern 111 facing away from the substrate 101 by any of various methods such as deposition, coating, and sputtering. A semiconductor thin film can also be formed on the side of the first interlayer dielectric layer 109 facing away from the substrate 101 by any of various methods such as deposition, coating, and sputtering. Then, a single patterning process can be performed on the semiconductor thin film to form a plurality of first active layer patterns 110.

[0193] Step 306 : forming a second gate insulating layer and a plurality of first gate signal lines in sequence on a side of the first active layer pattern facing away from the substrate.

[0194] Optionally, the material of the second gate insulating layer 118 may include silicon oxide. The material of the first gate signal line 103 may be a metal material. For example, the material of the first gate signal line 103 may be at least one of copper, titanium, molybdenum, and the first gate signal line 103 may be a stacked structure of titanium / aluminum / titanium. The thickness of the first gate signal line 103 may range from

[0195] For example, please refer to Figures 34 and 35. Figure 34 is a schematic diagram of a film structure for forming a second gate insulating layer 118 and a first gate signal line 103 according to an embodiment of the present application, and Figure 35 is a schematic diagram of a portion of the film structure of the display area corresponding to Figure 34. The second gate insulating layer 118 can be formed on the side of the first active layer pattern 110 facing away from the substrate 101 by any of a variety of methods, such as deposition, coating, and sputtering.

[0196] A metal film may be formed on the second gate insulating layer 118 and then patterned once to form a plurality of first gate signal lines 103. Here, the plurality of first gate signal lines 103 may be insulated from the first active layer pattern 110 by the second gate insulating layer 118.

[0197] Step 307 : forming a second interlayer dielectric layer and a plurality of data signal lines in sequence on a side of the plurality of first gate signal lines facing away from the substrate.

[0198] The material of the second interlayer dielectric layer 119 (English: inter layer dielectric 2; abbreviated: ILD2) may include silicon oxide. The material of the data signal line 104 may be a metal material. For example, the material of the data signal line 104 may be a metal material such as copper, titanium, molybdenum or alloy. The data signal line 104 may be a stacked structure of titanium / aluminum / titanium with a thickness range of

[0199] For example, please refer to Figures 36 and 37. Figure 36 is a schematic diagram of a film layer structure for forming a second interlayer dielectric layer 119 and multiple data signal lines 104 provided in an embodiment of the present application, and Figure 37 is a schematic diagram of a partial film layer structure of the display area corresponding to Figure 36.

[0200] The second interlayer dielectric layer 119 can be formed on the side of the first gate signal line 103 and the light shielding pattern 111 facing away from the substrate 101 by any of various methods, such as deposition, coating, and sputtering. Furthermore, a metal thin film can be formed on the second interlayer dielectric layer 119 by any of various methods, such as deposition, coating, and sputtering. Then, a single patterning process can be performed on the metal thin film to form a plurality of data signal lines 104.

[0201] The plurality of data signal lines 104 may include a data signal line 104 located in the AA region. The data signal line 104 located in the AA region may be electrically connected to the first active layer through a via hole penetrating the second interlayer dielectric layer 119 and the second gate insulating layer 118 .

[0202] The orthographic projection of the data signal line 104 located in the AA area on the substrate 101 and the orthographic projection of the first gate signal line 103 on the substrate 101 may have a first overlapping area c1, and the first overlapping area c1 may overlap with the orthographic projection of the reflective portion 1021 on the substrate 101. At least one of the multiple first overlapping areas c1 may be located in the orthographic projection of the reflective portion 1021 on the substrate 101.

[0203] At the same time, a second source 115 and a second drain 116 can be formed in the GOA region of the array substrate 100. The second source 115 and the second drain 116 located in the GOA region can be electrically connected to the second active layer through vias passing through the second interlayer dielectric layer 119, the second gate insulating layer 118, the first interlayer dielectric layer 109 and the first gate insulating layer 107.

[0204] Step 308 : forming a first passivation layer and a transfer electrode in sequence on a side of the plurality of data signal lines facing away from the substrate.

[0205] Optionally, the first passivation layer 120 (PVX1) can be made of an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride. The material of the transfer electrode 113 can be a transparent conductive material. For example, the material of the transfer electrode 113 can be indium tin oxide, which can increase the light transmittance of the array substrate 100 and, in turn, the aperture ratio of the display panel including the array substrate 100.

[0206] For example, please refer to Figures 38 and 39. Figure 38 is a schematic diagram of a film structure for forming a first passivation layer 120 and a transfer electrode 113 according to an embodiment of the present application, and Figure 39 is a schematic diagram of a portion of the film structure of the display area corresponding to Figure 38. The first passivation layer 120 can be formed on the side of the multiple data signal lines 104 facing away from the substrate 101 by any of a variety of methods, such as deposition, coating, and sputtering. A transparent conductive film can also be formed on the side of the first passivation layer 120 facing away from the substrate 101 by any of a variety of methods, such as deposition, coating, and sputtering. Then, a single patterning process is performed on the transparent conductive film to form multiple transfer electrodes 113. Each transfer electrode 113 can be electrically connected to the first active layer via a via hole that penetrates the first passivation layer 120, the second interlayer dielectric layer 119, and the second gate insulation layer.

[0207] Step 309 : forming a planar layer and a pixel electrode in sequence on the side of the transfer electrode facing away from the substrate.

[0208] Optionally, the material of the planarization layer 120 (PLN) may be an organic material such as resin. The material of the pixel electrode 112 may be a transparent conductive material. For example, the material of the pixel electrode 112 may be indium tin oxide.

[0209] For example, please refer to Figures 40 and 41. Figure 40 is a schematic diagram of a film structure for forming a planar layer 120 and a pixel electrode 112 provided in an embodiment of the present application, and Figure 41 is a schematic diagram of a partial film structure of a display area corresponding to Figure 40. The planar layer 120 can be formed on the side of the transfer electrode 113 facing away from the substrate 101 by any of a variety of methods such as deposition, coating, and sputtering, and a transparent conductive film can be formed on the side of the planar layer 120 facing away from the substrate 101 by any of a variety of methods such as deposition, coating, and sputtering. Then, a single patterning process is performed on the transparent conductive film to form a plurality of pixel electrodes 112. Each pixel electrode 112 can be electrically connected to the transfer electrode 113 through a via hole penetrating the planar layer 120.

[0210] Step 310 : forming a second passivation layer and a common electrode pattern in sequence on a side of the plurality of pixel electrodes facing away from the substrate.

[0211] Optionally, the second passivation layer 122 (English: passivation layer 2; abbreviated: PVX2) can be made of inorganic materials such as silicon nitride, silicon oxide or silicon oxynitride. The common electrode pattern 114 can include a transparent electrode layer having an opening, and the material of the transparent electrode layer can include indium tin oxide.

[0212] For example, please refer to Figures 20 and 21. A second passivation layer 122 and a transparent conductive film can be formed in sequence on the side of the multiple pixel electrodes 112 facing away from the substrate 101 by any of a variety of methods such as deposition, coating, sputtering, etc., and then, a composition process is performed on the transparent conductive film to form a transparent electrode layer.

[0213] It should be noted that the one-time patterning process in the above embodiment may include: photoresist coating, exposure, development and photoresist stripping.

[0214] In summary, an embodiment of the present application provides a method for manufacturing an array substrate, wherein the array substrate includes a substrate, a reflective pattern, and an array substrate having a plurality of first gate signal lines and a plurality of data signal lines. The reflective pattern includes a plurality of reflective portions, with an opening area between two adjacent reflective portions. Since the first gate signal lines and the data signal lines are both film layers with low light transmittance, the reflective pattern can overlap at least partially with the first gate signal lines and the data signal lines. When light from a light source is irradiated on the reflective pattern, the reflective pattern can reflect the light from the light source to other film layers, and the other film layers reflect at least part of the light from the light source toward the side of the reflective pattern away from the substrate. Therefore, the reflective pattern can improve the backlight utilization rate of a display panel including the array substrate, reduce the influence of the first gate signal lines and data signal lines with low light transmittance on the transmittance of the array substrate, solve the problem of poor display effect of the display panel using the array substrate in the related art, and improve the display effect of the display panel.

[0215] An embodiment of the present application further provides a display panel, which includes: an array substrate 100 and a color filter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate 100 and the color filter substrate. The array substrate 100 is the array substrate 100 in any of the above embodiments.

[0216] FIG42 is a schematic structural diagram of a display panel provided in an embodiment of the present application. Referring to FIG42 , the display panel may optionally further include multiple supporting portions 21 positioned between the array substrate 100 and the color filter substrate 22. The orthographic projection of at least one of the multiple supporting portions 21 on the substrate 101 is located within the orthographic projection of the reflective portion 1021 on the substrate 101. The supporting portion 21 can serve as a barrier, maintaining a uniform gap between the array substrate 100 and the color filter substrate 22. The orthographic projection of the supporting portion 21 on the substrate 101 is smaller than the orthographic projection of the reflective portion 1021 on the substrate 101 by 1 to 5 μm. Thus, by stacking the reflective portion 1021 and the supporting portion 21, the effect of the reflective pattern 102 on the light transmittance of the array substrate 100 can be reduced, thereby reducing the effect of the reflective pattern 102 on the aperture ratio of the display panel.

[0217] FIG43 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application, and FIG44 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG43 and FIG44 , optionally, the color filter substrate 22 includes a plurality of red (R) color resist blocks 222, a plurality of blue (B) color resist blocks 223, and a plurality of green (G) color resist blocks 224. The orthographic projection of the reflective portion 1021 on the substrate 101 overlaps with the orthographic projection of at least one of the plurality of red color resist blocks 222 on the substrate 101. The orthographic projection of the reflective portion 1021 on the substrate 101 overlaps with the orthographic projection of at least one of the plurality of blue color resist blocks 223 on the substrate 101. The orthographic projection of the reflective portion 1021 on the substrate 101 is staggered from the orthographic projection of the green color resist block 224 on the substrate 101. Since the transmittance of green light in the display panel is relatively low, the orthographic projection of the reflective portion 1021 on the substrate 101 can be staggered with the orthographic projection of the green color block 224 on the substrate 101 to reduce the impact of the reflective portion 1021 on the overall light extraction effect of the display panel. It will be understood that FIG44 shows the first gate signal line 103 and the data signal line 104 in the array substrate to more clearly illustrate the pixel area on the display panel.

[0218] Please refer to Figure 44. The two adjacent rows of pixel areas p1 in the display panel shown in Figure 44 can be staggered. The arrangement rules of the multiple reflective parts 1021 in the first direction f1 and the second direction f2 can refer to the arrangement method of the multiple reflective parts 1021 shown in Figure 1.

[0219] In summary, an embodiment of the present application provides a display panel comprising an array substrate and a color filter substrate, wherein the array substrate comprises a substrate, a reflective pattern, an array substrate comprising a plurality of first gate signal lines and a plurality of data signal lines. The reflective pattern comprises a plurality of reflective portions, with an opening area between two adjacent reflective portions. Since the first gate signal lines and the data signal lines are both film layers with low light transmittance, the reflective pattern can overlap at least partially with the first gate signal lines and the data signal lines. When light from a light source is irradiated onto the reflective pattern, the reflective pattern can reflect the light from the light source to other film layers, which in turn reflect at least part of the light from the light source toward the side of the reflective pattern away from the substrate. Therefore, the reflective pattern can improve the backlight utilization rate of the display panel comprising the array substrate, reduce the influence of the first gate signal lines and data signal lines with low light transmittance on the transmittance of the array substrate, solve the problem of poor display effect of the display panel using the array substrate in the related art, and improve the display effect of the display panel.

[0220] In this application, the term "and / or" simply describes an association between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0221] In this application, the term "at least one of A and B" simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. Similarly, "at least one of A, B, and C" means that seven possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, and A, B, and C exist simultaneously. Similarly, "at least one of A, B, C, and D" means that fifteen possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, D exists alone, A and B exist simultaneously, A and C exist simultaneously, A and D exist simultaneously, C and B exist simultaneously, D and B exist simultaneously, C and D exist simultaneously, C and D exist simultaneously, A, B, and C exist simultaneously, A, B, and D exist simultaneously, A, C, and D exist simultaneously, B, C, and D exist simultaneously, and A, B, C, and D exist simultaneously.

[0222] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0223] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless expressly limited otherwise.

[0224] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A reflective pattern located on the substrate, the reflective pattern comprising a plurality of reflective portions, and an opening area is provided between two adjacent reflective portions; a plurality of first gate signal lines located on a side of the reflective pattern away from the substrate; a plurality of data signal lines located on a side of the plurality of first gate signal lines away from the substrate; The orthographic projection of the first gate signal line on the substrate and the orthographic projection of the data signal line on the substrate have a first overlapping region, and at least one of the plurality of first overlapping regions is located in the orthographic projection of the reflective portion on the substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a buffer layer, a second active layer pattern, a first gate insulating layer, a plurality of second gate signal lines, a first interlayer dielectric layer and a first active layer pattern located between the plurality of first gate signal lines and the reflective pattern; The buffer layer, the second active layer pattern, the first gate insulating layer, the plurality of second gate signal lines, the first interlayer dielectric layer and the first active layer pattern are stacked and arranged in a direction away from the substrate.

3. The array substrate according to claim 2, characterized in that: The array substrate further comprises a light shielding pattern located between the light reflecting pattern and the first active layer pattern; The first active layer pattern includes a plurality of first active layers, the first active layer has a channel region, and an orthographic projection of the channel region on the substrate is located in an orthographic projection of the light shielding pattern on the substrate; An orthographic projection of the light-shielding pattern on the substrate overlaps with an orthographic projection of the light-reflecting pattern on the substrate.

4. The array substrate according to claim 2 or 3, characterized in that: The material of the reflective pattern includes at least one of molybdenum, aluminum, titanium and silver, and the thickness of the reflective pattern ranges from 50 angstroms to 2000 angstroms.

5. The array substrate according to claim 1, characterized in that: The array substrate further comprises a buffer layer located on a side of the plurality of first gate signal lines close to the substrate, a second active layer pattern, a first gate insulating layer, a plurality of second gate signal lines, a first interlayer dielectric layer and a first active layer pattern; The buffer layer, the second active layer pattern, the first gate insulating layer, the plurality of second gate signal lines, the first interlayer dielectric layer and the first active layer pattern are stacked and arranged in a direction away from the substrate; The reflective pattern and the plurality of second gate signal lines are in the same layer structure.

6. The array substrate according to claim 5, characterized in that: The material of the reflective pattern includes at least one of molybdenum, aluminum and titanium, and the thickness of the reflective pattern ranges from 1500 angstroms to 6000 angstroms.

7. The array substrate according to claim 1, characterized in that: The plurality of reflective portions are arranged in an array, the data signal lines extend along a first direction, and the plurality of data signal lines are arranged along a second direction, the first gate signal lines extend along the second direction, and the plurality of first gate signal lines are arranged along the first direction; The multiple reflection parts satisfy the following formula: L1 = n × H; L2=3n×W; Wherein, L1 is the distance between the centers of two adjacent reflection parts along the first direction, H is the shortest distance between the centers of two adjacent first gate signal lines in the first direction, and n is a positive integer greater than or equal to 1; The L2 is the distance between the centers of two adjacent reflection parts along the second direction, and the W is the shortest distance between the centers of two adjacent data signal lines in the second direction.

8. The array substrate according to claim 7, characterized in that: The plurality of first gate signal lines and the plurality of data signal lines satisfy the following formula: D1 / D2≥1.3; Wherein, the D1 is the distance between two adjacent first gate signal lines, and the D2 is the distance between two adjacent data signal lines.

9. The array substrate according to claim 1, characterized in that: The multiple reflective portions are arranged in multiple rows, the multiple rows of reflective portions are arranged along a first direction, and the multiple reflective portions in one row of reflective portions are arranged along a second direction, the first direction is the extension direction of the data signal line, and the second direction is the extension direction of the first gate signal line; The multiple reflective portions in two adjacent rows of reflective portions are arranged in a staggered manner.

10. The array substrate according to claim 1, characterized in that: The multiple reflective portions are arranged in multiple rows, the multiple rows of reflective portions are arranged along a first direction, and the multiple reflective portions in one row of reflective portions are arranged along a second direction, the first direction is the extension direction of the data signal line, and the second direction is the extension direction of the first gate signal line; A row of the reflection parts includes a plurality of first reflection parts and a plurality of second reflection parts, and the first reflection parts and the second reflection parts are alternately arranged along the second direction; The first overlapping area has a first side and a second side opposite to each other along the first direction, the center of the orthographic projection of the first reflecting portion on the substrate is located on the first side of the center of the first overlapping area, and the center of the orthographic projection of the second reflecting portion on the substrate is located on the second side of the center of the first overlapping area.

11. The array substrate according to claim 1, characterized in that: The shape of the orthographic projection of the reflective portion on the substrate includes at least one of a circle, an ellipse, a square and a regular hexagon.

12. The array substrate according to claim 1, characterized in that: The orthographic projection of the reflecting portion on the substrate is rectangular, the multiple reflecting portions correspond to the multiple first overlapping regions one by one, and the first overlapping regions are located in the orthographic projection of the corresponding reflecting portion on the substrate; The difference between the width of the reflective portion in the first direction and the width of the first overlapping region in the first direction is in the range of 1 micrometer to 8 micrometers, and the difference between the width of the reflective portion in the second direction and the width of the first overlapping region in the second direction is in the range of 1 micrometer to 6 micrometers; The first direction is an extending direction of the data signal line, and the second direction is an extending direction of the first gate signal line.

13. The array substrate according to claim 12, characterized in that: The multiple reflective portions are arranged in multiple rows, the multiple rows of reflective portions are arranged along the first direction, and the multiple reflective portions in one row of reflective portions are arranged along the second direction; The reflective pattern further includes a plurality of connecting portions, each of which is located between two adjacent reflective portions in a row of the reflective portions and is connected to the two adjacent reflective portions; The orthographic projection of the connection portion on the substrate is located in the orthographic projection of the first gate signal line on the substrate.

14. The array substrate according to claim 12, characterized in that: The reflective portion comprises a reflective portion main body and two first protruding structures, wherein the two first protruding structures are respectively located at two sides of the reflective portion main body in the second direction, and an opening area is provided between two adjacent first protruding structures of the reflective portion along the second direction; The orthographic projection of the first protruding structure on the substrate is located in the orthographic projection of the first gate signal line on the substrate.

15. The array substrate according to claim 12, characterized in that: The multiple reflective portions are arranged in multiple rows, the multiple rows of reflective portions are arranged along the first direction, and the multiple reflective portions in one row of reflective portions are arranged along the second direction; A row of the reflection parts includes a plurality of reflection part units, and one reflection part unit includes a plurality of reflection parts; In two adjacent reflection unit units, the length of the reflection part in one reflection unit in the first direction is a first length, and the length of the reflection part in the other reflection unit in the first direction is a second length, and the first length is greater than the second length.

16. The array substrate according to claim 1, characterized in that: The multiple reflection parts include multiple reflection part groups, one of the reflection part groups includes two rows of reflection parts, the multiple reflection part groups are arranged along a first direction, the two rows of reflection parts in one reflection part group are arranged along the first direction, and the multiple reflection parts in one row of reflection parts are arranged along a second direction, the first direction is the extension direction of the data signal line, and the second direction is the extension direction of the first gate signal line; The orthographic projections of the multiple reflecting parts in one row of reflecting parts in one reflecting part group on the substrate are circular, and the orthographic projections of the multiple reflecting parts in another row of reflecting parts on the substrate are rectangular.

17. A method for manufacturing an array substrate, characterized in that: The method comprises: forming a reflective pattern on a substrate, wherein the reflective pattern comprises a plurality of reflective portions, and an opening area is provided between two adjacent reflective portions; forming a plurality of first gate signal lines on the substrate having the light-reflecting pattern formed thereon; forming a plurality of first data signal lines on a substrate on which a plurality of first gate signal lines are formed; The orthographic projection of the first gate signal line on the substrate and the orthographic projection of the data signal line on the substrate have a first overlapping area, and the orthographic projection of the reflective portion on the substrate overlaps with the first overlapping area.

18. A display panel, characterized in that: The display panel comprises: an array substrate and a color filter substrate that are arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate is any one of claims 1 to 16.

19. The display panel according to claim 18, characterized in that: The display panel further includes a plurality of supporting parts located between the array substrate and the color filter substrate, and an orthographic projection of at least one of the plurality of supporting parts on the substrate is located in an orthographic projection of the reflecting part on the substrate.

20. The display panel according to claim 18, characterized in that: The color filter substrate includes a plurality of red color resist blocks, a plurality of blue color resist blocks and a plurality of green color resist blocks; The orthographic projection of the reflecting portion on the substrate overlaps with the orthographic projection of at least one red color block among the multiple red color blocks on the substrate, the orthographic projection of the reflecting portion on the substrate overlaps with the orthographic projection of at least one blue color block among the multiple blue color blocks on the substrate, and the orthographic projection of the reflecting portion on the substrate is staggered with the orthographic projection of the green color block on the substrate.

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