Display device

Abstract

The display device includes: a substrate; a first assembly wiring and a second assembly wiring on the substrate; a partition wall disposed on the first assembly wiring and the second assembly wiring, the partition wall having an assembly hole and at least one auxiliary hole extending in an outer direction of the assembly hole; a semiconductor light-emitting device located in the assembly hole; and a connection electrode connected to a side portion of the semiconductor light emitting device. The partition wall may include: a first partition wall layer; and a second partition wall layer on the first partition wall layer. An ashing rate of the first partition wall layer is equal to or greater than an ashing rate of the second partition wall layer.

Description

Technical Field

[0001] Embodiments relate to a display device. Background Art

[0002] Large-area displays include liquid crystal displays (LCD), OLED displays, and micro-LED displays (Micro-LEDdisplay).

[0003] The micro LED display is a display using a micro LED, which is a semiconductor light emitting device having a diameter or a cross-sectional area of ​​100 μm or less, as a display device.

[0004] Micro LED displays use micro LEDs, which are semiconductor light-emitting devices, as display devices, so they have excellent performance in many characteristics such as light-to-dark ratio, response speed, color reproduction rate, viewing angle, brightness, resolution, lifespan, luminous efficiency or brightness.

[0005] In particular, the micro-LED display can separate and combine screens in a modular manner, thereby having the advantages of free adjustment of size or resolution and the ability to achieve a flexible display.

[0006] However, a large-scale micro-LED display requires more than several million micro-LEDs, so there is a technical problem that it is difficult to quickly and accurately transfer the micro-LEDs to the display panel.

[0007] Recently developed transfer technologies include pick and place process, laser lift-off method or self-assembly method.

[0008] Among them, the self-assembly method, as a method for semiconductor light-emitting devices to find assembly positions in a fluid by themselves, is a method that is conducive to realizing large-screen display devices.

[0009] However, research on the technology of manufacturing displays through self-assembly of micro-LEDs is still incomplete.

[0010] In particular, in the prior art, when millions of semiconductor light-emitting devices are quickly transferred to a large display, although the transfer speed can be increased, the transfer error rate may increase, thereby causing a technical problem of reducing the transfer yield.

[0011] In the related art, although a transfer process using a self-assembly method of dielectrophoresis (DEP) has been attempted, there is a problem of low self-assembly rate due to the non-uniformity of the dielectrophoresis force.

[0012] Figure 1 It is a top view showing a state in which a semiconductor light emitting device is arranged in an assembly hole in a non-disclosed internal technology.

[0013] like Figure 1 As shown, the semiconductor light emitting device 8 is assembled into the assembly hole 7 provided in the partition wall 6 by self-assembly.

[0014] Then, for electrical connection of the semiconductor light emitting device 8 , a deposition process is performed to form a side electrode between the outer side surface of the semiconductor light emitting device 8 and the inner side surface of the assembly hole 7 .

[0015] However, if Figure 2 As shown, since the gap between the outer side surface of the semiconductor light emitting device 8 and the inner side surface of the assembly hole 7 is narrow, it is difficult for metal substances to be deposited in the gap, thereby causing a disconnection defect of the side electrode 5.

[0016] To prevent this disconnection, Figure 3 As shown, in addition to the assembly hole 7, an auxiliary hole 9 is formed. Due to the auxiliary hole 9, the metal substance is easily deposited in the auxiliary hole 9, so that the disconnection defect of the side electrode does not occur.

[0017] However, if Figure 4 As shown, when the dielectrophoretic force (DEP force) is generated for self-assembly, a failure in assembling the two semiconductor light emitting devices 4 and 8 occurs.

[0018] That is, both the assembly hole 7 and the auxiliary hole 9 are formed by removing the partition wall 6. As the partition wall 6 is removed, a dielectrophoretic force of a magnitude close to that of the dielectrophoretic force in the assembly hole 7 is also formed in the auxiliary hole 9. In the case where the magnitude of the dielectrophoretic force in the assembly hole 7 is a magnitude optimized for assembling the semiconductor light-emitting device 8 into the assembly hole 7, the dielectrophoretic force formed in the auxiliary hole 9 is not necessary. As a result, not only the semiconductor light-emitting device 8 matching the assembly hole 7, such as a red semiconductor light-emitting device, is assembled, but also the semiconductor light-emitting device 4 matching other assembly holes, such as a blue semiconductor light-emitting device, is assembled, so that poor assembly and poor color mixing occur. Here, poor color mixing refers to the situation where the semiconductor light-emitting device is assembled into an assembly hole into which other semiconductor light-emitting devices are to be assembled instead of the assembly hole into which it is to be assembled, thereby emitting other light instead of the desired color light from the sub-pixel including the assembly hole.

[0019] On the other hand, in order to prevent disconnection defects, it has been proposed to ensure a deposition margin by removing the partition walls. However, there is a problem that the ashing process for removing the partition walls takes too long. Summary of the invention

[0020] Problems to be solved by the invention

[0021] Embodiments are directed to solving the aforementioned problems and other problems.

[0022] Another object of the embodiment is to provide a display device capable of preventing disconnection of connection electrodes (side electrodes).

[0023] Another object of the embodiment is to provide a display device capable of preventing poor assembly or poor color mixing of dual semiconductor light emitting devices.

[0024] Another object of the embodiment is to provide a display device capable of shortening process time and reducing the number of process steps.

[0025] The technical problems of the embodiments are not limited to the technical problems described herein, but include technical problems that can be grasped through the description of the invention.

[0026] Technical solutions to the problem

[0027] In order to achieve the above or other purposes, according to one aspect of the embodiment, a display device includes: a substrate; a first assembly wiring and a second assembly wiring, which are located on the substrate; a partition wall, which is arranged on the first assembly wiring and the second assembly wiring, and has an assembly hole and at least one auxiliary hole extending toward the outside of the assembly hole; a semiconductor light-emitting device, which is located in the assembly hole; and a connecting electrode, which is connected to the side of the semiconductor light-emitting device; the partition wall includes: a first partition wall layer; and a second partition wall layer, which is located on the first partition wall layer; the ashing rate of the first partition wall layer is equal to or greater than the ashing rate of the second partition wall layer.

[0028] The viscosity of the first partition wall layer may be equal to or less than the viscosity of the second partition wall layer.

[0029] The thickness of the second partition wall layer may be equal to or smaller than the thickness of the first partition wall layer.

[0030] The auxiliary hole may be formed by removing the first partition wall layer or the second partition wall layer.

[0031] The connection electrode may be disposed at the assembly hole and the auxiliary hole.

[0032] The length of the auxiliary hole may be smaller than a width of the first assembly wiring or the second assembly wiring.

[0033] The auxiliary holes may include: at least one first auxiliary hole located on the first assembly wiring; and at least one second auxiliary hole located on the second assembly wiring.

[0034] The first auxiliary hole and the second auxiliary hole may be disposed symmetrically to each other.

[0035] The partition wall may have an expansion hole, the expansion hole includes the assembly hole, and the expansion hole has a second diameter greater than the first diameter of the assembly hole; the connecting electrode may be arranged between the outer side surface of the semiconductor light emitting device and the inner side surface of the expansion hole.

[0036] The second diameter of the expansion hole may be greater than the first diameter of the assembly hole by more than 2 micrometers.

[0037] The expansion hole may be formed by removing the first partition wall layer.

[0038] The auxiliary hole may extend toward an outer side of the expansion hole.

[0039] The first partition wall layer and the second partition wall layer may each contain an organic substance.

[0040] The partition wall may have a thickness smaller than a thickness of the semiconductor light emitting device.

[0041] Effects of the Invention

[0042] In an embodiment, Fig.13 As shown, the backplane substrate 300A before performing self-assembly can form a part of the partition wall 340, such as the first partition wall layer 341, in the auxiliary holes 362 and 363 extending in the lateral direction from the assembly hole 361. At this time, the ashing rate of the first partition wall layer 341 of the partition wall can be greater than the ashing rate of the second partition wall layer 342. That is, this means that the viscosity of the first partition wall layer 341 can be less than the viscosity of the second partition wall layer 342.

[0043] By performing a self-assembly process on the back panel substrate 300A, and after assembling the semiconductor light emitting device 150 ( Fig.16 ), the first partition wall layer 341 on the auxiliary holes 362 and 363 is removed by performing an ashing process, so that a sufficient space margin can be ensured on the side of the semiconductor light emitting device 150. Fig.18 As shown, even if the metal film 370 is deposited on the substrate 310, at least a sufficient space margin corresponding to the size of the auxiliary holes 362 and 363 can be ensured, thereby improving the film quality of the metal film 370. Then, even if the metal film 370 is patterned to form the connection electrodes 371 and 372 ( Fig.19), and no disconnection will occur at the connecting electrodes, thereby increasing the yield and improving reliability by preventing lighting defects.

[0044] On the other hand, Fig.23 As shown, the semiconductor light emitting device 150 can be assembled using the backplane substrate 300C in which a part of the partition wall 340, namely the first partition wall layer 341, is formed in the expansion hole 364. Then, the first partition wall layer 341 on the expansion hole 364 is removed by an ashing process, and a sufficient space margin along the periphery of the semiconductor light emitting device 150 is ensured in the expansion hole 364, and the connection electrode is arranged in this area, so that the connection electrode is arranged along the periphery of the semiconductor light emitting device 150 without interruption, so that the current can flow more smoothly, thereby realizing high brightness display.

[0045] On the other hand, Fig.28 As shown, there are a plurality of auxiliary holes 362-1, 362-2, 363-1, and 363-2, and connection electrodes are arranged in the plurality of auxiliary holes 362-1, 362-2, 363-1, and 363-2, so that a further improved high-brightness display can be achieved.

[0046] The additional scope to which the embodiment can be applied can become more clear through the following detailed description. However, those skilled in the art can clearly understand the various changes and modifications within the thought and scope of the embodiment, so it should be understood that the detailed description and specific embodiments such as the preferred embodiment are only exemplary. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a top view showing a state in which a semiconductor light emitting device is arranged in an assembly hole in a non-disclosed internal technology.

[0048] Figure 2 is shown with Figure 1 A cross-sectional view of a side electrode of a light-emitting device showing a disconnection defect of the side electrode.

[0049] Figure 3 It is a top view showing an auxiliary hole provided to prevent a disconnection defect.

[0050] Figure 4 FIG. 1 is a diagram showing a state in which two semiconductor light emitting devices are assembled due to an unnecessary increase in dielectrophoretic force.

[0051] Figure 5 The living room of a house in which the display device of the embodiment is installed is shown.

[0052] Figure 6 This is a block diagram schematically showing a display device according to the embodiment.

[0053] Figure 7 It is shown Figure 6 A circuit diagram of an example of a pixel.

[0054] Figure 8 yes Figure 5 An enlarged view of the first panel area in the display device.

[0055] Fig. 9 yes Figure 8 Magnified view of the A2 area.

[0056] Fig.10 This is a diagram showing an example in which the light-emitting device according to the embodiment is assembled on a substrate by a self-assembly method.

[0057] Fig.11 is a plan view showing the display device of the first embodiment.

[0058] Fig.12 is a cross-sectional view showing the display device of the first embodiment.

[0059] Fig.13 is a cross-sectional view showing a backplane substrate according to the first embodiment.

[0060] Fig.14 1 is a schematic diagram showing a process of manufacturing a display device using the backplane substrate of the first embodiment.

[0061] Fig.15 A diagram showing the form of auxiliary holes formed in the process of manufacturing a display device using the back panel substrate of the first embodiment.

[0062] Figures 16 to 20 A diagram showing a process of manufacturing a display device using the backplane substrate of the first embodiment.

[0063] Fig.21 is a cross-sectional view showing a backplane substrate according to a second embodiment.

[0064] Fig. 22 The embodiment of the second embodiment shows an ashing process performed after assembling the semiconductor light emitting device on the backplane substrate.

[0065] Fig.23 is a plan view showing a display device according to a second embodiment.

[0066] Fig.24 It is a cross-sectional view taken along line E1 - E2 of the display device of the second embodiment.

[0067] Fig.25 It is a cross-sectional view taken along line F1 - F2 of the display device of the second embodiment.

[0068] Fig.26 and Fig. 27is a cross-sectional view showing a backplane substrate according to a third embodiment.

[0069] Fig.28 is a plan view showing a display device according to a third embodiment.

[0070] The size, shape, value, etc. of the components shown in the drawings may be different from the actual ones. In addition, even if the same components are shown in different sizes, shapes, values, etc. between the drawings, this is just an example on the drawings, and the same components may have the same size, shape, value, etc. between the drawings. DETAILED DESCRIPTION

[0071] Below, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. Regardless of the figure numbers, the same or similar constituent elements are given the same figure numbers and their descriptions are omitted. The suffixes "module" and "unit" of the constituent elements used in the following description are given or mixed for the sake of easy writing of the specification, and they themselves do not have meanings or functions that distinguish each other. In addition, the accompanying drawings are used to make the embodiments disclosed in this specification easy to understand, and the technical ideas disclosed in this specification are not limited by the accompanying drawings. In addition, when it is mentioned that an element such as a layer, a region or a substrate exists "on" another constituent element, it should be understood that it can exist directly on another element, or there can be other intermediate elements between them.

[0072] The display device described in this specification may include a TV, a digital signage, a mobile terminal such as a mobile phone or a smartphone, a computer display such as a laptop or a desktop computer, a head-up display (HUD) for a vehicle, a backlight unit for a display, a display for VR (virtual reality), AR (augmented reality) or MR (mixed reality), a light source, etc. However, even in the form of a new product developed later, the configuration of the embodiments described in this specification can also be applied to a device capable of displaying.

[0073] Figure 5 The living room of a house in which the display device according to the embodiment is installed is shown.

[0074] Reference Figure 5 The display device 100 of the embodiment can display the status of various electronic products such as a washing machine 101, a sweeping robot 102, and an air purifier 103, can communicate with each electronic product based on IOT, and can also control each electronic product based on user setting data.

[0075] The display device 100 of the embodiment may include a flexible display manufactured on a thin and soft substrate. The flexible display maintains the characteristics of an existing flat panel display and can be bent or rolled like paper.

[0076] In a flexible display, visual information can be realized by independently controlling the light emission of unit pixels configured in a matrix form. A unit pixel refers to the smallest unit for realizing a color. The unit pixel of a flexible display can be realized by a light-emitting device. In an embodiment, the light-emitting device can be a Micro-LED or a Nano-LED, but is not limited thereto.

[0077] Figure 6 is a block diagram schematically showing a display device of an embodiment, Figure 7 It is shown Figure 6 A circuit diagram of an example of a pixel.

[0078] Reference Figure 6 and Figure 7 The display device of the embodiment may include a display panel 10 , a driving circuit 20 , a scan driving unit 30 , and a power supply circuit 50 .

[0079] The display device 100 of the embodiment may drive the light emitting devices in an active matrix (AM) mode or a passive matrix (PM) mode.

[0080] The driving circuit 20 may include a data driving section 21 and a timing control section 22 .

[0081] The display panel 10 may be formed in a rectangular shape, but is not limited thereto. That is, the display panel 10 may be formed in a circular or oval shape. At least one side of the display panel 10 may be formed to be curved with a prescribed curvature.

[0082] The display panel may include a display area DA. The display area DA is a region where a plurality of pixels PX are formed to display an image. The display panel may include a non-display area NDA. The non-display area DNA may be a region other than the display area DA.

[0083] As an example, the display area DA and the non-display area NDA may be defined on the same surface. For example, the non-display area DNA may surround the display area DA on the same surface together with the display area DA, but is not limited thereto.

[0084] As another example, although not shown in the figure, the display area DA and the non-display area NDA may be defined on different surfaces. For example, the display area DA may be defined on the top surface of the substrate, and the non-display area NDA may be defined on the bottom surface of the substrate. For example, the non-display area NDA may also be defined on the entire area or a portion of the bottom surface of the substrate.

[0085] On the other hand, the figure shows that the display area DA and the non-display area NDA are distinguished, but the display area DA and the non-display area NDA may not be distinguished. That is, there may be only the display area DA on the top surface of the substrate, and there may be no non-display area NDA. In other words, the entire area of ​​the top surface of the substrate is the display area DA for displaying an image, and there may be no frame area as the non-display area NDA.

[0086] The display panel 10 may include a plurality of data lines D1~Dm (m is an integer greater than 2), a plurality of scan lines S1~Sn (n is an integer greater than 2) intersecting the plurality of data lines D1~Dm, a high potential voltage line VDDL supplied with a high potential voltage, a low potential voltage line VSSL supplied with a low potential voltage VSS, and a plurality of pixels PX connected to the plurality of data lines D1~Dm and the plurality of scan lines S1~Sn.

[0087] Each of the plurality of pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit a first color light of a first main wavelength, the second sub-pixel PX2 may emit a second color light of a second main wavelength, and the third sub-pixel PX3 may emit a third color light of a third main wavelength. The first color light may be red light, the second color light may be green light, and the third color light may be blue light, but are not limited thereto. In addition, Figure 6 It is illustrated that each of the plurality of pixels PX includes three sub-pixels, but the present invention is not limited thereto. That is, each of the plurality of pixels PX may include more than four sub-pixels.

[0088] Each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 may be connected to at least one of the plurality of data lines D1-Dm, at least one of the plurality of scan lines S1-Sn, and a high potential voltage line VDDL. Figure 7 As shown, the first subpixel PX1 may include a plurality of light emitting devices LD, a plurality of transistors for supplying current to the plurality of light emitting devices LD, and at least one capacitor Cst.

[0089] Although not shown, each of the first sub-pixel PX1 , the second sub-pixel PX2 , and the third sub-pixel PX3 may include only one light emitting device LD and at least one capacitor Cst.

[0090] Each of the plurality of light emitting devices LD may be a semiconductor light emitting diode including a first electrode, a plurality of conductive semiconductor layers and a second electrode. Here, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode, but is not limited thereto.

[0091] The light emitting device LD may be one of a horizontal type light emitting device, a flip-chip type light emitting device, and a vertical type light emitting device.

[0092] like Figure 7 As shown, the plurality of transistors may include: a driving transistor DT, supplying current to the plurality of light emitting devices LD; and a scanning transistor ST, supplying a data voltage to the gate electrode of the driving transistor DT. The driving transistor DT may include: a gate electrode connected to the source electrode of the scanning transistor ST; a source electrode connected to a high potential voltage line VDDL to which a high potential voltage is applied; and a drain electrode connected to the plurality of first electrodes of the plurality of light emitting devices LD. The scanning transistor ST may include: a gate electrode connected to the scanning line Sk (k is an integer satisfying 1≤k≤n); a source electrode connected to the gate electrode of the driving transistor DT; and a drain electrode connected to the data line Dj (j is an integer satisfying 1≤j≤m).

[0093] The capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst stores a difference between a gate voltage and a source voltage of the driving transistor DT.

[0094] The driving transistor DT and the scanning transistor ST may be formed by thin film transistors. Figure 7 In the embodiment, the driving transistor DT and the scanning transistor ST are described with the driving transistor DT and the scanning transistor ST being formed by a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but the present invention is not limited thereto. The driving transistor DT and the scanning transistor ST may also be formed by an N-type MOSFET. In this case, the positions of the source electrode and the drain electrode of each of the driving transistor DT and the scanning transistor ST may be changed.

[0095] In addition, Figure 7In the embodiment, each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 is illustrated as including a 2T1C (2Transistor-1capacitor) having a driving transistor DT, a scanning transistor ST, and a capacitor Cst, but the present invention is not limited thereto. Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include a plurality of scanning transistors ST and a plurality of capacitors Cst.

[0096] The second sub-pixel PX2 and the third sub-pixel PX3 may be represented by substantially the same circuit diagram as the first sub-pixel PX1 , and thus detailed description thereof will be omitted.

[0097] The driving circuit 20 outputs a plurality of signals and a plurality of voltages for driving the display panel 10. To this end, the driving circuit 20 may include a data driving part 21 and a timing control part 22.

[0098] The data driving part 21 receives the digital video data DATA and the source control signal DCS from the timing control part 22. The data driving part 21 converts the digital video data DATA into a plurality of analog data voltages according to the source control signal DCS and supplies the analog data voltages to the plurality of data lines D1Dm of the display panel 10.

[0099] The timing control unit 22 receives digital video data DATA and a plurality of timing signals from a host system. The plurality of timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The host system may be an application processor of a smart phone or a tablet PC, a display, a system-on-chip of a TV, etc.

[0100] The timing control unit 22 generates a plurality of control signals for controlling the operation timing of the data driving unit 21 and the scan driving unit 30. The plurality of control signals may include a source control signal DCS for controlling the operation timing of the data driving unit 21 and a scan control signal SCS for controlling the operation timing of the scan driving unit 30.

[0101] The driving circuit 20 may be disposed in a non-display area NDA provided on one side of the display panel 10. The driving circuit 20 is formed by an integrated circuit (IC) and may be mounted on the display panel 10 in a COG (chip on glass) manner, a COP (chip on plastic) manner, or an ultrasonic bonding manner, but the present invention is not limited thereto. For example, the driving circuit 20 may be mounted on a circuit board (not shown) instead of the display panel 10.

[0102] The data driving unit 21 may be mounted on the display panel 10 by a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, and the timing control unit 22 may be mounted on a circuit board.

[0103] The scan driving unit 30 receives a scan control signal SCS from the timing control unit 22. The scan driving unit 30 generates a plurality of scan signals according to the scan control signal SCS and supplies the scan signals to the plurality of scan lines S1 to Sn of the display panel 10. The scan driving unit 30 includes a plurality of transistors and may be formed in the non-display area NDA of the display panel 10. Alternatively, the scan driving unit 30 may be formed by an integrated circuit, in which case, it may be mounted on a gate flexible film attached to the other side of the display panel 10.

[0104] The circuit board can be attached to a plurality of pads disposed on one side edge of the display panel 10 using an anisotropic conductive film. Therefore, a plurality of leads of the circuit board can be electrically connected to the plurality of pads. The circuit board can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film. The circuit board can be bent toward the lower portion of the display panel 10. Therefore, one side of the circuit board can be attached to one side edge of the display panel 10, and the other side can be configured at the lower portion of the display panel 10, and can be connected to a system board on which a host system is installed.

[0105] The power supply circuit 50 may generate a plurality of voltages required for driving the display panel 10 from the main power applied from the system board and supply the voltages to the display panel 10. For example, the power supply circuit 50 may generate a high potential voltage VDD and a low potential voltage VSS for driving the plurality of light emitting devices LD of the display panel 10 from the main power, and supply the voltages to the high potential voltage line VDDL and the low potential voltage line VSSL of the display panel 10. In addition, the power supply circuit 50 generates and supplies a driving voltage for driving the driving circuit 20 and the scanning driving section 30 from the main power.

[0106] Figure 8 yes Figure 3 An enlarged view of the first panel area in the display device.

[0107] Reference Figure 8 The display device 100 of the embodiment can be manufactured by mechanically and electrically connecting a plurality of panel areas such as the first panel area A1 by tiling.

[0108] The first panel area A1 may include each unit pixel ( Figure 6 A plurality of semiconductor light emitting devices 150 configured with PX).

[0109] For example, the unit pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. For example, a plurality of red semiconductor light emitting devices 150R may be configured in the first sub-pixel PX1, a plurality of green semiconductor light emitting devices 150G may be configured in the second sub-pixel PX2, and a plurality of blue semiconductor light emitting devices 150B may be configured in the third sub-pixel PX3. The unit pixel PX may also include a fourth sub-pixel not configured with a semiconductor light emitting device, but is not limited thereto.

[0110] Fig. 9 yes Figure 8 Magnified view of the A2 area.

[0111] Reference Fig. 9 The display device 100 of the embodiment may include a substrate 200, wiring harnesses 201 and 202, an insulating layer 206, and a plurality of semiconductor light emitting devices 150. More components may be included.

[0112] The assembly wiring may include a first assembly wiring 201 and a second assembly wiring 202 that are spaced apart from each other. The first assembly wiring 201 and the second assembly wiring 202 may generate a dielectrophoretic force for assembling the semiconductor light emitting device 150. For example, the semiconductor light emitting device 150 may be one of a horizontal semiconductor light emitting device, a flip-chip semiconductor light emitting device, and a vertical semiconductor light emitting device.

[0113] In order to realize each unit pixel (sub-pixel), the semiconductor light emitting device 150 may include a red semiconductor light emitting device 150R, a green semiconductor light emitting device 150G and a blue semiconductor light emitting device 150B, but is not limited thereto and may also have a red phosphor and a green phosphor, etc., to realize red and green respectively.

[0114] The substrate 200 may be a supporting member that supports components disposed on the substrate 200 or a protecting member that protects the components.

[0115] The substrate 200 may be a rigid substrate or a flexible substrate. The substrate 200 may be formed of sapphire, glass, silicon or polyimide. In addition, the substrate 200 may include a flexible material such as PEN (Polyethylene Naphthalate) and PET (Polyethylene Terephthalate). In addition, the substrate 200 may be a transparent material, but is not limited thereto. The substrate 200 may function as a supporting substrate of a display panel, and may also function as an assembly substrate when the light-emitting device is self-assembled.

[0116] The substrate 200 may be provided with Figure 6 and Figure 7 The circuits in the sub-pixels PX1 , PX2 , and PX3 are shown as backplanes such as transistors ST, DT, capacitors Cst, signal wirings, etc., but are not limited thereto.

[0117] The insulating layer 206 may include an organic material having insulation and flexibility such as polyimide, PAC, PEN, PET, polymer, or an inorganic material such as silicon oxide (SiO2) or silicon nitride series (SiNx), and may also be formed integrally with the substrate 200 to form a single substrate.

[0118] The insulating layer 206 may be a conductive adhesive layer having adhesiveness and conductivity, and the conductive adhesive layer is flexible, thereby realizing the flexible function of the display device. For example, the insulating layer 206 may be a conductive adhesive layer such as an anisotropic conductive film (ACF) or an anisotropic conductive medium, a solution containing conductive particles, etc. The conductive adhesive layer may be a layer having conductivity in a direction perpendicular to the thickness and electrical insulation in a direction horizontal to the thickness.

[0119] The insulating layer 206 may include an assembly hole 203 for inserting the semiconductor light emitting device 150. Therefore, during self-assembly, the semiconductor light emitting device 150 may be easily inserted into the assembly hole 203 of the insulating layer 206. The assembly hole 203 may be referred to as an insertion hole, a fixing hole, an alignment hole, etc. The assembly hole 203 may also be referred to as a hole.

[0120] The assembly hole 203 may be referred to as a hole, a slot, a groove, a recess, a pocket, or the like.

[0121] The assembly hole 203 may be different according to the shape of the semiconductor light emitting device 150. For example, the red semiconductor light emitting device, the green semiconductor light emitting device, and the blue semiconductor light emitting device may have different shapes, respectively, and may include an assembly hole 203 having a shape corresponding to the shape of each of these semiconductor light emitting devices. For example, the assembly hole 203 may include a first assembly hole for assembling a red semiconductor light emitting device, a second assembly hole for assembling a green semiconductor light emitting device, and a third assembly hole for assembling a blue semiconductor light emitting device. For example, the red semiconductor light emitting device may have a circular shape, the green semiconductor light emitting device may have a first elliptical shape including a first short axis and a second long axis, and the blue semiconductor light emitting device may have a second elliptical shape including a second short axis and a second long axis, but is not limited thereto. The second long axis of the ellipse of the blue semiconductor light emitting device may be greater than the second long axis of the ellipse of the green semiconductor light emitting device, and the second short axis of the ellipse of the blue semiconductor light emitting device may be smaller than the first short axis of the ellipse of the green semiconductor light emitting device.

[0122] On the other hand, the semiconductor light emitting device 150 can be mounted on the substrate 200 by, for example, a self-assembly method ( Fig.10 ) and transfer methods, etc.

[0123] Fig.10 This is a diagram showing an example in which the light-emitting device of the embodiment is assembled on a substrate by a self-assembly method.

[0124] based on Fig.10 , illustrating an example of assembling a semiconductor light emitting device to a display panel by utilizing a self-assembly method using an electromagnetic field.

[0125] The assembly substrate 200 described later may also function as a panel substrate 200 a in a display device after assembling the light emitting device, but the embodiment is not limited thereto.

[0126] Reference Fig.10, the semiconductor light emitting device 150 can be put into the chamber 1300 filled with the fluid 1200, and under the action of the magnetic field generated by the assembly device 1100, the semiconductor light emitting device 150 can move toward the assembly substrate 200. At this time, the light emitting device 150 adjacent to the assembly hole 207H of the assembly substrate 200 can be assembled to the assembly hole 207H under the action of the dielectrophoretic force caused by the electric field of the plurality of assembly wirings. The fluid 1200 can be water such as ultrapure water, but is not limited thereto. The chamber can be called a water tank, a cavity, a container, etc.

[0127] After the semiconductor light emitting device 150 is introduced into the chamber 1300, the assembly substrate 200 may be disposed on the chamber 1300. According to an embodiment, the assembly substrate 200 may also be introduced into the chamber 1300.

[0128] As shown in the figure, the semiconductor light emitting device 150 may be implemented by a vertical semiconductor light emitting device, but is not limited thereto, and a horizontal semiconductor light emitting device may be used.

[0129] The semiconductor light emitting device 150 may include a magnetic layer (not shown) having a magnetic body. The magnetic layer may include a magnetic metal such as nickel (Ni). The semiconductor light emitting device 150 put into the fluid includes a magnetic layer, and thus can move toward the assembly substrate 200 under the action of the magnetic field generated by the assembly device 1100. The magnetic layer may be arranged on the upper side, the lower side, or both sides of the light emitting device.

[0130] The assembly substrate 200 may include a pair of first assembly wiring 201 and second assembly wiring 202 corresponding to each semiconductor light emitting device 150 to be assembled. Each of the first assembly wiring 201 and the second assembly wiring 202 may be formed by laminating a single metal or a metal alloy, a metal oxide, etc. For example, each of the first assembly wiring 201 and the second assembly wiring 202 may include at least one of Cu, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, but is not limited thereto.

[0131] The first assembly wiring 201 and the second assembly wiring 202 form an electric field as an AC voltage is applied, and the semiconductor light emitting device 150 inserted into the assembly hole 207H can be fixed by the dielectrophoretic force generated by the electric field. The interval between the first assembly wiring 201 and the second assembly wiring 202 can be smaller than the width of the semiconductor light emitting device 150 and the width of the assembly hole 207H, and the assembly position of the semiconductor light emitting device 150 using the electric field can be fixed more accurately.

[0132] An insulating layer 215 is formed on the first assembled wiring 201 and the second assembled wiring 202, which can protect the first assembled wiring 201 and the second assembled wiring 202 from the influence of the fluid 1200 and prevent leakage of the current flowing in the first assembled wiring 201 and the second assembled wiring 202. For example, the insulating layer 215 can be formed of an inorganic insulator such as silicon dioxide, aluminum oxide, or an organic insulator in a single layer or multiple layers. The insulating layer 215 can have a minimum thickness for preventing the first assembled wiring 201 and the second assembled wiring 202 from being damaged when assembling the semiconductor light-emitting device 150, and can have a maximum thickness for stably assembling the semiconductor light-emitting device 150.

[0133] A partition wall 207 may be formed on the upper portion of the insulating layer 215 . A portion of the partition wall 207 may be located on the upper portion of the first and second assembly wirings 201 and 202 , and the remaining portion may be located on the upper portion of the assembly substrate 200 .

[0134] On the other hand, when manufacturing the assembly substrate 200 , a portion of the partition wall formed on the upper portion of the insulating layer 215 is removed so that an assembly hole 207H to which each of the plurality of semiconductor light emitting devices 150 is coupled and assembled to the assembly substrate 200 can be formed.

[0135] The assembly substrate 200 may be formed with assembly holes 207H for combining a plurality of semiconductor light emitting devices 150, and the surface formed with the assembly holes 207H may be in contact with the fluid 1200. The assembly holes 207H may guide the accurate assembly position of the semiconductor light emitting device 150.

[0136] On the other hand, the assembly hole 207H may have a shape and size corresponding to the shape of the semiconductor light emitting device 150 to be assembled in the corresponding position, thereby preventing other semiconductor light emitting devices or a plurality of semiconductor light emitting devices from being assembled in the assembly hole 207H.

[0137] Refer again Fig.10 After the assembly substrate 200 is arranged in the chamber, the assembly device 1100 applying the magnetic field may move along the assembly substrate 200. The assembly device 1100 may be a permanent magnet or an electromagnet.

[0138] In order to maximize the area affected by the magnetic field in the fluid 1200, the assembly device 1100 may move in contact with the assembly substrate 200. According to an embodiment, the assembly device 1100 may include a plurality of magnetic bodies or may also include a magnetic body of a size corresponding to the assembly substrate 200. In this case, the moving distance of the assembly device 1100 may also be limited within a specified range.

[0139] Under the effect of the magnetic field generated by the assembly apparatus 1100 , the semiconductor light emitting device 150 within the chamber 1300 may move toward the assembly apparatus 1100 and the assembly substrate 200 .

[0140] When the semiconductor light emitting device 150 moves toward the assembly apparatus 1100 , it can enter and be fixed to the assembly hole 207H under the action of the dielectrophoretic force formed by the electric field between the assembly wirings 201 and 202 .

[0141] Specifically, the first assembly wiring 201 and the second assembly wiring 202 can form an electric field under the action of an AC power source, and under the action of the electric field, a dielectrophoretic force can be formed between the assembly wirings 201 and 202. Under the action of the dielectrophoretic force, the semiconductor light emitting device 150 can be fixed to the assembly hole 207H on the assembly substrate 200.

[0142] At this time, a predetermined solder layer (not shown) is formed between the light emitting device 150 mounted on the mounting hole 207H of the mounting substrate 200 and the mounting wirings 201 and 202 , thereby improving the bonding strength of the light emitting device 150 .

[0143] In addition, after assembly, a molding layer (not shown) may be formed in the assembly hole 207H of the assembly substrate 200. The molding layer may be a resin including a transparent resin or a reflective material or a scattering material.

[0144] By utilizing the above-mentioned electromagnetic field self-assembly method, the time required to assemble each of the plurality of semiconductor light-emitting devices onto the substrate can be greatly shortened, thereby realizing a large-area high-pixel display more quickly and economically.

[0145] Below, refer to Figures 11 to 28 , various embodiments for solving the above problems are described. The following omitted description can be seen by Figures 1 to 10 And the above description related to this figure is easily understood.

[0146] [First embodiment]

[0147] Fig.11 is a plan view showing the display device of the first embodiment. Fig.12 is a cross-sectional view showing the display device of the first embodiment.

[0148] Reference Fig.11 and Fig.12 The display device 300 of the first embodiment may include a substrate 310 , a first assembly wiring 321 , a second assembly wiring 322 , a partition wall 340 , a semiconductor light emitting device 150 , and connection electrodes 371 , 372 .

[0149] The substrate 310 may be a supporting member that supports a plurality of components disposed on the substrate 310 or a protecting member that protects a plurality of components.

[0150] The first assembly substrate 321 and the second assembly wiring 322 can be respectively arranged on the substrate 310. For example, the first assembly substrate 321 and the second assembly wiring 322 can be respectively arranged on the same layer. For example, the first assembly wiring 321 and the second assembly wiring 322 can be connected to the top surface of the substrate 310, but is not limited thereto. For example, the first assembly substrate 321 and the second assembly wiring 322 can be respectively arranged on the same layer. For example, the first assembly substrate 321 and the second assembly wiring 322 can be arranged side by side with each other. The first assembly substrate 321 and the second assembly wiring 322 can respectively play the role of assembling the semiconductor light emitting device 150 to the assembly hole 361 in a self-assembly manner. That is, during self-assembly, under the action of the voltage supplied to the first assembly wiring 321 and the second assembly wiring 322, an electric field can be generated between the first assembly wiring 321 and the second assembly wiring 322, and under the action of the dielectrophoretic force formed by the electric field, due to the assembly device ( Fig.10 1100) and the semiconductor light emitting device 150 in motion may be assembled to the assembly hole 361. The assembly hole 361 may have a diameter D11 larger than the diameter D1 of the semiconductor light emitting device.

[0151] Although not shown in the figure, the first built-up wiring 321 and the second built-up wiring 322 may be arranged on different layers.

[0152] The partition wall 340 may be disposed on the first assembly wiring 321 and the second assembly wiring 322. The partition wall 340 may have an assembly hole 361 and auxiliary holes 362 and 363 for assembling the semiconductor light emitting device 150. For example, the first insulating layer 330 may be exposed into the assembly hole 361 and the auxiliary holes 362 and 363. For example, the bottom surface of the assembly hole 361 may be the top surface of the insulating layer 330. The auxiliary holes 362 and 363 may extend toward the outer side of the assembly hole 361.

[0153] The thickness of the partition wall 340 may be determined in consideration of the thickness T2 of the semiconductor light emitting device 150. For example, the thickness T1 of the partition wall 340 may be smaller than the thickness T2 of the semiconductor light emitting device 150. Therefore, the upper side of the semiconductor light emitting device 150 may be located at a higher position than the top surface of the partition wall 340. That is, the upper side of the semiconductor light emitting device 150 may protrude from the top surface of the partition wall 340 toward the upper direction.

[0154] The size of the assembly hole 361 may be determined in consideration of a tolerance margin for forming the assembly hole 361 and a margin for easily assembling the semiconductor light emitting device 150 into the assembly hole 361. For example, the size of the assembly hole 361 may be larger than the size of the semiconductor light emitting device 150. For example, when the semiconductor light emitting device 150 is assembled to the center of the assembly hole 361, the distance between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361 may be 2 μm or less, but is not limited thereto. For example, when the semiconductor light emitting device 150 is assembled to the center of the assembly hole 361, the interval L1 between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361 may be 1.5 μm or less.

[0155] For example, the assembly hole 361 may have a shape corresponding to the shape of the semiconductor light emitting device 150. For example, when the semiconductor light emitting device 150 is circular, the assembly hole 361 may also be circular. For example, when the semiconductor light emitting device 150 is rectangular, the assembly hole 361 may also be rectangular.

[0156] The partition wall 340 may have at least one auxiliary hole 362 , 363 extending in a lateral direction of the assembling hole 361 .

[0157] For example, the auxiliary holes may include a first auxiliary hole 362 formed on the first assembly wiring 321 and a second auxiliary hole 363 formed on the second assembly wiring 322. For example, the first auxiliary hole 362 and the second auxiliary hole 363 may be arranged along the Y direction. For example, the first auxiliary hole 362 may be formed by extending from the assembly hole 361 along the -Y direction, and the second auxiliary hole 363 may be formed by extending from the assembly hole 361 along the +Y direction.

[0158] The first auxiliary hole 362 and the second auxiliary hole 363 may be arranged symmetrically with each other. Fig.11 As shown, the first auxiliary hole 362 can be configured from the assembly hole 361 along the -Y axis direction, that is, perpendicularly across the direction of the first assembly wiring, and the second auxiliary hole 363 can be configured from the assembly hole 361 along the +Y axis direction, that is, perpendicularly across the direction of the second assembly wiring.

[0159] On the other hand, the auxiliary holes 362 and 363 may have enough space to allow the metal film used to form the connecting electrodes 371 and 372 to be deposited continuously without being disconnected. For example, the width W11 and the length L11 of the auxiliary holes 362 and 363 may be the same, but are not limited thereto. For example, the width W11 may be 2 μm to 4 μm. For example, the length L11 may be 2 μm to 4 μm. In the case where the width W11 or the length L11 is less than 2 μm, the metal film may be disconnected due to the narrow space of the auxiliary holes 362 and 363. In the case where the width W11 or the length L11 exceeds 4 μm, another semiconductor light-emitting device is attached to the auxiliary holes 362 and 363 during self-assembly due to the enlarged space, resulting in poor assembly and waste of semiconductor light-emitting devices, which may lead to increased manufacturing costs.

[0160] For example, the width W11 or length L11 of the auxiliary holes 362 and 363 may be greater than the interval L1 between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361. The width W11 or length L11 of the auxiliary holes 362 and 363 is greater than the interval L1 between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361. Therefore, when the metal film is deposited on the auxiliary holes 362 and 363 to form the connection electrodes 371 and 372, no electrical disconnection is formed in the connection electrodes 371 and 372, thereby preventing poor lighting.

[0161] For example, the length L11 of the auxiliary holes 362 and 363 may be smaller than the width W1 and W2 of the first assembly wiring 321 or the second assembly wiring 322. In the case where the length L11 of the auxiliary holes 362 and 363 is larger than the width W1 and W2 of the first assembly wiring 321 or the second assembly wiring 322, an electrical short circuit may occur between the first assembly wiring 321 and / or the second assembly wiring 322 of the pixel configuration adjacent to the connection electrodes 371 and 372 configured in the auxiliary holes 362 and 363.

[0162] On the other hand, as described above, due to the auxiliary holes 362 and 363, unnecessary dielectrophoretic force increases, so that assembly failure or color mixing failure caused by the dual semiconductor light emitting device may occur.

[0163] According to the embodiment, the partition wall 340 is composed of a first partition wall layer 341 and a second partition wall layer 342, and the first partition wall layer 341 is arranged in the auxiliary holes 362 and 363 before self-assembly, thereby preventing poor assembly or poor color mixing caused by an unnecessary increase in dielectrophoretic force during self-assembly.

[0164] According to an embodiment, after the semiconductor light emitting device 150 is assembled into the assembly hole 361 using a self-assembly process, the first partition wall layer 341 on the auxiliary holes 362 and 363 is removed, so that the connecting electrodes 371 and 372 to be subsequently formed on the side of the semiconductor light emitting device 150 will not be broken.

[0165] The first partition wall layer 341 on the auxiliary holes 362 and 363 may be removed by an ashing process. For example, the first partition wall layer 341 and the second partition wall layer 342 may be composed of organic substances having different viscosities from each other. For example, the viscosity of the first partition wall layer 341 may be equal to or less than the viscosity of the second partition wall layer 342. For example, the first partition wall layer 341 may have a viscosity of 10 cp or less under HI-900. For example, the second partition wall layer 342 may be about 90 cp under JSR.

[0166] The viscosity and the ashing rate (or etching rate) may be in an inversely proportional relationship. For example, as the viscosity decreases, the ashing rate may increase. Thus, the ashing rate of the first partition wall layer 341 may be equal to or greater than the ashing rate of the second partition wall layer 342.

[0167] In the backplane substrate, the thickness of the second partition wall layer 342 may be greater than the thickness of the first partition wall layer 341. Then, an ashing process is performed, whereby the first partition wall layer 341 on the auxiliary holes 362 and 363 is removed, so that a margin space for electrical connection on the side of the semiconductor light emitting device 150 can be sufficiently ensured. Then, by using a deposition process, connecting electrodes 371 and 372 are formed on the side of the semiconductor light emitting device 150 through the auxiliary holes 362 and 363, so that disconnection defects of the connecting electrodes 371 and 372 can be prevented. A more detailed description will be given later.

[0168] On the other hand, the thickness T1 of the partition wall 340 is smaller than the thickness T2 of the semiconductor light-emitting device 150 , so that the metal film to be formed into the connecting electrodes 371 , 372 can be more easily deposited on the interval L1 between the outer side surface of the semiconductor light-emitting device 150 and the inner side surface of the assembly hole 361 , thereby reducing the disconnection of the connecting electrodes 371 , 372 .

[0169] On the other hand, the semiconductor light emitting device 150 may be disposed in the assembly hole 361 .

[0170] The semiconductor light emitting device 150 may include one of a red semiconductor light emitting device generating red light, a green semiconductor light emitting device generating green light, and a blue semiconductor light emitting device generating blue light.

[0171] For example, during self-assembly, Fig.10The dispersed red semiconductor light emitting devices, green semiconductor light emitting devices and blue semiconductor light emitting devices are simultaneously moved by the same assembly device 1100 so as to be assembled into corresponding sub-pixels ( Figure 6 The respective assembly holes 361 of PX1, PX2, PX3).

[0172] In sub-pixel ( Figure 6 In the case where the sizes of the respective assembly holes 361 of the PX1, PX2, and PX3 are the same, the red semiconductor light emitting device, the green semiconductor light emitting device, and the blue semiconductor light emitting device may be assembled to other assembly holes 361 instead of the assembly hole 361 to be assembled. In order to solve this problem, the shapes of the red semiconductor light emitting device, the green semiconductor light emitting device, and the blue semiconductor light emitting device may be set differently, and the assembly holes 361 may be formed corresponding to the shapes of the different red semiconductor light emitting devices, the green semiconductor light emitting devices, and the blue semiconductor light emitting devices. That is, poor assembly or poor color mixing can be prevented by improving the exclusivity between the plurality of semiconductor light emitting devices 150.

[0173] For example, the shape of the red semiconductor light emitting device may be a circle, the shape of the green semiconductor light emitting device may be a first ellipse having a first short axis and a first long axis, and the shape of the blue semiconductor light emitting device may be a second ellipse having a second short axis shorter than the first short axis and a second long axis larger than the first long axis.

[0174] The semiconductor light emitting device 150 may be disposed in the assembly hole 361 and generate colored light. As described above, the semiconductor light emitting device 150 may include one of a red semiconductor light emitting device, a green semiconductor light emitting device, and a blue semiconductor light emitting device. For example, the red semiconductor light emitting device may be disposed in the first sub-pixel ( Fig. 9 The green semiconductor light emitting device may be configured in the second sub-pixel PX1, and the blue semiconductor light emitting device may be configured in the third sub-pixel PX3. Therefore, a full-color image may be displayed using red light emitted from the first sub-pixel PX1, green light emitted from the second sub-pixel PX2, and blue light emitted from the third sub-pixel PX3.

[0175] The semiconductor light emitting device 150 of the embodiment may be a vertical semiconductor light emitting device, but is not limited thereto. In this case, after the semiconductor light emitting device 150 is assembled to the assembly hole 361, the electrode 154 of the semiconductor light emitting device 150 may be electrically connected to the lower electrode wiring, that is, the first assembly wiring 321 or the second assembly wiring 322, and the upper side of the semiconductor light emitting device 150 may be electrically connected to the electrode wiring 380.

[0176] On the other hand, the semiconductor light emitting device 150 may include light emitting portions 151, 152, 153, an electrode 154, and a passivation layer 157. The semiconductor light emitting device 150 of the first embodiment may include more components.

[0177] The light emitting units 151 , 152 , and 153 may include a first conductive type semiconductor layer 151 , an active layer 152 , and a second conductive type semiconductor layer 153 , but may include more components.

[0178] The first conductive type semiconductor layer 151 may include a first conductive type dopant, and the second conductive type semiconductor layer 153 may include a second conductive type dopant. For example, the first conductive type dopant may be an n-type dopant such as silicon (Si), and the second conductive type dopant may be a p-type dopant such as boron (B).

[0179] The electrode 154 may be disposed on the lower side of the first conductive semiconductor layer 151. The electrode 154 may include at least one layer. For example, the electrode 154 may include: a bonding layer for bonding the semiconductor light emitting device 150 to the substrate 310; and a bonding layer for bonding the bonding layer to the lower side of the light emitting portion 151, 152, 153, such as the first conductive semiconductor layer 151. For example, the bonding layer may be composed of indium (In), tin (Sn), etc. For example, the bonding layer 154_2 may be composed of titanium (Ti), chromium (Cr), etc.

[0180] Although not shown, a second electrode may be disposed on the second conductive semiconductor layer 153. The second electrode may include at least one layer. The second electrode may include a transparent conductive layer and a magnetic layer. The transparent conductive layer may be composed of a transparent conductive material, such as ITO. The transparent conductive layer may obtain a current diffusion effect that causes the current generated by the voltage supplied from the electrode wiring 380 to diffuse uniformly to the entire area of ​​the second conductive semiconductor layer 153. That is, due to the transparent conductive layer, the current is uniformly diffused to the entire area of ​​the second conductive semiconductor layer 153, thereby generating holes in the entire area of ​​the second conductive semiconductor layer 153, and thus the amount of light generated by the recombination of holes and electrons in the active layer 152 is increased by increasing the amount of hole generation, thereby improving the light efficiency. The increase in light efficiency may lead to an increase in brightness.

[0181] The magnetic layer may include nickel (Ni), cobalt (Co), iron (Fe), etc. The magnetic layer may include SmCo, Gd-based, La-based, and Mn-based metals. The magnetic layer is magnetized by a magnetic body disposed in the assembly device 1100 during self-assembly, thereby playing a role in causing an attractive force to act between the semiconductor light-emitting device 150 and the magnetic body. Therefore, during self-assembly, as the magnetic body moves, the semiconductor light-emitting device 150 moves faster and more rapidly, thereby shortening the process time and improving the assembly yield rate.

[0182] The passivation layer 157 may protect the light emitting parts 151 , 152 , and 153 .

[0183] The passivation layer 157 prevents the semiconductor light emitting device 150 from being turned over during self-assembly, and can make the lower side of the semiconductor light emitting device 150, that is, the bottom surface of the first conductive type semiconductor layer 151 face the top surface of the first insulating layer 330. Therefore, during self-assembly, the lower side of the semiconductor light emitting device 150 faces the first insulating layer 330 and the upper side of the semiconductor light emitting device 150 is arranged in an upward direction, thereby preventing the semiconductor light emitting device 150 from being turned over and assembled and misaligned.

[0184] The connection electrodes 371 and 372 may be disposed in the auxiliary holes 362 and 363 of the partition wall 340. The connection electrodes 371 and 372 may be electrically connected to the side of the semiconductor light emitting device 150 in the auxiliary holes 362 and 363 of the partition wall 340. The auxiliary holes 362 and 363 are provided to be larger than the interval L1 between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361, and the connection electrodes 371 and 372 are formed through the auxiliary holes 362 and 363, so that the connection electrodes 371 and 372 are not disconnected.

[0185] For example, first sides of the connection electrodes 371 , 372 may be electrically connected to the first assembly wiring 321 and / or the second assembly wiring 322 through the first insulating layer 330 , and second sides of the connection electrodes 371 , 372 may be electrically connected to the side of the semiconductor light emitting device 150 .

[0186] For example, the connection electrodes 371 and 372 may be formed of at least one layer having excellent conductivity. For example, the connection electrodes 371 and 372 may include a first layer including molybdenum (Mo), a second layer including aluminum (Al), and a third layer including molybdenum (Mo).

[0187] According to the non-disclosed internal technology, the interval L1 between the inner side of the assembly hole 361 and the outer side of the semiconductor light emitting device 150 is very narrow, and the metal film used to form the connection electrodes 371 and 372 is deposited on the area with the narrow interval L1, so the metal film is disconnected and discontinuously connected. Even if the metal film is patterned to form the connection electrodes 371 and 372, an electrical disconnection occurs at the disconnected portion, resulting in poor lighting.

[0188] However, according to the embodiment, auxiliary holes 362 and 363 are formed by extending laterally from the assembly hole 361 of the partition wall 340 for assembling the semiconductor light-emitting device 150, and connecting electrodes 371 and 372 are arranged in the auxiliary holes 362 and 363, so that the connecting electrodes 371 and 372 are electrically connected to the side of the semiconductor light-emitting device 150 without being disconnected, thereby preventing poor lighting.

[0189] That is, the auxiliary holes 362 and 363 extending from the assembly hole 361 may be hollow spaces where the semiconductor light emitting device 150 is not configured. Therefore, after the semiconductor light emitting device 150 is assembled to the assembly hole 361, when the metal film is deposited on the partition wall 340 and the semiconductor light emitting device 150, the interval L1 between the inner side surface of the auxiliary holes 362 and 363 and the outer side surface of the semiconductor light emitting device 150 configured in the assembly hole 361 is increased by at least the extension length L11 of the auxiliary holes 362 and 363, so that the metal film deposited on the area between the inner side surface of the auxiliary holes 362 and 363 and the outer side surface of the semiconductor light emitting device 150 configured in the assembly hole 361 can be continuously connected without disconnection. Therefore, when the metal film is patterned to form the connection electrodes 371 and 372, the connection electrodes 371 and 372 are electrically connected to the side of the semiconductor light emitting device 150 without being electrically disconnected, thereby preventing poor lighting.

[0190] On the other hand, the connection electrode may include a first connection electrode 371 disposed in the first auxiliary hole 362 and a second connection electrode 372 disposed in the second auxiliary hole 363 .

[0191] For example, the first connection electrode 371 may be electrically connected to the first side 158a of the semiconductor light emitting device 150 through the assembly hole 361 in the first auxiliary hole 362. For example, the second connection electrode 372 may be electrically connected to the second side 158b of the semiconductor light emitting device 150 through the assembly hole 361 in the second auxiliary hole 363.

[0192] In an embodiment, although two connecting electrodes, namely the first connecting electrode 371 and the second connecting electrode 372, are electrically connected to the side of the semiconductor light emitting device 150, it is also possible that only one of the first connecting electrode 371 and the second connecting electrode 372 is connected to the side of the semiconductor light emitting device 150, and the other connecting electrode is omitted.

[0193] Each of the first connection electrode 371 and the second connection electrode 372 may include: a first connection region 371_1, 372_1, which is connected to the side of the semiconductor light-emitting device 150; a second connection region 371_2, 372_2, which extends from the first connection region 371_1, 372_1 and is connected to the top surface of one of the first assembly wiring 321 and the second assembly wiring 322; and a third connection region 371_3, 372_3, which extends from the second connection region 371_2, 372_2 and is connected to the inner side surface of the auxiliary holes 362, 363.

[0194] The upper side of the first connection region 371_1 and 372_1 may be connected to the passivation layer 157 of the semiconductor light emitting device 150 , and the lower side of the first connection region 371_1 and 372_1 may be connected to the side surface of the first conductive semiconductor layer 151 of the semiconductor light emitting device 150 and / or the side surface of the electrode 154 .

[0195] The first connection regions 371_1 and 372_1 and the third connection regions 371_3 and 372_3 may have the same height, but are not limited thereto.

[0196] On the other hand, although not shown, the connection electrode may be disposed along the periphery of the semiconductor light emitting device 150 in the assembly hole 361. For example, the connection electrode may be disposed between the inner side surface of the assembly hole 361 and the outer side surface of the semiconductor light emitting device 150.

[0197] For example, a first side of the connection electrode of the assembly hole 361 may be connected to the first connection electrode 371 in the auxiliary holes 362 , 363 , and a second side of the connection electrode of the assembly hole 361 may be connected to the second connection electrode 372 in the auxiliary holes 362 , 363 .

[0198] On the other hand, the assembly hole 361 and the auxiliary holes 362 and 363 are connected, so when a metal film is deposited to form the connection electrodes 371 and 372, the deposited film can be formed by continuous connection between the assembly hole 361 and the auxiliary holes 362 and 363. Therefore, the connection electrode of the assembly hole 361 can be connected to the first connection electrode 371 and / or the second connection electrode 372 through the auxiliary holes 362 and 363.

[0199] Therefore, the first connection regions 371_1 and 372_1 may be connected to the side of the semiconductor light emitting device 150 along the periphery of the semiconductor light emitting device 150 in the assembly hole 361, and the second connection region 273_2 may be connected to the top surface of one of the first assembly wiring 321 and the second assembly wiring 322 along the periphery of the semiconductor light emitting device 150 in the auxiliary holes 362 and 363. In addition, the second connection region 273_2 of the assembly hole 361 may extend from the auxiliary holes 362 and 363 to the second connection regions 371_2 and 372_2 and connect to the inner side surfaces of the auxiliary holes 362 and 363.

[0200] According to the embodiment, the connecting electrodes 371, 372 are not only arranged in the assembly hole 361, but also in the auxiliary holes 362, 363, and are attached to the side of the semiconductor light-emitting device 150, the top surface of the first assembly wiring 321 and / or the second assembly wiring 322 through the first insulating layer 330, and the inner side surfaces of the assembly hole 361 and the auxiliary holes 362, 363, so that the bonding force of the semiconductor light-emitting device 150 can be strengthened, thereby improving reliability.

[0201] On the other hand, the first connection electrode 371 may have a first groove 376, and the second connection electrode 372 may have a second groove 377. The first groove 376 and the second groove 377 form a metal film in a region with a sufficient space margin for deposition, and the thickness of the metal film may also be formed thin.

[0202] On the other hand, the display device 300 of the first embodiment may include a first insulating layer 330 , a second insulating layer 350 , a third insulating layer 360 , and an electrode wiring 380 .

[0203] The first insulating layer 330 may be disposed on the substrate 310. For example, the first insulating layer 330 may be composed of an inorganic substance or an organic substance. For example, the first insulating layer 330 may be composed of a substance having a dielectric constant related to the dielectrophoretic force.

[0204] The second insulating layer 350 may be disposed in each of the first groove 376 and the second groove 377. As will be described later in the manufacturing process, the partition wall 340 may function as a stopper for determining the height of the connection electrodes 371 and 372. That is, the connection electrodes 371 and 372 may be formed to have a height equivalent to the height of the second insulating layer 350. That is, if the height of the second insulating layer 350 is increased, the height of the connection electrodes 371 and 372 may also be increased.

[0205] The third insulating layer 360 may be disposed on the partition wall 340 and the second insulating layer 350. The third insulating layer 360 may be a planarization layer for easily forming the electrode wiring 380 or other layers. Therefore, the top surface of the third insulating layer 360 may have a flat surface. The first to third insulating layers 330, 350, 360 may be formed of an organic substance or an inorganic substance. For example, at least one insulating layer of the first to third insulating layers 330, 350, 360 may be composed of an organic substance. For example, at least two insulating layers of the first to third insulating layers 330, 350, 360 may be composed of the same substance.

[0206] The electrode wiring 380 may be disposed on the third insulating layer 360 and may be electrically connected to the semiconductor light emitting device 150 through the third insulating layer 360. For example, the electrode wiring 380 may be electrically connected to the upper side of the light emitting portions 151, 152, 153 through the third insulating layer 360 and the passivation layer 157 of the semiconductor light emitting device 150.

[0207] Therefore, under the action of the voltage supplied to the first assembled wiring 321 and / or the second assembled wiring 322 and the electrode wiring 380, the semiconductor light emitting device 150 may emit light.

[0208] According to the first embodiment, the partition wall 340 includes a first partition wall layer 341 and a second partition wall layer 342 having different ashing rates from each other. Before self-assembly, the first partition wall layer 341 is arranged on the auxiliary holes 362 and 363 to prevent poor assembly or poor color mixing. After self-assembly, the first partition wall layer 341 on the auxiliary holes 362 and 363 is removed, thereby preventing the connection electrodes 371 and 372 from being disconnected.

[0209] According to the first embodiment, the connecting electrodes 371, 372 are not only arranged in the assembly hole 361, but also in the auxiliary holes 362, 363, and are attached to the side of the semiconductor light-emitting device 150, the top surface of the first assembly wiring 321 and / or the second assembly wiring 322 through the first insulating layer 330, and the inner side surfaces of the assembly hole 361 and the auxiliary holes 362, 363, so that the bonding force of the semiconductor light-emitting device 150 can be strengthened, thereby improving reliability.

[0210] On the other hand, as described above, when the partition wall 340 in the auxiliary holes 362 and 363 is completely removed, during self-assembly, under the action of unnecessary dielectrophoretic forces formed in the auxiliary holes 363 and 363, more than two semiconductor light-emitting devices are assembled into the assembly hole 361, resulting in poor assembly or poor color mixing.

[0211] In the embodiment, depending on the self-assembly, a portion of the partition wall 340 is retained or completely removed in the auxiliary holes 362 and 363, thereby preventing poor assembly or poor color mixing. In addition, due to the space margin of the auxiliary holes 362 and 363, the disconnection of the connecting electrodes 371 and 372 can also be prevented.

[0212] First, you can set Fig.13 The backplane substrate 300A is shown. The backplane substrate 300A may be a base substrate for manufacturing the display device 300 by performing a self-assembly process and subsequent processes such as electrical connection.

[0213] A partition wall 340 including a first assembly wiring 321 and / or a second assembly wiring 322 , an insulating layer 330 , an assembly hole 361 , and auxiliary holes 362 and 363 may be formed on the substrate 310 , thereby manufacturing the backplane substrate 300A.

[0214] The partition wall 340 may be formed with a first partition wall layer 341 and a second partition wall layer 342 located on the first partition wall layer. The first partition wall layer 341 may be formed in the auxiliary hole but not in the assembly hole 361. That is, the first partition wall layer 341 may be formed on the substrate 310 except for the assembly hole 361. The second partition wall layer 342 may not be formed in the assembly hole 361 and the auxiliary holes 362, 363. That is, the second partition wall layer 342 may be formed on the substrate 310 except for the assembly hole 361 and the auxiliary holes 362, 363.

[0215] The first partition wall layer 341 does not vertically overlap the assembly hole 361, but may vertically overlap the auxiliary holes 362, 363. The second partition wall layer 342 may not vertically overlap each of the assembly hole 361 and the auxiliary holes 362, 363.

[0216] The partition wall 340 may have a multi-stage structure including a first partition wall layer 341 and a second partition wall layer 342 when viewed from the assembly hole 361 toward the outside. That is, the end of the second partition wall layer 342 may be spaced apart from the end of the first partition wall layer 341 toward the outside in the auxiliary holes 362 and 363, so that the second partition wall layer 342 may not overlap vertically with the auxiliary holes 362 and 363.

[0217] On the other hand, although not shown in the figure, a pixel circuit for each of the plurality of pixels and a plurality of signal lines connected to each pixel circuit may be provided on the backplane substrate 300A. The signal line may include Figure 6 and Figure 7 The shown devices include a plurality of data lines D1 -Dm, a plurality of scanning lines S1 -Sn, a high potential voltage line VDDL, a low potential voltage line VSSL, and the like.

[0218] like Fig.14 As shown, by performing a self-assembly process and subsequent processes on the back panel substrate 300A, a display device 300 in which the semiconductor light emitting devices 150 are arranged in respective pixels and electrically connected can be manufactured.

[0219] A backplane substrate 300A may be provided. Fig.15 As shown in (a), an assembly hole 361 may be provided on the backplane substrate 300A. As described above, the assembly hole 361 may be formed by the first partition wall layer 341 and the second partition wall layer 342 constituting the partition wall 340. That is, the first partition wall layer 341 and the second partition wall layer 342 are removed from each of the plurality of pixels, thereby forming the assembly hole 361 exposing the insulating layer 330. Fig.13 As shown, the first partition wall layer 341 is formed in the auxiliary holes 362 and 363, but the auxiliary holes 362 and 363 are not formed in a complete form. Fig.15 The auxiliary holes 362, 363 are not shown in (a).

[0220] like Fig.15 As shown in (b), an assembly process is performed so that the semiconductor light emitting device 150 can be assembled to the assembly hole 361. Then, an ashing process is performed so that the first partition wall layer 341 on the auxiliary holes 362 and 363 is removed to expose the insulating layer 330, thereby ensuring a space margin on the side of the semiconductor light emitting device 150.

[0221] like Fig.15 As shown in (c), a deposition process is performed to deposit a metal film in the auxiliary holes 362 and 363 where a sufficient space margin is ensured, thereby preventing disconnection of the connection electrodes 371 and 372 formed by a subsequent patterning process, thereby preventing lighting failure.

[0222] Figures 16 to 20 The process of manufacturing a display device using a backplane substrate according to the first embodiment is shown.

[0223] like Fig.16 As shown, a backplane substrate 300A may be provided.

[0224] For example, the backplane substrate 300A may be mounted in a chamber ( Fig.10 The semiconductor light emitting device 150 is placed in the fluid 1200 before the backplane substrate 300A is installed in the chamber 1300 or after the backplane substrate 300A is installed in the chamber 1300.

[0225] like Fig.13 As shown, a partition wall 340 having a first assembly wiring 321 and / or a second assembly wiring 322, an insulating layer 330, an assembly hole 361, and auxiliary holes 362 and 363 may be formed on the substrate 310, thereby manufacturing the backplane substrate 300A. The partition wall 340 has a multi-segment structure, the first partition wall layer 341 and the second partition wall layer 342 are not formed in the assembly hole 361, only the first partition wall layer 341 is formed in the auxiliary holes 362 and 363, and the first partition wall layer 341 and the second partition wall layer 342 may be formed on the substrate 310 other than this. The thickness T13 of the second partition wall layer 342 may be equal to or greater than the thickness T11 of the first partition wall layer 341.

[0226] On the other hand, an AC voltage may be applied to the first and second assembly wirings 321 and 322, thereby forming a dielectrophoretic force in the assembly hole 361. At this time, due to the thickness T11 of the first partition wall layer 341, the dielectrophoretic force is weak or may not be formed in the auxiliary holes 362 and 363.

[0227] Then, due to the zigzag movement or rotational motion of the magnet, the semiconductor light emitting device 150 in the fluid 1200 can move with the magnet. When the moving semiconductor light emitting device 150 passes through the corresponding assembly hole 361, the semiconductor light emitting device 150 can be assembled to the assembly hole 361 due to the dielectrophoretic force formed in the corresponding assembly hole 361.

[0228] like Fig.17 As shown, by performing the ashing process, the first partition wall layer 341 on the auxiliary holes 362 and 363 can be removed, and the first insulating layer 330 can be exposed. Thus, the first partition wall layer 341 located in the lateral direction of the semiconductor light emitting device 150 assembled to the assembly hole 361 is removed, and thus, due to the removal of the auxiliary holes 362 and 363 of the first partition wall layer 341, the space margin in the lateral direction of the semiconductor light emitting device 150 can be sufficiently ensured.

[0229] On the other hand, the top surface of the second partition wall layer 342 is removed by the ashing process, so the thickness of the second partition wall layer 342 can be reduced from T13 to T12. In this case, the thickness T12 of the second partition wall layer 342 can be equal to or less than the thickness T11 of the first partition wall layer 341.

[0230] like Fig.18 As shown, by performing an etching process, the first insulating layer 330 exposed to the assembly hole 361 and the auxiliary holes 362 and 363 is removed, so that the first assembly wiring 321 and / or the second assembly wiring 322 can be exposed.

[0231] Then, a metal film 370 may be deposited on the partition wall 340 and the semiconductor light emitting device 150. The metal film 370 is deposited to the auxiliary holes 362 and 363 where sufficient space margin is ensured, and thus has a sufficient thickness through the auxiliary holes 362 and 363, thereby preventing disconnection defects.

[0232] On the other hand, since the auxiliary holes 362 and 363 are relatively large in size, the metal film in the auxiliary holes 362 and 363 can form grooves 376 and 377 .

[0233] Then, an insulating film 351 may be formed on the metal film 370. The insulating film may be formed on the grooves 376 and 377 and the entire region of the substrate 310. The insulating film 351 may be formed of an organic material that can be easily formed to a thick thickness, but an inorganic material may also be used.

[0234] like Fig.19 As shown, by performing an ashing process, the remaining insulating film 351 except the insulating film 351 formed in the grooves 376 and 377 can be removed. The insulating film 351 formed in the grooves 376 and 377 can become the second insulating layer 350.

[0235] Then, by performing an etching process, the metal film 370 is etched, so that the connection electrodes 371 and 372 can be formed.

[0236] The first connection electrode 371 may include: a first connection region 371_1, which is connected to the first side of the semiconductor light emitting device 150, such as the electrode 154; a second connection region 371_2, which extends from the first connection region 371_1 and is connected to the top surface of the first assembly wiring 321 and / or the second assembly wiring 322; and a third connection region 371_3, which extends from the second connection region 371_2 and is connected to the inner side of the first auxiliary hole 362. Similarly, the second connection electrode 372 may include: a first connection region 372_1, which is connected to the second side of the semiconductor light emitting device 150, such as the electrode 154; a second connection region 372_2, which extends from the first connection region 372_1 and is connected to the top surface of the first assembly wiring 321 and / or the second assembly wiring 322; and a third connection region 372_3, which extends from the second connection region 372_2 and is connected to the inner side of the second auxiliary hole 363.

[0237] The second insulating layer 350 may function as a stopper that prevents the metal film 370 from being further etched below the top surface of the insulating film 351 .

[0238] like Fig. 20 As shown, a third insulating layer 360 may be formed on the entire area of ​​the substrate 310, such as the partition wall 340, the second insulating layer 350 and the semiconductor light emitting device 150, and the third insulating layer 360 and the passivation layer 157 of the semiconductor light emitting device 150 may be removed to form a contact hole.

[0239] Then, an electrode wiring 380 is formed on the third insulating layer 360 so that the electrode wiring 380 can be electrically connected to the upper side of the semiconductor light emitting device 150 through the contact hole.

[0240] On the other hand, the backplane substrate 300B may be provided with Fig.21 The partition wall 340 shown has a multi-segment structure.

[0241] like Fig.21 As shown, the partition wall 340 may include a first partition wall layer 341 and a second partition wall layer 342. The first partition wall layer 341 and the second partition wall layer 342 may not be formed in the assembly hole 361. Fig.13 Differently, the auxiliary holes 362 , 363 may be formed with the second partition wall layer 342 .

[0242] The first partition wall layer 341 and the second partition wall layer 342 may be formed on the substrate 310 except for the assembly hole 361 and the auxiliary holes 362 and 363. At this time, the second partition wall layer 342 may be formed on the first partition wall layer 341.

[0243] The manufacturing process of the backplane substrate 300B of the second embodiment is as follows. First, a first assembly wiring 321, a second assembly wiring 322, and an insulating layer 330 may be formed on the substrate 310. A first insulating film is formed on the insulating layer 330, and the first insulating film corresponding to each of the plurality of pixels is removed, so that an assembly hole 361 in which the insulating layer 330 is exposed can be formed. The first insulating film except the assembly hole 361 can become a first partition wall layer 341 having a thickness T11.

[0244] Then, a second insulating film may be formed on the first insulating film, and an exposure process may be performed using a halftone mask. At this time, when the second insulating film is formed of a passive photosensitive material, the halftone mask may have a first region, a second region, and a third region, wherein the first region has a transmittance of 0% in the second insulating film corresponding to the assembly hole 361, the second region has a transmittance of less than 30% in the second insulating film corresponding to the auxiliary holes 362 and 363, and the third region has a transmittance of 100% in the second insulating film on the substrate 310 other than the second insulating film.

[0245] By performing exposure and development processes, the second insulating film corresponding to the assembly hole 361 is removed, thereby exposing the insulating layer 330, and the top surface of the second insulating film corresponding to the auxiliary holes 362 and 363 is removed to form a second partition wall layer 342 with reduced thickness. The second insulating film corresponding to the substrate 310 other than this is not removed, so that a second partition wall layer 342 having a thickness T22 greater than the thickness T21 of the second partition wall layer 342 on the auxiliary holes 362 and 363 can be formed.

[0246] The display device 301 can be manufactured using the backplane substrate 300B of the second embodiment.

[0247] like Fig. 22 As shown, after the semiconductor light emitting device 150 is assembled to the assembly hole 361 on the substrate 310 by the assembly process, the second partition wall layer 342 on the auxiliary holes 362 and 363 can be removed by the ashing process. At this time, the thickness T22 of the second partition wall layer 342 on the substrate 310 except the assembly hole 361 and the auxiliary holes 362 and 363 is greater than the thickness T21 of the second partition wall layer 342 on the auxiliary holes 362 and 363. Therefore, even if the second partition wall layer 342 on the auxiliary holes 362 and 363 is removed, the second partition wall layer 342 on the substrate 310 except the assembly hole 361 and the auxiliary holes 362 and 363 can still have a prescribed thickness T23 and remain. The thickness of the second partition wall layer 342 on the substrate 310 except the assembly hole 361 and the auxiliary holes 362 and 363 can be reduced from T22 to T23.

[0248] [Second embodiment]

[0249] Fig.23 is a plan view showing a display device according to a second embodiment. Fig.24 It is a cross-sectional view taken along line E1 - E2 of the display device of the second embodiment. Fig.25 It is a cross-sectional view taken along line F1 - F2 of the display device of the second embodiment.

[0250] The second embodiment is the same as the first embodiment except that the interval L1+L2 between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the expansion hole 364 is greater than that of the first embodiment. In the second embodiment, for the components having the same shape, structure and / or function as those of the first embodiment, the same reference numerals are given and detailed description is omitted.

[0251] Reference Figure 23 to Figure 25 The display device 301 of the second embodiment may include a substrate 310, a first assembly wiring 321, a second assembly wiring 322, a first insulating layer 330, a partition wall 340, a second insulating layer 350, connecting electrodes 371, 372, a third insulating layer 360 and an electrode wiring 380.

[0252] The partition wall 340 may include an assembly hole 361. The partition wall 340 may have an expansion hole 364 having a second diameter D22 greater than a first diameter D11 of the assembly hole 361. In this case, the expansion hole 364 may be larger than the assembly hole 361 by an interval L2 along the periphery of the assembly hole 361.

[0253] When the semiconductor light emitting device 150 is assembled to the assembly hole 361, there is a gap of L1 between the outer side of the semiconductor light emitting device 150 and the assembly hole 361, so there may be a gap of L1+L2 between the outer side of the semiconductor light emitting device 150 and the expansion hole 364. That is, the expansion hole 364 may be larger than the semiconductor light emitting device 150 by a gap of L1+L2 along the periphery of the semiconductor light emitting device 150. Here, L2 may be 2 μm or more, but is not limited thereto.

[0254] The auxiliary holes 362 and 363 may extend toward the outside of the expansion hole 364. The auxiliary holes 362 and 363 may be connected or communicated with the expansion hole 364.

[0255] The connection electrodes 371 and 372 may be disposed on the region other than the semiconductor light emitting device 150 in the auxiliary holes 362 and 363 and the expansion hole 364. Here, the region other than the semiconductor light emitting device 150 may be a region corresponding to L1+L2.

[0256] The connection electrodes 371 and 372 may be formed by patterning after depositing the metal film in a deposition process. In this case, the metal film is deposited in a region with a sufficient space margin along the side direction of the semiconductor light emitting device 150, so it can be deposited thickly. As a result, the connection electrodes 371 and 372 formed by patterning the metal film are not disconnected, so that the yield can be improved by preventing lighting failure.

[0257] On the other hand, the interval between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361 in the second embodiment may be greater by L2 than the interval L1 between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361 in the first embodiment. That is, in the second embodiment, the interval between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the expansion hole 364 may be L1+L2. As described above, in the second embodiment, as the interval between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361 becomes further larger, the space margin on the side of the semiconductor light emitting device 150 is ensured, so that the connection electrodes 371 and 372 can also be connected to the side of the semiconductor light emitting device 150 without breaking the line through the interval L1+L2.

[0258] On the other hand, the display device 301 of the second embodiment can be Fig.26 and Fig. 27 The illustrated backplane substrate 300C is manufactured by performing a self-assembly process and subsequent processes.

[0259] like Fig.26 and Fig. 27 As shown, the backplane substrate 300C may have an assembly hole 361 and auxiliary holes 362 and 363. At this time, the assembly hole 361 may not vertically overlap with each of the first partition wall layer 341 and the second partition wall layer 342, and the auxiliary holes 362 and 363 may vertically overlap with the first partition wall layer 341. The first partition wall layer 341 and the second partition wall layer 342 may be formed on the remaining substrate 310 except the assembly hole 361 and the auxiliary holes 362 and 363. In addition, in the expansion hole 364, the first partition wall layer 341 may be formed in the area of ​​the interval equivalent to L2 from the assembly hole 361.

[0260] The semiconductor light emitting device 150 is assembled to Fig.26 and Fig. 27When the ash process is performed after the assembly hole 361 on the backplane substrate 300C shown, the first partition wall layer 341 on the auxiliary holes 362 and 363 can be removed. In addition, in the expansion hole 364, the first partition wall layer 341 on the area corresponding to the interval L2 from the assembly hole 361 can also be removed. Thus, the interval between the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the expansion hole 364 is L1+L2, which can be L2 larger than L1 in the first embodiment.

[0261] Then, in the case of performing the deposition process, the metal film may be deposited at the interval L1+L2 between the auxiliary holes 362, 363 and the outer side surface of the semiconductor light emitting device 150 and the inner side surface of the assembly hole 361. Therefore, along the periphery of the semiconductor light emitting device 150, a sufficient space margin is ensured on the side, so the metal film may be formed thickly.

[0262] Therefore, when the metal film is patterned to form connecting electrodes 371, 372, the connecting electrodes 371, 372 can be connected to the side of the semiconductor light-emitting device 150 and the first assembly wiring 321 and / or the second assembly wiring 322 without disconnection, thereby preventing poor lighting.

[0263] [Third embodiment]

[0264] Fig.28 is a plan view showing a display device according to a third embodiment.

[0265] The following description does not include Fig.28 The reference numerals shown may refer to Fig.12 , Fig.24 as well as Fig.25 .

[0266] Except for the auxiliary holes 362-1, 362-2, 363-1, 363-2, the third embodiment is the same as the first embodiment or the second embodiment. In the third embodiment, for the components having the same shape, structure and / or function as the first embodiment or the second embodiment, the same reference numerals are given and detailed description is omitted.

[0267] Reference Fig.28 In the display device 302 of the third embodiment, a plurality of auxiliary holes 362 - 1 , 362 - 2 , 363 - 1 , and 363 - 2 may be formed by extending from the assembly hole 361 in the lateral direction.

[0268] The plurality of auxiliary holes may include a first auxiliary hole and a second auxiliary hole. The first auxiliary hole may include a 1-1 auxiliary hole 362-1 and a 1-2 auxiliary hole 362-2 on the first assembly wiring 321. The second auxiliary hole may include a 2-1 auxiliary hole 363-1 and a 2-2 auxiliary hole 363-2 on the second assembly wiring 322.

[0269] For example, the 1-1 auxiliary hole 362-1 and the 2-1 auxiliary hole 363-1 may be located on the first diagonal line 391. For example, the 1-2 auxiliary hole 362-2 and the 2-2 auxiliary hole 363-2 may be located on the second diagonal line 392. The first diagonal line 391 and the second diagonal line 392 may intersect at 90 degrees, but are not limited thereto. Therefore, the 1-1 auxiliary hole 362-1, the 2-1 auxiliary hole 363-1, the 1-2 auxiliary hole 362-2, and the 2-2 auxiliary hole 363-2 may be spaced 90 degrees from each other with the center of the assembly hole 361 as a reference.

[0270] For example, the 1-1st auxiliary hole 362 - 1 , the 2-1st auxiliary hole 363 - 1 , the 1-2nd auxiliary hole 362 - 2 , and the 2-2nd auxiliary hole 363 - 2 may be radially arranged with the assembly hole 361 as the center.

[0271] For example, the 1-1st auxiliary hole 362 - 1 and the 1-2nd auxiliary hole 362 - 2 may be arranged on the first assembly wiring 321 , and the 2-1st auxiliary hole 363 - 1 and the 2-2nd auxiliary hole 363 - 2 may be arranged on the second assembly wiring 322 .

[0272] Connect the electrodes ( Fig.12 and Fig.24 371, 372) can be arranged in the assembly hole 361, the plurality of auxiliary holes 362-1, 362-2, 363-1, 363-2 and the expansion hole 364. The first connection electrode 371 can connect the first side of the semiconductor light emitting device 150 and the first assembly wiring 321 through the 1-1 auxiliary hole 362-1 and / or the 1-2 auxiliary hole 362-2. The second connection electrode 372 can connect the second side of the semiconductor light emitting device 150 and the second assembly wiring 322 through the 2-1 auxiliary hole 363-1 and / or the 2-2 auxiliary hole 363-2. In addition, the connection electrode can be arranged along the periphery of the semiconductor light emitting device 150. It can be arranged in the area other than the semiconductor light emitting device 150 in the assembly hole 361 or the expansion hole 364. Therefore, the connection electrode arranged in the area other than the semiconductor light emitting device 150 in the assembly hole 361 or the expansion hole 364 can be connected to the first connection electrode 371 and / or the second connection electrode 372.

[0273] According to the second embodiment, more connection electrodes are electrically connected to the semiconductor light emitting device 150, so that the brightness can be improved by achieving smoother voltage supply.

[0274] According to the second embodiment, the semiconductor light emitting device 150 may be more firmly bonded to the substrate 310 due to more connection electrodes, and thus the bonding force can be further improved.

[0275] According to the second embodiment, the auxiliary holes 362-1, 362-2, 363-1, 363-2 are formed at equal intervals from each other, so the semiconductor light emitting device 150 assembled to the assembly hole 361 can be aligned to an accurate position without being biased to one side during self-assembly.

[0276] On the other hand, the aforementioned display device may be a display panel. That is, in the embodiment, the display device and the display panel may be understood as having the same meaning. In the embodiment, the display device in the substantial meaning may include a display panel and a controller (or processor) capable of controlling the display panel in order to display an image.

[0277] The above detailed description should be understood as exemplary and should not be interpreted as limiting in all aspects. The scope of the embodiment should be determined by reasonable interpretation of the attached claims, and all changes within the equivalent scope of the embodiment are included in the scope of the embodiment.

[0278] Industrial Applicability

[0279] The embodiment can be applied to the display field of displaying images or information. The embodiment can be applied to the display field of displaying images or information using semiconductor light emitting devices. The semiconductor light emitting device can be a micron-scale semiconductor light emitting device or a nano-scale semiconductor light emitting device.

[0280] For example, the embodiments can be applied to TVs, digital signage, mobile terminals such as mobile phones or smart phones, computer displays such as laptops or desktop computers, HUDs (head-up displays) for vehicles, backlight units for displays, displays for VR (virtual reality), AR (augmented reality) or MR (mixed reality), light sources, etc.

Claims

1. A display device, in, include: substrate; A first assembly wiring and a second assembly wiring are located on the substrate; A partition wall, arranged on the first assembly wiring and the second assembly wiring, having an assembly hole and at least one auxiliary hole extending toward the outer side of the assembly hole; A semiconductor light emitting device is located in the assembly hole; as well as A connecting electrode connected to a side of the semiconductor light emitting device; The partition wall comprises: a first partition wall layer; and a second partition wall layer, located on the first partition wall layer; An ashing rate of the first partition wall layer is equal to or greater than an ashing rate of the second partition wall layer.

2. The display device according to claim 1, in, The viscosity of the first partition wall layer is equal to or lower than the viscosity of the second partition wall layer.

3. The display device according to claim 1, in, The thickness of the second partition wall layer is equal to or smaller than the thickness of the first partition wall layer.

4. The display device according to claim 1, in, The auxiliary hole is formed by removing the first partition wall layer or the second partition wall layer.

5. The display device according to claim 4, in, The connecting electrode is configured at the assembly hole and the auxiliary hole.

6. The display device according to claim 4, in, The length of the auxiliary hole is smaller than the width of the first assembly wiring or the second assembly wiring.

7. The display device according to claim 4, in, The auxiliary hole comprises: at least one first auxiliary hole located on the first assembly wiring; and At least one second auxiliary hole is located on the second assembly wiring.

8. The display device according to claim 7, in, The first auxiliary hole and the second auxiliary hole are arranged symmetrically to each other.

9. The display device according to claim 4, in, The partition wall has an expansion hole, the expansion hole includes the assembly hole and has a second diameter greater than the first diameter of the assembly hole; The connection electrode is arranged between the outer side surface of the semiconductor light emitting device and the inner side surface of the expansion hole.

10. The display device according to claim 9, in, The second diameter of the expansion hole is greater than the first diameter of the assembly hole by more than 2 micrometers.

11. The display device according to claim 9, in, The expansion hole is formed by removing the first partition wall layer.

12. The display device according to claim 11, in, The auxiliary hole extends toward the outside of the expansion hole.

13. The display device according to claim 1, in, The first partition wall layer and the second partition wall layer each contain an organic substance.

14. The display device according to claim 1, in, The partition wall has a thickness smaller than a thickness of the semiconductor light emitting device.

Images