Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises an array substrate; the array substrate comprises a substrate, a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are stacked on one side of the substrate; the first electrode layer comprises a plurality of first electrodes, the second electrode layer comprises a second electrode, the second electrode comprises a plurality of openings, and the openings are overlapped with the first electrodes in the thickness direction of the substrate; the array substrate further comprises a plurality of gate lines and a plurality of data lines, the gate lines extend in the first direction, and the second direction is perpendicular to the first direction. For one first electrode and one opening which are mutually overlapped, the length of the first electrode in the second direction is a first length, the length of the opening in the second direction is a second length, and the ratio of the second length to the first length is larger than or equal to 0.8. According to the scheme, the influence of the pixel black area on the edge of the opening can be reduced, the light transmittance of the display panel is improved, and the display effect is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] Liquid crystal display devices have the advantages of good image quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and play an important role in the field of flat panel displays. Virtual Reality (VR) liquid crystal display devices require a high pixel density (pixels per inch, PPI). However, when the PPI is high, the pixel pitch becomes smaller, the pixel aperture becomes smaller, and there may be a problem of uneven distribution of the pixel electric field, resulting in a low light transmittance of the display device and affecting the display effect. Summary of the Invention

[0003] The present invention provides a display panel and a display device to increase the light transmittance of the display panel and improve the display effect of the display panel.

[0004] In a first aspect, the present invention provides a display panel, including an array substrate;

[0005] The array substrate includes a substrate and a first electrode layer and a second electrode layer stacked on one side of the substrate, and the second electrode layer is located on the side of the first electrode layer away from the substrate; the first electrode layer includes a plurality of first electrodes, the second electrode layer includes a second electrode, the second electrode includes a plurality of openings, and along the thickness direction of the substrate, the openings overlap with the first electrodes;

[0006] The array substrate further includes a plurality of gate lines and a plurality of data lines, the gate lines extend in a first direction, and a second direction is perpendicular to the first direction;

[0007] For an overlapping first electrode and an opening, the length of the first electrode in the second direction is a first length, the length of the opening in the second direction is a second length, and the ratio of the second length to the first length is greater than or equal to 0.8.

[0008] In a second aspect, the present invention provides a display device, including the display panel provided in the first aspect of the present invention.

[0009] For the display panel provided in the embodiments of the present invention, by increasing the ratio of the length of the second electrode opening to the length of the first electrode, the distances between the two side edges of the opening in the second direction and the center of the opening are increased, which is beneficial to enhancing the electric field strength at the edge positions in the light-transmitting region of the sub-pixel. The black region of the pixel is farther away from the center of the pixel opening, improving the black region problem of the sub-pixel, further enhancing the overall light transmittance of the sub-pixel, and improving the display effect of the display panel. Description of the Drawings

[0010] Figure 1 Schematic structural diagram of a display panel provided for the comparative example of the present invention;

[0011] Figure 2 Schematic structural diagram of a display panel provided for an embodiment of the present invention;

[0012] Figure 3 is Figure 2 Enlarged structural diagram at A;

[0013] Figure 4 Schematic cross-sectional structure diagram of a display panel provided for an embodiment of the present invention;

[0014] Figure 5 Schematic structural diagram of another display panel provided for an embodiment of the present invention;

[0015] Figure 6 Schematic cross-sectional structure diagram of another display panel provided for an embodiment of the present invention;

[0016] Figure 7 Schematic diagram of the electric field between electrodes provided for an embodiment of the present invention;

[0017] Figure 8 Film layer layout of a third electrode layer provided for an embodiment of the present invention;

[0018] Figure 9 Film layer layout of a first electrode layer provided for an embodiment of the present invention;

[0019] Figure 10 Film layer layout of a second electrode layer provided for an embodiment of the present invention;

[0020] Figure 11 Projection schematic diagram of a partial structure in a display panel provided for an embodiment of the present invention;

[0021] Figure 12 Schematic structural diagram of yet another display panel provided for an embodiment of the present invention;

[0022] Figure 13 is Figure 12 Enlarged structural diagram at B;

[0023] Figure 14 Projection schematic diagram of a partial structure in another display panel provided for an embodiment of the present invention;

[0024] Figure 15 Film layer layout of another first electrode layer provided for an embodiment of the present invention;

[0025] Figure 16Another film layout of the second electrode layer provided by the embodiments of the present invention;

[0026] Figure 17 Another schematic structural diagram of a display panel provided by the embodiments of the present invention;

[0027] Figure 18 Another schematic structural diagram of a display panel provided by the embodiments of the present invention;

[0028] Figure 19 Another schematic projection diagram of a part of the structure in a display panel provided by the embodiments of the present invention;

[0029] Figure 20 Another schematic structural diagram of a display panel provided by the embodiments of the present invention;

[0030] Figure 21 Another schematic cross-sectional structural diagram of a display panel provided by the embodiments of the present invention;

[0031] Figure 22 For Figure 21 A schematic diagram of a part of the structure in the shown display panel;

[0032] Figure 23 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0033] Figure 24 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0034] Figure 25 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0035] Figure 26 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0036] Figure 27 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0037] Figure 28 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0038] Figure 29 For Figure 21 A schematic diagram of another part of the structure in the shown display panel;

[0039] Figure 30 A schematic enlarged partial structure diagram of a display panel provided by the embodiments of the present invention;

[0040] Figure 31 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0041] Figure 32 A schematic structure diagram of another display panel provided by an embodiment of the present invention;

[0042] Figure 33 A schematic projection diagram of a part of the structure in another display panel provided by an embodiment of the present invention;

[0043] Figure 34 A schematic structure diagram of another display panel provided by an embodiment of the present invention;

[0044] Figure 35 A schematic projection diagram of a part of the structure in another display panel provided by an embodiment of the present invention;

[0045] Figure 36 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0046] Figure 37 A schematic projection diagram of a part of the structure in another display panel provided by an embodiment of the present invention;

[0047] Figure 38 A schematic projection diagram of a part of the structure in another display panel provided by an embodiment of the present invention;

[0048] Figure 39 A schematic structure diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the accompanying drawings, rather than all structures.

[0050] It should be noted that the terms "having", "including", "comprising", etc. described in this application have an open meaning, that is, when it is described that a module "has", "includes", or "comprises" a first element, a second element, and / or a third element, it means that the module includes other elements in addition to the first element, the second element, and / or the third element. Additionally, the ordinal numbers such as "first", "second", and "third" in this application are not intended to limit the specific order, but only to distinguish each part. In this application, when it is described that layer A and layer B are "set on the same layer", it means that layer A and layer B are made of the same material and by the same process.

[0051] The display panel in the embodiments of the present invention may be a liquid crystal display panel, for example, it may be a VR liquid crystal display panel, but is not limited thereto. The present invention will be described by taking the VR liquid crystal display panel as an example. Figure 1 FIG. Figure 1 is a schematic structural diagram of a display panel provided in the comparative example of the present invention, and reference may be made to Figure 1 . For a liquid crystal display panel, generally at least two layers of electrodes are provided in the array substrate, including a pixel electrode layer and at least one common electrode layer. The pixel electrode layer includes a plurality of independent pixel electrodes 111'. The plurality of pixel electrodes 111' are arranged in an array in the row direction and the column direction. The common electrode layer includes a common electrode 121'. The common electrode 121' is generally disposed in the display area as a whole layer. The common electrode 121' includes a slit 122'. Along the thickness direction of the display panel (i.e., Figure 1 the top view direction shown), the slit 122' overlaps with the pixel electrode 111', and the electric field formed by the common electrode 121' and the pixel electrode 111' drives the liquid crystal molecules to rotate. On the side of the liquid crystal layer facing away from the array substrate, there is a grid-shaped black matrix BM'. The openings of the black matrix BM' define sub-pixel openings, that is, the light-transmitting regions A1' of the sub-pixels. The light provided by the backlight source in the liquid crystal display module exits from the liquid crystal display panel through the sub-pixel openings (the light-transmitting regions of the sub-pixels). Figure 1 In the comparative example shown in FIG. Figure 1 , the slit 122' is located in the light-transmitting region A1'. A part of the projection of the pixel electrode 111' is located in the light-transmitting region A1', and the other part extends outside the light-transmitting region A1'. The part of the pixel electrode 111' extending outside the light-transmitting region A1' is electrically connected to a pixel switching transistor (not shown in the figure) through a connection hole via', so as to transmit the signals required for display to the pixel electrode 111' through the pixel switching transistor.

[0052] The inventors have found through research that Figure 1 in the setting mode shown in FIG. Figure 1 , both the upper and lower edges and the left and right edges of the slit 122' are located in the light-transmitting region A1'. Since there is a difference in the electric field between the edge of the slit 122' and the central region of the slit 122', a black area is likely to be formed at the edge of the slit 122'; in addition, for the double-domain pixel design scheme, the pixel electrode 111' includes a corner, and there will be electric field disorder at the corner, which will also cause the black area problem of the sub-pixel. Figure 1 In the scheme shown in FIG. Figure 1 , the edge of the slit 122' and the corner of the pixel electrode 111' are both exposed in the light-transmitting region A1', resulting in the visibility of the black area and affecting the light transmittance of the display panel.

[0053] Based on the above problems, an embodiment of the present invention provides a display panel, including an array substrate; the array substrate includes a substrate and a first electrode layer and a second electrode layer stacked on one side of the substrate, and the second electrode layer is located on the side of the first electrode layer away from the substrate; the first electrode layer includes a plurality of first electrodes, the second electrode layer includes a second electrode, the second electrode includes a plurality of openings, and along the thickness direction of the substrate, the openings overlap with the first electrodes; the array substrate further includes a plurality of gate lines and a plurality of data lines, the gate lines extend in a first direction, and a second direction is perpendicular to the first direction;

[0054] For an overlapping first electrode and an opening, the length of the first electrode in the second direction is a first length, the length of the opening in the second direction is a second length, and the ratio of the second length to the first length is greater than or equal to 0.8.

[0055] Through the above technical solution, when the ratio of the second length to the second length increases, the distances between the two side edges of the opening in the second direction and the center of the opening increase, which is beneficial to enhancing the electric field strength at the edge positions in the light-transmitting region of the sub-pixel. The black region of the pixel is farther away from the center of the pixel opening, improving the black region problem of the sub-pixel, and further increasing the overall light transmittance of the sub-pixel.

[0056] The above is the core idea of the present invention. Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0057] Figure 2 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 3 is Figure 2 an enlarged structural diagram at A, Figure 4 It is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, Figure 4 can correspond to Figure 3 a cross-sectional view along the C-C' direction. Refer to Figures 2 - 4In an embodiment of the present invention, the display panel includes an array substrate 100; the array substrate 100 includes a substrate 10 and a first electrode layer 11 and a second electrode layer 12 stacked on one side of the substrate 10, the second electrode layer 12 is located on the side of the first electrode layer 11 away from the substrate 10; the first electrode layer 11 includes a plurality of first electrodes 111, the second electrode layer 12 includes a second electrode 121, the second electrode 121 includes a plurality of openings 122, and along a substrate thickness direction Z, the openings 122 overlap with the first electrodes 111; the array substrate 100 also includes a plurality of gate lines Gate and a plurality of data lines Data, the gate lines Gate extend along a first direction X, and the second direction Y is perpendicular to the first direction X; for a first electrode 111 and an opening 122 that overlap each other, the length of the first electrode 111 in the second direction Y is a first length L1, the length of the opening 122 in the second direction Y is a second length L2, and the ratio of the second length L2 to the first length L1 is greater than or equal to 0.8.

[0058] like Figures 2 - 4 As shown, taking the liquid crystal display module as an example, the display module may include a backlight module (not shown in the figure) and a liquid crystal display panel. The liquid crystal display panel includes an array substrate 100, a liquid crystal layer 200 and a color filter substrate 300. The array substrate 100 and the color filter substrate 300 are arranged opposite to each other, and the liquid crystal layer 200 is sandwiched between the array substrate 100 and the color filter substrate 300. The liquid crystal display panel is located on the light-emitting side of the backlight module. The light emitted by the backlight module is emitted after passing through the liquid crystal display panel, so that the liquid crystal display panel displays the picture. The array substrate 100 is used to set a pixel switch transistor (not shown in the figure). Under the control of the scanning signal provided by the gate line Gate, the data line Data provides a data voltage to the pixel electrode through the pixel switch transistor. The electric field formed by the pixel electrode and the common electrode controls the deflection of the liquid crystal molecules to adjust the light transmittance of the sub-pixel. The color filter substrate 300 may include a structure such as a color resistor 31. The light emitted by the backlight module is converted into a corresponding color light after passing through the color resistor 31, and finally a color image display is realized.

[0059] The array substrate 100 may include a substrate 10 and a plurality of conductive layers stacked on one side of the substrate 10, with adjacent conductive layers separated by insulating layers. The substrate 10 may be a rigid substrate or a flexible substrate, which is not limited in the embodiment of the present invention. The plurality of conductive layers at least include a first electrode layer 11 and a second electrode layer 12, and the first electrode layer 11 is located between the substrate 10 and the second electrode layer 12. The first electrode layer 11 and the second electrode layer 12 may be prepared using any conductive material, including but not limited to transparent conductive materials such as indium tin oxide (ITO). Using transparent conductive materials to prepare the first electrode layer 11 and the second electrode layer 12 is beneficial to improving the light transmittance of the display panel. Figure 2 and Figure 3 The top view of the display panel exemplarily shows a partial film layer structure, but not all film layers.

[0060] refer to Figure 2 and Figure 3 , the array substrate 100 further includes a plurality of gate lines Gate and a plurality of data lines Data, the gate lines Gate extend along a first direction X and are arranged in a second direction Y, and one gate line Gate can be connected to a plurality of pixel switch transistors in the same row, and is used to provide the required gate control signal to the pixel switch transistor. The extension direction of the data line Data intersects with the first direction X, and a plurality of data lines Data are arranged in the first direction X, and one data line Data can be connected to a plurality of pixel switch transistors in the same column, and is used to provide the pixel electrode with the data voltage signal required for display. The embodiment of the present invention does not limit the extension direction of the data line Data, and the extension direction of the data line Data can be adjusted according to the actual shape of the sub-pixel P, etc. The gate line Gate and the data line Data are respectively located in different conductive layers, and can be in different layers from the first electrode layer 11 and the second electrode layer 12. The gate line Gate and the gate line Gate can be prepared by any conductive material, including but not limited to metal materials. The intersection area of ​​the data line Data and the gate line Gate defines each sub-pixel P.

[0061] The first electrode layer 11 may include a plurality of independently arranged first electrodes 111, and the first electrodes 111 are arranged in an array along a first direction X and a second direction Y. The first direction X is the extension direction of the gate line Gate, i.e., the row direction shown in the figure, and the second direction Y is the arrangement direction of the gate line Gate, i.e., the column direction shown in the figure. The second electrode layer 12 may be arranged in the display area as a whole layer.

[0062] Further, continue to refer to Figures 2 - 4 The second electrode 121 includes a plurality of openings 122 arranged in an array along the first direction X and the second direction Y, and the openings 122 overlap with the orthographic projection of the first electrode 111 in the substrate thickness direction Z. A sub-pixel P may include a first electrode 111, at least one opening 122 overlapping with the first electrode 111, and a liquid crystal layer 200 and a color resist 31 overlapping with the first electrode 111.

[0063] The first electrode 111 can be used as a pixel electrode of the sub-pixel P, and the second electrode 121 can be used as a first common electrode (also called a top electrode) of the sub-pixel P. The second electrodes 121 corresponding to the plurality of sub-pixels P are electrically connected to each other. During the display process, an electric signal can be applied to the first electrode 111 and / or the second electrode 121, and the first electrode 111 and the second electrode 121 generate an electric field, thereby driving the liquid crystal molecules to rotate. The figure exemplarily shows that the first electrode 111 and the opening 122 are both in the shape of long strips, and the length of the first electrode 111 (opening 122) in the second direction Y is greater than the length of the first electrode 111 (opening 122) in the first direction X, but it is not limited thereto.

[0064] Among them, it should be noted that Figure 2 In the illustrated embodiment, a first electrode 111 overlaps with an opening 122, that is, the second electrode 121 corresponding to a sub-pixel P is provided with an opening 122. Actually, it is not limited thereto. Figure 5 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 6 It is a schematic cross-sectional structural diagram of another display panel provided by an embodiment of the present invention. Figure 6 It can correspond to Figure 5 a schematic cross-sectional structural diagram along the E-E' direction. In Figure 5 and Figure 6 In the illustrated embodiment, a first electrode 111 overlaps with two openings 122, that is, the second electrode 121 corresponding to a sub-pixel P is provided with two openings 122. In actual application, those skilled in the art can set the number of openings 122 corresponding to a first electrode 111 according to actual needs. By increasing the number of openings 122, the uniformity of the electric field distribution between the first electrode 111 and the second electrode 121 can be improved to a certain extent, and the display effect can be improved.

[0065] Furthermore, it is worth noting that, in order to improve the problems of the comparative example shown above, the embodiment of the present invention proposes that, for a first electrode 111 and an opening 122 that overlap each other in the same sub-pixel P, the first electrode 111 has a first length L1 in the second direction Y, and the opening 122 has a second length L2 in the second direction Y. The ratio of the second length L2 to the first length L1 can be greater than or equal to 0.8. For example, if the first length L1 of the first electrode 111 is the same as that in the comparative example, both being 15.4 μm, the opening 122 can be further etched downward along the second direction Y by a certain length, so that the second length L2 of the opening 122 is increased to 12.3 - 14.5 μm. Compared with the pixel electrode 111' with a length of 15.4 μm and the slit 122' with a length of 12 μm in the comparative example, the length of the opening 122 in the embodiment of the present invention is relatively increased, and the ratio of the second length L2 to the first length L1 is increased. Along the second direction Y, the opening 122 includes a part located in the light-transmitting area A1 and a part extending to the non-light-transmitting area (the part other than the light-transmitting area A1). The distances between the two side edges of the opening 122 along the second direction Y and the center of the pixel opening (i.e., the light-transmitting area of the sub-pixel) are increased, the distance between the pixel black area and the center of the pixel opening is farther, and it can be better blocked by the light-shielding structure, and the overall light transmittance of the pixel is improved.

[0066] Optionally, in some refined embodiments, the ratio of the second length L2 to the first length L1 may be greater than or equal to 0.9; if the first length L1 of the first electrode 111 is 15.4 μm, the second length L2 of the opening 122 may be increased to more than 13.86 μm; in some other refined embodiments, the ratio of the second length L2 to the first length L1 may be greater than or equal to 0.93; if the first length L1 of the first electrode 111 is 15.4 μm, the second length L2 of the opening 122 may be increased to more than 14.3 μm, but not limited thereto. Any solution for the lengths of the first electrode 111 and the opening 122 that satisfies the ratio of the second length L2 to the first length L1 being greater than or equal to 0.8 is within the scope of the technical solutions protected by the embodiments of the present invention. According to actual simulation tests, when the ratio of the second length L2 to the first length L1 is increased to more than 0.93, the light transmittance of the sub-pixel P can be increased by 9.2%.

[0067] In the display panel provided by the embodiment of the present invention, by setting the ratio of the second length L2 of the opening 122 in the second direction Y to the first length L1 of the first electrode 111 in the second direction Y to be greater than or equal to 0.8, the influence of the black area of the pixels at the edge of the opening 122 can be reduced, the light transmittance of the display panel can be improved, and the display effect can be enhanced.

[0068] Optionally, reference may continue to Figures 2 - 4 , in a possible embodiment, the array substrate 100 further includes a third electrode layer 13. Along the substrate thickness direction Z, the third electrode layer 13 is located between the first electrode layer 11 and the substrate 10; the third electrode layer 13 includes a third electrode 131. Along the substrate thickness direction Z, the third electrode 131 at least covers the first electrode 111 and the opening 122.

[0069] The third electrode layer 13 may be located on the side of the first electrode layer 11 away from the second electrode layer 12. That is, along the substrate thickness direction Z, the third electrode layer 13, the first electrode layer 11, and the second electrode layer 12 are stacked in sequence. Among them, the third electrode layer 13 may include a third electrode 131, and the third electrode 131 serves as the second common electrode (also referred to as the bottom electrode) of the sub-pixel P. The positive projection of the third electrode 131 in the substrate thickness direction Z at least covers the first electrode 111 and the opening 122. The first electrode 111 may be a pixel electrode, both the second electrode 121 and the third electrode 131 may be common electrodes, and the first electrode 111 forms an electric field with the second electrode 121 and the third electrode 131 respectively. Figure 7A schematic diagram of the electric field between electrodes provided by an embodiment of the present invention. In the figure, the dashed lines represent the electric field lines between the electrodes. The electric fields between the first electrode 111 and the second electrode 121, and between the first electrode 111 and the third electrode 131 act on liquid crystal molecules (not shown in the figure) to drive the rotation of the liquid crystal molecules. The material of the third electrode 131 may be the same as or different from that of the first electrode 111, and the embodiment of the present invention does not limit this.

[0070] Optionally, the third electrode layer 13 may include a third electrode 131 arranged in a whole layer, or the third electrode 131 is in a mesh shape, or the third electrode layer 13 may include a plurality of third electrodes 131, and the third electrodes 131 corresponding to at least some of the sub-pixels P are connected to each other. Figure 8 A film layout diagram of a third electrode layer provided by an embodiment of the present invention Figure 9 A film layout diagram of a first electrode layer provided by an embodiment of the present invention Figure 10 A film layout diagram of a second electrode layer provided by an embodiment of the present invention. With reference to Figures 8 - 10 , in some exemplary embodiments, the third electrode layer 13 may include a plurality of third electrodes 131 extending in the first direction X and arranged in the second direction Y. One third electrode 131 corresponds to a plurality of sub-pixels P in the same row. Since the third electrode 131 is a common electrode, sharing the same third electrode 131 by a plurality of sub-pixels P will not affect the display, and the mask design difficulty of the third electrode 131 can be reduced.

[0071] The advantage of designing three electrode layers is that capacitors can be formed between the electrodes overlapping in the thickness direction Z of the substrate. Specifically, the first electrode can form capacitors with the second electrode above it and the third electrode below it respectively, so as to ensure that there is a certain capacitance value between the pixel electrode and the common electrode of the sub-pixel. Especially for a VR display panel with a small size, the design of three electrode layers is more conducive to increasing the capacitance than the design of two electrode layers.

[0072] In addition, it should be noted that for a display panel with three electrode layers, due to the increase in the number of electrode layers, the light transmittance of the display panel itself is relatively low, and it is more necessary to adopt the solution in the present invention to improve the relative size relationship between the opening 122 and the first electrode 111 to improve the light transmittance.

[0073] Optionally, Figure 11 A projection schematic diagram of some structures in a display panel provided by an embodiment of the present invention. For reference, see Figures 2 - 11, the first electrode 111 has a first projection 1110 on the plane where the substrate 10 is located, and the opening 122 has a second projection 1220 on the plane where the substrate 10 is located; the first projection 1110 includes two first edges 1111 that are oppositely arranged and parallel along the second direction Y and two second edges 1112 that are oppositely arranged and parallel along the first direction X; the second projection 1220 includes two third edges 1221 that are oppositely arranged and parallel along the second direction Y and two fourth edges 1222 that are oppositely arranged and parallel along the first direction X; the display panel further includes a plurality of sub-pixels P arranged in an array, and the sub-pixel P includes the first electrode 111 and the opening 122 that overlap each other; in the same sub-pixel P, both the first edge 1111 and the third edge 1221 extend along the first direction X, and the extending directions of at least part of the second edge 1112 and at least part of the fourth edge 1222 intersect with the second direction Y.

[0074] Continue to refer to Figures 2 - 11 , in the display panel provided by the embodiment of the present invention, the pixel structure can be a pseudo-dual-domain pixel structure. The pseudo-dual-domain pixel structure refers to simulating the dual-domain effect by alternately arranging the domain directions of adjacent row sub-pixels (such as different electrode directions for odd and even rows). As shown in the figure, for the pseudo-dual-domain pixel structure, the extending direction of the first electrode 111 (opening 122) has a certain angle with the second direction Y, and the portions of two adjacent first electrodes 111 (openings 122) along the second direction Y located in the light-transmitting area A1 are symmetrically arranged along the horizontal symmetry axis S. In other words, the tilting directions of the portions of two adjacent first electrodes 111 (openings 122) along the second direction Y located in the light-transmitting area A1 are symmetrically arranged with respect to the symmetry axis S.

[0075] Specifically, the first projection 1110 is the orthographic projection of the first electrode 111 on the plane where the substrate 10 is located, and the second projection 1220 is the orthographic projection of the opening 122 on the plane where the substrate 10 is located. The first projection 1110 is formed by sequentially connecting two first edges 1111 and two second edges 1112 end to end to form a closed figure. The first edges 1111 refer to the two edges of the first projection 1110 oppositely arranged along the second direction Y, which can also be understood as the two edges of the first electrode 111 oppositely arranged along the second direction Y, and the two first edges 1111 are parallel to each other; the second edges 1112 refer to the two edges of the first projection 1110 oppositely arranged along the first direction X, which can also be understood as the two edges of the first electrode 111 oppositely arranged along the first direction X, and the two second edges 1112 are parallel to each other. Correspondingly, the second projection 1220 is formed by sequentially connecting two third edges 1221 and two fourth edges 1222 end to end to form a closed figure. The third edges 1221 refer to the two edges of the second projection 1220 oppositely arranged along the second direction Y, which can also be understood as the two edges of the opening 122 oppositely arranged along the second direction Y, and the two third edges 1221 are parallel to each other; the fourth edges 1222 refer to the two edges of the second projection 1220 oppositely arranged along the first direction X, which can also be understood as the two edges of the opening 122 oppositely arranged along the first direction X, and the two fourth edges 1222 are parallel to each other.

[0076] Among them, for the same sub-pixel P, the first edge 1111 and the third edge 1221 are parallel, and both can extend along the first direction X. The second edge 1112 and the fourth edge 1222 are parallel, and at least part of the extension direction of the second edge 1112 and at least part of the extension direction of the fourth edge 1222 form an angle with the second direction Y. Compared with the second direction Y, both the first electrode 111 and the opening 122 are inclined at a certain angle, and the pixel design adopts the pseudo-bidomain structure proposed above.

[0077] Compared with the single-domain pixel structure, the pseudo-bidomain pixel structure can achieve a wider viewing angle, and compared with the bidomain pixel structure, it does not require multiple alignment processes. In the embodiments of the present invention, the display panel structure is introduced with the pseudo-bidomain pixel structure, but the actual pixel structure is not limited thereto.

[0078] The extension direction of the data line Data can be matched with the specific pixel structure design in the display panel. For example, for the display panel with a pseudo-bidomain pixel structure, the extension direction of the data line Data may form a certain angle with the second direction Y. For some sub-pixels P with regular shapes, such as the first electrode 111 being a rectangle extending along the second direction Y, the extension direction of the data line Data is the second direction Y.

[0079] Reference Figure 1, in the comparative example, the pixel electrode 111' includes a parallelogram portion and a rectangular portion. The rectangular portion is located on the side of the parallelogram portion close to the connection hole between the pixel electrode 111' and the pixel switching transistor (not shown in the figure), and the rectangular portion is electrically connected to the connection hole via'. The advantage of setting the rectangular portion is that the pixel electrode 111' and the pixel switching transistor can be positively overlapped, improving the overlapping area of the pixel electrode 111'. The slit 122' is integrally parallelogram-shaped, and the slit 122' overlaps with the parallelogram portion of the pixel electrode 111' and does not extend to the rectangular portion area. In this design method, the connection area between the parallelogram portion and the rectangular portion of the pixel electrode 111' includes a corner ( Figure 1 the area of the dashed ellipse in the figure), while the slit 122' does not include a corner. The inventor found that for the parallelogram portion of the pixel electrode 111' and the corresponding slit 122', the edge of the pixel electrode 111' is parallel to the edge of the slit 122'; while for the rectangular portion of the pixel electrode 111' and the corresponding slit 122', the edge of the pixel electrode 111' is not parallel to the edge of the slit 122'. The electric field in the non-parallel region is different from that in the parallel region, and the electric field in this corner region is disordered. The change in the electric field in the non-parallel region (i.e., the lower edge of the slit 122') will exacerbate the problem of the pixel black area.

[0080] Based on this, the present embodiment further proposes that in a possible embodiment, in the same sub-pixel P, the contours of the first projection 1110 and the second projection 1220 are the same.

[0081] The same contour of the first projection 1110 and the second projection 1220 means that the outer contours of the first electrode 111 and the opening 122 are the same, or it can be understood that the outer shapes of the first electrode 111 and the opening 122 are similar figures. Specifically, the first edge 1111 of the first projection 1110 and the third edge 1221 of the second projection 1220 are edges that are close to each other and extend in parallel, and the second edge 1112 of the first projection 1110 and the fourth edge 1222 of the second projection 1220 are edges that are close to each other and extend in parallel. In this way, for the same sub-pixel P, the electric fields in different regions of the first electrode 111 and the opening 122 in the second direction Y are consistent, effectively improving the problem of the pixel black area at the edge of the opening 122.

[0082] Exemplarily, continue to refer to Figures 2 - 11 , in some embodiments, both the first projection 1110 and the second projection 1220 are parallelogram-shaped; in the same sub-pixel P, the second edge 1112 and the fourth edge 1222 are parallel, and the extension directions of the second edge 1112 and the fourth edge 1222 and the second direction Y have a first included angle θ1, 0° < θ1 < 20°.

[0083] Continue to refer to Figures 2 - 11, both the first projection 1110 and the second projection 1220 are parallelograms, that is, the outer shapes of the first electrode 111 and the second electrode 121 are parallelograms. In other words, compared with the comparative example, in this embodiment, the outer shape of the first electrode 111 can be set as a parallelogram having the same shape as the opening 122, and the opening 122 can be elongated downward, so as to realize the adjustment of the electric field.

[0084] Among them, the extending direction of the second edge 1112 can be regarded as the overall extending direction of the first electrode 111, and the extending direction of the fourth edge 1222 can be regarded as the overall extending direction of the opening 122. There is a first included angle θ1 between the extending direction of the first electrode 111 (opening 122) and the second direction Y. The value of the first included angle θ1 can be set according to actual requirements. For the current electrode lateral design scheme of the display panel, the first included angle θ1 can be set within the range of 0-20°. For example, in some embodiments, the first included angle θ1 can be 10° to meet the wide viewing angle requirement.

[0085] Among them, it should be noted that for the pseudo-dual-domain pixel structure, the symmetric setting of two adjacent first electrodes 111 (openings 122) along the second direction Y. For Figure 2 the first electrode 111 (opening 122) shown in the upper row, the first electrode 111 (opening 122) is inclined to the right side of the second direction Y to form the first included angle θ1; for the first electrode 111 (opening 122) in the lower row, the first electrode 111 (opening 122) is inclined to the left side of the second direction Y to form the first included angle θ1.

[0086] In this embodiment, both the first electrode 111 and the opening 122 are set as parallelograms. The connection vias via of the first electrode 111 and the pixel switching transistor (including Figure 2 the first via via1 and the second via via2 shown) change from the forward lap joint to the oblique lap joint, and the power supply and display can still be normally completed.

[0087] In addition, it can be understood that the display panel should include sub-pixels P of different colors, such as red, green, and blue sub-pixels. The sub-pixels P of different colors are realized by different color filters 31 in the color filter substrate 300. The specific arrangement manner of the sub-pixels P of different colors in the embodiments of the present invention is not limited, and those skilled in the art can set it according to actual requirements. In the embodiments of the present invention, it is taken as an example that the sub-pixels P in the same column emit the same color light, and the columns of sub-pixels P of different colors are alternately arranged along the first direction X. For example, the columns of red, green, and blue sub-pixels are alternately arranged along the first direction X. Among them, the inclination angles of the first electrodes 111 (openings 122) corresponding to the sub-pixels P of the same color can be the same, and the inclination angles of the first electrodes 111 (openings 122) corresponding to the sub-pixels P of different colors can be the same or different. The embodiments of the present invention do not limit this.

[0088] Exemplarily, Figure 12 FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 13 is Figure 12 an enlarged structural diagram at B. Figure 14 FIG. 4 is a schematic projection diagram of a partial structure in another display panel provided by an embodiment of the present invention. Figure 15 FIG. 5 is a layer layout diagram of another first electrode layer provided by an embodiment of the present invention. Figure 16 FIG. 6 is a layer layout diagram of another second electrode layer provided by an embodiment of the present invention. Refer to Figures 12 - 16 , in some other embodiments, the shape of the opening 122 can be set to a shape similar to that of the pixel electrode, and the opening 122 can be elongated downward, so as to realize the adjustment of the electric field.

[0089] Specifically, as Figures 12 - 16 shown, a second edge 1112 includes a first line segment 11121 and a second line segment 11122 connected to each other, and the first line segment 11121 and the second line segment 11122 are respectively connected to different first edges 1111; a fourth edge 1222 includes a third line segment 12221 and a fourth line segment 12222 connected to each other, and the third line segment 12221 and the fourth line segment 12222 are respectively connected to different third edges 1221; wherein, the first line segment 11121 and the third line segment 12221 are parallel, the second line segment 11122 and the fourth line segment 12222 are parallel, the second line segment 11122 and the fourth line segment 12222 extend along the second direction Y, and the extension directions of the first line segment 11121 and the third line segment 12221 have a first included angle θ1 with the second direction Y, 0° < θ1 < 20°.

[0090] In this embodiment, for the first projection 1110, the first edge 1111, the first line segment 11121, and the second line segment 11122 are connected end to end in sequence to form a closed figure. The first line segment 11121 may refer to the part of the second edge 1112 close to the upper first edge 1111, and the second line segment 11122 may refer to the part of the second edge 1112 close to the lower first edge 1111. One side of the first line segment 11121 facing away from the first edge 1111 to which it is connected is connected to the second line segment 11122, and one side of the second line segment 11122 facing away from the first line segment 11121 to which it is connected is connected to another first edge 1111. Among them, the two first line segments 11121 corresponding to the same first electrode 111 are parallel and inclined at a first angle θ1 with respect to the second direction Y. The two second line segments 11122 corresponding to the same first electrode 111 are parallel and all extend along the second direction Y. In one first projection 1110, the two relatively arranged first line segments 11121 and the first edge 1111 connecting the two first line segments 11121 form the parallelogram part of the first projection 1110 (first electrode 111); the two relatively arranged second line segments 11122 and the first edge 1111 connecting the two second line segments 11122 form the rectangular part of the first projection 1110 (first electrode 111).

[0091] Correspondingly, for the second projection 1220, the third edge 1221, the third line segment 12221, and the fourth line segment 12222 are connected end to end in sequence to form a closed figure. The third line segment 12221 may refer to the part of the fourth edge 1222 close to the upper third edge 1221, and the fourth line segment 12222 may refer to the part of the fourth edge 1222 close to the lower third edge 1221. One side of the third line segment 12221 facing away from the third edge 1221 to which it is connected is connected to the fourth line segment 12222, and one side of the fourth line segment 12222 facing away from the third line segment 12221 to which it is connected is connected to another third edge 1221. Among them, the two third line segments 12221 corresponding to the same opening 122 are parallel and inclined at a first angle θ1 with respect to the second direction Y. The two fourth line segments 12222 corresponding to the same opening 122 are parallel and all extend along the second direction Y. In one second projection 1220, the two relatively arranged third line segments 12221 and the third edge 1221 connecting the two third line segments 12221 form the parallelogram part of the second projection 1220 (opening 122); the two relatively arranged fourth line segments 12222 and the third edge 1221 connecting the two fourth line segments 12222 form the rectangular part of the second projection 1220 (opening 122).

[0092] Along the thickness direction of the substrate, the parallelogram portion of the first electrode 111 overlaps with the parallelogram portion of the opening 122, and the rectangular portion of the first electrode 111 overlaps with the rectangular portion of the opening 122.

[0093] Among them, for the specific setting method of the first included angle θ1, reference can be made to the above embodiments, which will not be elaborated here. In this embodiment, by stretching the opening 122 downward and setting the shape of the region where the opening 122 is stretched downward to be a rectangle corresponding to the first electrode 111, the design with the same outline of the first electrode 111 and the opening 122 can also be realized; and in this setting method, the connection via of the first electrode 111 and the pixel switching transistor maintains a positive overlap, which can ensure a relatively large overlap area. The setting method of the third electrode layer in this embodiment is the same as that in the above embodiments, which will not be elaborated here.

[0094] Optionally, Figure 17 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 18 is a schematic structural diagram of yet another display panel provided by an embodiment of the present invention, Figure 19 is a schematic projection diagram of a partial structure in yet another display panel provided by an embodiment of the present invention. Refer to Figures 17 - 19 , the sub-pixel P further includes a transistor 14 (i.e., the pixel switching transistor mentioned above). Along the thickness direction of the substrate, the film layer where the transistor 14 is located is between the substrate 10 and the first electrode layer 11; the transistor 14 includes an active layer 140, and the active layer 140 includes a first active sub-portion 141, a second active sub-portion 142, and a third active sub-portion 143. The two ends of the second active sub-portion 142 are respectively connected to the first active sub-portion 141 and the third active sub-portion 143; the first active sub-portion 141 has a first sub-projection sub-portion 1411 in the plane of the substrate 10, the second active sub-portion 142 has a second sub-projection sub-portion 1421 in the plane of the substrate 10, and the third active sub-portion 143 has a third sub-projection sub-portion 1431 in the plane of the substrate 10.

[0095] The charging of the sub-pixel P is mainly completed by the transistor 14. The first pole and the second pole of the transistor 14 are respectively electrically connected to the data line Data and the first electrode 111, and the gate of the transistor 14 is electrically connected to the gate line Gate. The effective enable signal transmitted by the gate line Gate is used to control the transistor 14 to conduct. When the transistor 14 conducts, the data voltage signal on the data line Data can be written into the first electrode 111, thereby completing the charging of the sub-pixel P.

[0096] Among them, in a sub-pixel P, along the thickness direction of the substrate, the gate line Gate overlaps with the active layer 140, and the overlapping area serves as the gate of the transistor 14; the data line Data is electrically connected to the active layer 140 through the third via hole via3, and the electrically connected portion of the two serves as the first electrode of the transistor 14; the first electrode 111 is electrically connected to the active layer 140 through the first via hole via1 and the second via hole via2, and the electrically connected portion of the two serves as the second electrode of the transistor 14. The connection vias between the first electrode 111 and the pixel switch transistor mentioned above are the connection vias between the first electrode 111 and the active layer 140 of the transistor 14.

[0097] Figure 19 Figure (a) shows Figure 18 projection of the active layer, the first electrode and the opening in the display panel, Figure 19 Figure (b) shows Figure 18 The projection of the active layer, the first electrode and the opening in the display panel. Figure 2 and Figure 17 The solution shown in FIG. 1 is that both the first electrode 111 and the opening 122 are designed as parallelograms. Figure 12 and Figure 18 As shown, the first electrode 111 and the opening 122 are both designed as a parallelogram plus a rectangle, and the active layer 140 may be in a U-shaped configuration, including a first active subdivision 141, a third active subdivision 143, and a second active subdivision 142 connected therebetween. The first active subdivision 141, the second active subdivision 142, and the third active subdivision 143 are an integrated structure, and are divided based on the shape of the active layer 140. The first active subdivision 141 and the third active subdivision 143 may refer to the left and right sides of the U-shape, and the second active subdivision 142 may refer to the bottom side of the U-shape connecting the left and right sides.

[0098] For example, Figure 17 and Figure 19 In the scheme shown in Figure (a), the first electrode 111 and the opening 122 are designed to be parallelograms. For example, the first sub-projection portion 1411 in the same sub-pixel P is located on the side of the fourth edge 1222 facing the fourth edge 1222 of another sub-pixel P, the second sub-projection portion 1421 is located on the side of the third edge 1221 facing the third edge 1221 of another sub-pixel P, the third sub-projection portion 1431 at least partially overlaps with the first projection 1110, and the third active portion 143 is electrically connected to the first electrode 111 through the via.

[0099] like Figures 17 - 19As shown, the first electrode 111 (first projection 1110), the opening 122 (second projection 1220) and the active layer 140 in the same sub-pixel P may be defined as corresponding to each other, and the first sub-projection portion 1411 of the first active portion 141 may be located between two first projections 1110 (or second projections 1220) adjacent to each other along the first direction X. The second sub-projection portion 1421 of the second active portion 142 may be located on the side of the corresponding first electrode 111 (opening 122) facing the first electrode 111 (opening 122) of the adjacent sub-pixel P along the second direction Y. In other words, for the first projection 1110 (second projection 1220) and the second sub-projection portion 1421 corresponding to each other, the second sub-projection portion 1421 is located on the side of the corresponding first edge 1111 (third edge 1221) away from the center of the first projection 1110. The figure exemplarily shows that the second sub-projection section 1421 in a sub-pixel P overlaps with the first projection 1110 in the sub-pixel P adjacent to it along the second direction Y. In practice, the invention is not limited thereto. The second sub-projection section 1421 may also be located between two first projections 1110 adjacent to each other along the second direction Y. The extension direction of the third active section 143 may be the same as or different from the extension direction of the first active section 141. The third sub-projection section 1431 of the third active section 143 extends upward from the location of the second sub-projection section 1421 to the corresponding first projection 1110, ensuring that the third sub-projection section 1431 overlaps with the first projection 1110. The third active section 143 is electrically connected to the first electrode 111 of the upper layer through the via hole via, thereby realizing the connection between the active layer 140 and the first electrode 111.

[0100] Figure 20 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 21 A schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present invention, Figure 22 for Figure 21 The schematic diagram of a part of the structure of the display panel is shown. Figure 23 for Figure 21 The schematic diagram of another part of the structure of the display panel is shown. Figure 24 for Figure 21 The schematic diagram of another part of the structure of the display panel is shown. Figure 25 for Figure 21 The schematic diagram of another part of the structure of the display panel is shown. Figure 25 for Figure 21 The schematic diagram of another part of the structure of the display panel is shown. Figure 27 for Figure 21 The schematic diagram of another part of the structure of the display panel is shown. Figure 28 for Figure 21 The schematic diagram of another part of the structure of the display panel is shown. Figure 29 for Figure 21Schematic diagram of another part of the structure in the display panel shown Figure 20 It is a layout overlay of multiple film layers of the display panel Figure 22 The figure shows a schematic cross-section of the overall film layer of the display panel, corresponding to Figure 2 、 Figure 9 、 Figure 10 and Figure 17 The sub-pixel shape design shown Figures 21 - 28 It is the layout of a single film layer. It can be combined with reference to Figure 2 、 Figures 8 - 10 、 Figure 17 、 Figures 20 - 29 , the film layer where the transistor 14 and the signal line are located can be between the substrate 10 and the first electrode layer 11. When the array substrate 100 includes the third electrode layer 13, the film layer where the transistor 14 is located can be between the substrate 10 and the third electrode layer 13. Exemplarily, in some embodiments, the conductive layer of the array substrate 100 may further include a stacked first metal layer M1 (layout as shown in Figure 23 ), a second metal layer M2 (layout as shown in Figure 25 ), a third metal layer M3 (layout as shown in Figure 26 ), and a fourth metal layer M4 (layout as shown in Figure 29 ). The first metal layer M1, the second metal layer M2, and the third metal layer M3 are sequentially located between the active layer 140 ( Figure 22 shown) and the third electrode layer 13 ( Figure 8 shown), and the fourth metal layer M4 can be between the first electrode layer 11 ( Figure 9 shown) and the second electrode layer 122 ( Figure 10 shown). From the direction of the first metal layer M1 pointing to the second electrode layer 12, the insulating layers between adjacent two conductive layers are the first insulating layer 161 - the fifth insulating layer 165 in sequence. There may be no insulating layer between the fourth metal layer M4 and the second electrode layer 12, and the two are in direct contact to reduce the resistance of the second electrode layer 12.

[0101] Among them, the gate line Gate can be located in the first metal layer M1, the data line Data can be located in the second metal layer M2, and the third metal layer M3 can be used for a plurality of conductive pads 20. Along the thickness direction of the substrate, the conductive pads 20 overlap with the active layer 140 and the first electrode 111 respectively, and the conductive pads 20 overlap with the first via via1 and the second via via2 located in the corresponding insulating layer respectively. The first electrode 111 can be in contact with the conductive pad 20 through the second via via2 to achieve electrical connection, and the conductive pad 20 is in contact with the active layer 140 through the first via via1 to achieve electrical connection. The conductive pad 20 not only serves as a transfer structure between the first electrode 111 and the active layer 140, but also can play a role in blocking light leakage, improving the display contrast. The fourth metal layer M4 can include a plurality of metal light-shielding blocks 15. Along the thickness direction Z of the substrate, the metal light-shielding blocks 15 can overlap with the data line Data, and the orthographic projection of the metal light-shielding blocks 15 on the plane where the substrate 10 is located is located between two adjacent second projections. The presence of the fourth metal layer M4 can improve metal light leakage and reduce ambient light reflection. The number of the above metal layers and the structural settings in the metal layers are only examples, and are not limited thereto in practice. Certain metal layers can be added or removed according to actual needs, or the order of certain metal layers can be adjusted.

[0102] For the electrical connection manner between the first electrode 111 and the active layer 140, if no insulating layer is provided between the conductive pad and the active layer, the conductive pad can be directly lapped on the active layer without providing the first via.

[0103] Figure 30 It is a schematic diagram of a partial enlarged structure of a display panel provided by an embodiment of the present invention. Figure 31 It is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. Figure 30 The top view corresponding to a sub-pixel. Figure 31 Can correspond to Figure 30 The schematic cross-sectional structure diagram along the D-D' direction. Reference can be made in combination with Figure 17 、 Figures 20 - 31 For the four-layer metal layer scheme shown in the figure, the connection via of the active layer 140 of the transistor 14 can include: the first via via1 in the insulating layer between the active layer 140 and the third metal layer M3 (as Figure 24 shown), the second via via2 in the insulating layer between the third metal layer M3 and the first electrode layer 11 (including Figure 27 the first sub-via via21 in the third insulating layer 163 between the third metal layer M3 and the third electrode layer 13 shown and Figure 28The second sub-via (via22) in the fourth insulating layer 164 between the shown third electrode layer M3 and the first electrode layer 11. The active layer 140 is electrically connected to the first electrode 111 through the first via (via1), the conductive spacer 20, the first sub-via (via21), and the second sub-via (via22).

[0104] Figure 32 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 32 It is a layout overlay of the multi-film layers of the display panel, corresponding to Figures 12 - 16 the designed shape of the shown sub-pixel. Figure 32 and Figure 20 The other film layers in the shown display panel except the first electrode layer 11 and the second electrode layer 12 can be the same, which will not be elaborated here.

[0105] Optionally, reference can be continued to Figure 17 and Figure 19 In the (a) figure, in a possible embodiment, the extending directions of at least part of the first active division 141 and at least part of the third active division 143 are parallel to the extending direction of the second edge 1112.

[0106] Since the projection of the active layer 140 on the plane where the substrate 10 is located surrounds at least part of the first projection 1110 (second projection 1220) of the corresponding sub-pixel P. When both the first electrode 111 and the opening 122 are set as parallelograms, the extending direction of the first electrode 111 or the opening 122 (i.e., the extending directions of the second edge 1112 and the fourth edge 1222) can be defined as the third direction, and the included angle between the third direction and the second direction Y is θ1.

[0107] In this embodiment, at least part of the regions in the first active division 141 and at least part of the regions in the third active division 143 can be correspondingly set to extend along the third direction, so that the extending directions of the first active division 141 and the third active division 143 are parallel to the tilting direction of the first electrode 111 (opening 122). In this way, a relatively large overlapping area between the third active division 143 and the first electrode 111 can be ensured, avoiding the problem of reduced overlapping area caused by the change in the shape of the first electrode 111, and ensuring the electrical connection effect between the transistor 14 and the first electrode 111.

[0108] Among them, Figure 17 and Figure 19 In the active layer 140 shown in the (a) figure, the second active division 142 extends along the first direction X. In this way, the channel length of the transistor 14 remains basically unchanged, and the driving ability of the transistor 14 will not be affected. Figure 33 It is a schematic projection diagram of part of the structure in another display panel provided by an embodiment of the present invention, Figure 33In the shown active layer 140, the extending direction of the second active sub - part 142 forms a certain angle with the first direction X. This is equivalent to tilting the entire existing active layer 140 by a certain angle. In this way, without adjusting the mask of the active layer 140, the manufacturing cost can be reduced.

[0109] Exemplarily, for Figure 18 and Figure 19 in the solution shown in Figure (b) where both the first electrode 111 and the opening 122 are designed as a parallelogram plus a rectangle, the first sub - projection sub - part 1411 in the same sub - pixel P is located on one side of the fourth line segment 12222 of the fourth line segment 12222 of another sub - pixel P towards the other sub - pixel P. The second sub - projection sub - part 1421 is located on one side of the third edge 1221 of the third edge 1221 of another sub - pixel P towards the other sub - pixel P. The third sub - projection sub - part 1431 overlaps at least partially with the first projection 1110, and the third active sub - part 143 is electrically connected to the first electrode 111 through a via.

[0110] As Figure 18 and Figure 19 shown in Figure (b), the first sub - projection sub - part 1411 is located between two first projections 1110 (between the second projections 1220) adjacent along the first direction X, and at least part of the area of the first sub - projection sub - part 1411 is located between two adjacent second edges 1112 (fourth edges 1222) extending along the second direction Y. The positions of the second sub - projection sub - part 1421 and the third sub - projection sub - part 1431 are the same as those in the above embodiments and will not be elaborated here. In this embodiment, the orthographic projection of the active layer 140 on the plane where the substrate 10 is located surrounds at least part of the rectangular part corresponding to the sub - pixel P.

[0111] Further optionally, at least part of the first active sub - part 141 and at least part of the third active sub - part 143 extend along the second direction Y.

[0112] Figure 18 and Figure 19 shown in Figure (b), when both the first electrode 111 and the opening 122 are set as a parallelogram part plus a rectangle part, at least part of the area in the first active sub - part 141 of the active layer 140 and at least part of the area in the third active sub - part 143 can still extend along the second direction Y. Without changing the shape of the active layer 140 in the prior art, a large overlapping area between the third active sub - part 143 and the first electrode 111 can be ensured.

[0113] Optionally, Figure 34 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 35 is a projection schematic diagram of part of the structure in another display panel provided by an embodiment of the present invention. Reference can be made to Figure 34 and Figure 35, the first electrode 111 has a first projection 1110 on the plane where the substrate 10 is located, and the opening 122 has a second projection 1220 on the plane where the substrate 10 is located; the first projection 1110 includes two first edges 1111 that are oppositely arranged and parallel along the second direction Y and two second edges 1112 that are oppositely arranged and parallel along the first direction X; the second projection 1220 includes two third edges 1221 that are oppositely arranged and parallel along the second direction Y and two fourth edges 1222 that are oppositely arranged and parallel along the first direction X; the display panel further includes a first light-shielding structure 17, and the first light-shielding structure 17 extends along the first direction X and is arranged along the second direction Y; the first light-shielding structure 17 has a third projection 171 on the plane where the substrate 10 is located, and the third projection 171 covers the first edge 1111 and the third edge 1221.

[0114] The inventors found that pixel black areas not only exist in the lower (below along the second direction Y) edge of the opening 122, but also in part of the upper edge of the opening 122. The formation reason of the upper pixel black area may be related to the electric field distribution. Based on this problem, in this embodiment, it is proposed that a first light-shielding structure 17 can be arranged in the display panel, and the first light-shielding structure 17 is used to block the upper and lower edges of the opening 122.

[0115] Exemplarily, the light-shielding structure 17 can be in a strip shape, and a plurality of first light-shielding structures 17 extend along the first direction X and are arranged along the second direction Y. Among them, the first light-shielding structure 17 is arranged in a different layer from the first electrode layer 11 and the second electrode layer 12. The third projection 171 of the first light-shielding structure 17 on the plane where the substrate 10 is located covers the first edge 1111 of the first projection 1110 and the third edge 1221 of the second projection 1220, that is, along the substrate thickness direction Z, the first light-shielding structure 17 covers the upper and lower edges of the first electrode 111 and the upper and lower edges of the opening 122, and the first light-shielding structure 17 plays a light-shielding effect.

[0116] Figure 2 and Figure 12 The embodiment shown also includes the first light-shielding structure 17, but the first light-shielding structure 17 only covers the lower edges (the first edge and the third edge below along the second direction Y) of the first electrode 111 and the opening 122. Compared with the non-overlapping of the upper edge of the opening 122 with the first light-shielding structure 17, in this embodiment, the first electrode 111 and the opening 122 can be moved upward (moved upward along the second direction Y) by a certain length together, so that the upper edge of the opening 122 (the first electrode 111) overlaps with the first light-shielding structure 17, so that the pixel black area moves below the first light-shielding structure 17, thereby further improving the light transmittance.

[0117] It should be noted that when moving the first electrode 111 and the opening 122, it is necessary to ensure that the lower edge of the opening 122 also overlaps with the first light-shielding structure 17.

[0118] Optionally, in a possible embodiment, the length of the overlapping area of ​​the third projection 171 and the first projection 1110 in the second direction Y is a third length L3, and the length of the overlapping area of ​​the third projection 171 and the second projection 1220 in the second direction Y is a fourth length L4; wherein, 1μm<L3<3μm, 1μm<L4<3μm.

[0119] The overlapping length L3 of the overlapping area of ​​the third projection 171 and the first projection 1110 can be understood as the shielding length of the first light shielding structure 17 to the edge of the first electrode 111, and the overlapping length L4 of the overlapping area of ​​the third projection 171 and the second projection 1220 is the shielding length of the first light shielding structure 17 to the edge of the opening 122. Figure 34 and Figure 35 As shown, since the pixel black area is formed in a partial area of ​​the edge of the opening 122, in order to ensure that the first light shading structure 17 can better block the pixel black area, this embodiment stipulates that the third length L3 and the fourth length L4 can be set within the range of 1-3μm, ensuring that the first light shading structure 17 blocks the pixel black areas at the upper and lower edges to a large extent.

[0120] According to actual simulation tests, compared with the solution in the comparative example, the solution of this embodiment can increase the light transmittance of the sub-pixel P by 16.5%.

[0121] The film position of the first light shielding structure 17 is not limited in the embodiment of the present invention, and those skilled in the art can set it according to actual needs. For example, reference can be made to Figure 34 and Figure 35 In some embodiments, along the thickness direction of the substrate, the film layer where the first light shielding structure 17 is located is located between the first electrode layer 11 and the substrate 10 .

[0122] Figure 34 and Figure 35 In the illustrated embodiment, the first light shielding structure 17 may be located on the side of the first electrode layer 11 facing away from the second electrode layer 12, and light shielding is performed using the film layer below the first electrode layer 11. The first light shielding structure 17 may be a metal material or a non-metallic light shielding material. For example, as described above, the first electrode layer 11 and the substrate 10 include multiple metal layers, and one or more of the metal layers may be used to form the first light shielding structure 17.

[0123] Exemplary, reference Figure 21 In some embodiments, a fifth metal layer M5 is further included between the film layer where the active layer 140 is located and the substrate 10, and the first light shielding structure 17 may be located in the fifth metal layer M5. In particular, along the substrate thickness direction Z, the first light shielding structure 17 may also cover the channel region of the active layer 140 to prevent external ambient light from irradiating the channel region to form photogenerated carriers and prevent transistor leakage.

[0124] Exemplary, reference Figure 2 and Figure 12 In other embodiments, the film layer where the first light shielding structure 17 is located may be located on the side of the second electrode layer 12 away from the first electrode layer 11, for example, may be located on the color filter substrate 300. In this way, the film layer where the first light shielding structure 17 is located is closer to the light emitting side of the display panel, visually improving the shielding effect.

[0125] Optional, you can continue to refer to Figure 2 , Figure 12 , Figure 34 and Figure 35 The display panel also includes a second shading structure 18, which extends along the second direction Y and is arranged along the first direction X; the opening 122 has a second projection 1220 on the plane where the substrate 10 is located, and the second shading structure 18 has a fourth projection 181 on the plane where the substrate 10 is located, and the fourth projection 181 is located between two adjacent second projections 1220 along the first direction X.

[0126] like Figure 2 , Figure 11 , Figure 34 and Figure 35 As shown, the second light shielding structure 18 may be in a strip shape and extend along the second direction Y and be arranged in the first direction X. The fourth projection 181 of the second light shielding structure 18 is located between two second projections 1220 adjacent to each other along the first direction X. The fourth projection 181 may cover the projection of the data line Data and may cover the first sub-projection portion of the active layer. The second light shielding structure 18 and the first light shielding structure 17 intersect, and the area defined at the intersection corresponds to the sub-pixel area. The second light shielding structure 18 and the first light shielding structure 17 may jointly shield the area outside the pixel opening.

[0127] Optional, such as Figure 34 and Figure 35 As shown, in some embodiments, along the thickness direction of the substrate, the second shading structure 18 can cover the left and right edges of the first electrode 11, that is, the two side edges of the first electrode 11 opposite to each other along the first direction X extend to the non-light-transmitting area. In this way, even if the electric field turbulence at the left and right edges of the first electrode 11 forms a black area, the black area can also be blocked by the second shading structure 18, thereby further improving the transmittance.

[0128] In an embodiment not shown in the drawings of the present invention, the first electrode 11 and the second light shielding structure 18 may not overlap, and the left and right edges of the first electrode 11 are located in the light-transmitting area, which will not be described in detail in the embodiment of the present invention.

[0129] The film position of the second light shielding structure 18 is not limited in the embodiment of the present invention, and those skilled in the art can set it according to actual needs. For example, reference can be made to Figures 2 - 4The display panel further includes a liquid crystal layer 200 and a color filter substrate 300 . Along the substrate thickness direction Z, the liquid crystal layer 200 is located between the array substrate 100 and the color filter substrate 300 ; the second light shielding structure 18 is located on the color filter substrate 300 .

[0130] As an optional solution, the second light shielding structure 18 may be located in the color filter substrate 300, and the second light shielding structure 18 may overlap the color resist 31 along the first direction X. For a solution in which the red, green, and blue sub-pixels P are arranged alternately along the first direction X, the second light shielding structure 18 is used to space two adjacent color resists 31 of different colors, thereby avoiding crosstalk between adjacent light rays of different colors.

[0131] In this embodiment, the second light shielding structure 18 is made of black light shielding material, which can be the same as the black matrix material in the existing display panel color filter substrate 300. Figure 2 and Figure 12 In the illustrated embodiment, the first light shielding structure 17 and the second light shielding structure 18 are intersected in the same layer to form a grid-shaped light shielding layer. In this way, the first light shielding structure 17 and the second light shielding structure 18 can be manufactured in the same process.

[0132] Figure 34 and Figure 35 In the illustrated embodiment, the film layer where the first light shielding structure 17 is located can be located between the active layer 140 and the substrate 10, and the film layer where the second light shielding structure 18 is located can be located in the color filter substrate 300, that is, the second light shielding structure 18 and the first light shielding structure 17 are respectively located on opposite sides of the liquid crystal layer 200. The advantage of such a setting is that, since the metal layer alignment (MA) process accuracy is less than the overlay accuracy control (OVL) process accuracy, by designing the grid light shielding layer of the same layer as the first light shielding structure 17 and the second light shielding structure 18 of different layers, the problem of smaller pixel openings caused by the limited MA process accuracy can be avoided, thereby ensuring a high transmittance.

[0133] Figure 36 A schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present invention is shown. Figure 37 A schematic projection diagram of a partial structure of another display panel provided in an embodiment of the present invention can be combined with reference to Figure 21 , Figure 36 and Figure 37 Along the substrate thickness direction Z, the film layer where the gate line Gate is located is located between the first electrode layer 11 and the substrate 10; the orthographic projection of the gate line Gate on the plane where the substrate 10 is located and the orthographic projection of the opening 122 on the plane where the substrate 10 is located have an overlapping area.

[0134] As described above, the gate line Gate can be formed in the first metal layer M1. In this embodiment, the first electrode 111 and the opening 122 are moved up as a whole (upward along the second direction Y) by a certain length so that the upper edge of the opening 122 overlaps with the gate line Gate. The gate line Gate is used to block the black area of ​​the pixel, which can also achieve the effect of improving the transmittance.

[0135] As described above, the overlapping area of ​​the gate line Gate and the active layer 140 forms the gate of the transistor, and the active layer 140 is close to the lower edge of the first electrode 111. Therefore, the sub-pixel P controlled by a gate line Gate should be located above the gate line Gate along the second direction Y, that is, the gate line Gate corresponding to the sub-pixel P is close to the lower edge of the sub-pixel P along the second direction Y. The overlap of the gate line Gate and the opening 122 mentioned in this embodiment may refer to the overlap of the gate line Gate and the opening 122 in the sub-pixel P below it along the second direction Y, or in other words, the gate line Gate and the opening 122 whose projections overlap each other, and the sub-pixel P corresponding to the opening 122 is not driven and controlled by the gate line Gate.

[0136] Optional, you can continue to refer to Figure 36 and Figure 37 The first electrode 111 has a first projection 1110 on the plane where the substrate 10 is located, and the opening 122 has a second projection 1220 on the plane where the substrate 10 is located; the first projection 1110 includes two first edges 1111 that are relatively arranged and parallel along the second direction Y and two second edges 1112 that are relatively arranged and parallel along the first direction X; the second projection 1220 includes two third edges 1221 that are relatively arranged and parallel along the second direction Y and two fourth edges 1222 that are relatively arranged and parallel along the first direction X; the orthographic projection of the gate line Gate on the plane where the substrate 10 is located covers at least a portion of the first edge 1111 and at least a portion of the third edge 1221.

[0137] The pixel black area is close to the upper and lower edges of the opening 122. In this embodiment, along the thickness direction of the substrate, the gate line Gate covers at least part of the upper and lower edges of the first electrode 111 (the first edge 1111) and at least part of the upper and lower edges of the opening 122 (the third edge 1221), thereby ensuring the shielding effect of the gate line Gate on the pixel black area.

[0138] Optional, you can continue to refer to Figure 36 and Figure 37 Along the substrate thickness direction 3, the first light shielding structure 17 can cover the gate line Gate, prevent the display panel from leaking light, and improve the display effect.

[0139] Optional, you can continue to refer to Figure 3 , Figure 11 , Figure 13 andFigure 14 The first electrode 111 has a first projection 1110 on the plane where the substrate 10 is located, and the opening 122 has a second projection 1220 on the plane where the substrate 10 is located; the first projection 1110 includes two first edges 1111 that are relatively arranged and parallel along the second direction Y and two second edges 1112 that are relatively arranged and parallel along the first direction X; the second projection 1220 includes two third edges 1221 that are relatively arranged and parallel along the second direction Y and two fourth edges 1222 that are relatively arranged and parallel along the first direction X; the display panel also includes a plurality of sub-pixels P arranged in an array, and the sub-pixels P include the first electrodes 111 and the openings 122 that overlap each other; in the same sub-pixel P, the spacing between the first edge 1111 and the adjacent third edge 1221 is a first spacing d1, 0μm≤d1≤1μm.

[0140] The spacing between the first edge 1111 and the adjacent third edge 1221 refers to the spacing between the upper edge of the first projection 1110 and the upper edge of the opening 122 in the same sub-pixel P, and the spacing between the lower edge of the first projection 1110 and the lower edge of the opening 122, that is, the spacing between the upper edge (lower edge) of the first electrode 111 along the second direction Y and the upper edge (lower edge) of the opening 122 along the second direction Y.

[0141] As an optional solution, after the length of the opening 122 along the second direction Y is extended, the distance between the first edge 1111 and the third projection 171 adjacent to each other in the same sub-pixel P can be shortened to 0-1 μm, so that the upper and lower edges of the first electrode 111 and the upper and lower edges of the opening 122 are closer. In this way, the opening size can be ensured to be larger, and the electric field at the upper and lower edges of the opening 122 can be made more uniform. In addition, the first light shielding structure 17 can also more easily shield the upper and lower edges of the first electrode 111 (opening 122).

[0142] Optional, you can continue to refer to Figure 3 , Figure 11 , Figure 13 and Figure 14 For an embodiment in which a first electrode 111 overlaps with an opening 122 , in the same sub-pixel P, a distance between the second edge 1112 and an adjacent fourth edge 1222 is a second distance d2 , where 0 μm<d2<1 μm.

[0143] The spacing between the second edge 1112 and the adjacent fourth edge 1222 refers to the spacing between the left edge of the first projection 1110 (along the first direction X) and the left edge of the opening 122 in the same sub-pixel P, and the spacing between the right edge of the first projection 1110 and the right edge of the opening 122, that is, the spacing between the left and right edges of the first electrode 111 along the first direction X and the left and right edges of the opening 122 along the second direction Y.

[0144] As an optional solution, when the length of the opening 122 along the second direction Y is extended, the spacing between the second edge 1112 and the fourth projection 181 adjacent to each other in the same sub-pixel P along the first direction X can be controlled to be maintained within a range of 0-1 μm, so that the left and right edges of the first electrode 111 and the left and right edges of the opening 122 are close. The size of the opening 122 is ensured to be large, and the electric field at the left and right edges of the opening 122 is relatively uniform. Exemplarily, in some embodiments, the second spacing d2 can be 0.75 μm, but is not limited thereto.

[0145] It should be noted that when forming the opening 122, the spacing between different positions of the second edge 1112 and the fourth edge 1222 along the first direction X should be controlled to be consistent within the range allowed by the process error, and the second edge 1112 and the fourth edge 1222 should be kept parallel as much as possible.

[0146] Optional, you can continue to refer to Figure 3 , Figure 11 , Figure 13 and Figure 14 For a first electrode 111 and an opening 122 that overlap each other, the length of the first electrode 111 in the first direction X is greater than the length of the opening 122 in the first direction X, and the first length L1 is greater than the second length L2.

[0147] Taking the first electrode 111 and the opening 122 extending along the third direction as an example, the length of the first electrode 111 in the first direction X can be regarded as the width of the first electrode 111, and the length of the opening 122 in the first direction X can be regarded as the width of the opening 122. In this embodiment, the width of the first electrode 111 is greater than the width of the opening 122. In the same sub-pixel P, along the first direction X, the two fourth edges 1222 of the second projection 1220 are both located between the two second edges 1112 of the first projection 1110. In addition, the first length L1 of the first electrode 111 is greater than the first length L1 of the opening 122. In this arrangement, the size of the opening 122 in the second electrode 121 is smaller than the size of the first electrode 111, which can enhance the control capability of the liquid crystal molecules, and the smaller size of the opening 122 can reduce the interaction of the electric fields between adjacent sub-pixels P, reducing the possibility of crosstalk; in addition, setting the size of the first electrode 111 to be larger is also conducive to the transistor 14 supplying power to the first electrode 111.

[0148] Part of the edge of the first electrode 111 (first projection 1110 ) exceeds the corresponding edge of the opening 122 (second projection 1220 ). As shown in the figure, the upper edge of the first electrode 111 exceeds the upper edge of the opening 122 , but the present invention is not limited thereto.

[0149] Optional, Figure 38 A schematic diagram of a projection of a partial structure of another display panel provided in an embodiment of the present invention can be referred to Figure 38In a possible embodiment, in the substrate thickness direction Z, the first electrode 111 may cover the opening 122 .

[0150] like Figure 38 As shown, in the same sub-pixel P, along the first direction X, the two fourth edges 1222 of the second projection 1220 are both located between the two second edges 1112 of the first projection 1110; along the second direction Y, the two third edges 1221 of the second projection 1220 are both located between the two first edges 1111 of the first projection 1110. In this arrangement, a more uniform electric field can be formed in the opening 122 area, so that the liquid crystal molecules rotate more uniformly in the entire sub-pixel P area.

[0151] Optional, you can continue to refer to Figure 2 , Figure 12 , Figures 17 - 20 The array substrate 100 also includes a transistor 14. Along the substrate thickness direction, the film layer where the transistor 14 is located is located between the substrate 10 and the first electrode layer 11; the transistor 14 includes an active layer 140, and the active layer 140 is electrically connected to the first electrode 111 through a via hole via. Along the substrate thickness direction Z, the connecting via hole via and the opening 122 of the active layer 140 and the first electrode 111 overlap.

[0152] The specific configuration of the transistor 14 can refer to the above embodiment and will not be repeated here. In this embodiment, the connecting via hole via between the active layer 140 and the first electrode 111 overlaps with the opening 122. In other words, along the second direction Y, the opening 122 of the second electrode 121 extends downward to overlap with the third active portion 143 of the active layer 140, ensuring that the length of the opening 122 is relatively large.

[0153] Optionally, the display panel provided in the embodiment of the present invention may further include any structure known to those skilled in the art, such as a cover plate on the side of the color filter substrate 300 facing away from the liquid crystal layer 200, which is neither described nor limited in the embodiment of the present invention.

[0154] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 39 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present invention. Figure 39 As shown, the display device includes the display panel 1000 provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (such as a smart watch, a VR device), and a car display device, which is not limited by the embodiment of the present invention.

[0155] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: comprising an array substrate; The array substrate comprises a substrate and a first electrode layer and a second electrode layer stacked on one side of the substrate, wherein the second electrode layer is located on a side of the first electrode layer away from the substrate; the first electrode layer comprises a plurality of first electrodes, the second electrode layer comprises a second electrode, and the second electrode comprises a plurality of openings, and the openings overlap with the first electrodes along the thickness direction of the substrate; The array substrate further comprises a plurality of gate lines and a plurality of data lines, wherein the gate lines extend along a first direction, and a second direction is perpendicular to the first direction; For a first electrode and an opening that overlap each other, the length of the first electrode in the second direction is a first length, the length of the opening in the second direction is a second length, and the ratio of the second length to the first length is greater than or equal to 0.

8.

2. The display panel according to claim 1, characterized in that: The first electrode has a first projection on the plane where the substrate is located, and the opening has a second projection on the plane where the substrate is located; the first projection includes two first edges that are arranged oppositely and parallel along the second direction and two second edges that are arranged oppositely and parallel along the first direction; the second projection includes two third edges that are arranged oppositely and parallel along the second direction and two fourth edges that are arranged oppositely and parallel along the first direction; The display panel also includes a plurality of sub-pixels arranged in an array, and the sub-pixels include the first electrodes and the openings that overlap each other; in the same sub-pixel, the first edge and the third edge both extend along the first direction, and the extension direction of at least part of the second edge and at least part of the fourth edge intersects with the second direction.

3. The display panel according to claim 2, characterized in that: The first projection and the second projection are both parallelograms; In the same sub-pixel, the second edge is parallel to the fourth edge, and the extending directions of the second edge and the fourth edge have a first angle θ1 with the second direction, where 0°<θ1<20°.

4. The display panel according to claim 3, characterized in that: The sub-pixel further includes a transistor, and along the thickness direction of the substrate, the film layer where the transistor is located is located between the substrate and the first electrode layer; The transistor includes an active layer, the active layer includes a first active sub-section, a second active sub-section and a third active sub-section, two ends of the second active sub-section are respectively connected to the first active sub-section and the third active sub-section; the first active sub-section has a first sub-projection sub-section on the plane where the substrate is located, the second active sub-section has a second sub-projection sub-section on the plane where the substrate is located, and the third active sub-section has a third sub-projection sub-section on the plane where the substrate is located; The first sub-projection portion in the same sub-pixel is located on the side of the fourth edge facing the fourth edge of another sub-pixel, the second sub-projection portion is located on the side of the third edge facing the third edge of another sub-pixel, the third sub-projection portion at least partially overlaps with the first projection, and the third active portion is electrically connected to the first electrode through a via.

5. The display panel according to claim 4, characterized in that: An extension direction of at least a portion of the first active sub-portion and at least a portion of the third active sub-portion is parallel to an extension direction of the second edge.

6. The display panel according to claim 2, characterized in that: One of the second edges includes a first line segment and a second line segment connected to each other, wherein the first line segment and the second line segment are respectively connected to different first edges; one of the fourth edges includes a third line segment and a fourth line segment connected to each other, wherein the third line segment and the fourth line segment are respectively connected to different third edges; Among them, the first line segment is parallel to the third line segment, the second line segment is parallel to the fourth line segment, the second line segment and the fourth line segment extend along the second direction, and the extension direction of the first line segment and the third line segment has a first angle θ1 with the second direction, 0°<θ1<20°.

7. The display panel according to claim 6, characterized in that: The sub-pixel further includes a transistor, and along the thickness direction of the substrate, the film layer where the transistor is located is located between the substrate and the first electrode layer; The transistor includes an active layer, the active layer includes a first active sub-section, a second active sub-section and a third active sub-section, two ends of the second active sub-section are respectively connected to the first active sub-section and the third active sub-section; the first active sub-section has a first sub-projection sub-section on the plane where the substrate is located, the second active sub-section has a second sub-projection sub-section on the plane where the substrate is located, and the third active sub-section has a third sub-projection sub-section on the plane where the substrate is located; The first sub-projection portion in the same sub-pixel is located on the side of the fourth line segment facing the fourth line segment of another sub-pixel, the second sub-projection portion is located on the side of the third edge facing the third edge of another sub-pixel, the third sub-projection portion at least partially overlaps with the first projection, and the third active portion is electrically connected to the first electrode through a via.

8. The display panel according to claim 7, characterized in that: At least a portion of the first active subsection and at least a portion of the third active subsection extend along the second direction.

9. The display panel according to claim 2, characterized in that: In the same sub-pixel, the first projection and the second projection have the same profile.

10. The display panel according to claim 1, characterized in that: The first electrode has a first projection on the plane where the substrate is located, and the opening has a second projection on the plane where the substrate is located; the first projection includes two first edges that are arranged oppositely and parallel along the second direction and two second edges that are arranged oppositely and parallel along the first direction; the second projection includes two third edges that are arranged oppositely and parallel along the second direction and two fourth edges that are arranged oppositely and parallel along the first direction; The display panel further includes a first light-shielding structure, which extends along the first direction and is arranged along the second direction; the first light-shielding structure has a third projection on the plane where the substrate is located, and the third projection covers the first edge and the third edge.

11. The display panel according to claim 10, characterized in that: The length of the overlapping area between the third projection and the first projection in the second direction is a third length L3, and the length of the overlapping area between the third projection and the second projection in the second direction is a fourth length L4; Among them, 1μm<L3<3μm, 1μm<L4<3μm.

12. The display panel according to claim 10, characterized in that: Along the thickness direction of the substrate, the film layer where the first light-shielding structure is located is located between the first electrode layer and the substrate.

13. The display panel according to claim 1, characterized in that: The film layer where the gate line is located is located between the first electrode layer and the substrate; An orthographic projection of the gate line on the plane where the substrate is located and an orthographic projection of the opening on the plane where the substrate is located have an overlapping area.

14. The display panel according to claim 13, characterized in that: The first electrode has a first projection on the plane where the substrate is located, and the opening has a second projection on the plane where the substrate is located; the first projection includes two first edges that are arranged oppositely and parallel along the second direction and two second edges that are arranged oppositely and parallel along the first direction; the second projection includes two third edges that are arranged oppositely and parallel along the second direction and two fourth edges that are arranged oppositely and parallel along the first direction; The orthographic projection of the gate line on the plane where the substrate is located covers at least a portion of the first edge and at least a portion of the third edge.

15. The display panel according to claim 1, characterized in that: The first electrode has a first projection on the plane where the substrate is located, and the opening has a second projection on the plane where the substrate is located; the first projection includes two first edges that are arranged oppositely and parallel along the second direction and two second edges that are arranged oppositely and parallel along the first direction; the second projection includes two third edges that are arranged oppositely and parallel along the second direction and two fourth edges that are arranged oppositely and parallel along the first direction; The display panel further includes a plurality of sub-pixels arranged in an array, wherein the sub-pixels include the first electrodes and the openings overlapping each other; in the same sub-pixel, a distance between the first edge and the adjacent third edge is a first distance d1, 0μm≤d1≤1μm.

16. The display panel according to claim 1, characterized in that: The first electrode has a first projection on the plane where the substrate is located, and the opening has a second projection on the plane where the substrate is located; the first projection includes two first edges that are arranged oppositely and parallel along the second direction and two second edges that are arranged oppositely and parallel along the first direction; the second projection includes two third edges that are arranged oppositely and parallel along the second direction and two fourth edges that are arranged oppositely and parallel along the first direction; The display panel also includes a plurality of sub-pixels arranged in an array, and the sub-pixels include the first electrodes and the openings that overlap each other; in the same sub-pixel, the spacing between the second edge and the adjacent fourth edge is a second spacing d2, 0μm<d2<1μm.

17. The display panel according to claim 1, characterized in that: For a first electrode and an opening that overlap each other, a length of the first electrode in the first direction is greater than a length of the opening in the first direction, and the first length is greater than the second length.

18. The display panel according to claim 17, characterized in that: The first electrode covers the opening.

19. The display panel according to claim 1, characterized in that: The array substrate further comprises a transistor, and along the thickness direction of the substrate, the film layer where the transistor is located is located between the substrate and the first electrode layer; The transistor includes an active layer, the active layer is electrically connected to the first electrode through a via hole, and along the thickness direction of the substrate, the connecting via hole of the active layer and the first electrode overlaps with the opening.

20. The display panel according to claim 1, characterized in that: The display panel further includes a second light shielding structure, which extends along the second direction and is arranged along the first direction; The opening has a second projection on the plane where the substrate is located, and the second light shielding structure has a fourth projection on the plane where the substrate is located. The fourth projection is located between two adjacent second projections along the first direction.

21. The display panel according to claim 20, characterized in that: The display panel further comprises a liquid crystal layer and a color filter substrate, wherein the liquid crystal layer is located between the array substrate and the color filter substrate along the thickness direction of the substrate; The second light shielding structure is located on the color filter substrate.

22. The display panel according to claim 1, characterized in that: The array substrate further comprises a third electrode layer, and along the thickness direction of the substrate, the third electrode layer is located between the first electrode layer and the substrate; The third electrode layer includes a third electrode. Along the thickness direction of the substrate, the third electrode at least covers the first electrode and the opening.

23. A display device, characterized in that: A display panel comprising any one of claims 1-22.

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