Efficient management system, method and device for complex electronic system and medium
By designing a complex electronic system efficient management system, using cluster management nodes and container proxy technology, unified management of FPGA resources and collaborative management of multi-level computing resources are realized, the problem of FPGA resource management in embedded devices is solved, computing efficiency and development and deployment convenience are improved, and efficient computing and real-time requirements in the embedded field are met.
Patent Information
- Application Number
- CN202510202979.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2025-06-10
AI Technical Summary
The prior art is difficult to effectively manage FPGA resources in embedded devices, resulting in cloud-native applications facing the problems of resource limitation, power consumption sensitivity and real-time requirements in the embedded field.
By designing a complex electronic system efficient management system, using cluster management nodes, CPU clusters, FPGA management node clusters, FPGA computing node clusters and RapidIO management nodes, unified management of FPGA resources and collaborative management of multi-level computing resources are realized. The system uses containers to proxy FPGA resources to realize parameter issuance and computational results interoperability, and realizes efficient computing collaboration and resource sharing through RapidIO interoperability.
It realizes efficient management of FPGA resources in embedded cloud native environment, improves computing efficiency and convenience of development and deployment, eliminates the problem of restricted FPGA resources, and meets the requirements for efficient computing and real-time in the embedded field.
Smart Images
Figure CN120123084A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of complex electronic system management, and more specifically, to an efficient management system, method, device and medium for complex electronic systems. Background Art
[0002] Applications running on embedded devices vary. When an application needs to use an FPGA, the hardware is usually designed in such a way that the FPGA is directly connected to the CPU via PCIE, enabling the FPGA to become a driver of the CPU to achieve functions such as algorithm acceleration. However, in the embedded field, due to limited FPGA resources, especially in the context of localization, multiple FPGAs need to cooperate to implement real-time domain algorithms to provide computing acceleration for the CPU. When the FPGA resources corresponding to a certain CPU have been occupied, this method is no longer applicable.
[0003] In the embedded environment, there is a lack of a unified resource management platform. Even though embedded cloud native applies the advantages of cloud native to embedded devices and realizes efficient application development and deployment of the CPU, it still cannot solve the management problem of FPGAs. Summary of the Invention
[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an efficient management system, method, device and medium for complex electronic systems, which can not only improve the computing efficiency of embedded cloud native applications, but also improve the convenience of development and deployment.
[0005] The purpose of the present invention is achieved through the following solutions:
[0006] An efficient management system for complex electronic systems, comprising:
[0007] A cluster management node, a CPU cluster, an FPGA management node cluster, an FPGA computing node cluster, and a RapidIO management node; the CPU computing nodes are interconnected via Ethernet to form a CPU cluster, which is managed by a container management platform; the FPGA management nodes are interconnected via Ethernet to form an FPGA management node cluster, which is managed by a container platform; the FPGA computing nodes are interconnected via a RapidIO bus to form an FPGA computing node cluster, and each FPGA is managed by one or more FPGA management nodes;
[0008] The cluster management node directly manages the CPU cluster and the FPGA management node cluster; the FPGA management node acts as an agent for the FPGA computing node; the cluster management node, the CPU cluster, and the FPGA management node communicate with each other via Ethernet; the FPGA computing nodes communicate with each other via a RapidIO bus; the FPGA management node and the FPGA computing node communicate with each other via a high-speed port.
[0009] Further, it includes the following task execution process:
[0010] One task is jointly completed by multiple CPUs and multiple FPGAs required for orchestration. Among them, the CPU computing nodes have programs issued by the container management platform and load the programs. The FPGA computing nodes have programs issued by the container management platform to the FPGA management nodes, and the FPGA management nodes load the FPGA programs. The FPGA computing node clusters communicate collaboratively through RapidIO. The operation results are transmitted to the FPGA management nodes through high-speed ports, and the FPGA management nodes upload them to the required CPU computing nodes.
[0011] A method for efficient management of complex electronic systems, based on the complex electronic system efficient management system described in any one of the above, includes the following resource deployment process steps:
[0012] S1. The cluster management node executes the deployment policy and initiates the deployment;
[0013] S2. The cluster management node distributes the CPU program to the CPU nodes through the container image according to the orchestration requirements and the deployment policy, and installs and deploys the application program;
[0014] S3. After installing and deploying the application program, the cluster management node obtains the status of the FPGA through the FPGA management node and selects eligible FPGA resources;
[0015] S4. After obtaining the FPGA resources, the FPGA program is distributed to the FPGA management node; the FPGA management node loads the FPGA program to complete the deployment of the FPGA program.
[0016] Further, in steps S1 to S4, if any process among CPU resource selection, CPU program deployment, FPGA resource selection, and FPGA program deployment fails, the entire deployment process fails.
[0017] A method for efficient management of complex electronic systems, based on the complex electronic system efficient management system described in any one of the above, includes the following FPGA inter-resource communication networking process steps:
[0018] Step Sa. After the FPGA program is loaded, the switching chip detects the RapidIO signal and notifies the RapidIO network management node to implement the FPGA network access process;
[0019] Step Sb. After the cluster management node queries that all FPGA nodes in this task of the RapidIO network management have accessed the network, it notifies the RapidIO network management node to configure the communication routes between the FPGA nodes that have accessed the network this time;
[0020] Step Sc, after all the routing configurations are successful, the cluster management node notifies the RapidIO network management node to configure the virtual communication channels between the FPGA nodes that have joined the network this time, enabling communication between FPGA clusters.
[0021] Further, in Steps Sa to Sc, a failure in joining the network, a failure in routing configuration, or a failure in virtual communication channel configuration will all result in the failure of FPGA cluster networking and, at the same time, the failure of the entire deployment process.
[0022] An efficient management method for complex electronic systems, based on the efficient management system for complex electronic systems described in any one of the above, includes the following steps for FPGA cluster and CPU networking:
[0023] Step 1, after the CPU program is deployed, start the server program for communicating with the FPGA management node.
[0024] Step 2, after the FPGA program is loaded, the FPGA management node actively initiates a high-speed connection handshake request with the FPGA to complete high-speed link establishment.
[0025] Step 3, after the FPGA management node establishes a high-speed connection with the FPGA, actively start the client connection program for communicating with the corresponding CPU to achieve transparent forwarding of FPGA data to CPU data; and this communication path is also used to implement functions such as FPGA parameter distribution, FPGA status reporting, and FPGA operation result reporting.
[0026] Further, in Steps 1 to 3, a failure in establishing a high-speed connection between the FPGA and the FPGA management node or a failure in establishing a connection between the FPGA management node and the CPU will result in the failure of FPGA and CPU communication networking, and further lead to the failure of the entire deployment process.
[0027] A computer device includes a processor and a memory, and a computer program is stored in the memory. When the computer program is loaded and executed by the processor, it performs the method described in any one of the above.
[0028] A computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to perform the method described in any one of the above.
[0029] The beneficial effects of the present invention include:
[0030] The present invention realizes unified management of the embedded environment through cloud native, realizes rapid installation and deployment of the embedded environment, and improves the CPU acceleration ability through the cooperation of multiple FPGAs.
[0031] The present invention uses an FPGA as a shared computing resource cluster to pair any CPU with any FPGA cluster and achieve integrated management of the CPU and FPGA. This framework can solve problems such as resource constraints, power consumption sensitivity, and high real-time requirements faced by cloud-native applications in the embedded field, and eliminates the limitation that a single CPU-driven FPGA cannot meet the application's need to use multiple cascaded FPGAs to form a dedicated computing unit.
[0032] The present invention proposes a new idea that can achieve efficient management of complex electronic systems. Specifically, an FPGA is used as a shared computing resource cluster to form multi-level computing resources, and these FPGA resource sets are proxied by containers to achieve parameter distribution and the interconnection of operation results with other CPUs, thereby pairing any CPU with any FPGA cluster and achieving integrated management of the CPU and FPGA. At the same time, the solution of the present invention provides an FPGA resource orchestration framework based on container proxy, allowing different FPGA resources to be freely combined to form multi-level computing resources and communicate through RapidIO, thereby achieving efficient computing collaboration and computing resource sharing. In this way, the advantages of FPGAs can be better utilized in the embedded cloud-native environment, improving the performance and reliability of application programs, and thus promoting the development of embedded systems. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts.
[0034] Figure 1 It is a network connection diagram of the present invention;
[0035] Figure 2 is Figure 1 a resource deployment flowchart of the network;
[0036] Figure 3 is Figure 1 a resource communication networking flowchart between FPGAs of the network;
[0037] Figure 4 is Figure 1 a networking flowchart of an FPGA cluster and a CPU of the network. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0038] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended, replaced in any way.
[0039] The specific implementation process of the present invention is as follows:
[0040] As Figure 1 shown, in a preferred embodiment, a complex electronic system efficient management system is specifically provided, including: a cluster management node, a CPU cluster, an FPGA management node cluster (FPGA C), an FPGA computing node cluster, and a RapidIO management node; the cluster management node directly manages the CPU cluster and the FPGA management node; the FPGA management node acts as an agent for the FPGA computing node; the cluster management node, the CPU cluster, and the FPGA management node communicate with each other through Ethernet; the FPGA nodes communicate with each other through the RapidIO bus; the FPGA management node and the FPGA node communicate with each other through a high-speed port (HP).
[0041] As Figure 2 shown, the cluster management node executes the deployment policy and initiates the deployment; the cluster management node, according to the deployment policy, distributes the CPU program to the CPU node through the container image and installs and deploys the application program; the cluster management node obtains the status of the FPGA through the FPGA management node, selects eligible FPGA resources, and distributes the FPGA program to the FPGA management node; the FPGA management node loads the FPGA program to complete the deployment of the FPGA program.
[0042] It should be noted that Figure 2 in, if any process of CPU resource selection, CPU program deployment, FPGA resource selection, and FPGA program deployment fails, the entire deployment process fails.
[0043] As Figure 3 shown, after the FPGA program is loaded, the switching chip detects the RapidIO signal and notifies the RapidIO network management node to implement the FPGA network access process. After the cluster management node queries that all FPGA nodes in this task of the RapidIO network management are networked, it notifies the RapidIO network management node to configure the communication routing between the FPGA nodes that have networked this time; the cluster management node notifies the RapidIO network management node to configure the virtual communication channels between the FPGA nodes that have networked this time to achieve the interconnection between FPGA clusters.
[0044] It should be noted that Figure 3 in, network access failure, routing configuration failure, and virtual communication channel configuration failure will all cause the FPGA cluster networking to fail, and at the same time cause the entire deployment process to fail.
[0045] AsFigure 4 As shown in Figure 4 , after the CPU program deployment is completed, start the server program for communicating with the FPGA management node; after the FPGA program is loaded, the FPGA management node actively initiates a high-speed connection handshake request with the FPGA to complete high-speed link establishment; after the FPGA management node establishes a high-speed connection with the FPGA, actively start the client connection program for communicating with the corresponding CPU to achieve transparent forwarding of FPGA data to CPU data; this communication path realizes functions such as FPGA parameter distribution, FPGA status reporting, and FPGA operation result reporting.
[0046] Figure 4 In Figure 4 , if the high-speed connection establishment between the FPGA and the FPGA management node fails, or the connection establishment between the FPGA management node and the CPU fails, it will cause the communication networking between the FPGA and the CPU to fail, and further lead to the failure of the entire deployment process.
[0047] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or extended, replaced in any logical manner from the above specific implementation manners, such as the disclosed technical principles, disclosed technical features, or implicitly disclosed technical features.
[0048] Embodiment 1
[0049] An efficient management system for complex electronic systems includes: a cluster management node, a CPU cluster, an FPGA management node cluster, an FPGA computing node cluster, and a RapidIO management node; the CPU computing nodes are interconnected through Ethernet to form a CPU cluster, which is managed by a container management platform; the FPGA management nodes are interconnected through Ethernet to form an FPGA management node cluster, which is managed by a container platform; the FPGA computing nodes are interconnected through a RapidIO bus to form an FPGA computing node cluster, and each FPGA is managed by one or more FPGA management nodes;
[0050] The cluster management node directly manages the CPU cluster and the FPGA management node cluster; the FPGA management node acts as an agent for the FPGA computing node; the cluster management node, the CPU cluster, and the FPGA management node communicate with each other through Ethernet; the FPGA computing nodes communicate with each other through a RapidIO bus; the FPGA management node and the FPGA computing node communicate with each other through a high-speed port.
[0051] Embodiment 2
[0052] Based on Embodiment 1, it includes the following task execution process:
[0053] A task is jointly completed by multiple CPUs and multiple FPGAs required for orchestration. Among them, the CPU computing nodes are issued with programs by the container management platform and the programs are loaded. The FPGA computing nodes are issued with programs by the container management platform to the FPGA management nodes, and the FPGA management nodes load the FPGA programs. The FPGA computing node clusters communicate collaboratively through RapidIO. The operation results are transmitted to the FPGA management nodes through high-speed ports and uploaded by the FPGA management nodes to the required CPU computing nodes.
[0054] Embodiment 3
[0055] A method for efficient management of complex electronic systems, based on the complex electronic system efficient management system described in any one of Embodiment 1 or Embodiment 2, includes the following resource deployment process steps:
[0056] S1. The cluster management node executes the deployment policy and initiates the deployment;
[0057] S2. The cluster management node distributes the CPU program to the CPU nodes through the container image according to the orchestration requirements and the deployment policy, and installs and deploys the application program;
[0058] S3. After installing and deploying the application program, the cluster management node obtains the status of the FPGA through the FPGA management node and selects eligible FPGA resources;
[0059] S4. After obtaining the FPGA resources, the FPGA program is distributed to the FPGA management node; the FPGA management node loads the FPGA program to complete the deployment of the FPGA program.
[0060] Embodiment 4
[0061] On the basis of Embodiment 3, in steps S1 to S4, if any process of CPU resource selection, CPU program deployment, FPGA resource selection, and FPGA program deployment fails, the entire deployment process fails.
[0062] Embodiment 5
[0063] A method for efficient management of complex electronic systems, based on the complex electronic system efficient management system of Embodiment 1 or Embodiment 2, includes the following FPGA inter-resource communication networking process steps:
[0064] Step Sa. After the FPGA program is loaded, the switching chip detects the RapidIO signal and notifies the RapidIO network management node to implement the FPGA network access process;
[0065] Step Sb, after the cluster management node queries that all FPGA nodes for this task in the RapidIO network management are online, it notifies the RapidIO network management node to configure the communication routes between the FPGA nodes that are online this time.
[0066] Step Sc, after all route configurations are successful, the cluster management node notifies the RapidIO network management node to configure the virtual communication channels between the FPGA nodes that are online this time, so as to achieve interconnection between FPGA clusters.
[0067] Embodiment 6
[0068] Based on Embodiment 5, in Steps Sa to Sc, a failure in network access, a failure in route configuration, or a failure in virtual communication channel configuration will all cause the failure of FPGA cluster networking and, at the same time, the failure of the entire deployment process.
[0069] Embodiment 7
[0070] An efficient management method for complex electronic systems, based on the efficient management system for complex electronic systems described in any one of Embodiments 1 or 2, includes the following steps for networking an FPGA cluster and a CPU:
[0071] Step 1, after the CPU program deployment is completed, start the server program for communicating with the FPGA management node.
[0072] Step 2, after the FPGA program is loaded, the FPGA management node actively initiates a high-speed connection handshake request with the FPGA to complete high-speed link establishment.
[0073] Step 3, after the FPGA management node establishes a high-speed connection with the FPGA, it actively starts the client connection program for communicating with the corresponding CPU to achieve transparent forwarding of FPGA data to CPU data; and this communication path is also used to implement functions such as FPGA parameter distribution, FPGA status reporting, and FPGA operation result reporting.
[0074] Embodiment 8
[0075] Based on Embodiment 7, in Steps 1 to 3, a failure in establishing a high-speed connection between the FPGA and the FPGA management node or a failure in establishing a connection between the FPGA management node and the CPU will cause the failure of FPGA-CPU communication networking, and further lead to the failure of the entire deployment process.
[0076] Embodiment 9
[0077] A computer device includes a processor and a memory, and a computer program is stored in the memory. When the computer program is loaded and executed by the processor, it performs the method described in any one of Embodiments 3 to 8.
[0078] Embodiment 10
[0079] A computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to perform the method described in any one of Embodiments 3 to 8.
[0080] The units involved in the embodiments of the present invention can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.
[0081] According to one aspect of the embodiments of the present invention, there is provided a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the methods provided in the above various alternative implementation manners.
[0082] As another aspect, the embodiments of the present invention further provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device implements the methods described in the above embodiments.
Claims
1. An efficient management system for complex electronic systems, characterized in that: include: Cluster management node, CPU cluster, FPGA management node cluster, FPGA computing node cluster and RapidIO management node; The CPU computing nodes are interconnected through Ethernet to form a CPU cluster, which is managed by the container management platform; the FPGA management nodes are interconnected through Ethernet to form an FPGA management node cluster, which is managed by the container platform; the FPGA computing nodes are interconnected through the RapidIO bus to form an FPGA computing node cluster, and each FPGA is managed by one or more FPGA management nodes; The cluster management node directly manages the CPU cluster and the FPGA management node cluster; the FPGA management node acts as an agent for the FPGA computing node; The cluster management node, CPU cluster, and FPGA management node are interconnected through Ethernet; the FPGA computing nodes are interconnected through the RapidIO bus; and the FPGA management node and FPGA computing node are interconnected through the high-speed port.
2. The complex electronic system efficient management system according to claim 1, characterized in that: The task execution process includes the following: A task is completed by multiple CPUs and multiple FPGAs required for orchestration. The container management platform sends programs to and loads programs on the CPU computing node. The container management platform sends programs to the FPGA computing node, and the FPGA management node loads the FPGA program. The FPGA computing node clusters communicate with each other through RapidIO, and the calculation results are transmitted to the FPGA management node through the high-speed port, and then uploaded to the required CPU computing node by the FPGA management node.
3. A method for efficient management of complex electronic systems, characterized in that: The efficient management system of complex electronic systems according to any one of claims 1-2 comprises the following resource deployment process steps: S1, the cluster management node executes the deployment strategy and initiates deployment; S2: The cluster management node sends the CPU program to the CPU node through the container image according to the orchestration requirements and deployment strategy, and installs and deploys the application program; S3, after the application is installed and deployed, the cluster management node obtains the FPGA status through the FPGA management node and selects the FPGA resources that meet the conditions; S4, after the FPGA resources are acquired, the FPGA program is sent to the FPGA management node; The FPGA management node loads the FPGA program to complete the FPGA program deployment.
4. The complex electronic system efficient management method according to claim 3, characterized in that: In step S1 to step S4, if any process of CPU resource selection, CPU program deployment, FPGA resource selection, and FPGA program deployment fails, the entire deployment process fails.
5. A method for efficient management of complex electronic systems, characterized in that: The efficient management system of complex electronic systems according to any one of claims 1 to 2 includes the following steps of inter-FPGA resource communication networking process: Step Sa, after the FPGA program is loaded, the switching chip detects the RapidIO signal and notifies the RapidIO network management node to implement the FPGA network access process; Step Sb, after the cluster management node queries the RapidIO network management for all FPGA nodes of this task and they are connected to the network, the cluster management node is notified to configure the communication routes between the FPGA nodes that are connected to the network this time; Step Sc: After all routes are configured successfully, the cluster management node notifies the RapidIO network management node to configure virtual communication channels between the FPGA nodes that are connected to the network this time, so as to achieve intercommunication between FPGA clusters.
6. The complex electronic system efficient management method according to claim 5, characterized in that: In steps Sa to Sc, network access failure, routing configuration failure, and virtual communication channel configuration failure will all lead to FPGA cluster networking failure, and the entire deployment process will fail.
7. A method for efficient management of complex electronic systems, characterized in that: The efficient management system of complex electronic systems according to any one of claims 1 to 2 includes the following steps of FPGA cluster and CPU networking process: Step 1: After the CPU program is deployed, start the server program that communicates with the FPGA management node; Step 2: After the FPGA program is loaded, the FPGA management node actively initiates a high-speed connection handshake request with the FPGA to complete the high-speed link establishment; Step 3: After the FPGA management node establishes a high-speed connection with the FPGA, it actively starts the client connection program that communicates with the corresponding CPU to realize transparent forwarding of FPGA data to CPU data; and this communication path is also used to realize the functions of FPGA parameter distribution, FPGA status reporting and FPGA operation result reporting.
8. The complex electronic system efficient management method according to claim 7, characterized in that: In steps 1 to 3, failure to establish a high-speed connection between the FPGA and the FPGA management node, and failure to establish a connection between the FPGA management node and the CPU will cause the communication network between the FPGA and the CPU to fail, and then cause the entire deployment process to fail.
9. A computer device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 3 to 8 is executed.
10. A computer-readable storage medium, characterized in that: A computer program is stored in the readable storage medium, and the computer program is loaded by a processor to execute the method according to any one of claims 3 to 8.