Coding and decoding method, device and electronic equipment

Abstract

The present invention discloses a coding and decoding method, device and electronic device. The method includes the following steps: S1. Coding step; S2. Data selection step; S3. Decoding step. Combining weight reduction coding and decoding with ECC coding and decoding. Method 1 changes the coding method of ECC, and enables the ECC coding and decoding to have a weight reduction function by separately inverting the user data bits and the check bits. Method 2 simultaneously changes the input data and coding method of ECC. First, the input data of ECC is changed through the first layer of weight reduction coding, so that ECC can generate a check bit with a smaller Hamming weight, and then the ECC coding and decoding is further enabled to have a weight reduction function by inverting the check bits.

Description

Technical Field

[0001] The present invention relates to a coding and decoding method, a device and an electronic device. Background Art

[0002] Spin transfer torque magnetic random access memory (STT-MRAM) stands out among emerging memory technologies due to its non-volatility, high endurance, high storage density, and full compatibility with CMOS processes. It has become the preferred solution for the future of embedded nonvolatile memories (eNVM). However, STT-MRAM can be subject to failures such as write failures, read disturb, and short-circuit hard errors, which affect its reliability. These three types of failures exhibit asymmetric behavior.

[0003] 1) Write failure. Writing stored data in STT-MRAM is an asymmetric process. Given the same write current amplitude, the time it takes to write a "0→1" sequence is longer than the time it takes to write a "1→0" sequence. Therefore, the write reliability of an STT-MRAM cell primarily depends on the "0→1" write failure rate.

[0004] 2) Read disturb failure. To improve reliability, the direction of the STT-MRAM read current is typically designed to be the same as the current direction of the "1→0" write. Therefore, read disturb failure only affects the high-resistance cells storing "1" and does not affect the low-resistance cells storing "0."

[0005] 3) Short-circuit hard errors. Continuous use of STT-MRAM during its lifecycle can cause oxide barrier breakdown or oxide thickness changes, leading to short-circuit hard errors in the memory cells, manifesting as permanent failures such as stuck-at-0.

[0006] By reducing the Hamming weight of the stored codeword, the asymmetric nature of STT-MRAM failures can be exploited to effectively reduce the probability of writing "0→1" and reading "1," thereby reducing write failures and read disturb failures. Simultaneously, this method increases the probability of writing "0" to a shorted bit, allowing the correct data to be read directly from the shorted bit, alleviating the error correction pressure placed on the ECC by shorted hard errors.

[0007] However, conventional ECC codecs do not have the ability to reduce the Hamming weight. Summary of the Invention

[0008] To solve the above problems, the present application provides a coding and decoding method, device and electronic device.

[0009] The present invention provides the following technical solutions:

[0010] A coding and decoding method comprises the following steps:

[0011] S1. Collection steps

[0012] Collect binary data and form source code;

[0013] The binary data described in this application may be a set of discrete digital information of arbitrary bit width from any data source in any storage form. The arbitrary storage form includes, but is not limited to, electronic charge storage, magnetic domain orientation storage, photon modulation storage, and resistive switching effect storage. The arbitrary data sources include, but are not limited to, sources generated by computing devices, sources perceived by the physical environment, biological signal sources, and human-computer interaction sources.

[0014] S2. Encoding steps

[0015] S2.1. Generate an ECC check bit based on the source code through ECC encoding, and add a first flag bit for marking the data state of the ECC check bit. Concatenate the source code, the ECC check bit, and the first flag bit to form a first set of data. Invert the ECC check bit to obtain the one's complement of the ECC check bit. Simultaneously, invert the first flag bit to obtain the one's complement of the first flag bit. Concatenate the source code, the one's complement of the ECC check bit, and the one's complement of the first flag bit to form a second set of data. The data state of the ECC check bit is either the original state or the inverted state.

[0016] S2.2. Add a second flag bit to mark the data state of the source code after the first set of data, which is used as the first set of output data; invert the first set of output data to obtain the inverse of the first set of output data, which is used as the second set of output data; add a second flag bit to the second set of data to obtain the third set of output data; invert the third set of output data to obtain the inverse of the third set of output data, which is used as the fourth set of output data; the data state of the source code is either the original state or the inverse state;

[0017] S3. Data selection step

[0018] Calculate the Hamming weights of the first, second, third, and fourth output data groups respectively, and select the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > third group of output data > fourth group of output data > second group of output data;

[0019] S4. Decoding steps

[0020] S4.1. Restore the ECC check bit and source code based on the first flag bit and the second flag bit of the stored data;

[0021] S4.2. Perform ECC decoding based on the restored source code and ECC check bits.

[0022] An apparatus for implementing the above-mentioned encoding and decoding method includes at least:

[0023] The acquisition module is used to collect binary data and form source code;

[0024] The encoding module generates an ECC check bit through ECC encoding according to the source code, and adds a first flag bit for marking the data state of the ECC check bit, and splices the source code, the ECC check bit and the first flag bit to form a first group of data; inverts the ECC check bit to obtain the inverse of the ECC check bit, and at the same time, inverts the first flag bit to obtain the inverse of the first flag bit, and splices the source code, the inverse of the ECC check bit and the inverse of the first flag bit to form a second group of data; the data state of the ECC check bit is the original state or the inverse state; adds a second flag bit for marking the data state of the source code after the first group of data as the first group of output data; inverts the first group of output data to obtain the inverse of the first group of output data as the second group of output data; adds a second flag bit after the second group of data as the third group of output data; inverts the third group of output data to obtain the inverse of the third group of output data as the fourth group of output data; the data state of the source code is the original state or the inverse state;

[0025] The data selection module calculates the Hamming weights of the first, second, third, and fourth output data groups, respectively, and selects the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > third group of output data > fourth group of output data > second group of output data;

[0026] The decoding module restores the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data respectively; and performs ECC decoding according to the restored source code and the ECC check bit.

[0027] A coding and decoding method comprises the following steps:

[0028] S1. Collection steps

[0029] Collect binary data and form source code;

[0030] S2. Encoding steps

[0031] S2.1. Generating at least one set of coded data using at least one encoding method based on the source code, adding a first flag for identifying the source code and the encoding method of the coded data, concatenating the source code and the first flag to form a first set of data; and concatenating the coded data and the first flag to form coded flag data.

[0032] S2.2. Generate ECC check bits respectively according to the first group of data and the coding flag data through ECC encoding, and add a second flag bit for marking the data state of the ECC check bits; splice the first group of data and the corresponding ECC check bits and the corresponding second flag bits as the first group of output data; invert the ECC check bits to obtain the inverse of the ECC check bits, and at the same time, invert the second flag bit to obtain the inverse of the second flag bit, and splice the first group of data and the inverse of the corresponding ECC check bits and the inverse of the corresponding second flag bit as the second group of output data; splice the coding flag data and the corresponding ECC check bits and the second flag bit as the first coding flag data output data; invert the ECC check bits of the coding flag data to obtain the inverse of the ECC check bits, and at the same time, invert the second flag bit of the coding flag data to obtain the inverse of the second flag bit, and splice the coding flag data and the inverse of the corresponding ECC check bits and the inverse of the corresponding second flag bit as the second coding flag data output data; the data state of the ECC check bits is the original state or the inverted state;

[0033] S3. Data selection step

[0034] Calculate the Hamming weights of the first group of output data, the second group of output data, the first coding flag data output data, and the second coding flag data output data respectively, and select the group of data with the smallest Hamming weight as the stored data; if there is more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > second group of output data > first coding flag data output data and second coding flag data output data, and the corresponding decoding methods are arranged from low to high complexity;

[0035] S4. Decoding steps

[0036] S4.1. Restore the ECC check bit based on the second flag bit of the stored data;

[0037] S4.2. Perform ECC decoding based on the restored ECC check bits;

[0038] S4.3. Restore the source code based on the first flag bit of the ECC decoded data.

[0039] Furthermore, the encoding method includes at least one of the inverse code, Gray code, backward XOR coding, and cyclic shift coding. The above decoding methods are arranged from low to high in complexity as inverse code, Gray code, backward XOR coding, and cyclic shift coding.

[0040] An apparatus for implementing the above-mentioned encoding and decoding method includes at least:

[0041] The acquisition module is used to collect binary data and form source code;

[0042] The encoding module is used to form at least one set of encoded data according to the source code through at least one encoding method, and add a first flag bit for marking the encoding method of the source code and the encoded data, splicing the source code and the first flag bit to form a first set of data; splicing the encoded data and the first flag bit to form encoded flag data; generating ECC check bits according to the first set of data and the encoded flag data through ECC encoding, and adding a second flag bit for marking the data state of the ECC check bits; splicing the first set of data and the corresponding ECC check bits and the corresponding second flag bit as the first set of output data; inverting the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, the second flag bit is also inverted. Inverting to obtain the inverse of the second flag bit, splicing the first group of data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit as the second group of output data; splicing the coded flag data and the corresponding ECC check bit and the second flag bit as the first coded flag data output data; inverting the ECC check bit of the coded flag data to obtain the inverse of the ECC check bit, and at the same time, inverting the second flag bit of the coded flag data to obtain the inverse of the second flag bit, splicing the coded flag data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit as the second coded flag data output data; the data state of the ECC check bit is the original state or the inverse state;

[0043] The data selection module calculates the Hamming weights of the first group of output data, the second group of output data, the first coding mark data output data, and the second coding mark data output data, and selects the group of data with the smallest Hamming weight as the stored data; if there is more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > second group of output data > first coding mark data output data and second coding mark data output data, and the decoding method complexity corresponding to the data is arranged from low to high;

[0044] The decoding module restores the ECC check bit according to the second flag bit of the stored data; performs ECC decoding according to the restored ECC check bit; and restores the source code according to the first flag bit of the ECC decoded data.

[0045] An electronic device, comprising:

[0046] one or more processors;

[0047] a memory for storing one or more programs;

[0048] When the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method.

[0049] A computer-readable storage medium stores computer instructions, which implement the steps of the above method when executed by a processor.

[0050] The beneficial effects of the present invention are as follows:

[0051] (1) Combining weight reduction coding and decoding with ECC coding and decoding. Method 1 changes the ECC coding method and enables the ECC coding and decoding to have weight reduction function by inverting the user data bits and check bits separately. Method 2 changes the ECC input data and coding method at the same time. First, the ECC input data is changed through the first layer of weight reduction coding so that ECC can generate check bits with smaller Hamming weight. Then, the ECC coding and decoding is further enhanced with weight reduction function by inverting the check bits.

[0052] (2) Provide a variety of optional encoding and decoding schemes. Based on the characteristics of different input data sets, the weight reduction encoding method and encoding and decoding order with the best weight reduction effect can be flexibly selected in advance according to the software simulation results, thereby maximizing the reduction of Hamming weight.

[0053] (3) Low redundancy overhead and low complexity. The present invention only adds two flag bits to indicate the inversion mode or weight-reduced decoding mode to be performed on the stored data, resulting in low area overhead. Methods 1 and 2 generate two sets of parallel data through the first layer of encoding and perform the second layer of encoding in parallel, without generating unnecessary delay overhead. The inversion operation can be directly implemented through the XOR operation in digital circuit implementation, which is low in complexity and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is a schematic diagram of embodiment 1 of a coding and decoding method of the present invention;

[0055] Figure 2 This is a schematic diagram of embodiment 3 of a coding and decoding method of the present invention. DETAILED DESCRIPTION

[0056] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the specific implementation methods, structures, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0057] The present invention combines weight reduction coding and decoding with ECC coding and decoding, and adds a first flag bit and a second flag bit, thereby providing a reference for restoration and decoding. In the storage process, the present invention selects the data with the smallest Hamming weight for storage through calculation, that is, the data with the most 0s and the least 1s in the binary data, thereby reducing write failure faults and read interference faults.

[0058] The embodiments of the present invention are further described below with reference to a number of embodiments.

[0059] Example 1

[0060] When writing data, the source code input[m:0] is fed into the ECC encoder. The ECC encoder first performs ECC encoding on the source code input to generate the ECC parity bit. The parity is then appended to the input and the first flag bit, E0, is added to "0." This creates the first set of data: input + parity + "0," recorded as ecc0[n+1:0]. The parity is inverted, appended to the input, and the first flag bit, E0, is added to "1." This creates the second set of data: input + ~parity + "1," recorded as ecc1[n+1:0].

[0061] Input ecc0 and ecc1 to the reduced-weight encoder. In the reduced-weight encoder, a second flag bit, E1, is added after ecc0 to form the first set of output data: input + parity + "0" + "0", recorded as ecc_r0[n+2:0]. ecc_r0 is inverted to form the second set of output data: ~input + ~parity + "1" + "1", recorded as ecc_r1[n+2:0]. A second flag bit, E1, is added after ecc1 to form the third set of output data: input + ~parity + "1" + "0", recorded as ecc_r2[n+2:0]. ecc_r2 is inverted to form the fourth set of output data: ~input + parity + "0" + "1", recorded as ecc_r3[n+2:0].

[0062] Calculate the Hamming weights of the four groups of data from ecc_r0 to eccr3, and select the group with the smallest Hamming weight as the stored data, recorded as ecc_r[n+2:0]. If there are more than one group of data with the smallest Hamming weight, the priority order of selection is: ecc_r0>ecc_r2>ecc_r3>ecc_r1.

[0063] When reading data, the stored data ecc_r is read and sent to the weight reduction decoder. In the weight reduction decoder, the first flag bit E0 is XORed with the ECC check bit to restore the parity, and the second flag bit E1 is XORed with the ECC user data bit to restore the input. The output data of the weight reduction decoder is input + parity, which is recorded as ecc[n:0].

[0064] Input ecc[n:0] to the ECC decoder. In the ECC decoder, the restored input is ECC decoded according to the restored parity to obtain the read data output[m:0].

[0065] An apparatus for implementing the above-mentioned encoding and decoding method includes at least:

[0066] The acquisition module is used to collect binary data and form source code;

[0067] The encoding module generates an ECC check bit through ECC encoding according to the source code, and adds a first flag bit for marking the data state of the ECC check bit, and splices the source code, the ECC check bit and the first flag bit to form a first group of data; inverts the ECC check bit to obtain the inverse of the ECC check bit, and at the same time, inverts the first flag bit to obtain the inverse of the first flag bit, and splices the source code, the inverse of the ECC check bit and the inverse of the first flag bit to form a second group of data; the data state of the ECC check bit is the original state or the inverse state; adds a second flag bit for marking the data state of the source code after the first group of data as the first group of output data; inverts the first group of output data to obtain the inverse of the first group of output data as the second group of output data; adds a second flag bit after the second group of data as the third group of output data; inverts the third group of output data to obtain the inverse of the third group of output data as the fourth group of output data; the data state of the source code is the original state or the inverse state;

[0068] The data selection module calculates the Hamming weights of the first, second, third, and fourth output data groups, respectively, and selects the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > third group of output data > fourth group of output data > second group of output data;

[0069] The decoding module restores the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data respectively; and performs ECC decoding according to the restored source code and the ECC check bit.

[0070] An electronic device, comprising:

[0071] one or more processors;

[0072] a memory for storing one or more programs;

[0073] When the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method.

[0074] In the embodiments provided in this application, it should be understood that the disclosed methods and systems can also be implemented in other ways. The method and system embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the methods and systems, methods, and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a portion of code, and the module, program segment, or a portion of code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0075] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0076] On the other hand, a computer-readable storage medium stores computer instructions thereon, which, when executed by a processor, implement the steps of the above-mentioned method. When the computer program is executed by the processor, it implements the method of any one of the above-mentioned first aspects. If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory 101 (ROM), a random access memory 101 (RAM), a magnetic disk or an optical disk.

[0077] Example 2

[0078] Taking numerical examples as an example, the details are as follows:

[0079] In this embodiment, the input codeword set is 16-bit full data, and the ECC encoding and decoding method is the BCH code with 2 correction and 3 detection. One storage address has 16 data storage bits, 11 ECC check bits, and 2 flag bits.

[0080] Write the source code input[15:0] as 16'd1101011101011011. After ECC encoding, generate the ECC check bit parity[10:0] as 11'd10111101100. Connect parity to input and add the first flag bit E0="0" as the first group of data ecc0[27:0] is 28'd1101011101011011_10111101100_0; invert parity, connect it to input and add the first flag bit E0="1" as the second group of data ecc1[27:0] is 28'd1101011101011011_01000010011_1.

[0081] Input ecc0 and ecc1 to the weight reduction encoder. In the weight reduction encoder, add the second flag E1 = "0" after ecc0, as the first set of output data ecc_r0 [28: 0] is 29'd1101011101011011_10111101100_0_0; invert ecc_r0, as the second set of output data ecc_r1 [28: 0] is 29'd0010100010100100_01000010011_ 1_1; add the second flag bit E1 = "0" after ecc1, and the third group of output data ecc_r2[28:0] is 29'd1101011101011011_01000010011_1_0; invert ecc_r2, and the fourth group of output data ecc_r3[28:0] is 29'd0010100010100100_10111101100_0_1.

[0082] Calculate and compare the Hamming weights of the four groups of data after two-layer encoding. The Hamming weight of codeword * is represented by H(*), H(ecc_r0)=18, H(ecc_r1)=11, H(ecc_r2)=16, H(ecc_r3)=13, so ecc_r1 is selected as the storage data, recorded as ecc_r.

[0083] Assume that a two-bit soft error occurs during data storage in ecc_r, resulting in data 29'd0011100010100100_11000010011_1_1. When reading data, ecc_r is sent to the reduced-weight decoder. In the reduced-weight decoder, the first flag bit (1) is XORed with the ECC check bits (11000010011) to restore the parity value to "00111101100." The second flag bit (1) is XORed with the ECC user data bits (0011100010100100) to restore the input value to "1100011101011011." The resulting output data from the reduced-weight decoder, ecc[26:0], is 27'd110001110101011_00111101100.

[0084] Input ecc[26:0] to the ECC decoder. In the ECC decoder, the restored input is subjected to a 2-check-3-correction BCH decoding operation based on the restored parity, and the correct read data output[15:0] is 16'd1101011101011011.

[0085] Changing the ECC encoding method and inverting the data bits and check bits separately enables ECC encoding and decoding to reduce weight. The number of "0→1" writes has been reduced from 18 to 11, reducing the write failure rate; the number of "1" reads has been reduced from 18 to 13, reducing the read disturb failure rate.

[0086] Only two flag bits are added to indicate the inversion of the stored data, resulting in minimal area overhead. The first level of encoding generates two sets of parallel data, and the second level of encoding is performed in parallel, eliminating any unnecessary latency. The inversion operation is implemented directly via an XOR operation in digital circuits, resulting in low complexity and high efficiency.

[0087] Example 3

[0088] When writing data, the source code input[m:0] is input to the weight reduction encoder. In the weight reduction encoder, a first flag bit E0 = "000" is added to the source code input as the first set of data input + "000", recorded as input0[m+3:0]. The source code input is weight reduction encoded and the first flag bit E0 is added as the encoding flag data input_rx+E0, recorded as inputx[m+3:0]. Among them, the weight reduction encoding method is the inverse code, Gray code, backward XOR encoding, and circular shift encoding, corresponding to x being 1, 2, 3, and 4 respectively, and the corresponding first flag bit E0 being 001, 010, 011, and 100 respectively. Depending on the number of encoding methods to be marked, the first flag bit can be 1 bit (can mark two encoding methods), 2 bits (can mark four encoding methods), 3 bits (can mark eight encoding methods), or more bits can be used, and can be set according to actual needs. In this embodiment, the first flag bit uses 3 bits, marking 5 different encoding methods (including the source code).

[0089] Input 0, input 1, input 2, input 3, and input 4 are fed into the ECC encoder. The ECC encoder first performs ECC encoding on input 0 to generate the ECC parity bit. Parity is concatenated after input 0 and a second flag bit, E1, is added to equal "0." This results in the first output data set: input + "000" + parity + "0," denoted as ecc_r0[n+4:0]. Parity is inverted, concatenated after input 0, and a second flag bit, E1, is added to equal "1." This results in the second output data set: input + "000" + ~parity + "1," denoted as ecc_r1[n+4:0]. Then, input1 is ECC-encoded to generate the ECC check bit parity_r1. Parity_r1 is connected to input1 and the second flag bit E1 = "0" is added. The output data is input_r1 + "001" + parity_r1 + "0" as the first group of first-coded flag data, recorded as ecc_r11[n+4:0]. Parity_r1 is inverted, connected to input1 and the second flag bit E1 = "1" is added. The output data is input_r1 + "001" + ~ parity_r1 + "1" as the first group of second-coded flag data, recorded as ecc_r12[n+4:0]. Then, input2 is ECC-encoded to generate the ECC check bit parity_r2. Parity_r2 is connected to input2 and the second flag bit E1 = "0" is added to output the second set of first-coded flag data: input_r2 + "010" + parity_r2 + "0", recorded as ecc_r21[n+4:0]. Parity_r2 is inverted, connected to input2 and the second flag bit E1 = "1" is added to output the second set of second-coded flag data: input_r2 + "010" + ~parity_r2 + "1", recorded as ecc_r22[n+4:0]. Then, ECC encoding is performed on input3 to generate the ECC check bit parity_r3. Parity_r3 is connected to input3 and the second flag bit E1 = "0" is added. The output data is input_r3 + "011" + parity_r3 + "0" as the third set of first coding flag data, recorded as ecc_r31[n+4:0]. Parity_r3 is inverted, connected to input3 and the second flag bit E1 = "1" is added. The output data is input_r3 + "011" + ~ parity_r3 + "1" as the third set of second coding flag data, recorded as ecc_r32[n+4:0].Then, ECC encoding is performed on input4 to generate the ECC check bit parity_r4. Parity_r4 is connected to input4 and the second flag bit E1 = "0" is added to output the fourth set of first-coded flag data: input_r4 + "100" + parity_r4 + "0", recorded as ecc_r41[n+4:0]. Parity_r4 is inverted, connected to input4 and the second flag bit E1 = "1" is added to output the fourth set of second-coded flag data: input_r4 + "100" + ~parity_r4 + "1", recorded as ecc_r42[n+4:0].

[0090] Calculate the Hamming weights of 10 groups of data, namely ecc_r0, eccr1, ecc_r11, ecc_r12, ecc_r21, ecc_r22, ecc_r31, ecc_r32, ecc_r41 and ecc_r42, and select the group of data with the smallest Hamming weight as the storage data, recorded as ecc_r[n+4:0]; if there is more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > second group of output data > first coding flag data output data and second coding flag data output data, and the decoding method complexity corresponding to the data is arranged from low to high.

[0091] When reading data, the stored data ecc_r is read and sent to the ECC decoder. In the ECC decoder, the second flag bit E1 is first XORed with the ECC check bit to restore the parity or parity_r1 or parity_r2 or parity_r3 or parity_r4. Based on the restored ECC check bit, the first group of data or the encoded flag data is ECC decoded to obtain the ECC decoder output data output + "000" or output_r1 + "001" or output_r2 + "010" or output_r3 + "011" or output_r4 + "100", recorded as output_r[m+3:0].

[0092] Input output_r to the weight reduction decoder. In the weight reduction decoder, the corresponding weight reduction decoding mode is selected according to the first flag E0, and the read data output[m:0] is obtained through the weight reduction decoding operation.

[0093] An apparatus for implementing the above-mentioned encoding and decoding method includes at least:

[0094] The acquisition module is used to collect binary data and form source code;

[0095] The encoding module is used to form at least one set of encoded data according to the source code through at least one encoding method, and add a first flag bit for marking the encoding method of the source code and the encoded data, splicing the source code and the first flag bit to form a first set of data; splicing the encoded data and the first flag bit to form encoded flag data; generating ECC check bits according to the first set of data and the encoded flag data through ECC encoding, and adding a second flag bit for marking the data state of the ECC check bits; splicing the first set of data and the corresponding ECC check bits and the corresponding second flag bit as the first set of output data; inverting the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, the second flag bit is also inverted. Inverting to obtain the inverse of the second flag bit, splicing the first group of data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit as the second group of output data; splicing the coded flag data and the corresponding ECC check bit and the second flag bit as the first coded flag data output data; inverting the ECC check bit of the coded flag data to obtain the inverse of the ECC check bit, and at the same time, inverting the second flag bit of the coded flag data to obtain the inverse of the second flag bit, splicing the coded flag data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit as the second coded flag data output data; the data state of the ECC check bit is the original state or the inverse state;

[0096] The data selection module calculates the Hamming weights of the first group of output data, the second group of output data, the first coding mark data output data, and the second coding mark data output data, and selects the group of data with the smallest Hamming weight as the stored data; if there is more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > second group of output data > first coding mark data output data and second coding mark data output data, and the decoding method complexity corresponding to the data is arranged from low to high;

[0097] The decoding module restores the ECC check bit according to the second flag bit of the stored data; performs ECC decoding according to the restored ECC check bit; and restores the source code according to the first flag bit of the ECC decoded data.

[0098] Example 4

[0099] Taking numerical examples as an example, the details are as follows:

[0100] In this embodiment, the input codeword set is 8-bit full data. The weight reduction encoding and decoding methods are selected from inverse code, Gray code, backward XOR code, and cyclic shift code. The ECC encoding and decoding method is 1-corrected Hamming code. One storage address has 8 data storage bits, 4 ECC check bits, and 4 flag bits.

[0101] Write source code input [7:0] as 8'b11100111. In the weight reduction encoder, add the first flag bit E0 = "000" to the source code input, as the first group of data input0 [10:0] is 11'b11100111_000; perform inverse encoding on the source code input and add the first flag bit E0 = "001" as the first group of encoding flag data input1 [10:0] is 11'b00011000001; perform Gray encoding on the source code input and add the first flag bit E0 = "010" as the second group of encoding flag The flag data input2[10:0] is 11'b10010100010; the source code input is backward XOR-encoded and the first flag bit E0 = "011" is added, and the third set of coded flag data input3[10:0] is 11'b00101001_011; the source code input is cyclically shift-encoded and the first flag bit E0 = "100" is added, and the fourth set of coded flag data input4[10:0] is 11'b01111110_100.

[0102] Input 0, input 1, input 2, input 3, and input 4 are fed into the ECC encoder. The ECC encoder first performs ECC encoding on input 0, generating the ECC check bits parity[3:0] as 4'b1000. The parity bit is concatenated after input 0 and the second flag bit E1 is added as "0." The first output data set, ecc_r0[15:0], is 16'11100111_0001000_0. The parity bit is inverted, concatenated after input 0, and the second flag bit E1 is added as "1." The second output data set, ecc_r1[15:0], is 16'11100111_0000111_1. Then, input1 is ECC-encoded to generate ECC check bits parity_r1[3:0] of 0100. Parity_r1 is connected to input1 and the second flag bit E1 = "0" is added. The output data ecc_r11[15:0] is 16'00011000 _001_0100_0 as the first group of first-encoded flag data. Parity_r1 is inverted, connected to input1 and the second flag bit E1 = "1" is added. The output data ecc_r12[15:0] is 16'00011000 _001_1011_1 as the first group of second-encoded flag data. Then, input2 is ECC-encoded to generate the ECC check bit parity_r2[3:0] as 1100. Parity_r2 is connected to input2 and the second flag bit E1 = "0" is added. As the second set of first-coded flag data, the output data ecc_r21[15:0] is 16'10010100 _0101100_0. Parity_r2 is inverted, connected to input2 and the second flag bit E1 = "1" is added. As the second set of second-coded flag data, the output data ecc_r22[15:0] is 16'10010100 _0100011_1. Then, input3 is ECC-encoded to generate the ECC check bits parity_r3[3:0] as 0111. Parity_r3 is connected to input3 and the second flag bit E1 = "0" is added. As the third set of first-coded flag data, the output data ecc_r31[15:0] is 16'00101001 _0110111_0. Parity_r3 is inverted, connected to input3 and the second flag bit E1 = "1" is added. As the third set of second-coded flag data, the output data ecc_r32[15:0] is 16' 00101001 _0111000_1.Then, input4 is ECC-encoded to generate ECC check bits parity_r4[3:0] of 0001. Parity_r4 is connected to input4 and the second flag bit E1 = "0" is added. The output data ecc_r41[15:0] is 16' 01111110_1000001_0 as the fourth group of first-coded flag data. Parity_r4 is inverted, connected to input4 and the second flag bit E1 = "1" is added. The output data ecc_r42[15:0] is 16' 01111110_1001110_1 as the fourth group of second-coded flag data.

[0103] Calculate and compare the Hamming weights of the 10 groups of codewords after two-layer encoding, H(ecc_r0)=7, H(ecc_r1)=10, H(ecc_r11)=4, H(ecc_r12)=7, H(ecc_r21)=6, H(ecc_r22)=7, H(ecc_r31)=8, H(ecc_r32)=7, H(ecc_r41)=8, H(ecc_r41)=11, so ecc_r11 is selected as the storage codeword, recorded as ecc_r.

[0104] Assume that a three-bit short hard error occurs during data storage in ecc_r, resulting in data 16'b00001000_0010100_0. When data is read, ecc_r is read into the ECC decoder. The ECC decoder first performs an XOR operation on the second flag bit (0) and the ECC check bits (0100) to restore parity_r1 to "0100." Then, the data 15'b00001000_0010100 is decoded using the corrected 1 Hamming code. The resulting ECC decoder output data output_r[10:0] is 11'b00011000_001.

[0105] Input output_r[10:0] to the weight reduction decoder. In the weight reduction decoder, the inversion is selected as the weight reduction decoding mode according to the first flag "001". The correct read data output[7:0] obtained through the weight reduction decoding operation is 8'b11100111.

[0106] The ECC input data and encoding scheme are simultaneously modified. A first-level weight reduction encoding scheme modifies the ECC input data, enabling ECC to generate parity bits with a lower Hamming weight. Furthermore, the parity bits are inverted, further enhancing the weight reduction capability of the ECC encoding and decoding. The number of "0→1" writes is reduced from 8 to 4, reducing the write failure rate; the number of "1" reads is reduced from 6 to 2, reducing the read disturb failure rate. Only two flag bits are added to indicate the inversion and weight reduction decoding methods for the stored data, resulting in minimal area overhead. The first-level encoding generates two sets of parallel data, and the second-level encoding is performed in parallel, eliminating any unnecessary latency. The inversion operation is implemented directly via an XOR operation in digital circuits, resulting in low complexity and high efficiency.

[0107] Furthermore, because DATA4 is stored in the shorted bit, this bit of data is erroneous. Although DATA5 and DATA0 are also stored in the shorted bit, their written data is "0," consistent with the data after the short-circuit error, so these two bits of data do not appear to be erroneous. Ultimately, the ECC decoder detects the single-bit error and corrects it. If no encoding or decoding is performed, DATA4 would be correct, while DATA5 and DATA0 would be erroneous, resulting in two errors in total, which cannot be properly corrected by the Hamming code ECC, which only corrects one bit.

[0108] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as above in terms of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the technical solution of the present invention, make some changes or modifications to equivalent embodiments using the technical contents disclosed above. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A coding and decoding method, characterized in that: The steps include: S1. Collection steps Collect binary data and form source code; S2. Encoding steps S2.

1. Generate an ECC check bit based on the source code through ECC encoding, and add a first flag bit for marking the data state of the ECC check bit. Concatenate the source code, the ECC check bit, and the first flag bit to form a first set of data. Invert the ECC check bit to obtain the one's complement of the ECC check bit. Simultaneously, invert the first flag bit to obtain the one's complement of the first flag bit. Concatenate the source code, the one's complement of the ECC check bit, and the one's complement of the first flag bit to form a second set of data. The data state of the ECC check bit is either the original state or the inverted state. S2.

2. Add a second flag bit to mark the data state of the source code after the first set of data, which is used as the first set of output data; invert the first set of output data to obtain the inverse of the first set of output data, which is used as the second set of output data; add a second flag bit to the second set of data to obtain the third set of output data; invert the third set of output data to obtain the inverse of the third set of output data, which is used as the fourth set of output data; the data state of the source code is either the original state or the inverse state; S3. Data selection step Calculate the Hamming weights of the first, second, third, and fourth output data groups respectively, and select the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > third group of output data > fourth group of output data > second group of output data; S4. Decoding steps S4.

1. Restore the ECC check bit and source code based on the first flag bit and the second flag bit of the stored data; S4.

2. Perform ECC decoding based on the restored source code and ECC check bits.

2. A device for implementing a coding and decoding method according to claim 1, characterized in that: At least: The acquisition module is used to collect binary data and form source code; The encoding module generates an ECC check bit through ECC encoding according to the source code, and adds a first flag bit for marking the data state of the ECC check bit, and splices the source code, the ECC check bit and the first flag bit to form a first group of data; inverts the ECC check bit to obtain the inverse of the ECC check bit, and at the same time, inverts the first flag bit to obtain the inverse of the first flag bit, and splices the source code, the inverse of the ECC check bit and the inverse of the first flag bit to form a second group of data; the data state of the ECC check bit is the original state or the inverse state; adds a second flag bit for marking the data state of the source code after the first group of data as the first group of output data; inverts the first group of output data to obtain the inverse of the first group of output data as the second group of output data; adds a second flag bit after the second group of data as the third group of output data; inverts the third group of output data to obtain the inverse of the third group of output data as the fourth group of output data; the data state of the source code is the original state or the inverse state; The data selection module calculates the Hamming weights of the first, second, third, and fourth output data groups, respectively, and selects the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: first group of output data > third group of output data > fourth group of output data > second group of output data; The decoding module restores the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data respectively; and performs ECC decoding according to the restored source code and the ECC check bit.

3. A coding and decoding method, characterized in that: The steps include: S1. Collection steps Collect binary data and form source code; S2. Encoding steps S2.

1. Generating at least one set of coded data using at least one encoding method based on the source code, adding a first flag for identifying the source code and the encoding method of the coded data, concatenating the source code and the first flag to form a first set of data; and concatenating the coded data and the first flag to form coded flag data. S2.

2. Generate ECC check bits respectively according to the first group of data and the coding flag data through ECC encoding, and add a second flag bit for marking the data state of the ECC check bits; splice the first group of data and the corresponding ECC check bits and the corresponding second flag bits as the first group of output data; invert the ECC check bits to obtain the inverse of the ECC check bits, and at the same time, invert the second flag bit to obtain the inverse of the second flag bit, and splice the first group of data and the inverse of the corresponding ECC check bits and the inverse of the corresponding second flag bit as the second group of output data; splice the coding flag data and the corresponding ECC check bits and the second flag bit as the first coding flag data output data; invert the ECC check bits of the coding flag data to obtain the inverse of the ECC check bits, and at the same time, invert the second flag bit of the coding flag data to obtain the inverse of the second flag bit, and splice the coding flag data and the inverse of the corresponding ECC check bits and the inverse of the corresponding second flag bit as the second coding flag data output data; the data state of the ECC check bits is the original state or the inverted state; S3. Data selection step Calculate the Hamming weights of the first set of output data, the second set of output data, the first coding mark data output data, and the second coding mark data output data respectively, and select the set of data with the smallest Hamming weight as the storage data; If there are more than one group of data with the smallest Hamming weight, the priority order of selection is: the first group of output data > the second group of output data > the first coding mark data output data and the second coding mark data output data, and the decoding method complexity corresponding to them is arranged from low to high; S4. Decoding steps S4.

1. Restore the ECC check bit based on the second flag bit of the stored data; S4.

2. Perform ECC decoding based on the restored ECC check bits; S4.

3. Restore the source code based on the first flag bit of the ECC decoded data.

4. The method according to claim 3, characterized in that The encoding method includes at least one of inverse code, Gray code, backward XOR coding, and cyclic shift coding.

5. A device for implementing a coding and decoding method as claimed in claim 3 or 4, characterized in that: At least: The acquisition module is used to collect binary data and form source code; The encoding module is used to form at least one set of encoded data according to the source code through at least one encoding method, and add a first flag bit for marking the encoding method of the source code and the encoded data, splicing the source code and the first flag bit to form a first set of data; splicing the encoded data and the first flag bit to form encoded flag data; generating ECC check bits according to the first set of data and the encoded flag data through ECC encoding, and adding a second flag bit for marking the data state of the ECC check bits; splicing the first set of data and the corresponding ECC check bits and the corresponding second flag bits as the first set of output data; inverting the ECC check bits to obtain the inverse code of the ECC check bits At the same time, the second flag bit is also inverted to obtain the inverse of the second flag bit, and the first group of data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit are spliced ​​as the second group of output data; the encoding flag data and the corresponding ECC check bit and the second flag bit are spliced ​​together to output data as the first encoding flag data; the ECC check bit of the encoding flag data is inverted to obtain the inverse of the ECC check bit, and at the same time, the second flag bit of the encoding flag data is also inverted to obtain the inverse of the second flag bit, and the encoding flag data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit are spliced ​​together to output data as the second encoding flag data; The data state of the ECC check bit is the original state or the inverted state; a data selection module, calculating the Hamming weights of the first set of output data, the second set of output data, the first coded mark data output data, and the second coded mark data output data, respectively, and selecting the set of data with the smallest Hamming weight as the storage data; If there are more than one group of data with the smallest Hamming weight, the priority order of selection is: the first group of output data > the second group of output data > the first coding mark data output data and the second coding mark data output data, and the decoding method complexity corresponding to them is arranged from low to high; A decoding module restores an ECC check bit according to the second flag bit of the stored data; and performs ECC decoding according to the restored ECC check bit; The source code is restored based on the first flag bit of the ECC decoded data.

6. An electronic device, characterized in that: include: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claim 1, claim 3, and claim 4.

7. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the instruction is executed by a processor, the steps of the method according to any one of claim 1, claim 3 or claim 4 are implemented.

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