EtherCAT communication system and method based on FPGA, equipment and storage medium

Abstract

The invention relates to the technical field of industrial automation communication, in particular to an EtherCAT communication system and method based on an FPGA, equipment and a storage medium, and the system comprises an EtherCAT IP Core, an MII interface module, an MII-LVDS conversion module, an LVDS-MII conversion module and an LVDS interface module which are realized based on the FPGA. The advantages of the FPGA and the LVDS technology are fully exerted, the communication performance and reliability are improved, and the comprehensive effects of high integration, high real-time performance, high flexibility and high integrity are achieved.

Description

Technical Field

[0001] The present invention relates to the field of industrial automation communication technology, and specifically to an EtherCAT communication system, method, device and storage medium based on FPGA. Background Art

[0002] EtherCAT (Ethernet Control Automation Technology), as a high-performance industrial Ethernet fieldbus protocol, has been widely used in the field of industrial automation. It has the advantages of high speed, real-time, flexibility, etc., and can meet the high requirements of industrial control systems for data transmission.

[0003] Traditional EtherCAT communication usually uses an Ethernet interface for data transmission. However, in some specific application scenarios, such as those sensitive to spatial dimensions, requiring short-distance transmission or high-speed serial data transmission, the traditional Ethernet interface may not be able to meet the requirements.

[0004] FPGA (Field Programmable Gate Array) is a programmable logic chip, and users can define its functions by changing the configuration information. FPGA can be reprogrammed an unlimited number of times after manufacturing to implement the required digital logic functions, and this characteristic makes FPGA have extremely high flexibility and reconfigurability.

[0005] LVDS (Low Voltage Differential Signaling) technology has the advantages of high speed, low power consumption, strong anti-interference ability, etc., and can provide reliable high-speed data transmission. Combining EtherCAT communication with an LVDS interface can give full play to the advantages of both and improve the performance and reliability of industrial control systems.

[0006] However, in the prior art, there is a lack of an effective solution to efficiently and stably transmit EtherCAT data received by MII (Media Independent Interface) through an LVDS interface, and at the same time accurately send the LVDS received data through the MII interface.

[0007] For the above reasons, the present invention designs an EtherCAT communication system, method, device and storage medium based on FPGA, which gives full play to the advantages of LVDS technology, improves communication performance and reliability, and achieves the comprehensive effects of high integration, high real-time performance, high flexibility and high integrity. Summary of the Invention

[0008] The objective of the present invention is to overcome the deficiencies of the prior art and provide an EtherCAT communication system, method, device, and storage medium based on FPGA, which fully exploits the advantages of LVDS technology, improves communication performance and reliability, and achieves an integrated effect of high integration, high real-time performance, high flexibility, and high integrity.

[0009] The present invention provides an EtherCAT communication system based on FPGA. The communication system includes an EtherCAT IP Core implemented based on FPGA, an MII interface module, an MII-LVDS conversion module, an LVDS-MII conversion module, and an LVDS interface module.

[0010] The EtherCAT IP Core performs data interaction with the MII-LVDS conversion module and the LVDS-MII conversion module respectively through its built-in MII interface via the MII interface module. The MII-LVDS conversion module performs data interaction with the slave station at the subsequent stage of the external LVDS device through the LVDS interface module, and the LVDS-MII conversion module performs data interaction with the slave station at the previous stage of the external LVDS device through the LVDS interface module. The LVDS interface module is used to communicate with the external LVDS device.

[0011] The EtherCAT IP Core is responsible for parsing and generating EtherCAT frames, processing the logic related to the communication protocol, and passing the data to be sent to the MII interface module. At the same time, it receives the data transmitted from the MII interface module for processing.

[0012] The logic related to the communication protocol includes frame header recognition, command parsing, and data reading and writing.

[0013] The MII-LVDS conversion module includes a clock synchronization sub-module, a data acquisition sub-module, a serialization sub-module, and an LVDS transmission sub-module.

[0014] The LVDS-MII conversion module includes an LVDS reception sub-module, a deserialization sub-module, and a data transmission sub-module.

[0015] An EtherCAT communication method based on FPGA includes the following steps:

[0016] S1, the EtherCAT IP Core parses and generates EtherCAT frames and performs data interaction with the MII interface module.

[0017] S2, The MII interface module receives the data to be sent from the EtherCAT IP Core and sends it out through the MII interface. At the same time, it receives the data transmitted from the MII interface and passes it to the EtherCAT IP Core, and receives the data transmitted from the LVDS-MII conversion module and sends it to the EtherCAT IP Core through the MII interface;

[0018] S3, The clock synchronization sub-module of the MII-LVDS conversion module converts the MII clock into a 100M LVDS clock to ensure synchronization between the two; the data acquisition sub-module captures MII data at the rising edge of the MII clock; the serialization sub-module converts the parallel MII data into serial data; the LVDS transmission sub-module converts the serial data into LVDS differential signals through the differential I / O resources of the FPGA and sends them out through the LVDS interface;

[0019] S4, The LVDS receiving sub-module of the LVDS-MII conversion module receives the LVDS signal transmitted from the external device through the differential I / O resources of the FPGA and converts it into single-ended serial data; the deserialization sub-module converts the serial data into parallel MII data; the data transmission sub-module passes the parallel MII data to the MII interface module;

[0020] S5, The LVDS interface module sends out the LVDS signal generated by the MII-LVDS conversion module and receives the signal transmitted from the external LVDS device and passes it to the LVDS-MII conversion module for processing.

[0021] The internal logic of the FPGA to implement S1 to S5 includes the sending process and the receiving process;

[0022] The sending process specifically includes the following steps:

[0023] F1, Clock synchronization: Using the clock management resources inside the FPGA, convert the clock signal mii_clk of the MII interface into a 100M LVDS clock signal lvds_100m_clk;

[0024] According to different FPGA models, use the corresponding clock management primitives and adjust the parameters according to the frequency and period of mii_clk to ensure the generation of a stable 100M clock signal;

[0025] F2, MII data acquisition: At the rising edge of the MII clock mii_clk, capture the data of the MII interface through the mii_data_capture module; when the tx_en signal is valid, store the 4-bit data on the md bus into the captured_data register and make the data_valid signal valid to indicate that valid data has been captured;

[0026] F3, EtherCAT Protocol Processing: Use an off-the-shelf EtherCAT IP Core to perform EtherCAT protocol processing on the data collected by the MII interface; this EtherCAT IP Core parses the received EtherCAT frames, identifies the frame header and command type information, and performs corresponding data read and write operations according to the protocol requirements. At the same time, it passes the data to be sent to the MII interface module;

[0027] F4, Data Serialization: Driven by the 100M LVDS clock lvds_100m_clk, the serializer module converts the parallel MII data parallel_data into serial data serial_data. It uses a 3-bit counter bit_count to control the data shift operation, shifting out 4-bit parallel data one by one to achieve serialization processing;

[0028] F5, LVDS Signal Transmission: The lvds_transmitter module converts the serialized serial data serial_data into LVDS differential signals lvds_p and lvds_n through the differential I / O resources of the FPGA for transmission; according to different FPGA models, use the corresponding differential I / O primitives to achieve the conversion from single-ended signals to differential signals, ensuring reliable data transmission in the LVDS standard;

[0029] The receiving process specifically includes the following steps:

[0030] J1, LVDS Signal Reception: The lvds_receiver module receives the differential signals lvds_p and lvds_n from an external LVDS device through the differential I / O resources of the FPGA and converts them into single-ended serial data serial_data; use a general differential input primitive to achieve the conversion from differential signals to single-ended signals;

[0031] J2, Data Deserialization: Driven by the 100M LVDS clock lvds_100m_clk, the deserializer module converts the serial data serial_data into parallel MII data parallel_data; use a 3-bit counter bit_count to control the data collection. After collecting 4 bits of data each time, make the data_valid_out signal valid, indicating that a set of complete parallel data has been obtained through deserialization;

[0032] J3, Transfer Data to the MII Interface: The data sending sub-module of the LVDS-MII conversion module passes the deserialized parallel MII data parallel_data to the MII interface module and makes the send_en_from_lvds signal valid;

[0033] J4, MII Interface Transmission: When the send_en_from_lvds signal is valid, the MII interface module sends the received parallel MII data data_from_lvds through the MII interface; at the same time, the data received by the MII interface is passed to the EtherCAT IP Core for subsequent protocol processing.

[0034] The clock management primitives in F1 include the PLL of Xilinx and the PLL of Altera; the differential I / O primitives in F5 include the IOBUFDS of Xilinx and the differential output primitives of Altera.

[0035] An electronic device includes a processor and a memory storing a program. The program includes instructions that, when executed by the processor, cause the processor to execute an EtherCAT communication method based on an FPGA.

[0036] A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute an EtherCAT communication method based on an FPGA.

[0037] Compared with the prior art, the present invention converts the EtherCAT data received by the MII interface into 100M serial LVDS signals for transmission, giving full play to the advantages of high speed, low power consumption, and strong anti-interference ability of the LVDS technology, and improving the performance and reliability of EtherCAT communication. In addition, the present invention integrates the MII-LVDS conversion function and the LVDS-MII conversion function into the EtherCAT IP Core, reducing the use of external hardware, improving the system integration, and reducing the cost and power consumption. The present invention adopts a direct data acquisition, serialization, and deserialization processing method, avoiding the delay caused by using a FIFO. During normal continuous data transmission, the delay is about 48.5ns, meeting the real-time requirements of industrial automation systems.

[0038] The present invention is implemented based on a general FPGA and has good flexibility and scalability. It can customize and optimize the EtherCAT protocol processing logic, MII-LVDS conversion module, and LVDS-MII conversion module according to different application requirements.

[0039] In addition, the present invention also realizes a complete two-way communication process of sending data from the MII interface to the LVDS interface and accurately sending the data received from the LVDS interface through the MII interface, meeting the actual requirements of industrial automation communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1This is a schematic diagram of the system framework of the present invention. Detailed implementation manners

[0041] The present invention will now be further described in conjunction with the accompanying drawings.

[0042] Refer to Figure 1 , the present invention provides an EtherCAT communication system based on FPGA. The communication system includes an EtherCAT IP Core implemented based on FPGA, an MII interface module, an MII-LVDS conversion module, an LVDS-MII conversion module, and an LVDS interface module;

[0043] The EtherCAT IP Core has a built-in MII interface. It is mainly responsible for receiving and parsing the 4-bit parallel data of the MII into standard data, and then converting the standard data into serial 0101 signal data that can be sent by LVDS through the MII-LVDS conversion module and the LVDS-MII conversion module. Finally, the digital signal is converted into a physical signal of LVDS through the LVDS interface module by using the hardware interface on the FPGA. However, the MII interface cannot transmit data through LVDS, so an MII interface module is added as a functional block to communicate with the MII-LVDS conversion module and the LVDS-MII conversion module respectively.

[0044] The EtherCAT IP Core conducts data interaction with the MII-LVDS conversion module and the LVDS-MII conversion module respectively through its built-in MII interface via the MII interface module. The MII-LVDS conversion module conducts data interaction with the slave station at the rear stage of the external LVDS device through the LVDS interface module, and the LVDS-MII conversion module conducts data interaction with the slave station at the front stage of the external LVDS device through the LVDS interface module. The LVDS interface module is used to communicate with the external LVDS device.

[0045] The data transmission path of EtherCAT is from the front-stage module of the LVDS device to the system of the present invention, then to the rear-stage module of the LVDS device, and then the data is returned to the design of the present invention through the rear-stage module and then returned to the front stage. Since it is full-duplex bidirectional communication, there are MII-LVDS and LVDS-MII modules between the present invention and the front and rear-stage modules.

[0046] The EtherCAT IP Core is responsible for parsing and generating EtherCAT frames, processing the logic related to the communication protocol, and passing the data to be sent to the MII interface module, while receiving the data transmitted by the MII interface module for processing.

[0047] The logic related to the communication protocol includes frame header recognition, command parsing, and data reading and writing.

[0048] The MII-LVDS conversion module includes a clock synchronization sub-module, a data acquisition sub-module, a serialization sub-module, and an LVDS transmission sub-module.

[0049] The LVDS-MII conversion module includes an LVDS reception sub-module, a deserialization sub-module, and a data transmission sub-module.

[0050] An EtherCAT communication method based on FPGA includes the following steps:

[0051] S1, The EtherCAT IP Core parses and generates EtherCAT frames, and performs data interaction with the MII interface module;

[0052] S2, The MII interface module receives the data to be transmitted from the EtherCAT IP Core and sends it out through the MII interface. At the same time, it receives the data transmitted from the MII interface and passes it to the EtherCAT IP Core, and receives the data transmitted from the LVDS-MII conversion module and sends it to the EtherCAT IP Core through the MII interface;

[0053] S3, The clock synchronization sub-module of the MII-LVDS conversion module converts the MII clock into a 100M LVDS clock to ensure synchronization between the two; the data acquisition sub-module captures MII data at the rising edge of the MII clock; the serialization sub-module converts the parallel MII data into serial data; the LVDS transmission sub-module converts the serial data into LVDS differential signals through the differential I / O resources of the FPGA and sends them out through the LVDS interface;

[0054] S4, The LVDS reception sub-module of the LVDS-MII conversion module receives the LVDS signal transmitted from an external device through the differential I / O resources of the FPGA and converts it into single-ended serial data; the deserialization sub-module converts the serial data into parallel MII data; the data transmission sub-module passes the parallel MII data to the MII interface module;

[0055] S5, The LVDS interface module sends out the LVDS signal generated by the MII-LVDS conversion module, and receives the signal transmitted from an external LVDS device and passes it to the LVDS-MII conversion module for processing.

[0056] The internal logic of the FPGA to implement S1 to S5 includes a transmission process and a reception process;

[0057] The specific steps of the transmission process include the following:

[0058] F1, Clock Synchronization: Utilize the clock management resources inside the FPGA to convert the clock signal mii_clk of the MII interface into a 100M LVDS clock signal lvds_100m_clk;

[0059] According to different FPGA models, use the corresponding clock management primitives and adjust the parameters based on the frequency and period of mii_clk to ensure the generation of a stable 100M clock signal;

[0060] F2, MII Data Acquisition: At the rising edge of the MII clock mii_clk, capture the data of the MII interface through the mii_data_capture module; when the tx_en signal is valid, store the 4-bit data on the md bus into the captured_data register and make the data_valid signal valid to indicate that valid data has been captured;

[0061] F3, EtherCAT Protocol Processing: Use an off-the-shelf EtherCAT IP Core to process the EtherCAT protocol for the data collected from the MII interface; this EtherCAT IP Core parses the received EtherCAT frame, identifies the frame header and command type information, and performs corresponding data read and write operations according to the protocol requirements. At the same time, pass the data to be sent to the MII interface module;

[0062] F4, Data Serialization: Driven by the 100M LVDS clock lvds_100m_clk, the serializer module converts the parallel MII data parallel_data into serial data serial_data. Use a 3-bit counter bit_count to control the data shift operation and shift out the 4-bit parallel data bit by bit to achieve serialization processing;

[0063] F5, LVDS Signal Transmission: The lvds_transmitter module converts the serialized serial data serial_data into LVDS differential signals lvds_p and lvds_n through the differential I / O resources of the FPGA for transmission; according to different FPGA models, use the corresponding differential I / O primitives to achieve the conversion from single-ended signal to differential signal and ensure reliable data transmission in accordance with the LVDS standard;

[0064] The receiving process specifically includes the following steps:

[0065] J1, LVDS Signal Reception: The lvds_receiver module receives the differential signals lvds_p and lvds_n from an external LVDS device through the differential I / O resources of the FPGA and converts them into single-ended serial data serial_data; a common differential input primitive is used to implement the conversion from differential signals to single-ended signals.

[0066] J2, Data Deserialization: Driven by the 100M LVDS clock lvds_100m_clk, the deserializer module converts the serial data serial_data into parallel MII data parallel_data; a 3-bit counter bit_count is used to control data collection, and after every 4 bits of data are collected, the data_valid_out signal becomes valid, indicating that a complete set of parallel data has been deserialized.

[0067] J3, Data Transfer to MII Interface: The data sending sub-module of the LVDS-MII conversion module transfers the deserialized parallel MII data parallel_data to the MII interface module and makes the send_en_from_lvds signal valid.

[0068] J4, MII Interface Transmission: When the MII interface module receives the valid send_en_from_lvds signal, it transmits the received parallel MII data data_from_lvds through the MII interface; at the same time, it transfers the data received by the MII interface to the EtherCAT IP Core for subsequent protocol processing.

[0069] The clock management primitives in F1 include the PLL of Xilinx and the PLL of Altera; the differential I / O primitives in F5 include the IOBUFDS of Xilinx and the differential output primitive of Altera.

[0070] An electronic device includes a processor and a memory storing a program, and the program includes instructions that, when executed by the processor, cause the processor to execute an EtherCAT communication method based on FPGA.

[0071] A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute an EtherCAT communication method based on FPGA.

[0072] The specific module design code of the present invention is as follows:

[0073] 1. Clock Synchronization Module:

[0074]

[0075]

[0076] 2. MII Data Acquisition Module:

[0077]

[0078]

[0079] 3. Serialization Module:

[0080]

[0081]

[0082] 4. LVDS Transmission Module:

[0083]

[0084]

[0085] 5. LVDS Reception Module

[0086]

[0087]

[0088] 6. Deserialization Module:

[0089]

[0090]

[0091]

[0092] 7. MII Interface Module:

[0093]

[0094]

[0095]

[0096] 8. Top-Level Module:

[0097]

[0098]

[0099]

[0100]

[0101] The above are only the preferred embodiments of the present invention, which are only used to help understand the method and its core idea of the present application. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art in the technical field, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

[0102] As a whole, the present invention solves the deficiencies in the prior art that traditional EtherCAT communication can only perform data transmission through an Ethernet interface, resulting in the inability to adapt to occasions where spatial size is sensitive, short-distance transmission or high-speed serial data transmission is required. By using FPGA combined with LVDS technology, the communication performance and reliability are improved, and an integrated effect of high integration, high performance, low latency, high real-time performance, high flexibility and scalability, and high integrity is achieved.

Claims

1. An EtherCAT communication system based on FPGA, characterized in that: The communication system includes an EtherCAT IP Core, an MII interface module, an MII-LVDS conversion module, an LVDS-MII conversion module and an LVDS interface module implemented based on FPGA; The EtherCAT IP Core exchanges data with the MII-LVDS conversion module and the LVDS-MII conversion module through its own MII interface and the MII interface module. The MII-LVDS conversion module exchanges data with the subsequent slave station of the external LVDS device through the LVDS interface module. The LVDS-MII conversion module exchanges data with the previous slave station of the external LVDS device through the LVDS interface module. The LVDS interface module is used to communicate with the external LVDS device.

2. The FPGA-based EtherCAT communication system according to claim 1, characterized in that: The EtherCAT IP Core is responsible for parsing and generating EtherCAT frames, processing logic related to the communication protocol, and passing the data to be sent to the MII interface module, while receiving the data from the MII interface module for processing.

3. The FPGA-based EtherCAT communication system according to claim 2, characterized in that: The logic related to the communication protocol includes frame header recognition, command parsing and data reading and writing.

4. The FPGA-based EtherCAT communication system according to claim 1, characterized in that: The MII-LVDS conversion module includes a clock synchronization submodule, a data acquisition submodule, a serialization submodule and an LVDS transmission submodule.

5. The FPGA-based EtherCAT communication system according to claim 1, characterized in that: The LVDS-MII conversion module includes an LVDS receiving submodule, a deserialization submodule and a data sending submodule.

6. An EtherCAT communication method based on FPGA, characterized in that: The following steps are involved: S1, the EtherCAT IP Core parses and generates EtherCAT frames, and interacts with the MII interface module for data; S2, the MII interface module receives the data to be sent from the EtherCAT IP Core and sends it out through the MII interface, receives the data from the MII interface and passes it to the EtherCAT IP Core, and receives the data from the LVDS-MII conversion module and sends it to the EtherCAT IP Core through the MII interface; S3, the clock synchronization submodule of the MII-LVDS conversion module converts the MII clock into a 100M LVDS clock to ensure synchronization between the two; the data acquisition submodule captures the MII data at the rising edge of the MII clock; The serialization submodule converts the parallel MII data into serial data; the LVDS transmission submodule converts the serial data into LVDS differential signals through the differential I / O resources of the FPGA and transmits them through the LVDS interface; S4, the LVDS receiving submodule of the LVDS-MII conversion module receives the LVDS signal from the external device through the differential I / O resources of the FPGA and converts it into single-ended serial data; The deserialization submodule converts serial data into parallel MII data; the data transmission submodule transmits the parallel MII data to the MII interface module; S5, the LVDS interface module sends out the LVDS signal generated by the MII-LVDS conversion module, and receives the signal from the external LVDS device and transmits it to the LVDS-MII conversion module for processing.

7. The FPGA-based EtherCAT communication method according to claim 6, characterized in that: The internal logic of S1 to S5 implemented by the FPGA includes a sending process and a receiving process; The sending process is specific The following steps are involved: F1, clock synchronization: using the clock management resources inside the FPGA, convert the clock signal mii_clk of the MII interface into a 100M LVDS clock signal lvds_100m_clk; Use the corresponding clock management primitives according to different FPGA models, and adjust the parameters according to the frequency and period of mii_clk to ensure the generation of a stable 100M clock signal; F2, MII data acquisition: At the rising edge of the MII clock mii_clk, the data of the MII interface is captured through the mii_data_capture module; when the tx_en signal is valid, the 4-bit data on the md bus is stored in the captured_data register, and the data_valid signal is valid to indicate that valid data is captured; F3, EtherCAT protocol processing: Use the existing EtherCAT IP Core to perform EtherCAT protocol processing on the data collected by the MII interface; the EtherCAT IP Core parses the received EtherCAT frame, identifies the frame header and command type information, and performs corresponding data read and write operations according to the protocol requirements, and passes the data to be sent to the MII interface module; F4, data serialization: driven by the 100M LVDS clock lvds_100m_clk, the serializer module converts the parallel MII data parallel_data into serial data serial_data, uses a 3-bit counter bit_count to control the data shift operation, and shifts the 4-bit parallel data out one by one to achieve serialization; F5, LVDS signal transmission: The lvds_transmitter module converts the serial data serial_data into LVDS differential signals lvds_p and lvds_n through the differential I / O resources of the FPGA for transmission; according to different FPGA models, the corresponding differential I / O primitives are used to realize the conversion from single-ended signals to differential signals, ensuring that data is reliably transmitted according to the LVDS standard; The receiving process is specifically The following steps are involved: J1, LVDS signal reception: The lvds_receiver module receives the differential signals lvds_p and lvds_n from the external LVDS device through the differential I / O resources of the FPGA, and converts them into single-ended serial data serial_data; the conversion from differential signals to single-ended signals is realized using the general differential input primitive; J2, data deserialization: driven by the 100M LVDS clock lvds_100m_clk, the deserializer module converts the serial data serial_data into the parallel MII data parallel_data; a 3-bit counter bit_count is used to control the data collection. After collecting 4 bits of data, the data_valid_out signal is enabled, indicating that a complete set of parallel data is obtained by deserialization; J3, data transfer to MII interface: the data sending submodule of the LVDS-MII conversion module transfers the parallel MII data parallel_data obtained by deserialization to the MII interface module, and makes the send_en_from_lvds signal valid; J4, MII interface sending: When the MII interface module receives a valid send_en_from_lvds signal, it sends the received parallel MII data data_from_lvds through the MII interface; at the same time, it passes the data received by the MII interface to the EtherCAT IP Core for subsequent protocol processing.

8. The FPGA-based EtherCAT communication method according to claim 7, characterized in that: The clock management primitives in F1 include Xilinx's PLL and Altera's PLL; the differential I / O primitives in F5 include Xilinx's IOBUFDS and Altera's differential output primitive.

9. An electronic device, characterized in that: The method comprises a processor and a memory storing a program, the program comprising instructions which, when executed by the processor, cause the processor to perform the method according to claim 6 or 7.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method of claim 6 or 7.

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