Multi-FPGA multi-constraint hypergraph division algorithm considering logic unit replication

Abstract

The invention discloses a hypergraph partitioning algorithm. The hypergraph partitioning algorithm comprises the following steps of integrating and constructing a data structure; performing hypergraph division on the circuit netlist into N parts by adopting mtKahypar; mapping the circuit nodes to the corresponding FPGAs by using a Steiner tree; using a legalization algorithm to cancel nodes which do not conform to FPGA resource constraints and hop count constraints from the current division, storing the nodes in a list data structure, and setting a current division result as an initial solution; carrying out linear programming mathematical modeling; utilizing a greedy algorithm to copy the nodes to the maximum income so as to reduce an objective function, and then obtaining a final solution. Compared with the prior art, the method has the advantages that the problems of resource limitation and cross-FPGA connection in FPGA division are effectively solved by combining the mtKahypar algorithm, the Steiner tree algorithm, the linear programming algorithm and the greedy algorithm, and the efficiency, accuracy and adaptability of hypergraph division are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a hypergraph partitioning algorithm that considers logic unit replication with multiple constraints for multiple FPGAs. Background Art

[0002] With the rapid expansion of the scale of integrated circuit design, a single FPGA (Field-Programmable Gate Array) can no longer meet the simulation requirements for designs with a scale of up to billions of gates. In a multi-FPGA system, the design needs to be distributed across multiple FPGAs for simulation, which poses higher requirements on the quality and speed of the partitioning algorithm. Unreasonable partitioning will increase the number of connections across FPGAs, resulting in a decrease in the operating frequency of the DUT (Design Under Test), thereby affecting the efficiency and accuracy of simulation.

[0003] In the prior art, hypergraph partitioning algorithms are widely used in integrated circuit design, especially suitable for dealing with high-order interaction relationships in large-scale circuits. However, these algorithms face the following challenges in multi-FPGA scenarios:

[0004] Insufficient timing optimization: The partitioning results often ignore the timing requirements of the design, resulting in limited simulation efficiency.

[0005] Complex placement and routing: The difficulty of placement and routing inside the FPGA increases, affecting the overall performance.

[0006] Connection density problem: The increase in the number of connections across FPGAs significantly reduces the system operating frequency.

[0007] Research shows that in the layout design of VLSI circuits, the technique of combining vertex replication with the HP (Hypergraph Partitioning) model can effectively reduce the number of connections between networks and the routing density. Vertex replication refers to replicating the same logic units or gates in multiple networks to share the connection load. Introducing the logic unit replication technique in hypergraph partitioning can not only optimize the connections across FPGAs but also improve the timing performance. Although replicating logic units increases some resource overhead, the system simulation efficiency can be significantly improved by reducing the cross-FPGA connections between networks.

[0008] The application of the hardware simulation platform in IC verification shows that its high performance and full visualization features make it a key tool for dealing with the interaction between SoC hardware and software. However, the existing hypergraph partitioning algorithms have not fully utilized the potential of logic unit replication and are difficult to meet the requirements of efficient partitioning in multi-FPGA systems. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a hypergraph partitioning algorithm combined with logic unit replication in response to the deficiencies raised in the above-mentioned background technology. For multi-FPGA simulation scenarios in large-scale integrated circuit design, by optimizing the partitioning and replication strategies, cross-FPGA connections are significantly reduced, the DUT operating frequency and simulation efficiency are improved, and at the same time, resource utilization and wiring complexity are ensured to be within a controllable range.

[0010] In order to solve the above technical problems, the present invention provides a technical solution: a hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints, which includes the following steps:

[0011] Step 1: Create a parser to extract the information required for segmentation and integrate it to build a data structure;

[0012] Step 2: Use mtKahypar to divide the circuit netlist into N parts by hypergraph, where N is the number of FPGA parts;

[0013] Step 3: Use the Steiner tree to map the circuit nodes to the corresponding FPGA;

[0014] Step 4: Use the legalization algorithm to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition, store them in a list data structure, and set the current partition result as the initial solution;

[0015] Step 5: Perform linear programming mathematical modeling. One of the core innovations of this invention is to introduce a linear programming model to optimize the partitioning results. By defining the objective function and constraints, the initial solution and the nodes that do not meet the constraints are jointly optimized to obtain the optimal solution. This method is significantly different from the traditional hypergraph partitioning algorithm and reflects the advantages of linear programming in multi-FPGA partitioning.

[0016] Step 6: Use the greedy algorithm to replicate the nodes with the maximum benefit to reduce the objective function and then get the final solution.

[0017] Furthermore, the step 1 of making a parser to extract the information required for the division is specifically performed by the following steps:

[0018] A. Delete useless comments, spaces and line breaks to sort out valid string data;

[0019] B. Lexical analysis: Use symbols and characters such as brackets, colons, and semicolons as morphemes to convert a string into a lexical string;

[0020] C. Syntax analysis: According to the separator, a finite state machine is used to extract key-value pairs in the lexical string and store the key-value pairs in a recursive structure;

[0021] D. Find value: Recursively find the key containing a certain string from the above structure, take out its value and store it in the database.

[0022] Furthermore, in step 2, the mtkhypar algorithm is used to partition the hypergraph, and the following steps are used for preprocessing:

[0023] A. In order to reduce the time of repeated distance calculation and reduce the time complexity, the distance between every two nodes is calculated in advance and stored in a two-dimensional array structure;

[0024] B. An improved algorithm based on mtKahypar is developed to quickly and accurately locate the unassigned nodes adjacent to the input nodes, and based on this, efficiently select the node sequence that meets the constraints for FPGA allocation.

[0025] Furthermore, in step three, the circuit nodes are mapped to the corresponding FPGA using the Steiner tree, and the mapping is performed using the following steps:

[0026] A. Construct a minimum Steiner tree to map the circuit nodes to the corresponding FPGA to optimize the connection length between nodes and reduce the number of cross-FPGA connections;

[0027] B. Optimize FPGA mapping through Steiner tree and use the legality check function to filter out illegal partition nodes.

[0028] Furthermore, in step 4, a legalization algorithm is used to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition. Specifically, the legalization is performed using the following steps:

[0029] A. Design a legality check function to ensure that the resource consumption and maximum number of interconnections of each FPGA do not exceed the limit;

[0030] B. Nodes that do not meet the constraints will be removed and stored in a list, and the partition results that meet the constraints will be used as the initial solution.

[0031] Furthermore, in step five, linear programming mathematical modeling is performed, and the solution is specifically solved by the following steps:

[0032] A. Define decision variables, objective functions, and constraints, and use the solver to find the optimal solution;

[0033] B. Pass the initial solution and nodes that do not meet the constraints into the linear programming solution.

[0034] Furthermore, in step six, the greedy algorithm is used to replicate the nodes with the maximum benefit to reduce the objective function. Specifically, the replication is performed using the following steps:

[0035] A. Construct a sparse matrix for each node to record the source nodes and drain nodes connected to it;

[0036] B. Calculate the cost function for replicating a node. Based on this, sort all the nodes by cost and sort the FPGAs that contribute cost to this node. Thus, the nodes to be replicated first can be obtained, and at the same time, the FPGAs to which replication is preferred can be obtained.

[0037] After adopting the above method, the present invention has the following advantages: By combining mtKahypar, Steiner tree, linear programming, and greedy algorithm, the present invention effectively solves the resource limitation and cross-FPGA connection problems in FPGA partitioning, and significantly improves the efficiency, accuracy, and adaptability of hypergraph partitioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of a hypergraph partitioning algorithm considering logic unit replication with multiple constraints for multiple FPGAs;

[0039] Figure 2 It is a schematic diagram for solving step five of a hypergraph partitioning algorithm considering logic unit replication with multiple constraints for multiple FPGAs;

[0040] Figure 3 It is a schematic diagram of step six of a hypergraph partitioning algorithm considering logic unit replication with multiple constraints for multiple FPGAs. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The following further elaborates on the present invention in detail with reference to the accompanying drawings.

[0042] Combined with the attached Figures 1-3 , a hypergraph partitioning algorithm considering logic unit replication with multiple constraints for multiple FPGAs, the entire program is written in Python. First, parse the input design file, then construct a circuit diagram and an FPGA graph and convert them into a specific format. Next, use the Mt-KaHyPar tool for preliminary partitioning to map the design onto the FPGAs. Subsequently, through the legalization step, filter out the illegal partitioning nodes, and optimize them through linear programming and greedy algorithm to find the best FPGA mapping scheme, and finally output the optimized result. Next, each step will be elaborated in detail:

[0043] Step 1: Make a parser to extract the information required for partitioning and integrate and construct a data structure. The specific steps for making the parser to extract the information required for partitioning are as follows:

[0044] A. Delete the useless comments, spaces, and line breaks, and sort out the valid string data;

[0045] B. Lexical analysis: Using symbols and characters such as parentheses, colons, and semicolons as morphemes, convert the string into a lexical string;

[0046] C. Syntax analysis: According to the delimiters, use a finite state machine to extract key-value pairs in the lexical string and store the key-value pairs in a recursive structure;

[0047] D. Find value: Recursively find the key containing a certain string from the above structure and extract its value and store it in the database.

[0048] To improve the execution efficiency of the algorithm, it is crucial to write a parser that can handle multiple file inputs and convert them into appropriate data structures. The following is an explanation of the main data structures used in the parser:

[0049]

[0050] The general process of the Parser is as follows:

[0051] Read the design.are to populate the nodes dictionary, with the node name as the key and the node resource list as the value. At the same time, generate node_id_map for the mapping between node ID and name.

[0052] Read the design.info file and populate the FPGAs dictionary to store the maximum interconnection number and resource limit of the FPGA. At the same time, generate fpga_id_map for the mapping between FPGA name and ID.

[0053] Read the design.net file, parse the network information, and populate the nets list.

[0054] Read the design.topo file, obtain the hop limit, and at the same time populate the topo list. Then use the Floyd-Warshall algorithm to calculate the shortest paths between all FPGAs to establish hop_map.

[0055] To improve the efficiency of subsequent processing, after the file parsing is completed, the following measures are taken: First, to adapt to the use of the Mt-KaHyPar tool, construct the entire circuit netlist into a hypergraph and export it in the hmetis format. This helps to optimize the subsequent processing flow. Second, considering the requirements of FPGA mapping, construct the FPGA as a graph and output it in the metis format. These steps are all to ensure higher efficiency and performance during the FPGA mapping process.

[0056] Step two: Divide the circuit netlist into N parts as a hypergraph, where N is the number of FPGAs. Use an algorithm for hypergraph partitioning. Specifically, the following steps are used for preprocessing:

[0057] A. To reduce the repeated calculation of distance time and lower the time complexity, the distances between every two nodes are calculated in advance and stored using a two-dimensional array structure.

[0058] B. Quickly and accurately locate the unassigned nodes adjacent to the input node, and based on this, efficiently select a node sequence that meets the constraints for FPGA allocation.

[0059] In the process of implementing efficient hypergraph partitioning, Mt-KaHyPar is selected as the main tool. It is a hypergraph partitioner that supports multi-threading and stands out among similar tools with its excellent processing speed. The reasons for choosing Mt-KaHyPar mainly include the following two points:

[0060] Fast processing ability: Mt-KaHyPar can quickly process large-scale hypergraph data, significantly shortening the partitioning time. This makes it very ideal in application scenarios where an initial partition needs to be generated quickly.

[0061] Multi-threading support: The multi-threading feature of this tool makes full use of the multi-core processing power of modern computers, making the partitioning process more efficient.

[0062] When using Mt-KaHyPar for hypergraph partitioning, the goal of the initial partition is to quickly divide the hypergraph into M parts, where M is set according to the number of FPGAs. By dividing the hypergraph into several parts, subsequent optimization algorithms can operate on smaller sub-problems, thereby improving the overall optimization efficiency.

[0063] Step 3: Map the circuit nodes to the corresponding FPGAs using the Steiner tree. The circuit nodes are mapped to the corresponding FPGAs using the Steiner tree, specifically by following the steps below for mapping:

[0064] A. Construct the minimum Steiner tree to map the circuit nodes to the corresponding FPGAs, so as to optimize the connection length between nodes and reduce the number of cross-FPGA connections.

[0065] B. Optimize the FPGA mapping through the Steiner tree and use a legality check function to filter out illegal partition nodes.

[0066] In FPGA mapping, the minimum Steiner tree is used for guidance. The Steiner tree is used to find the shortest tree-like structure connecting a given set of nodes. When partitioning the circuit diagram onto the FPGA diagram, it is desired that the circuit nodes be as close as possible, essentially optimizing a layout such that the connection length between nodes (in the abstract sense of physical layout or logical connection) is as short as possible.

[0067] Under the guidance of the Steiner tree, we can prioritize directly connected nodes for partitioning, ensuring that their distance in physical space is minimized. This not only helps to meet the hop constraints, but also the hyperedges connect multiple nodes. The Steiner tree can minimize the number of hyperedges cut during the partitioning process. In this way, the nodes within the hyperedges are kept in the same FPGA as much as possible, thereby reducing the number of cross-FPGA connections and reducing the cutting overhead.

[0068] Step 4: Use the legalization algorithm to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition, store them in a list data structure, set the current partition result as the initial solution, and use the legalization algorithm to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition. Specifically, the following steps are used for legalization:

[0069] A. Design a legality check function to ensure that the resource consumption and maximum number of interconnections of each FPGA do not exceed the limit;

[0070] B. Nodes that do not meet the constraints will be removed and stored in a list, and the partition results that meet the constraints will be used as the initial solution.

[0071] Since the question requires the use of hard constraints, the FPGA mapping based on the minimum Steiner tree cannot ensure the global legality. Therefore, a legality check function is designed to verify the legality of the current result. For the nodes that violate the rule, they are removed from the partitioned FPGA and stored in a list, and then the relaxation operation is performed to ensure that the current partition result is legal. This legal result will be used as the initial partition of the linear programming solver and passed to the subsequent linear programming solver to implement soft constraints so that the linear programming solver can find a better solution within the time limit. The symbol explanation is shown in Table 1 below:

[0072]

[0073] The specific expression of the legality check function is as follows:

[0074] Resource constraints are legal: If an FPGA i Resource usage U i >R i , then from V i Remove the node that exceeds the resource and add this node to V violated ;

[0075] Hop constraint: If the source node s of a hyperedge is allocated to FPGA i The drain node d directly connected to it is divided into FPGA j , and h ij >h maxThen remove the drain node from the corresponding FPGA j and add the drain node to V violated

[0076] The legalized output result is the partitioning result after removing illegal nodes. Since in an actual circuit, there are more than millions of cells. This result will be used as the initial solution for linear programming, aiming to reduce the solution space of linear programming and improve the solution speed.

[0077] Step 5: Conduct linear programming mathematical modeling. One of the core innovations of the present invention is to introduce a linear programming model to optimize the partitioning result. By defining the objective function and constraint conditions, jointly optimize the initial solution and the nodes that do not meet the constraints to obtain the optimal solution. This method is significantly different from traditional hypergraph partitioning algorithms, reflecting the advantages of linear programming in multi-FPGA partitioning. Conduct linear programming mathematical modeling, specifically solved by the following steps:

[0078] A. Define decision variables, objective function, and constraint conditions, and use the solver to find the optimal solution;

[0079] B. Input the initial solution and the nodes that do not meet the constraints for linear programming solution.

[0080] Use the linear programming solver to partition the violated nodes under the condition of conforming to the mathematical model. The linear programming mathematical modeling is as follows, and the symbols are shown in Table 1:

[0081] 1. Define decision variables:

[0082] x n,m : If node n is assigned to FPGA m, then x n,m = 1, otherwise 0.

[0083] y k,m : If the hyperedge k is cut (the source node and the drain node are not on the same FPGA), and the source node is on FPGA m and at least one of its drain nodes is on a different FPGA, then y k,m = 1, otherwise 0.

[0084] 2. Define the objective function as minimizing the hop of all cut edges multiplied by the weight of this edge:

[0085]

[0086] Here Z is the objective function, representing the quantity to be minimized, and wk is the weight of hyperedge k.

[0087] 3. Define resource constraints:

[0088] Node allocation constraint: Each node can only be allocated to one FPGA.

[0089]

[0090] Here, is the total number of nodes, and is the total number of FPGAs. This constraint means that each node can only be allocated to one FPGA. Resource constraint: The resource consumption on each FPGA cannot exceed the resource limit.

[0091]

[0092] Maximum interconnection number constraint: Ensure that the maximum interconnection number of each FPGA does not exceed the limit.

[0093]

[0094] Hop constraint: Ensure that the source and drain of the hyperedge do not exceed the hop constraint

[0095] h i,j ≤h max

[0096] The linear programming solution model is as follows:

[0097]

[0098] Solve the violated nodes through the above mathematical model using a linear programming solver to obtain a better solution. The specific process is as follows: First, establish a linear programming problem according to the above mathematical model. Then, take the nodes that do not satisfy the constraint conditions (such as nodes that do not satisfy the resource constraint, interconnection line constraint, etc.) as variables and solve them using a linear programming solver. The linear programming solver will find the optimal solution of the objective function under the condition of satisfying all constraint conditions, so as to obtain the optimized allocation scheme of the nodes.

[0099] Step 6: Use the greedy algorithm to copy the nodes with the maximum benefit to reduce the objective function, and then obtain the final solution. Use the greedy algorithm to copy the nodes with the maximum benefit to reduce the objective function. Specifically, the following steps are used for copying:

[0100] A. Construct a sparse matrix for each node to record the source nodes and drain nodes connected to it;

[0101] B. Calculate the cost function of copying a node. Based on this, sort the costs of all nodes, and at the same time sort the FPGAs that contribute to the cost of this node. Therefore, the nodes to be copied first can be obtained, and at the same time the FPGAs to which they are copied first can be obtained.

[0102] After obtaining an optimal solution using a linear programming solver, to further optimize the objective function, consider replicating logic units. During the replication process, the previous constraints still need to be followed, and a greedy algorithm is used to achieve the maximum degree of replication.

[0103] Core idea:

[0104] Construct a sparse matrix for each node to record the source nodes and drain nodes connected to it. By querying a certain node, it is possible to know which drain nodes it is connected to as a source node, which source nodes it is connected to as a drain node, and also includes the number of hops between nodes and the weight of the edge.

[0105] Cost function:

[0106] The cost function for replicating a node is defined as:

[0107] cost = decrease_cost - increase_cost

[0108] Calculation of decrease_cost:

[0109] When traversing a node, if among the drain nodes connected to it as a source node, there are multiple cases belonging to the same FPGA, consider it as an edge connecting these nodes.

[0110] Calculate the number of hops using the source node and drain node, and multiply by the weight. Note to avoid duplicate calculations. This result is the cost reduction after replication.

[0111] If the connected drain nodes come from different FPGAs, the cost reduction for each edge needs to be calculated separately.

[0112] Calculation of increase_cost:

[0113] When the node is a drain node, the increase in cost is the number of hops between the other nodes connected to it and the weight.

[0114] Node sorting and optimization:

[0115] Based on the cost function, sort all nodes by cost, and at the same time sort the FPGAs that contribute cost to this node.

[0116] In this way, the nodes to be replicated first can be obtained, and at the same time the FPGAs to which replication is preferred can be obtained.

[0117] The greedy algorithm will, under the premise of meeting the constraints, replicate as many nodes as possible to reduce the objective function.

[0118] The present invention and its embodiments have been described above. Such description is not restrictive, and the actual structure is not limited thereto. In summary, if those of ordinary skill in the art are inspired by it and design, without creative efforts, structural modes and embodiments similar to the technical solution without departing from the gist of the present invention, they shall fall within the protection scope of the present invention.

Claims

1. A hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints, characterized by: It includes the following steps: Step 1: Create a parser to extract the information required for segmentation and integrate it to build a data structure; Step 2: Use mtKahypar to divide the circuit netlist into N parts by hypergraph, where N is the number of FPGA parts; Step 3: Use the Steiner tree to map the circuit nodes to the corresponding FPGA; Step 4: Use the legalization algorithm to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition, store them in a list data structure, and set the current partition result as the initial solution; Step 5: Perform linear programming mathematical modeling. One of the core innovations of the present invention is to introduce a linear programming model to optimize the partitioning results. By defining the objective function and constraints, the initial solution and the nodes that do not meet the constraints are jointly optimized to obtain the optimal solution. This method is significantly different from the traditional hypergraph partitioning algorithm and reflects the advantages of linear programming in multi-FPGA partitioning. Step 6: Use the greedy algorithm to replicate the nodes with the maximum benefit to reduce the objective function and then get the final solution.

2. According to claim 1, a hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints, characterized in that: The step 1 of making a parser to extract the information required for the division is specifically performed by the following steps: A. Delete useless comments, spaces and line breaks to sort out valid string data; B. Lexical analysis: Use symbols and characters such as brackets, colons, and semicolons as morphemes to convert a string into a lexical string; C. Syntax analysis: According to the separator, a finite state machine is used to extract key-value pairs in the lexical string and store the key-value pairs in a recursive structure; D. Find value: Recursively find the key containing a certain string from the above structure, take out its value and store it in the database.

3. The hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints according to claim 1 is characterized in that: Step 2 uses the mtkhypar algorithm to partition the hypergraph, and specifically uses the following steps for preprocessing: A. In order to reduce the time of repeated distance calculation and reduce the time complexity, the distance between every two nodes is calculated in advance and stored in a two-dimensional array structure; B. An improved algorithm based on mtKahypar is developed to quickly and accurately locate the unassigned nodes adjacent to the input nodes, and based on this, efficiently select the node sequence that meets the constraints for FPGA allocation.

4. The hypergraph partitioning algorithm for multiple FPGAs and multiple constraints considering logic unit replication according to claim 1, characterized in that: Step 3 uses the Steiner tree to map the circuit nodes to the corresponding FPGA. Specifically, the mapping is performed using the following steps: A. Construct a minimum Steiner tree to map the circuit nodes to the corresponding FPGA to optimize the connection length between nodes and reduce the number of cross-FPGA connections; B. Optimize FPGA mapping through Steiner tree and use the legality check function to filter out illegal partition nodes.

5. The hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints according to claim 1, characterized in that: Step 4: Use the legalization algorithm to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition. Specifically, the following steps are used for legalization: A. Design a legality check function to ensure that the resource consumption and maximum number of interconnections of each FPGA do not exceed the limit; B. Nodes that do not meet the constraints will be removed and stored in a list, and the partition results that meet the constraints will be used as the initial solution.

6. The hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints according to claim 1, characterized in that: Step 5: Perform linear programming mathematical modeling, specifically using the following steps to solve: A. Define decision variables, objective functions, and constraints, and use the solver to find the optimal solution; B. Pass the initial solution and nodes that do not meet the constraints into the linear programming solution.

7. The hypergraph partitioning algorithm considering logic unit replication with multiple FPGAs and multiple constraints according to claim 1 is characterized in that: Step 6: Use the greedy algorithm to copy the node with the maximum benefit to reduce the objective function. Specifically, the following steps are used for copying: A. Build a sparse matrix for each node to record the source nodes and drain nodes connected to it; B. Calculate the cost function of replicating a node. Based on this, sort all nodes by cost and sort the FPGAs that contribute to the cost of the node. This way, you can get the nodes that are replicated first and the FPGAs that are replicated first.

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