Chip post-emulation verification method and device, equipment and storage medium
By automatically generating the target timing simulation verification model in the post-chip simulation stage, the risk of lack of simulation universality and manual writing of timing models in the existing technology is solved, and efficient and accurate chip simulation verification is achieved.
Patent Information
- Application Number
- CN202510344112.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-10
AI Technical Summary
The existing post-image verification technology lacks simulation versatility and requires manual writing of timing models, which poses a risk of debugging errors, affecting simulation efficiency and accuracy.
By determining the verification model requirements in the post-imitation stage of the chip, the target timing simulation verification model is automatically generated, and a standardized timing model is generated using the signal table of the preset timing model and the verification parameters to reduce the risk of manual intervention and errors.
It improves the efficiency and accuracy of chip simulation, reduces the risk of debugging errors, simplifies the post-imitation verification process, and improves work efficiency.
Smart Images
Figure CN120124547A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip simulation, and in particular, to a method, device, equipment and storage medium for post-layout simulation verification of a chip. Background Art
[0002] Before the actual manufacture of a chip, designers can use simulation tools and techniques to evaluate the chip power consumption to ensure that the chip design meets expectations.
[0003] Chip post-layout simulation is an important link in the digital integrated circuit design process. The main purpose is to verify whether the functions and timings of the chip after placement and routing are correct under actual working conditions. Post-layout simulation is usually carried out on the basis of pre-layout simulation (functional simulation), adding real delay information to ensure the accuracy and reliability of the design considering actual process parameters. Post-layout simulation can confirm the timings of multiple clock domains, check for problems that may arise due to asynchronous processing, adjust the test mode to adapt to appropriate timing margins, and check whether the insertion of clock switching circuits and DFT (Design For Test) logic affects the function. However, the current chip post-layout simulation lacks simulation generality, and due to project differences, some timing models need to be manually written, posing a risk of debugging errors.
[0004] It can be seen that how to improve the efficiency of chip simulation while reducing the risk of debugging errors is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of the embodiments of the present invention is to provide a method, device, equipment and storage medium for post-layout simulation verification of a chip, which can reduce the workload of backend staff and reduce the risk of debugging errors while improving the efficiency of chip simulation. The specific solutions are as follows:
[0006] In a first aspect, the present application discloses a method for post-layout simulation verification of a chip, including:
[0007] Performing a simulation verification operation on a target chip, and determining a verification model requirement when the simulation verification operation is in the chip post-layout simulation stage;
[0008] Determining target timing signals from the signal table of a preset timing model based on the verification model requirement, and generating a target timing simulation verification model based on the verification parameters corresponding to the verification model requirement and the target timing signals;
[0009] Connecting the target timing simulation verification model to the post-layout simulation environment corresponding to the chip post-layout simulation stage, so as to perform post-layout simulation verification on the target chip based on the target timing simulation verification model.
[0010] Optionally, perform a simulation verification operation on the target chip, and determine the verification model requirements when the simulation verification operation is in the post-layout simulation stage of the chip, including:
[0011] Perform a simulation verification operation on the target chip, and when the simulation verification operation is in the post-layout simulation stage of the chip, obtain the block netlist corresponding to the design part to be tested of the target chip;
[0012] Based on the block netlist, determine whether the simulation verification model corresponding to the design part to be tested contains a timing model;
[0013] If the simulation verification model does not contain a timing model, determine the verification model requirements based on the block netlist.
[0014] Optionally, determine the target timing signals from the signal table of the preset timing model based on the verification model requirements, and generate a target timing simulation verification model based on the verification parameters corresponding to the verification model requirements and the target timing signals, including:
[0015] Obtain the signal table of the preset timing model, and determine the target timing signals from the signal table of the preset timing model based on the verification model requirements and all interface protocols corresponding to the design part to be tested;
[0016] Generate a target interface characteristic table based on all interface protocols and the target timing signals, and obtain the timing parameters issued by the chip verification policy for each target timing signal in the target interface characteristic table;
[0017] Obtain the static resource processing method of the first target interface protocol corresponding to each target timing signal, and determine the protocol initial code corresponding to each target timing signal based on the static resource processing method;
[0018] Based on the target interface characteristic table, splice the timing parameters of each target timing signal with the corresponding protocol initial code to obtain the first initial timing simulation verification model;
[0019] Obtain the timing interface code segment of the first target interface protocol corresponding to each target timing signal, and connect the timing interface code segment with the design part to be tested to obtain the second initial timing simulation verification model;
[0020] Based on the preset code splicing method, splice the first initial timing simulation verification model and the second initial timing simulation verification model to obtain the target timing simulation verification model.
[0021] Optionally, obtain the static resource processing method of the first target interface protocol corresponding to each target timing signal, and determine the protocol initial code corresponding to each target timing signal based on the static resource processing method, including:
[0022] Obtain the static resource processing method of the first target interface protocol corresponding to each target timing signal;
[0023] Use the command-line interpreter in the preset hardware description language to crawl the code segment corresponding to the static resource processing method to obtain the protocol initial code corresponding to each target timing signal.
[0024] Optionally, determine the target timing signal from the signal table of the preset timing model based on the verification model requirements and all interface protocols corresponding to the design part to be tested, including:
[0025] Determine the second target interface protocol from all interface protocols corresponding to the design part to be tested based on the verification model requirements; the second target interface protocol is the interface protocol without a corresponding timing simulation model among all interface protocols;
[0026] Determine the target timing signal from the signal table of the preset timing model based on the second target interface protocol.
[0027] Optionally, obtain the timing parameters issued by the chip verification party for each target timing signal in the target interface characteristic table, including:
[0028] Based on the preset spreadsheet, obtain the target signal assignment file uploaded by the chip verification party; the target signal assignment file is a file recording the assignment parameters and the timing signals corresponding to the assignment parameters; the assignment parameters are defined by the chip verification party based on the verification model requirements;
[0029] Determine the timing parameters of each target timing signal in the target interface characteristic table based on the target signal assignment file.
[0030] Optionally, determine the timing parameters of each target timing signal in the target interface characteristic table based on the target signal assignment file, including:
[0031] Use the preset code script to extract the assignment parameters and the timing signals corresponding to the assignment parameters from the target signal assignment file;
[0032] Match the assignment parameters and the timing signals corresponding to the assignment parameters with each target timing signal in the target interface characteristic table to determine the timing parameters of each target timing signal.
[0033] In a second aspect, the present application discloses a chip post-layout simulation verification device, including:
[0034] A model verification requirement determination module, configured to perform a simulation verification operation on the target chip and determine the verification model requirements when the simulation verification operation is in the chip post-layout simulation stage;
[0035] A model generation module, configured to determine target timing signals from a signal table of a preset timing model based on verification model requirements, and generate a target timing simulation verification model based on verification parameters corresponding to the verification model requirements and the target timing signals;
[0036] A post-layout simulation verification module, configured to connect the target timing simulation verification model to a post-layout simulation environment corresponding to the post-layout stage of the chip, so as to perform post-layout simulation verification on the target chip based on the target timing simulation verification model.
[0037] Thirdly, the present application discloses an electronic device, including:
[0038] A memory, configured to store a computer program;
[0039] A processor, configured to execute the computer program to implement the foregoing chip post-layout simulation verification method.
[0040] Fourthly, the present application discloses a computer-readable storage medium, configured to store a computer program, where the computer program, when executed by a processor, implements the foregoing chip post-layout simulation verification method.
[0041] In the present invention, a simulation verification operation is performed on a target chip, and verification model requirements are determined when the simulation verification operation is in the post-layout stage of the chip; target timing signals are determined from a signal table of a preset timing model based on the verification model requirements, and a target timing simulation verification model is generated based on verification parameters corresponding to the verification model requirements and the target timing signals; the target timing simulation verification model is connected to a post-layout simulation environment corresponding to the post-layout stage of the chip, so as to perform post-layout simulation verification on the target chip based on the target timing simulation verification model.
[0042] It can be seen from the above technical solutions that the present application determines, from a signal table of a preset timing model, target timing signals required for verification parameters of a timing verification simulation model required in verification model requirements through the verification model requirements obtained in the post-layout stage of the chip, and then determines a final target timing simulation verification model based on the target timing signals and the corresponding verification parameters. In this way, a timing simulation verification model can be automatically generated, and since the generation of the model is based on a preset signal table, the generated timing model can be guaranteed to be standard and not prone to errors. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.
[0044] Figure 1 It is a schematic diagram of an application scenario for chip post-layout simulation verification disclosed by the present invention;
[0045] Figure 2 Flow chart of a post-layout simulation verification method disclosed by the present invention;
[0046] Figure 3 Architecture diagram of a specific behaviorless timing model package disclosed by the present invention;
[0047] Figure 4 Flow chart of a specific post-layout simulation verification method disclosed by the present invention;
[0048] Figure 5 Flow chart of a specific post-layout simulation verification method disclosed by the present invention;
[0049] Figure 6 Structure diagram of a post-layout simulation verification device disclosed by the present invention;
[0050] Figure 7 Structure diagram of an electronic device disclosed by the present invention. Specific embodiments
[0051] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0052] The terms "including" and "having" in the specification of the present invention and any deformations related to "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.
[0053] In order to enable those skilled in the art of this technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0054] In the design of digital integrated circuits, the back-end netlist block is an important concept in the design process. The back-end netlist usually refers to the gate-level netlist generated after synthesis. It is a circuit diagram obtained by converting the RTL (Register Transfer Level Code) code in the front-end design into standard cells based on a process library. In the back-end design, a block usually refers to a circuit area with a specific function, which can be divided according to the hierarchical design of the circuit. Each block contains a certain number of macro cells and standard cells. Since the back-end netlist is mostly delivered in the form of blocks, the simulation verification team usually receives an incomplete netlist, so there is no behavioral timing model to solve the situation of incomplete simulation netlist. The application scenario of the present invention is as Figure 1 shown. The design under test is CHIP-TOP-BLOCK (the top-level block of the chip); the chip interface simulation model is a real-scene simulation model used to test and verify the function, timing, and logic circuit of the design under test; the behavioral timing model is a netlist model that needs to have behaviors in the current scenario, and is mostly delivered together with the block netlist; the no-behavioral timing model is generally a model with a missing block netlist interface and needs to be supplemented by back-end simulation personnel. The present invention discloses a method for post-chip verification, which can generate the above-mentioned no-behavioral timing model through an automated method.
[0055] See Figure 2 shown. An embodiment of the present application discloses a method for post-chip simulation verification, including:
[0056] Step S11: Perform a simulation verification operation on the target chip, and determine the verification model requirements when the simulation verification operation is in the post-chip simulation stage.
[0057] In this embodiment, a simulation verification operation is performed on the target chip, and verification model requirements are determined when the simulation verification operation is in the post-layout simulation stage of the chip, including: performing a simulation verification operation on the target chip, and when the simulation verification operation is in the post-layout simulation stage of the chip, obtaining the block netlist corresponding to the design part to be tested of the target chip; judging whether a timing model is included in the simulation verification model corresponding to the design part to be tested based on the block netlist; if the timing model is not included in the simulation verification model, determining the verification model requirements based on the block netlist. That is, when the simulation verification of the target chip is performed and the simulation verification reaches the post-layout simulation block stage, it is determined whether there is a requirement for a timing model in the block. Specifically, it is judged whether the backend provides the entire netlist for the design part to be tested corresponding to the target chip. If the backend provides the entire netlist, it means that there is no internal requirement for a timing model in the design part to be tested, and only an external timing model is needed. If the block netlist provided by the backend is incomplete, the verification model requirements can be determined according to the missing interface model in the block netlist.
[0058] Two concepts are explained here. The behavioral timing model is the netlist model in which behaviors need to occur in the current scenario, and it is usually delivered together with the block netlist; the non-behavioral timing model is generally the missing model of the block netlist interface, which needs to be supplemented by the backend simulation personnel. For example Figure 3As shown, it is instantiated from the interface signal unit in the behaviorless timing model package. All timing units are encapsulated in the form of a package and can be directly called by the System Verilog (SV, a hardware description language) platform during simulation. For the DFT (Discrete Fourier Transform) signal timing unit, aiming at the DFT logic in the CHIP-TOP-BLOCK netlist, a behaviorless timing model is constructed by assigning values to the timing signal unit. The work content of DFT is to design a test circuit at the RTL (Register-Transfer Level), verify the test circuit in the verification phase, insert test logic in the synthesis phase, and provide test vectors in the test phase. The DFT signal timing unit includes signals in the verification phase, synthesis phase, and test phase, and the signal assignments in different phases are different. The AHB (Advanced High Performance Bus) protocol unit aims at the missing block module with the AHB bus as the bus interface. The model signal values cover the AHB protocol and output AHB protocol signals without affecting the system bus function. The APB (Advanced Peripheral Bus) protocol unit aims at the missing block module with the APB bus as the bus interface. The model signal values cover the APB protocol and output APB protocol signals without affecting the system bus function. The AXI (Advanced eXtensible Interface, a bus protocol) protocol unit aims at the missing block module with the AXI bus as the bus interface. The model signal values cover the AXI protocol and output AXI protocol signals without affecting the system bus function. The timing check unit checks the timing in the verilog specify manner.
[0059] Step S12: Determine the target timing signal from the signal table of the preset timing model based on the verification model requirements, and generate a target timing simulation verification model based on the verification parameters corresponding to the verification model requirements and the target timing signal.
[0060] In this embodiment, a target timing signal is determined from a signal table of a preset timing model based on the requirements of a verification model, and a target timing simulation verification model is generated based on the verification parameters corresponding to the verification model requirements and the target timing signal, including: obtaining the signal table of the preset timing model, and determining the target timing signal from the signal table of the preset timing model based on the verification model requirements and all interface protocols corresponding to the design part to be tested; generating a target interface characteristic table based on all interface protocols and the target timing signal, and obtaining the timing parameters issued by the chip verification party for each target timing signal in the target interface characteristic table; obtaining the static resource processing method of the first target interface protocol corresponding to each target timing signal, and respectively determining the protocol initial code corresponding to each target timing signal based on the static resource processing method; based on the target interface characteristic table, splicing the timing parameters of each target timing signal with the corresponding protocol initial code to obtain a first initial timing simulation verification model; obtaining the timing interface code segment of the first target interface protocol corresponding to each target timing signal, and connecting the timing interface code segment with the design part to be tested to obtain a second initial timing simulation verification model; splicing the first initial timing simulation verification model and the second initial timing simulation verification model based on a preset code splicing method to obtain a target timing simulation verification model.
[0061] Specifically, first, after obtaining the verification model requirements, that is, determining the missing model (behaviorless timing model) from the block netlist, the signal table of the preset timing model is obtained. Here, the preset timing model is a behaviorless timing model. The signal table of the behaviorless timing model is shown in Table 1 below:
[0062] Table 1
[0063]
[0064] Furthermore, determining the target timing signal from the signal table of the preset timing model based on the verification model requirements and all interface protocols corresponding to the design part to be tested includes: determining the second target interface protocol from all interface protocols corresponding to the design part to be tested based on the verification model requirements; the second target interface protocol is the interface protocol without a corresponding timing simulation model among all interface protocols; determining the target timing signal from the signal table of the preset timing model based on the second target interface protocol. That is, after determining the missing model (behaviorless timing model) from the block netlist according to the verification model requirements, according to Figure 1Among them, for all the interface protocols corresponding to the design part to be measured, it is determined that there is no interface protocol for which the corresponding timing simulation model is provided in the block netlist provided by the backend. Among them, the timing model corresponding to the second target interface protocol is the target no-behavior timing model here. Then, according to the signals recorded in Table 1, the target timing signals corresponding to each target no-behavior timing model are determined. For example, the signal types corresponding to the DFT signals include: scan chain type {tck, reset, ce, se, ue, sel, si}; built-in self-test type {se, te, reset}; boundary scan type {test_si1, test_si2, test_si3...}; logic BIST (Built-in Self Test) type {test_si1, test_si2, test_si3...}. In this way, and based on the characteristics of dividing blocks in a general SOC (System on Chip), a no-behavior timing model of a component can be constructed. When the interface timing netlist of a block is missing, it can be equivalently replaced in the current simulation scenario to accelerate the simulation process and achieve synchronous simulation with the backend staff.
[0065] Furthermore, after determining the target timing signals, a target interface characteristic table can be generated based on all the interface protocols and the target timing signals, and the timing parameters issued by the chip verification party for each target timing signal in the target interface characteristic table can be obtained. Specifically, obtaining the timing parameters issued by the chip verification party for each target timing signal in the target interface characteristic table includes: obtaining the target signal assignment file uploaded by the chip verification party for the interface based on a preset spreadsheet; the target signal assignment file is a file recording the assignment parameters and the timing signals corresponding to the assignment parameters; the assignment parameters are defined by the chip verification party based on the requirements of the verification model; determining the timing parameters of each target timing signal in the target interface characteristic table based on the target signal assignment file. That is, obtaining the target signal assignment file uploaded by the chip verification party for each timing signal in the target interface characteristic table through a preset interaction window. Among them, the target signal assignment file is filled in by the chip verification party using Excel (a spreadsheet software) and includes timing parameters (assignment parameters) and the specific pointing of the signal (the timing signal corresponding to the assignment parameter). In addition, a corresponding assignment parameter acquisition window can be directly generated for each timing signal in the target interface characteristic table through the preset interaction window, and each chip verification party can choose to directly input the assignment parameters corresponding to the timing signal in the window. In this way, the subsequent step of analyzing the target signal assignment file can be omitted, and the chip simulation efficiency can be improved. And since the assignment parameter acquisition window and the timing signal are in one-to-one correspondence, the accuracy of determining the assignment parameters can be ensured to a certain extent.
[0066] Specifically, the timing parameters of each target timing signal in the target interface characteristic table are determined based on the target signal assignment file, including: extracting the assignment parameters and the timing signals corresponding to the assignment parameters from the target signal assignment file by using a preset code script; and matching the assignment parameters and the timing signals corresponding to the assignment parameters with each target timing signal in the target interface characteristic table to determine the timing parameters of each target timing signal. That is, a preset code script can be used to analyze the target signal assignment file obtained from a preset interaction window. The preset code script includes, but is not limited to, a Python (a programming language) script. Then, the assignment parameters and the timing signals corresponding to the assignment parameters are extracted from the target signal assignment file. Finally, the assignment parameters and the timing signals corresponding to the assignment parameters are matched with each target timing signal in the target interface characteristic table to determine the timing parameters of each target timing signal.
[0067] In this embodiment, after obtaining the timing parameters of each target timing signal, the static resource processing method of the first target interface protocol corresponding to each target timing signal is obtained, and the protocol initial code corresponding to each target timing signal is determined based on the static resource processing method, including: obtaining the static resource processing method of the first target interface protocol corresponding to each target timing signal; and using the command-line interpreter in a preset hardware description language to crawl the code segment corresponding to the static resource processing method to obtain the protocol initial code corresponding to each target timing signal. Specifically, for the code part without behavioral timing, the static processing part of the protocol is adopted to make the bus or transmission protocol in the IDLE state. The command-line interpreter in a preset hardware description language can be used, that is, the shell in the System Verilog language is used to capture the code part without behavioral timing to obtain the protocol initial code corresponding to each target timing signal and store it locally.
[0068] In this embodiment, after reading the protocol initial codes corresponding to the target timing signals, the timing parameters of the target timing signals can be concatenated with the corresponding protocol initial codes based on the previously determined target interface characteristic table to obtain a first initial timing simulation verification model. The timing interface code segments of the first target interface protocol corresponding to the target timing signals are obtained, and the timing interface code segments are connected to the design part under test to obtain a second initial timing simulation verification model. The first initial timing simulation verification model and the second initial timing simulation verification model are concatenated based on a preset code concatenation method to obtain a target timing simulation verification model. That is, at this time, two parts are obtained through the above steps. One is the timing parameters of the target timing signals, and the other is the protocol initial codes corresponding to the behaviorless timing models of the target timing signals. Then, the timing parameters are concatenated with the corresponding protocol initial codes to obtain a first initial timing simulation verification model. After obtaining the first initial timing simulation verification model, it can be concatenated with the timing interface code segments to obtain a second initial timing simulation verification model. It should be noted here that the timing interface code segments can provide an interface for the model, and this code segment is used to connect to the DUT (Device Under Test), forming an effective behaviorless timing model. Finally, according to Figure 1 the application scenario of the behaviorless timing model in Figure 1 , the corresponding code concatenation method is determined, and the first initial timing simulation verification model and the second initial timing simulation verification model are concatenated to obtain a target timing simulation verification model. In this way, since the model interface is generated based on the established timing interface code segments, it can ensure that the automatically generated behaviorless timing model has a standard model interface timing and is not prone to errors.
[0069] Step S13: Connect the target timing simulation verification model to the post-layout simulation environment corresponding to the post-layout simulation stage of the chip, so as to perform post-layout simulation verification on the target chip based on the target timing simulation verification model.
[0070] In this embodiment, after obtaining the target timing simulation verification model, the interface corresponding to the target timing simulation verification model is connected to the post-layout simulation environment corresponding to the post-layout simulation stage of the chip for simulation. It should be noted here that the internal timing model of the chip generated by this application checks for timing violations, including Setup / hold violations, Recovery / Removal violations, Width violations, and whether the IP interface timing conforms to the datasheet, etc.
[0071] In this embodiment, a simulation verification operation is performed on the target chip, and verification model requirements are determined when the simulation verification operation is in the post-layout simulation stage of the chip; based on the verification model requirements, target timing signals are determined from the signal table of the preset timing model, and a target timing simulation verification model is generated based on the verification parameters corresponding to the verification model requirements and the target timing signals; the target timing simulation verification model is connected to the post-layout simulation environment corresponding to the post-layout simulation stage of the chip, so as to perform post-layout simulation verification on the target chip based on the target timing simulation verification model.
[0072] It can be seen from the above technical solution that in this application, based on the verification model requirements obtained in the post-layout simulation stage of the chip, the target timing signals required for the verification parameters of the timing verification simulation model required in the verification model requirements are determined from the signal table of the preset timing model. Then, based on the target timing signals and the corresponding verification parameters, the final target timing simulation verification model is determined. In this way, the timing simulation verification model can be automatically generated, and since the generation of the model is based on the preset signal table, the generated timing model can be guaranteed to be standard and not prone to errors.
[0073] Refer to Figure 4 and Figure 5 As shown, this application embodiment also correspondingly discloses a chip post-layout simulation verification method. Specifically, first Figure 4Among them, in step 1, the chip verification party uses Excel to fill in the timing parameters and the specific signal directions, corresponding to the signal data table of the behaviorless timing model (Table 1), and matches the protocol signals with the model values according to the protocol. Step 2 is the code part of the behaviorless timing, adopting the static processing part of the protocol to make the bus or transmission protocol in the IDLE state. Step 3 is the timing interface code segment, which provides an interface for the model, and uses this code segment to connect with the DUT to form an effective timingless model. In step 4, a python script is used to extract the user-defined parameters in the excel, and then match them with the protocol code and model signals. Immediately following step 5, the timing description is captured through the shell, and the code segment obtained in step 2 is captured through the shell script and stored. Then, in step 6, the custom parameters in step 1 are spliced with the code segment obtained in step 2 through the signal table to obtain the core part of the behaviorless timing model, making the protocol in the IDLE state. Finally, in step 7, the core part of the code segment obtained in step 6 is spliced with the interface code segment to obtain a complete behaviorless timing model. In the actual operation process, there are 7 steps in the process of generating the behaviorless timing model. First, when the simulation verification reaches the post-layout simulation block stage, it is determined whether the block has a requirement for a timing model. If the backend provides the entire netlist, there is no requirement for a timingless model, and only an external timing model is required. If the entire netlist is not provided, a timingless model is required. Then, according to the block characteristics (Table 1), select those that meet the protocol requirements from the characteristics to generate an interface characteristic table. Then, according to Figure 4 process 3, according to the block netlist interface, generate an interface code segment. The chip verification party fills in the parameter Excel according to the verification requirements (i.e., Figure 4 process 1); Next, combining Figure 4 processes 4, 5, and 6, using the interface characteristic table in step 2 as the intermediate segment, splice the parameter excel and the protocol timing code segment; Finally, splice the code segment generated according to the block interface with the result code in process 5; and connect the interface to the simulation environment for simulation.
[0074] It can be seen that this embodiment can automatically generate a timing simulation verification model, and since the generation of the model is based on a preset signal table, it can ensure that the generated timing model is standard and not prone to errors.
[0075] Refer to Figure 6 As shown, this application embodiment also correspondingly discloses a chip post-layout verification device, including:
[0076] A model verification requirement determination module 11, configured to perform a simulation verification operation on a target chip, and determine a verification model requirement when the simulation verification operation is in the chip post-layout stage;
[0077] The model generation module 12 is configured to determine target timing signals from the signal table of a preset timing model based on the verification model requirements, and generate a target timing simulation verification model based on the verification parameters corresponding to the verification model requirements and the target timing signals.
[0078] The post-layout simulation verification module 13 is configured to connect the target timing simulation verification model to the post-layout simulation environment corresponding to the post-layout stage of the chip, so as to perform post-layout simulation verification on the target chip based on the target timing simulation verification model.
[0079] In this embodiment, it can be seen from the above technical solution that in this embodiment, based on the verification model requirements obtained in the post-layout stage of the chip, the target timing signals required for the verification parameters of the timing verification simulation model required in the verification model requirements are determined from the signal table of the preset timing model. Then, based on the target timing signals and the corresponding verification parameters, the final target timing simulation verification model is determined. In this way, the timing simulation verification model can be automatically generated, and since the generation of the model is based on the preset signal table, the generated timing model can be guaranteed to be standard and not prone to errors.
[0080] Furthermore, an embodiment of the present application also discloses an electronic device. Figure 7 It is a structural diagram of an electronic device shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation to the scope of use of the present application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the chip post-layout simulation verification method disclosed in any of the foregoing embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.
[0081] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.
[0082] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be short-term storage or permanent storage.
[0083] Among them, the operating system 221 is used to manage and control each hardware device and computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the chip post-layout verification method executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs that can be used to complete other specific tasks.
[0084] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the foregoing disclosed chip post-layout verification method is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.
[0085] Furthermore, the present application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, the foregoing disclosed alarm aggregation method is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.
[0086] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and reference can be made to the description in the method part for related parts.
[0087] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.
[0088] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.
[0089] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.
[0090] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this text to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. At the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.
Claims
1. A chip post-simulation verification method, characterized in that: include: Performing a simulation verification operation on a target chip, and determining verification model requirements when the simulation verification operation is in a chip post-simulation stage; Determine a target timing signal from a signal table of a preset timing model based on the verification model requirement, and generate a target timing simulation verification model based on verification parameters corresponding to the verification model requirement and the target timing signal; The target timing simulation verification model is connected to the post-simulation environment corresponding to the chip post-simulation stage, so as to perform post-simulation verification on the target chip based on the target timing simulation verification model.
2. The chip post-simulation verification method according to claim 1, characterized in that: The simulation verification operation is performed on the target chip, and the verification model requirement is determined when the simulation verification operation is in the chip post-simulation stage, including: Performing a simulation verification operation on a target chip, and when the simulation verification operation is in a chip post-simulation stage, obtaining a block netlist corresponding to a design part to be tested corresponding to the target chip; Determine whether the simulation verification model corresponding to the design part to be tested includes a timing model based on the block netlist; If the simulation verification model does not include a timing model, the verification model requirement is determined based on the block netlist.
3. The chip post-simulation verification method according to claim 2, characterized in that: The step of determining a target timing signal from a signal table of a preset timing model based on the verification model requirement, and generating a target timing simulation verification model based on verification parameters corresponding to the verification model requirement and the target timing signal, includes: Obtaining a signal table of a preset timing model, and determining a target timing signal from the signal table of the preset timing model based on the verification model requirements and all interface protocols corresponding to the design part to be tested; Generate a target interface characteristic table based on all the interface protocols and the target timing signals, and obtain the timing parameters issued by the chip verification party for each of the target timing signals in the target interface characteristic table; Acquire a static resource processing mode of the first target interface protocol corresponding to each of the target timing signals, and determine the protocol initial code corresponding to each of the target timing signals based on the static resource processing mode; Based on the target interface characteristic table, the timing parameters of each of the target timing signals are spliced with the corresponding protocol initial code to obtain a first initial timing simulation verification model; Acquire a timing interface code segment of the first target interface protocol corresponding to each of the target timing signals, and connect the timing interface code segment with the design part to be tested to obtain a second initial timing simulation verification model; The first initial timing simulation verification model and the second initial timing simulation verification model are spliced based on a preset code splicing method to obtain a target timing simulation verification model.
4. The chip post-simulation verification method according to claim 3, characterized in that: The acquiring of the static resource processing mode of the first target interface protocol corresponding to each of the target timing signals, and determining the protocol initial code corresponding to each of the target timing signals based on the static resource processing mode, includes: Acquire a static resource processing mode of the first target interface protocol corresponding to each of the target timing signals; The command line interpreter in the preset hardware description language is used to crawl the code segments corresponding to the static resource processing method to obtain the protocol initial code corresponding to each of the target timing signals.
5. The chip post-simulation verification method according to claim 3, characterized in that: The determining the target timing signal from the signal table of the preset timing model based on the verification model requirements and all interface protocols corresponding to the design part to be tested includes: Determine a second target interface protocol from all interface protocols corresponding to the design part to be tested based on the verification model requirement; the second target interface protocol is an interface protocol that has no corresponding timing simulation model among all the interface protocols; A target timing signal is determined from a signal table of the preset timing model based on the second target interface protocol.
6. The chip post-simulation verification method according to claim 5, characterized in that: The obtaining of the timing parameters issued by the chip verification party for each of the target timing signals in the target interface characteristic table includes: Obtaining a target signal assignment file uploaded by a chip verifier based on a preset electronic spreadsheet acquisition interface; the target signal assignment file is a file that records assignment parameters and timing signals corresponding to the assignment parameters; the assignment parameters are defined by the chip verifier based on the verification model requirements; The timing parameters of each of the target timing signals in the target interface characteristic table are determined based on the target signal assignment file.
7. The chip post-simulation verification method according to claim 6, characterized in that: The determining the timing parameters of each of the target timing signals in the target interface characteristic table based on the target signal assignment file includes: Extracting the assignment parameters and the timing signals corresponding to the assignment parameters from the target signal assignment file using a preset code script; The assignment parameters and the timing signals corresponding to the assignment parameters are matched with each of the target timing signals in the target interface characteristic table to determine the timing parameters of each of the target timing signals.
8. A chip post-simulation verification device, characterized in that: include: A model verification requirement determination module is used to perform simulation verification operations on a target chip and determine verification model requirements when the simulation verification operations are in a chip post-simulation stage; A model generation module, used to determine a target timing signal from a signal table of a preset timing model based on the verification model requirement, and generate a target timing simulation verification model based on verification parameters corresponding to the verification model requirement and the target timing signal; The post-simulation verification module is used to connect the target timing simulation verification model to the post-simulation environment corresponding to the chip post-simulation stage, so as to perform post-simulation verification on the target chip based on the target timing simulation verification model.
9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the chip post-simulation verification method as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip post-simulation verification method according to any one of claims 1 to 7 are implemented.