Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel. The cascade adjustment module of the shift registers is used for adjusting a cascade output end to output a second power supply signal or a second clock signal according to signals on the first control node and the third control node, and the cascade output end of the ith-level shift register is electrically connected with the trigger write-in module of the (i + 1) th-level shift register; the output adjusting module is used for adjusting a scanning output end to output a target signal or a fourth power supply signal or a third clock signal according to a third control node, a signal on the cascade output end and the first control signal, the target signal comprises the third power supply signal or the fourth clock signal, and the scanning output end is used for being electrically connected with a pixel circuit; wherein the refresh cycle of the third clock signal is smaller than the refresh cycles of the first clock signal and the second clock signal. In the embodiment of the invention, the gate drive circuit can output complex waveforms to meet the requirements of the pixel circuit.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a gate driving circuit and a display panel. Background Art

[0002] In a display panel, a pixel circuit drives a light-emitting element to emit light, and the pixel circuit is controlled by a gate driving circuit. With the development of display technologies, display functions are becoming more and more diverse. For example, with the rise of Virtual Reality (VR) and Augmented Reality (AR), or in other requirements, the pixel circuit requires more complex row scanning signals for control.

[0003] However, the waveform of the scanning signal that the gate driving circuit in the related art can provide is relatively single and cannot meet the requirements of the pixel circuit for complex waveforms. Summary of the Invention

[0004] Embodiments of this application provide a gate driving circuit and a display panel. The gate driving circuit can output complex waveforms to meet the requirements of the pixel circuit.

[0005] In a first aspect, embodiments of this application provide a gate driving circuit, including a plurality of cascaded shift registers. The shift register includes: a trigger writing module for writing a trigger signal to a first control node according to a first clock signal accessed by it; a power writing module for writing a first power signal to a second control node according to the first clock signal accessed by it; a clock writing module for writing the first clock signal to a third control node according to the signal on the first control node, and the third control node is electrically connected to the second control node; a first adjustment module for writing a second power signal to the first control node according to a second clock signal and the signal on the third control node; a cascaded adjustment module for adjusting the cascaded output terminal to output the second power signal or the second clock signal according to the signals on the first control node and the third control node. The cascaded output terminal of the i-th shift register is electrically connected to the trigger writing module of the (i + 1)-th shift register; an output adjustment module for adjusting the scanning output terminal to output a target signal or a fourth power signal or a third clock signal according to the signals on the third control node, the cascaded output terminal, and a first control signal. The target signal includes a third power signal or a fourth clock signal, and the scanning output terminal is used to be electrically connected to the pixel circuit; wherein, the refresh period of the third clock signal is less than the refresh periods of the first clock signal and the second clock signal.

[0006] In a second aspect, embodiments of this application provide a display panel, including a pixel circuit and the gate driving circuit as described in the embodiments of the first aspect. The scanning output terminal of the shift register in the gate driving circuit is electrically connected to the pixel circuit.

[0007] In the embodiments of the present application, the shift register includes a trigger writing module, a power writing module, a clock writing module, a first adjustment module, a cascade adjustment module, and an output adjustment module. Through the coordinated control of the trigger writing module, the power writing module, the clock writing module, and the first adjustment module, the cascade adjustment module can output a signal for triggering the next-stage shift register. Compared with the related art where the output end of the shift register is electrically connected to both the pixel circuit and the trigger signal end of the next-stage shift register, in the embodiments of the present application, a cascade adjustment module is additionally added, and the output end of the cascade adjustment module is no longer electrically connected to the pixel circuit, which can reduce the load of the cascade adjustment module and is beneficial to the stability of the cascade signal. In addition, through the coordinated control of the trigger writing module, the power writing module, the clock writing module, the first adjustment module, and the cascade adjustment module, the output adjustment module can output a signal including multiple pulses of the third clock signal within one frame, that is, the shift register can output a scanning signal with multiple pulses to meet the requirements of the pixel circuit for complex pulses.

[0008] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically exemplified below. Description of the Drawings

[0009] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, purposes, and advantages of the present application will become more obvious, where the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0010] Figure 1 Fig. shows a schematic structural diagram of a shift register in a gate driving circuit provided by an embodiment of the present application;

[0011] Figure 2 Fig. shows another schematic structural diagram of a shift register in a gate driving circuit provided by an embodiment of the present application;

[0012] Figure 3 Fig. shows still another schematic structural diagram of a shift register in a gate driving circuit provided by an embodiment of the present application;

[0013] Figure 4 Fig. shows still another schematic structural diagram of a shift register in a gate driving circuit provided by an embodiment of the present application;

[0014] Figure 5 Fig. shows still another schematic structural diagram of a shift register in a gate driving circuit provided by an embodiment of the present application;

[0015] Figure 6Shows another structural schematic diagram of a shift register in the gate driving circuit provided by an embodiment of the present application;

[0016] Figure 7 Shows Figure 5 a timing schematic diagram of;

[0017] Figure 8 Shows a cascading schematic diagram of a shift register in the gate driving circuit provided by an embodiment of the present application;

[0018] Figure 9 Shows a timing schematic diagram of a multi - stage shift register in the gate driving circuit provided by an embodiment of the present application;

[0019] Figure 10 Shows Figure 6 a timing schematic diagram of. Detailed implementation manners

[0020] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only for providing a better understanding of the present application by showing examples of the present application.

[0021] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0022] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "on top of" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or region.

[0023] It should be understood that the term "and / or" used herein is merely a correlative relationship describing associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0024] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0025] Without departing from the spirit or scope of the present application, various modifications and changes can be made to the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0026] The embodiments of the present application provide a gate driving circuit and a display panel. The following will describe the embodiments of the present application with reference to the accompanying drawings.

[0027] The gate driving circuit provided by the embodiments of the present application can be used to drive a display panel. Of course, in other application scenarios, the gate driving circuit provided by the embodiments of the present application can also be used to drive non-display devices.

[0028] The gate driving circuit provided by the embodiments of the present application includes a plurality of cascaded shift registers. Here, "cascaded" means that the signal output by the previous-stage shift register serves as the trigger signal for the next-stage shift register, and the trigger signal is used to start the shift register to work.

[0029] As Figure 1 shown, the shift register 10 includes a trigger writing module 11, a power writing module 12, a clock writing module 13, a first adjustment module 14, a cascaded adjustment module 15, and an output adjustment module 16.

[0030] The trigger writing module 11 is configured to write the trigger signal SIN to the first control node N1 according to the first clock signal SCK1 it accesses. The power supply writing module 12 is configured to write the first power supply signal VGL to the second control node N2 according to the first clock signal SCK1 it accesses. The clock writing module 13 is configured to write the first clock signal SCK1 to the third control node N3 according to the signal on the first control node N1, and the third control node N3 is electrically connected to the second control node N2. The first adjustment module 14 is configured to write the second power supply signal VGH to the first control node N1 according to the second clock signal SCK2 and the signal on the third control node N3. The cascade adjustment module 15 is configured to adjust the cascade output terminal Vout to output the second power supply signal VGH or the second clock signal SCK2 according to the signals on the first control node N1 and the third control node N3. The cascade output terminal of the i-th stage shift register is electrically connected to the trigger writing module of the (i + 1)-th stage shift register. The output adjustment module 16 is configured to adjust the scan output terminal Scan to output the target signal or the fourth power supply signal VDD or the third clock signal SCK3 according to the signals on the third control node N3, the cascade output terminal Vout, and the first control signal SW1. The target signal includes the third power supply signal VDDL or the fourth clock signal SCK4, and the scan output terminal Scan is used to be electrically connected to the pixel circuit.

[0031] The refresh period of the third clock signal SCK3 is less than the refresh periods of the first clock signal SCK1 and the second clock signal SCK2. Exemplarily, the refresh periods of the first clock signal SCK1 and the second clock signal SCK2 may be the same. It can be understood that the refresh frequencies of the first clock signal SCK1 and the second clock signal SCK2 are less than the refresh frequency of the third clock signal SCK3. In the same time duration, the number of refreshes of the third clock signal SCK3 is greater than the number of refreshes of the first clock signal SCK1 and the second clock signal SCK2.

[0032] It can be understood that for the trigger writing module 11, its control terminal accesses the first clock signal SCK1, its first terminal accesses the trigger signal SIN, and its second terminal is electrically connected to the first control node N1.

[0033] For the power supply writing module 12, its control terminal accesses the first clock signal SCK1, its first terminal accesses the first power supply signal VGL, and its second terminal is electrically connected to the second control node N2.

[0034] For the clock writing module 13, its control terminal is electrically connected to the first control node N1, its first terminal accesses the first clock signal SCK1, and its second terminal is electrically connected to the third control node N3.

[0035] Exemplarily, the third control node N3 and the second control node N2 can be directly connected through a connection line. Or in other examples, other modules can also be provided to connect the third control node N3 and the second control node N2.

[0036] For the first adjustment module 14, its control terminal is connected to the second clock signal SCK2 and the third control node N3, its first terminal is connected to the second power supply signal VGH, and its second terminal is electrically connected to the first control node N1.

[0037] The clock writing module 13 and the first adjustment module 14 are modules for mutual control between the first control node N1 and the third control node N3, so as to avoid the timing of the first control node N1 and the third control node N3 from being disordered, thereby avoiding mis-conduction of the cascaded adjustment module and the output adjustment module, and ensuring the normal operation of the shift register. For example, when the first control node N1 is at a low level, the clock writing module 13 is turned on, and the first clock signal SCK1 is written to the third control node N3. For example, when the third control node N3 and the second clock signal SCK2 are at a low level, the first adjustment module 14 is turned on, and the second power supply signal VGH is written to the first control node N1, and the second power supply signal VGH can be a high-level signal.

[0038] For the cascaded adjustment module 15, its control terminal is electrically connected to the first control node N1 and the third control node N3, its first input terminal is connected to the second power supply signal VGH, and its second input terminal is connected to the second clock signal SCK2. It includes an adjusted cascaded output terminal Vout. In two mutually cascaded shift registers, the cascaded output terminal Vout of the upper-level shift register is electrically connected to the first terminal of the trigger writing module of the lower-level shift register.

[0039] Exemplarily, the cascaded adjustment module 15 can control the cascaded output terminal Vout to output the second clock signal SCK2 according to the signal on the first control node N1, and control the cascaded output terminal Vout to output the second power supply signal VGH according to the signal on the third control node N3. In the embodiments of the present application, the first power supply signal VGL can be a negative voltage signal, and the second power supply signal VGH is a positive voltage signal.

[0040] Compared with the related art in which the output terminal of the shift register is electrically connected to both the pixel circuit and the trigger signal terminal of the next-level shift register, an additional cascaded adjustment module is added in the embodiments of the present application. The output terminal of the cascaded adjustment module is no longer electrically connected to the pixel circuit, which can reduce the load of the cascaded adjustment module and is beneficial to the stability of the cascaded signal.

[0041] For the output adjustment module 16, its control terminal is electrically connected to the third control node N3 and the cascaded output terminal Vout, and its control terminal receives the first control signal SW1, its first input terminal receives the third clock signal SCK3, its second input terminal receives the fourth power supply signal VDD, its third input terminal receives the third power supply signal VDDL or the fourth clock signal SCK4, and it includes a scan output terminal Scan. The scan signal output by the scan output terminal Scan is used to drive the pixel circuit.

[0042] Exemplarily, the output adjustment module 16 can control the scan output terminal Scan to output the third clock signal SCK3 according to the signal on the cascaded output terminal Vout, control the scan output terminal Scan to output the fourth power supply signal VDD according to the signal on the third control node N3, and control the scan output terminal Scan to output the third power supply signal VDDL or the fourth clock signal SCK4 according to the first control signal SW1. In the embodiment of the present application, the third power supply signal VDDL can be a negative voltage signal, and the fourth power supply signal VDD is a positive voltage signal.

[0043] Since the refresh period of the third clock signal SCK3 is relatively small, under the coordinated control of the third control node N3, the cascaded output terminal Vout, and the first control signal SW1, the scan output terminal Scan can output a signal including multiple pulses of the third clock signal SCK3 within one period (i.e., within one frame), that is, the shift register can output a multi-pulse scan signal to meet the requirements of the pixel circuit for complex pulses.

[0044] In addition, taking the transistor of the pixel circuit being turned on under the control of a low-level scan signal and the third power supply signal VDDL being a low-level signal as an example, under the coordinated control of the third control node N3, the cascaded output terminal Vout, and the first control signal SW1, the scan output terminal Scan can output the third power supply signal VDDL for a relatively long period within one period (i.e., within one frame), that is, the shift register can output a conduction pulse with a relatively long duration to meet the requirements of the pixel circuit for a long conduction pulse.

[0045] In the embodiments of the present application, the shift register includes a trigger writing module, a power writing module, a clock writing module, a first adjustment module, a cascade adjustment module, and an output adjustment module. Through the coordinated control of the trigger writing module, the power writing module, the clock writing module, and the first adjustment module, the cascade adjustment module can be enabled to output a signal for triggering the next-stage shift register. Compared with the related art where the output end of the shift register is electrically connected to both the pixel circuit and the trigger signal end of the next-stage shift register, an additional cascade adjustment module is added in the embodiments of the present application. The output end of the cascade adjustment module is no longer electrically connected to the pixel circuit, which can reduce the load of the cascade adjustment module and is beneficial to the stability of the cascade signal. In addition, through the coordinated control of the trigger writing module, the power writing module, the clock writing module, the first adjustment module, and the cascade adjustment module, the output adjustment module can be enabled to output a signal including multiple pulses of the third clock signal within one frame, that is, the shift register can output a multi-pulse scan signal to meet the requirements of the pixel circuit for complex pulses.

[0046] In some embodiments, as Figure 2 shown, the shift register further includes a second adjustment module 17. The second adjustment module 17 is configured to write the signal of the second control node N2 or the second power supply signal VGH to the third control node N3 according to the first control signal SW1 and the second control signal SW2.

[0047] For example, when the second control signal SW2 is at a low level, the second adjustment module 17 transmits the signal of the second control node N2 to the third control node N3; when the first control signal SW1 is at a low level, the second adjustment module 17 transmits the second power supply signal VGH to the third control node N3.

[0048] In the embodiments of the present application, adding the second adjustment module 17 to control the third control node N3 means that there are more modules to control the potential of the third control node N3, which is beneficial to preventing the third control node N3 from floating, thereby improving the reliability of the shift register; in addition, adding the first control signal SW1 and the second control signal SW2 to control the second adjustment module 17 can make the timing more flexible, so that it is easier to complicate the waveform of the scan signal output by the shift register.

[0049] Exemplarily, within one frame, the first control signals SW1 accessed by multiple shift registers are the same. That is to say, the first control signal SW1 is a global signal.

[0050] Exemplarily, within one frame, the second control signals SW2 accessed by multiple shift registers are the same. That is to say, the second control signal SW2 is a global signal.

[0051] It is understandable that the timings of the first control signal SW1 and the second control signal SW2 are different. As an example, the first control signal SW1 and the second control signal SW2 are inverted signals, that is, when the first control signal SW1 is at a high level, the second control signal SW2 is at a low level; conversely, when the first control signal SW1 is at a low level, the second control signal SW2 is at a high level.

[0052] In some embodiments, as Figure 3 shown, the shift register further includes a third adjustment module 18, and the third adjustment module 18 is configured to write the second power supply signal VGH to the cascaded output terminal Vout according to the first control signal SW1.

[0053] For example, when the first control signal SW1 is at a low level, the third adjustment module 18 transmits the second power supply signal VGH to the cascaded output terminal Vout.

[0054] Exemplarily, the first control signal SW1 accessed by the third adjustment module 18, the second adjustment module 17, and the output adjustment module 16 is the same control signal.

[0055] In the embodiments of the present application, adding the third adjustment module 18 to control the cascaded output terminal Vout enables more modules to control the potential of the cascaded output terminal Vout, which is beneficial to preventing the cascaded output terminal Vout from floating, thereby improving the reliability of the shift register; in addition, adding the first control signal SW1 to control the third adjustment module 18 can make the timing more flexible, and thus it is easier to complicate the waveform of the scan signal output by the shift register.

[0056] In some embodiments, as Figure 4 shown, the shift register further includes a fourth adjustment module 19, and the fourth adjustment module 19 is configured to write the first power supply signal VGL to the second control node N2 according to the third adjustment signal SW3 and the second clock signal SCK2.

[0057] For example, when the third adjustment signal SW3 and the second clock signal SCK2 are at a low level, the fourth adjustment module 19 transmits the first power supply signal VGL to the second control node N2. When any one of the third adjustment signal SW3 and the second clock signal SCK2 is at a high level, the fourth adjustment module 19 is disconnected.

[0058] In the embodiments of the present application, a fourth adjustment module 19 is added to control the second control node N2. In this way, there are more modules to control the potential of the second control node N2, which is beneficial to preventing the second control node N2 from floating, thereby improving the reliability of the shift register. In addition, a new third control signal SW3 is added to control the fourth adjustment module 19, which can make the timing more flexible, and thus it is easier to complicate the waveform of the scan signal output by the shift register. Moreover, both the fourth adjustment module 19 and the power writing module 12 are connected to the first power signal VGL, so that the second control node N2 will not be connected to other power signals, making the output ability of the shift register stronger, which is beneficial to the stable light emission of the pixel.

[0059] Exemplarily, within one frame, the third control signals SW3 accessed by multiple shift registers are the same. That is to say, the third control signal SW3 is a global signal.

[0060] Exemplarily, the first control signal SW1, the second control signal SW2, and the third control signal SW3 are different control signals.

[0061] In some embodiments, as Figure 5 or Figure 6 shown, the output adjustment module 16 includes a first output sub-module 161, a second output sub-module 162, and a third output sub-module 163.

[0062] The first output sub-module 161, whose control end is electrically connected to the cascaded output end Vout, whose first end is connected to the third clock signal SCK3, and whose second end is electrically connected to the scan output end Scan;

[0063] The second output sub-module 162, whose control end is electrically connected to the third control node N3, whose first end is connected to the fourth power signal VDD, and whose second end is electrically connected to the scan output end Scan;

[0064] The third output sub-module 163, whose control end is connected to the first control signal SW1, whose first end is connected to the target signal, and whose second end is electrically connected to the scan output end Scan. As Figure 5 shown, the target signal includes the third power signal VDDL, or, as Figure 6 shown, the target signal includes the fourth clock signal SCK4.

[0065] Exemplarily, when the cascaded output end Vout is at a low level, the first output sub-module 161 is turned on, and the first output sub-module 161 transmits the third clock signal SCK3 to the scan output end Scan, that is, the scan output end Scan outputs the third clock signal SCK3.

[0066] When the third control node N3 is at a low level, the second output sub-module 162 is turned on, and the second output sub-module 162 transmits the fourth power signal VDD to the scan output terminal Scan. That is, the fourth power signal VDD is output at the scan output terminal Scan.

[0067] When the first control signal SW1 is at a low level, the third output sub-module 163 is turned on, and the third output sub-module 163 transmits the third power signal VDDL or the fourth clock signal SCK4 to the scan output terminal Scan. That is, the third power signal VDDL or the fourth clock signal SCK4 is output at the scan output terminal Scan.

[0068] Within the same stage, one of the first output sub-module 161, the second output sub-module 162, and the third output sub-module 163 is turned on, and the other two are turned off. The first output sub-module 161, the second output sub-module 162, and the third output sub-module 163 can be turned on in different stages.

[0069] The output adjustment module 16 needs to control the scan output terminal Scan to output three signals. In the embodiment of the present application, the output adjustment module includes three sub-modules, and the three sub-modules are respectively used to control the output of the three signals, so as to improve the accuracy of the signals output by the scan output terminal Scan.

[0070] In some embodiments, such as Figure 5 or Figure 6 As shown, the cascade adjustment module 15 includes a fourth sub-output module 151 and a fifth sub-output module 152.

[0071] The fourth sub-output module 151, its control end is electrically connected to the first control node N1, its first end accesses the second clock signal SCK2, and its second end is electrically connected to the cascade output terminal Vout;

[0072] The fifth sub-output module 152, its control end is electrically connected to the third control node N3, its first end accesses the second power signal VGH, and its second end is electrically connected to the cascade output terminal Vout.

[0073] Exemplarily, when the first control node N1 is at a low level, the fourth sub-output module 151 is turned on, and the fourth sub-output module 151 transmits the second clock signal SCK2 to the cascade output terminal Vout. That is, the second clock signal SCK2 is output at the cascade output terminal Vout.

[0074] When the third control node N3 is at a low level, the fifth sub-output module 152 is turned on, and the fifth sub-output module 152 transmits the second power signal VGH to the cascade output terminal Vout. That is, the second power signal VGH is output at the cascade output terminal Vout.

[0075] In addition, the third adjustment module 18 is also used to control the signal output from the cascaded output terminal Vout. For example, when the first control signal SW1 is at a low level, the third adjustment module 18 is turned on, and the third adjustment module 18 transmits the second power signal VGH to the cascaded output terminal Vout. That is, the signal output from the cascaded output terminal Vout is the second power signal VGH.

[0076] In the same stage, one of the fourth sub-output module 151 and the fifth sub-output module 152 is turned on, and the other is turned off. The fifth sub-output module 152 and the third adjustment module 18 can be turned on in different stages, or in other examples, in certain time periods, the fifth sub-output module 152 and the third adjustment module 18 can be turned on simultaneously. Since both transmit the second power signal VGH, even if both are turned on, it will not cause signal crosstalk.

[0077] The cascaded adjustment module 15 needs to control two signals output from the cascaded output terminal Vout. In the embodiment of the present application, the cascaded adjustment module includes two sub-modules, and the two sub-modules are respectively used to control the output of the two signals, which can improve the accuracy of the signal output from the cascaded output terminal.

[0078] In some embodiments, such as Figure 5 or Figure 6 as shown, the second adjustment module 17 includes a first sub-adjustment module 171 and a second sub-adjustment module 172.

[0079] The first sub-adjustment module 171, its control terminal is connected to the second control signal SW2, its first end is electrically connected to the second control node N2, and its second end is electrically connected to the third control node N3;

[0080] The second sub-adjustment module 172, its control terminal is connected to the first control signal SW1, its first end is connected to the second power signal VGH, and its second end is electrically connected to the third control node N3.

[0081] For example, when the second control signal SW2 is at a low level, the first sub-adjustment module 171 is turned on, and the first sub-adjustment module 171 transmits the signal of the second control node N2 to the third control node N3 to realize the writing of the first power signal VGL into the third control node N3.

[0082] When the first control signal SW1 is at a low level, the second sub-adjustment module 172 is turned on, and the second sub-adjustment module 172 transmits the second power signal VGH to the third control node N3 to maintain or change the potential of the third control node N3.

[0083] In the embodiment of the present application, by setting the second adjustment module 17 as two sub-modules, it is convenient to separately control the writing of the first power signal VGL or the second power signal 192 into the third control node N3.

[0084] In some embodiments, such as Figure 5 or Figure 6 as shown, the shift register further includes a fourth adjustment module 19, and the fourth adjustment module 19 includes a third sub - adjustment module 191 and a fourth sub - adjustment module 192.

[0085] The third sub - adjustment module 191, its control terminal is connected to the second clock signal SCK2, its first terminal is connected to the first power signal VGL, and its second terminal is electrically connected to the first terminal of the fourth sub - adjustment module 192;

[0086] The fourth sub - adjustment module 192, its control terminal is connected to the third control signal SW3, and its second terminal is electrically connected to the second control node N2.

[0087] For example, when the second clock signal SCK2 is at a low level, the third sub - adjustment module 191 is turned on, and the third sub - adjustment module 191 transmits the first power signal VGL to the first terminal of the fourth sub - adjustment module 192. When the third control signal SW3 is at a low level, the fourth sub - adjustment module 192 is turned on, and the fourth sub - adjustment module 192 transmits the signal at its first terminal to the second control node N2.

[0088] In the embodiments of the present application, the fourth adjustment module 19 includes two series - connected sub - modules, and the control signals of the two series - connected sub - modules are different, so that it is convenient to control both of the series - connected sub - modules to be turned on when needed, so as to realize writing the first power signal VGL to the second control node N2.

[0089] Exemplarily, each module or sub - module includes a transistor. For example, as Figure 5 or Figure 6 shown, the trigger writing module 11 includes a first transistor T1, the clock writing module 13 includes a second transistor T2, the first adjustment module 14 includes a third transistor T3 and a fourth transistor T4, the power writing module includes a fifth transistor T5, the fourth adjustment module 19 includes a sixth transistor T6 and a seventh transistor T7, the second adjustment module 18 includes an eighth transistor T8 and a ninth transistor T2, the cascaded adjustment module includes an eleventh transistor T11 and a twelfth transistor T12, the third adjustment module 18 includes a thirteenth transistor T13, and the output adjustment module 16 includes a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16. The connection relationships of each transistor can be seen in the circuit diagram and will not be elaborated here one by one.

[0090] Exemplarily, to reduce leakage current, at least some transistors can be set to include two series - connected sub - transistors. For example, both the first transistor T1 and the fifth transistor T5 are composed of two series - connected sub - transistors.

[0091] Exemplarily, the shift register may further include a tenth transistor T10. The gate of the eleventh transistor T11 is electrically connected to the first control node N1 through the tenth transistor T10. The tenth transistor T10 is a normally-open transistor, which can reduce the leakage current of the shift register and improve stability.

[0092] Exemplarily, the shift register further includes a first capacitor C1. One end of the first capacitor C1 is connected to the second power supply signal VGH, and the other end is electrically connected to the third control node N3. The first capacitor C1 can stabilize the potential of the third control node N3.

[0093] Exemplarily, the shift register further includes a second capacitor C2. One end of the second capacitor C2 is electrically connected to the gate of the eleventh transistor T11, and the other end is electrically connected to the cascaded output terminal Vout. The second capacitor C2 can couple the gate potential of the eleventh transistor T11 to a lower potential, so that the eleventh transistor T11 conducts more fully.

[0094] Figure 7 For Figure 5 the simulation timing diagram of a shown shift register. The following combines Figure 5 and Figure 7 to introduce an exemplary working process of the shift register. For ease of explanation, the connection node of the gate of the eleventh transistor T11 and the tenth transistor T10 is marked as the fourth control node N4. In addition, the following examples are described by taking each transistor as being turned on at a low level (the transistor is conducting when it is turned on) and turned off at a high level (the transistor is disconnected when it is turned off).

[0095] At stage t1, the first control signal SW1, the third control signal SW3, the trigger signal SIN, and the second clock signal SCK2 are at high level, the first clock signal SCK1 and the second control signal SW2 are at low level, and the third clock signal SCK3 is at a high-to-low transition level. At this stage, the potentials of the first control node N1 and the fourth control node N4 are equal to the potential of the second power supply signal VGH, the potential of the third control node N3 is equal to the difference between the first power supply signal VGL and the threshold voltage of the fifth transistor T5 (VGL - vth5), where vth5 represents the threshold voltage of the fifth transistor T5, and the potential of the second control node N2 is equal to the difference between the first power supply signal VGL and the threshold voltage of the fifth transistor T5 (VGL - vth5). It should be noted that the second control node N2 is coupled by the first clock signal SCK1, and the potential will even be lower. During this stage, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, and the cascaded output terminal Vout outputs the second power supply signal VGH. The fourteenth transistor T14 and the sixteenth transistor T16 are turned off, and the fifteenth transistor T15 is turned on, and the scan output terminal Scan outputs the fourth power supply signal VDD.

[0096] At stage t2, the first control signal SW1, the third control signal SW3, the trigger signal SIN, and the first clock signal SCK1 are at high level, the second clock signal SCK2 and the second control signal SW2 are at low level, the third clock signal SCK3 is at a level with high and low transitions. The potential of the second control node N2 is the same in stage t2 and stage t1, that is, the potential of the second control node N2 is equal to VGL - vth5. The states of transistors T11 to T16 are the same in stage t2 and stage t1. That is, in stage t2, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, and the cascade output terminal Vout outputs the second power supply signal VGH. The fourteenth transistor T14 and the sixteenth transistor T16 are turned off, the fifteenth transistor T15 is turned on, and the scan output terminal Scan outputs the fourth power supply signal VDD.

[0097] At stage t3, the first control signal SW1 is at low level, the second control signal SW2, the third control signal SW3, and the trigger signal SIN are at high level, the first clock signal SCK1, the second clock signal SCK2, and the third clock signal SCK3 are at levels with high and low transitions, and among them, the refresh frequency of the third clock signal SCK3 is large. The eighth transistor T8 is turned off, the second control node N2 is coupled by the first clock signal SCK1, and the voltage of the second control node N2 will fluctuate, but this has no impact on the shift register. The ninth transistor T9 is turned on, the potential of the third control node N3 becomes the potential of the second power supply signal VGH. The twelfth transistor T12 and the fifteenth transistor T15 are turned off, the potentials of the first control node N1 and the second control node N2 are equal to the potential of the second power supply signal VGH. The eleventh transistor T11 is turned off, but at this time the thirteenth transistor T13 is turned on, so the cascade output terminal Vout will not be floating, and the potential of the cascade output terminal Vout is equal to the potential of the second power supply signal VGH. The fourteenth transistor T14 is turned off, the sixteenth transistor T16 is turned on, and the potential of the scan output terminal Scan is equal to the potential of the third power supply signal VDDL.

[0098] At stage t4, the third control signal SW3 and the first clock signal SCK1 are at low level, the first control signal SW1, the second control signal SW2, the trigger signal SIN, and the second clock signal SCK2 are at high level, the third clock signal SCK3 is at a level with high and low transitions, the eighth transistor T8 is turned off, the second control node N4 is coupled by the first clock signal SCK1, the voltage of the second control node N4 is lower than that of the first power supply signal VGL, but it has no impact on the circuit. During this stage, the potential of the third control node N3 is equal to the difference between the first power supply signal VGL and the threshold voltage of the fifth transistor T5 (VGL - vth5), and the twelfth transistor T12 and the fifteenth transistor T15 are turned on. The potentials of the first control node N1 and the fourth control node N4 are equal to the potential of the second power supply signal VGH, the eleventh transistor T11 is turned off, the cascaded output terminal Vout outputs the second power supply signal VGH, the fourteenth transistor is turned off, and the scan output terminal Scan outputs the fourth power supply signal VDD.

[0099] At stage t5, the first control signal SW1, the third control signal SW3, and the second clock signal SCK2 are at high level, the second control signal SW2, the first clock signal SCK1, and the trigger signal SIN are at low level, the third clock signal SCK3 is at a level with high and low transitions, and the potentials of both the second control node N2 and the third control node N3 are equal to the difference between the first power supply signal VGL and the threshold voltage of the fifth transistor T5 (VGL - vth5), and the potentials of both the first control node N1 and the fourth control node N4 are equal to the difference between the first power supply signal VGL and the threshold voltage of the first transistor T1 (VGL - vth1), where vth1 represents the threshold voltage of the first transistor T1. The eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are turned on, the fourteenth transistor T14 and the sixteenth transistor T16 are turned off, the cascaded output terminal Vout outputs the second power supply signal VGH, and the scan output terminal Scan outputs the fourth power supply signal VDD.

[0100] At stage t6, the first control signal SW1, the third control signal SW3, the first clock signal SCK1, and the trigger signal SIN are at high level, the second control signal SW2 and the second clock signal SCK2 are at low level, the third clock signal SCK3 is at a level with high and low transitions. The potentials of the first control node N1 and the fourth control node N4 are both equal to the difference between the first power supply signal VGL and the threshold voltage of the first transistor T1 (VGL - vth1). The fourth control node N4 is coupled by the second capacitor C2, and the voltage of the fourth control node N4 is lower than the first power supply signal VGL. The eleventh transistor T11 is turned on, and the cascaded output terminal Vout outputs the low level of the second clock signal SCK2. The potentials of the second control node N2 and the third control node N3 are equal to the second power supply signal VGH. The twelfth transistor T12 and the fifteenth transistor T15 are turned off, and the fourteenth transistor T14 is turned on. The scan output terminal Scan outputs multiple pulses of the third clock signal SCK3.

[0101] Subsequently, stages t1 and t2 are repeated.

[0102] In some embodiments, as introduced above, the target signal includes the third power supply signal VDDL.

[0103] Exemplarily, the high levels of the first clock signal SCK1 and the second clock signal SCK2 are both equal to the second power supply signal VGH, and the low levels of the first clock signal SCK1 and the second clock signal SCK2 are both equal to the first power supply signal VGL. The high level of the third clock signal SCK3 is equal to the fourth power supply signal VDD, the low level of the third clock signal SCK3 is equal to the third power supply signal VDDL, the voltage of the third power supply signal VDDL is greater than the voltage of the first power supply signal VGL, and the voltage of the fourth power supply signal CDD is less than the voltage of the second power supply signal VGH. This embodiment can ensure that the third clock signal SCK3 can be output to the scan output terminal Scan through the fourteenth transistor T14.

[0104] In some embodiments, as Figure 7 shown, the scan signal output by the scan output terminal Scan includes a first conduction pulse p1 and a second conduction pulse p2, and the width of the first conduction pulse p1 is greater than the width of the second conduction pulse p2. Specifically, the scan output terminal Scan outputs the first conduction pulse p1 at stage t3, and the scan output terminal Scan outputs two second conduction pulses p2 at stage t6. In the embodiments of the present application, the conduction pulses are shown as low - level pulses for illustration.

[0105] In the embodiments of the present application, the shift register can output two types of pulses with unequal pulse widths, which can better meet the requirements of the pixel circuit for complex waveforms.

[0106] Exemplarily, within one frame, the number of the second conduction pulses p2 includes multiple.

[0107] For example, the relationship between the refresh periods of the third clock signal SCK3 and the first clock signal SCK1 can be adjusted to control the number of second conduction pulses p2 within one frame. For instance, if the refresh period of the first clock signal SCK1 is 3 times that of the third clock signal SCK3, the number of second conduction pulses p2 within one frame is 2. Another example is that if the refresh period of the first clock signal SCK1 is 4 times that of the third clock signal SCK3, the number of second conduction pulses p2 within one frame is 3. And so on.

[0108] Exemplarily, as Figure 8 shown, the gate driving circuit includes a plurality of cascaded shift registers. Scan1 represents the scan output terminal of the first-stage shift register, Scan2 represents the scan output terminal of the second-stage shift register, Scan3 represents the scan output terminal of the third-stage shift register, Scan4 represents the scan output terminal of the fourth-stage shift register, and so on.

[0109] As Figure 9 shown, the signal waveforms output from the scan output terminals of the first-stage shift register to the fourth-stage shift register are shown. Within one frame, the first conduction pulses output from the scan output terminal of the i-th stage shift register and the scan output terminal of the (i + 1)-th stage shift register overlap, and the second conduction pulses output are misaligned.

[0110] For example, the first conduction pulses of the scan output terminals Scan1 to Scan4 overlap in time, and the second conduction pulses of the scan output terminals Scan1 to Scan4 are sequential in time.

[0111] In some embodiments, as Figure 6 shown, the target signal includes a fourth clock signal SCK4; the conduction pulse of the fourth clock signal SCK4 overlaps in time with the longer conduction pulse output from the scan output terminal Sout. For example, Scan1 represents the scan output terminal of the first-stage shift register, Scan2 represents the scan output terminal of the second-stage shift register, Scan3 represents the scan output terminal of the third-stage shift register, Scan4 represents the scan output terminal of the fourth-stage shift register. The scan output terminals of each stage of shift register can output a longer conduction pulse and at least one shorter conduction pulse, and the conduction pulse of the fourth clock signal SCK4 overlaps in time with the longer conduction pulses output from the scan output terminals of each stage of shift register.

[0112] Exemplarily, the fourth clock signal SCK4 is a global signal, and the fourth clock signal SCK4 accessed by each stage of shift register is the same.

[0113] It should be noted that in the embodiments of the present application, P-type transistors are used for illustration. Those skilled in the art can make simple adjustments to the timing or circuit structure and replace the P-type transistors with N-type transistors. For N-type transistors, the conduction level is high level and the cut-off level is low level. That is, when the gate potential of the N-type transistor is high level, it conducts between its first pole and second pole; when the gate potential of the N-type transistor is low level, it turns off between its first pole and second pole. For P-type transistors, the conduction level is low level and the cut-off level is high level. That is, when the gate potential of the P-type transistor is low level, it conducts between its first pole and second pole; when the gate potential of the P-type transistor is high level, it turns off between its first pole and second pole. In specific implementation, the gate of each of the above transistors serves as its control pole. And according to the signal of the gate of each transistor and its type, its first pole can be used as the source pole and the second pole as the drain pole, or its first pole can be used as the drain pole and the second pole as the source pole, which is not distinguished here. In addition, the conduction level and cut-off level in the embodiments of the present application are both general references. The conduction level refers to any level that can make the transistor conduct, and the cut-off level refers to any level that can make the transistor cut off / turn off.

[0114] The present application also provides a display panel, including a pixel circuit and the gate driving circuit provided by the present application. Exemplarily, the display panel can be applied to mobile phones, wearable products, computers, televisions, in-vehicle display devices and other display devices with display functions. The present application does not make specific limitations in this regard. The display panel provided by the embodiments of the present application has the beneficial effects of the gate driving circuit provided by the embodiments of the present application. For the specific description of the gate driving circuit, reference can be made to the above embodiments. Details are not described again in this embodiment.

[0115] In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The purpose of selecting and specifically describing these embodiments in this specification is to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit, characterized in that: A plurality of cascaded shift registers are included, wherein the shift register comprises: A trigger writing module, used for writing a trigger signal into the first control node according to the first clock signal connected thereto; A power writing module, used for writing a first power signal into a second control node according to the first clock signal connected thereto; a clock writing module, configured to write the first clock signal into a third control node according to a signal on the first control node, wherein the third control node is electrically connected to the second control node; A first regulating module, configured to write a second power supply signal into the first control node according to a second clock signal and a signal on the third control node; a cascade adjustment module, configured to adjust the cascade output terminal to output the second power supply signal or the second clock signal according to the signals on the first control node and the third control node, wherein the cascade output terminal of the i-th stage shift register is electrically connected to the trigger writing module of the i+1-th stage shift register; an output regulating module, configured to regulate the scan output terminal to output a target signal or a fourth power signal or a third clock signal according to the third control node, the signal on the cascade output terminal and the first control signal, wherein the target signal includes the third power signal or the fourth clock signal, and the scan output terminal is configured to be electrically connected to a pixel circuit; The refresh period of the third clock signal is smaller than the refresh periods of the first clock signal and the second clock signal.

2. The shift register according to claim 1, characterized in that: The shift register further includes: a second regulating module, configured to write the signal of the second control node or the second power supply signal into a third control node according to the first control signal and the second control signal; Preferably, the first control signal connected to the plurality of shift registers is the same; Preferably, the second control signal connected to the plurality of shift registers is the same.

3. The shift register according to claim 1, wherein: The shift register further includes: A third regulating module is configured to write the second power supply signal into the cascade output terminal according to the first control signal.

4. The shift register according to claim 1, wherein: The shift register further includes: a fourth regulating module, configured to write the first power signal into the second control node according to a third regulating signal and the second clock signal; Preferably, the third control signal connected to the plurality of shift registers is the same.

5. The shift register according to any one of claims 1 to 4, characterized in that: The output regulation module comprises: A first output submodule, a control end of which is electrically connected to the cascade output end, a first end of which is connected to the third clock signal, and a second end of which is electrically connected to the scan output end; A second output submodule, a control end of which is electrically connected to the third control node, a first end of which is connected to the fourth power signal, and a second end of which is electrically connected to the scan output end; A third output submodule, a control end of which is connected to the first control signal, a first end of which is connected to the target signal, and a second end of which is electrically connected to the scan output end; Preferably, the cascade regulation module comprises: a fourth sub-output module, whose control end is electrically connected to the first control node, whose first end is connected to the second clock signal, and whose second end is electrically connected to the cascade output end; A fifth sub-output module, whose control end is electrically connected to the third control node, whose first end is connected to the second power supply signal, and whose second end is electrically connected to the cascade output end.

6. The shift register according to claim 2, characterized in that: The second adjustment module includes: a first sub-regulation module, a control end of which is connected to the second control signal, a first end of which is electrically connected to the second control node, and a second end of which is electrically connected to the third control node; a second sub-regulation module, a control end of which is connected to the first control signal, a first end of which is connected to the second power signal, and a second end of which is electrically connected to the third control node; Preferably, the shift register further includes a fourth regulating module, and the fourth regulating module includes: a third sub-regulating module, a control end of which is connected to the second clock signal, a first end of which is connected to the first power signal, and a second end of which is electrically connected to the first end of the fourth sub-regulating module; A fourth sub-regulation module, whose control end is connected to the third control signal, and whose second end is electrically connected to the second control node.

7. The shift register according to any one of claims 1 to 4, characterized in that: The target signal includes a third power signal; The high level of the third clock signal is equal to the fourth power signal, the low level of the third clock signal is equal to the third power signal, the voltage of the third power signal is greater than the voltage of the first power signal, and the voltage of the fourth power signal is less than the voltage of the second power signal.

8. The shift register according to any one of claims 1 to 4, characterized in that: The target signal includes a fourth clock signal, and an on pulse of the fourth clock signal and a longer on pulse outputted from the scan output terminal overlap in time.

9. The shift register according to any one of claims 1 to 4, characterized in that: The scanning signal outputted by the scanning output terminal includes a first conduction pulse and a second conduction pulse, and the width of the first conduction pulse is greater than the width of the second conduction pulse; Preferably, within one frame, the number of the second conduction pulses includes a plurality; Preferably, within one frame, the first conduction pulse outputted by the scan output terminal of the i-th stage shift register overlaps with the scan output terminal of the (i+1)-th stage shift register, and the second conduction pulse outputted is staggered.

10. A display panel, characterized in that: include: Pixel circuit; And a gate drive circuit according to any one of claims 1 to 9; The scan output end of the shift register in the gate driving circuit is electrically connected to the pixel circuit.

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