Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device; the display panel is configured by arranging a part of a first pull-up control module, a part of a first inversion module, a first negative bias prevention module and a first reset module along a second direction, arranging the first pull-up control module, the first inversion module, the first negative bias prevention module and the first reset module in a vertical direction, reducing the horizontal space occupied by the first pull-up control module, the first inversion module, the first negative bias prevention module and the first reset module, reducing the horizontal space occupied by the first type of gate circuit, and further reducing the space occupied by the gate drive circuit and the frame of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are widely used in various fields due to their advantages such as lightweight, wide viewing angle, low power consumption, fast response speed, low temperature resistance, high luminous efficiency, and the ability to fabricate flexible displays. Furthermore, to reduce the number of driver chips, decrease bezel size, and lower costs, gate driver circuits are often used instead of gate driver chips to drive the pixel circuits. Specifically, the gate driver circuit includes the gate circuit of the switching transistor that controls the pixel circuit. However, in the use of display devices, it has been found that the gate circuit of the switching transistor that controls the pixel circuit occupies a large space, resulting in a larger bezel size for the display device.

[0003] Therefore, current display devices suffer from a technical problem where the gate circuit of the switching transistor controlling the pixel circuit occupies a large space, resulting in a large bezel for the display device. Summary of the Invention

[0004] This application provides a display panel and a display device to solve the technical problem that current display devices have large bezels due to the large space occupied by the gate circuit of the switching transistor controlling the pixel circuit.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel comprising:

[0006] Multiple rows of pixels, each pixel including a light-emitting device and a pixel driving circuit including a switching transistor;

[0007] A multi-stage gate driving circuit is electrically connected to the corresponding pixel driving circuit. Each stage of the gate driving circuit includes a first type of gate circuit. The first signal output terminal of the first type of gate circuit is electrically connected to the switching transistor. The first type of gate circuit includes a first pull-up control module, a first pull-up module, a first pull-down module, a first pull-down sustaining module, a first inverting module, a first anti-negative bias module, and a first reset module. The first pull-up control module and the first pull-up module are electrically connected to the first pull-up node of the first type of gate circuit. The first pull-down module is electrically connected to the first pull-up node and the first signal output terminal of the first type of gate circuit at this stage. The first pull-down sustaining module is electrically connected between the first pull-up node and the first low-potential signal line of the display panel. The first inverting module is electrically connected to the first pull-up node, the first low-potential signal line, and the low-frequency signal line of the display panel. The first anti-negative bias module is electrically connected between the first high-potential signal line of the display panel and the first pull-up node. The first reset module is electrically connected between the first pull-up node and the first low-potential signal line.

[0008] The pixel driving circuit and the first type of gate circuit are arranged along a first direction, and a part of the first pull-up control module, a part of the first inverting module, the first anti-negative bias module and the first reset module are arranged along a second direction. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0009] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.

[0010] This application provides a display panel and a display device. The display panel arranges a portion of a first pull-up control module, a portion of a first inverting module, a first anti-negative bias module, and a first reset module along a second direction. By arranging the first pull-up control module, the first inverting module, the first anti-negative bias module, and the first reset module in a vertical space, the horizontal space occupied by the first pull-up control module, the first inverting module, the first anti-negative bias module, and the first reset module is reduced, thereby reducing the horizontal space occupied by the first type of gate circuit, and further reducing the space occupied by the gate driving circuit, thus reducing the bezel of the display panel. Attached Figure Description

[0011] Figure 1 This is a schematic diagram for comparison of display devices.

[0012] Figure 2 This is a plan view of the display panel provided in an embodiment of this application.

[0013] Figure 3This is a cross-sectional schematic diagram of the display panel provided in an embodiment of this application.

[0014] Figure 4 This is a circuit diagram of the pixel driving circuit provided in an embodiment of this application.

[0015] Figure 5 A circuit diagram of a first type of gate circuit provided for an embodiment of this application.

[0016] Figure 6 A circuit diagram of a second type of gate circuit provided for an embodiment of this application.

[0017] Figure 7 A circuit diagram of a third type of gate circuit provided for an embodiment of this application.

[0018] Figure 8 A stack-up diagram of the light-shielding layer, active layer, first gate layer, first source-drain layer and second source-drain layer of the display panel provided in the embodiments of this application.

[0019] Figure 9 for Figure 8 An exploded view of the light-shielding layer of the display panel.

[0020] Figure 10 for Figure 8 An exploded view of the active layer of the display panel.

[0021] Figure 11 for Figure 8 An exploded view of the first gate layer of the display panel.

[0022] Figure 12 for Figure 8 An exploded view of the first source-drain layer of the display panel.

[0023] Figure 13 for Figure 8 An exploded view of the second source-drain layer of the display panel.

[0024] Figure 14 for Figure 8 A stacked diagram of the light-shielding layer and active layer of the display panel.

[0025] Figure 15 for Figure 8 The stack-up diagram of the light-shielding layer, active layer and first gate layer of the display panel.

[0026] Figure 16 for Figure 8 The stack-up diagram of the light-shielding layer, active layer, first gate layer and first source-drain layer of the display panel.

[0027] Figure 17 for Figure 8The overlay diagram of the light-shielding layer and the first via of the display panel.

[0028] Figure 18 for Figure 8 The overlay diagram of the light-shielding layer and the first source / drain layer.

[0029] Figure 19 for Figure 8 The stack-up diagram of the first gate layer and the second via is shown.

[0030] Figure 20 for Figure 8 The stack-up diagram of the first gate layer and the first source / drain layer in the image.

[0031] Figure 21 for Figure 8 The stack-up diagram of the first source / drain layer and the third via in the image.

[0032] Figure 22 for Figure 8 The stack-up diagram of the first source / drain layer with the third and fourth vias.

[0033] Figure 23 for Figure 8 The stack-up diagram of the first source-drain layer and the second source-drain layer in the image.

[0034] Figure 24 for Figure 8 A partial enlarged view of the area corresponding to the first type of gate circuit in the display panel.

[0035] Figure 25 for Figure 24 An exploded view of the light-shielding layer of the display panel.

[0036] Figure 26 for Figure 24 An exploded view of the active layer of the display panel.

[0037] Figure 27 for Figure 24 An exploded view of the first gate layer of the display panel.

[0038] Figure 28 for Figure 24 An exploded view of the first source-drain layer of the display panel.

[0039] Figure 29 for Figure 24 An exploded view of the second source-drain layer of the display panel.

[0040] Figure 30 for Figure 8 A partial enlarged view of the area corresponding to the second type of gate circuit in the display panel.

[0041] Figure 31 for Figure 30 An exploded view of the light-shielding layer of the display panel.

[0042] Figure 32 for Figure 30 An exploded view of the active layer of the display panel.

[0043] Figure 33 for Figure 30 An exploded view of the first gate layer of the display panel.

[0044] Figure 34 for Figure 30 An exploded view of the first source-drain layer of the display panel.

[0045] Figure 35 for Figure 30 An exploded view of the second source-drain layer of the display panel.

[0046] Figure 36 for Figure 8 A magnified view of a portion of the area corresponding to the third type of gate circuit in the display panel.

[0047] Figure 37 for Figure 36 An exploded view of the light-shielding layer of the display panel.

[0048] Figure 38 for Figure 36 An exploded view of the active layer of the display panel.

[0049] Figure 39 for Figure 36 An exploded view of the first gate layer of the display panel.

[0050] Figure 40 for Figure 36 An exploded view of the first source-drain layer of the display panel.

[0051] Figure 41 for Figure 36 An exploded view of the second source-drain layer of the display panel. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0053] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "electrical connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0054] This application provides some comparative display devices to illustrate the principle behind the technical problems arising from the embodiments of this application. It should be understood that these comparative display devices cannot be considered as prior art in the embodiments of this application. For example... Figure 1 As shown, the comparison display device 1 includes a pixel circuit 11 and a gate circuit 12. The gate circuit 12 has a wiring region 121 and a transistor region 122. A signal trace 121a is set in the wiring region 121, and a thin-film transistor 122a is set in the transistor region 122. The gate circuit 12 operates normally by extending the signal trace 121a from the wiring region 121 to the transistor region 122 and connecting it to the corresponding transistor 122a. However, since the signal trace 121a is placed on the same layer as the source and drain of the transistor, in order to avoid short circuits between the unconnected signal traces and the source and drain of the transistor, the signal traces need to be spaced apart from the source and drain of the transistor. This results in the wiring region 121 and the transistor region 122 needing to be set separately. The wiring region 121 requires a large space, and when the signal trace 121a extends into the transistor region 122, each transistor needs to occupy more space to avoid the unconnected signal trace 121a, resulting in the gate circuit 12 occupying a large space. Therefore, current display devices suffer from a technical problem where the lateral space occupied by the thin-film transistor setting area and signal routing area in the gate drive circuit is relatively large, resulting in a large bezel for the display device.

[0055] This application provides a display panel and a display device to solve the above-mentioned technical problems.

[0056] This application embodiment addresses the problem that the wiring area and transistor area in a comparative display device need to be set up separately, resulting in a large space occupied by both the wiring area and the transistor area. By adjusting the setting position of the signal lines, the setting film layer of the signal lines, the arrangement of the signal lines, and / or adjusting the setting position of the transistors, the arrangement of the transistors, and the design of the transistor structure, the space occupied by the gate driving circuit 22 is reduced, and the bezel of the display panel 2 is reduced.

[0057] Figure 1 This is a schematic diagram for comparison of display devices. Figure 2 This is a plan view of the display panel provided in an embodiment of this application. Figure 3 This is a cross-sectional schematic diagram of the display panel provided in an embodiment of this application. Figure 4 This is a circuit diagram of the pixel driving circuit provided in an embodiment of this application. Figure 5 A circuit diagram of a first type of gate circuit provided for an embodiment of this application. Figure 6 A circuit diagram of a second type of gate circuit provided for an embodiment of this application. Figure 7 A circuit diagram of a third type of gate circuit provided for an embodiment of this application. Figure 8 A stack-up diagram of the light-shielding layer, active layer, first gate layer, first source-drain layer and second source-drain layer of the display panel provided in the embodiments of this application. Figure 9 for Figure 8 An exploded view of the light-shielding layer of the display panel. Figure 10 for Figure 8 An exploded view of the active layer of the display panel. Figure 11 for Figure 8 An exploded view of the first gate layer of the display panel.

[0058] Figure 12 for Figure 8 An exploded view of the first source-drain layer of the display panel. Figure 13 for Figure 8 An exploded view of the second source-drain layer of the display panel. Figure 14 for Figure 8 A stacked diagram of the light-shielding layer and active layer of the display panel. Figure 15 for Figure 8 The stack-up diagram of the light-shielding layer, active layer and first gate layer of the display panel. Figure 16 for Figure 8 The stack-up diagram of the light-shielding layer, active layer, first gate layer and first source-drain layer of the display panel. Figure 17 for Figure 8 The overlay diagram of the light-shielding layer and the first via of the display panel. Figure 18 for Figure 8 The overlay diagram of the light-shielding layer and the first source / drain layer. Figure 19 for Figure 8 The stack-up diagram of the first gate layer and the second via is shown. Figure 20 for Figure 8 The stack-up diagram of the first gate layer and the first source / drain layer in the image. Figure 21 for Figure 8 The stack-up diagram of the first source / drain layer and the third via in the image. Figure 22 for Figure 8 The stack-up diagram of the first source / drain layer with the third and fourth vias. Figure 23 for Figure 8 The stack-up diagram of the first source-drain layer and the second source-drain layer in the image. Figure 24for Figure 8 A partial enlarged view of the area corresponding to the first type of gate circuit in the display panel. Figure 25 for Figure 24 An exploded view of the light-shielding layer of the display panel. Figure 26 for Figure 24 An exploded view of the active layer of the display panel. Figure 27 for Figure 24 An exploded view of the first gate layer of the display panel. Figure 28 for Figure 24 An exploded view of the first source-drain layer of the display panel. Figure 29 for Figure 24 An exploded view of the second source-drain layer of the display panel. Figure 30 for Figure 8 A partial enlarged view of the area corresponding to the second type of gate circuit in the display panel. Figure 31 for Figure 30 An exploded view of the light-shielding layer of the display panel. Figure 32 for Figure 30 An exploded view of the active layer of the display panel. Figure 33 for Figure 30 An exploded view of the first gate layer of the display panel. Figure 34 for Figure 30 An exploded view of the first source-drain layer of the display panel. Figure 35 for Figure 30 An exploded view of the second source-drain layer of the display panel. Figure 36 for Figure 8 A magnified view of a portion of the area corresponding to the third type of gate circuit in the display panel. Figure 37 for Figure 36 An exploded view of the light-shielding layer of the display panel. Figure 38 for Figure 36 An exploded view of the active layer of the display panel. Figure 39 for Figure 36 An exploded view of the first gate layer of the display panel. Figure 40 for Figure 36 An exploded view of the first source-drain layer of the display panel. Figure 41 for Figure 36 An exploded view of the second source-drain layer of the display panel.

[0059] like Figure 2 As shown, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. The display area 201 is provided with a plurality of pixels 23. Each pixel 23 includes a light-emitting device (LED) and a pixel driving circuit 21 for driving the LED. The non-display area 202 is provided with a multi-level gate driving circuit 22. The multi-level gate driving circuit 22 can be arranged along the second direction Y. The gate driving circuit 22 outputs a scanning signal to the pixel driving circuit 21.

[0060] Specifically, such as Figure 2 As shown, the non-display area 202 can be arranged around the display area 201, but this embodiment is not limited to this. The non-display area 202 can be arranged on one side, two sides, or three sides of the display area 201, and the non-display area 202 can be bent to the back of the display area 201. The non-display area 202 may include an upper border area, a lower border area, a left border area, and a right border area. The gate driving circuit 22 can be arranged in the left border area and / or the right border area. The gate driving circuit 22 can be arranged along the first direction X on one side or both sides of the display area 201.

[0061] like Figure 3 As shown, as a specific structure of a display panel 2 in an embodiment of this application, the display panel 2 includes a substrate 211, a light-shielding layer 212, a buffer layer 213, a semiconductor layer 214, a first gate insulating layer 215, an active layer 216, a second gate insulating layer 217, a first gate layer 218, a third gate insulating layer 232, a second gate layer 225, a first interlayer insulating layer 219, a first source-drain layer 221, a passivation layer 222, a first planarization layer 224, a second source-drain layer 223, a second planarization layer 226, a third planarization layer 227, a pixel electrode layer 228, a first pixel definition layer 229, a second pixel definition layer 231, a light-emitting functional layer, and a common electrode layer, which are arranged sequentially.

[0062] Specifically, the material of semiconductor layer 214 includes oxide semiconductor, specifically metal oxide, and more specifically indium gallium zinc oxide.

[0063] Specifically, the material of the active layer 216 may include one of silicon semiconductor and oxide semiconductor, specifically low-temperature polycrystalline silicon or metal oxide, specifically Ln-IZO (indium zinc oxide doped with lanthanide elements) or IGZTO (indium gallium zinc tin oxide).

[0064] Specifically, such as Figure 3 As shown, Figure 3 The illustration shows that the display panel 2 includes a semiconductor layer 214 and an active layer 216, but the embodiments of this application are not limited to this, and the display panel 2 may include only one of the semiconductor layer 214 and the active layer 216.

[0065] Specifically, such as Figure 3 As shown, Figure 3 The illustration shows a display panel comprising two gate layers, but the embodiments of this application are not limited thereto; the display panel may include one gate layer or three gate layers.

[0066] Specifically, such as Figure 3 As shown, Figure 3The illustration shows a display panel 2 including a first source-drain layer 221 and a second source-drain layer 223, but the embodiments of this application are not limited thereto. The display panel 2 may include a first source-drain layer 221, a second source-drain layer 223 and a third source-drain layer.

[0067] Specifically, such as Figure 3 As shown, Figure 3 The light-shielding layer 212 is shown to be disposed only in the display area 201, but the embodiments of this application are not limited to this, and the light-shielding layer 212 may be disposed in the non-display area 202.

[0068] Specifically, such as Figure 3 As shown, Figure 3 The transistors in the display area 201 are shown to use semiconductor layer 214 as active parts, and the transistors in the non-display area 202 are shown to use active layer 216 as active parts. However, the embodiments of this application are not limited to this. Some transistors in the display area 201 may use semiconductor layer 214 as active parts, and some transistors in the display area 201 may use active layer 216 as active parts. Similarly, some transistors in the non-display area 202 may use semiconductor layer 214 as active parts, and some transistors in the non-display area 202 may use active layer 216 as active parts.

[0069] Specifically, such as Figure 3 As shown, Figure 3 The embodiment of this application uses an organic light-emitting diode display panel 2 as an example for illustration, but the embodiment is not limited to this. The display panel 2 can be a liquid crystal display panel 2 or other types of display panels 2.

[0070] Specifically, such as Figures 5 to 7 As shown, each gate drive circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c.

[0071] like Figures 2 to 41As shown, this application embodiment provides a display panel 2, which includes multiple rows of pixels 23 and multiple levels of gate driving circuits 22. Each pixel 23 includes a light-emitting device (LED) and a pixel driving circuit 21. The multiple levels of gate driving circuits 22 are electrically connected to the corresponding pixel driving circuits 21. Each level of the gate driving circuit 22 includes a first type of gate circuit 22a, a second type of gate circuit 22b, and a third type of gate circuit 22c disposed along a first direction X. The first type of gate circuit 22a is connected to at least a first clock signal line CKA, a second clock signal line CKB, a first high-potential signal line VGH1, and a first low-potential signal line VGH1. The high potential signal line VGL1, the second low potential signal line VGL2, the first reset control line VST1, and the low frequency signal line LC are electrically connected. The second type of gate circuit 22b is electrically connected to at least the first high potential signal line VGH1, the second low potential signal line VGL2, the third clock signal line CKC of the display panel, and the second reset control line VST2 of the display panel. The third type of gate circuit 22c is electrically connected to at least the first high potential signal line VGH1, the second high potential signal line VGH2, the second low potential signal line VGL2, and the third low potential signal line VGL3.

[0072] The display panel 2 further includes a substrate 211, an active layer 216, a first gate layer 218, a first source-drain layer 221, and a second source-drain layer 223, which are sequentially disposed thereon. At least one of the following is disposed on the second source-drain layer 223: the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC.

[0073] This application provides a display panel 2. By setting a first source-drain layer 221 and a second source-drain layer 223, at least one of the following is disposed in the second source-drain layer 223: a first clock signal line CKA, a second clock signal line CKB, a third clock signal line CKC, a first high-potential signal line VGH1, a second high-potential signal line VGH2, a first low-potential signal line VGL1, a second low-potential signal line VGL2, a third low-potential signal line VGL3, a first reset control line VST1, a second reset control line VST2, and a low-frequency signal line LC. This reduces the number of traces in the first source-drain layer, thereby reducing the lateral space occupied by the first source-drain layer, and further reducing the space occupied by the gate drive circuit, thus reducing the bezel of the display panel.

[0074] Specifically, compared to conventional display devices where the source, drain, and signal traces of transistors are formed in the first source-drain layer, where each signal trace, transistor source, and drain occupies lateral space, and where signal traces need to be wound to connect to the transistor source and drain, further occupying lateral space and resulting in a larger width of the first source-drain layer and consequently a larger bezel of the gate drive circuit, this embodiment reduces the number of traces in the first source-drain layer and the lateral space occupied by the first source-drain layer by placing at least some signal lines in the second source-drain layer. Furthermore, the signal lines in the second source-drain layer can overlap with the traces in the first source-drain layer or the source and drain of transistors in the thickness direction, reducing the space occupied by the connecting lines, the space occupied by the gate drive circuit, and the bezel of the display panel.

[0075] In some embodiments, such as Figures 8 to 23 As shown, at least one of the first reset control line VST1, the low-frequency signal line LC, the first clock signal line CKA, the second clock signal line CKB, the first low-potential signal line VGL1, and the second low-potential signal line VGL2 is disposed on the second source-drain layer 223. By disposing at least one of the first reset control line VST1, the low-frequency signal line LC, the first clock signal line CKA, the second clock signal line CKB, the first low-potential signal line VGL1, and the second low-potential signal line VGL2 on the second source-drain layer 223, the lateral space occupied by the signal lines electrically connected to the first type of gate circuit can be reduced, thereby reducing the bezel of the display panel.

[0076] Specifically, compared to the comparison display device where each signal line connected to the first type of gate circuit 22a needs to be set in the first source-drain layer and needs to extend from the wiring area to the transistor area, resulting in a large lateral space occupation, the embodiment of this application sets the signal lines connected to the first type of gate circuit 22a in the second source-drain layer, thereby reducing the width of the first source-drain layer and shortening the distance between the signal lines set in the second source-drain layer and the connected transistors, thereby reducing the space occupied by the connection lines, reducing the space occupied by the gate driving circuit, and reducing the bezel of the display panel.

[0077] In some embodiments, such as Figures 8 to 23 As shown, the first reset control line VST1 is disposed on the second source-drain layer 223. By disposing the first reset control line VST1 on the second source-drain layer 223, the first reset control line VST1 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate drive circuit 22 and reducing the bezel of the display panel.

[0078] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29 As shown, the first type of gate circuit 22a includes a first pull-up control module 311. The projection of the first reset control line VST1 onto the substrate 211 is spaced from the projection of the first pull-up control module 311 onto the substrate 211. By maintaining a gap between the projection of the first reset control line VST1 onto the substrate and the projection of the first pull-up control module 311 onto the substrate 211, the first reset control line VST1 does not affect the signal lines and transistor signals in the first type of gate circuit 22a, and space is reserved for other signal lines.

[0079] Specifically, the above embodiment is illustrated by the example that there is a gap between the projection of the first reset control line VST1 on the substrate 211 and the projection of the first pull-up control module 311 on the substrate 211. However, the embodiments of this application are not limited to this. The projection of the first reset control line VST1 on the substrate 211 may overlap with each module in the first type of gate circuit 22a. For example, the projection of the first reset control line VST1 on the substrate 211 may overlap with the projection of the first pull-up control module 311 on the substrate 211, or the projection of the first reset control line VST1 on the substrate 211 may overlap with the projection of the first reset module 317 on the substrate 211.

[0080] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29 As shown, the first type of gate circuit 22a includes a first reset module 317, which is electrically connected to the first reset control line VST1.

[0081] The first source-drain layer 221 includes a first source connection line LD1. The projection of the first reset control line VST1 onto the substrate 211 is spaced from the projection of the first reset module 317 onto the substrate 211. The first reset control line VST1 is connected to the first reset module 317 via the first source connection line LD1. By maintaining a gap between the projection of the first reset control line VST1 onto the substrate 211 and the projection of the first reset module 317 onto the substrate 211, the first reset control line VST1 does not affect the signal lines and transistor signals in the first type of gate circuit 22a, and space is reserved for other signal lines. Furthermore, the connection between the first reset control line VST1 and the first reset module 317 via the first source connection line LD1 ensures a normal connection between the first reset control line VST1 and the first reset module.

[0082] In some embodiments, such as Figures 8 to 23As shown, the low-frequency signal line LC is disposed on the second source-drain layer 223. By disposing the low-frequency signal line LC on the second source-drain layer 223, the low-frequency signal line LC does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0083] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29 As shown, the first type of gate circuit 22a includes a first inverting module 315, and the low-frequency signal line LC is electrically connected to the first inverting module 315; the projection of the low-frequency signal line LC on the substrate 211 overlaps with the projection of the first inverting module 315 on the substrate 211. By making the projection of the low-frequency signal line LC on the substrate 211 overlap with the projection of the first inverting module 315 on the substrate 211, the signal lines and transistor signals in the first type of gate circuit 22a are not affected, and space can be reserved for other signal lines.

[0084] In some embodiments, such as Figures 8 to 23 As shown, the first clock signal line CKA is disposed on the second source-drain layer 223. By disposing the first clock signal line CKA on the second source-drain layer 223, the first clock signal line CKA does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate drive circuit 22 and reducing the bezel of the display panel.

[0085] Specifically, it is understood that each clock signal line in the display panel 2 includes multiple clock lines. These multiple clock lines occupy a large space in the first source-drain layer. Furthermore, the multiple clock lines located outside the transistor region and extending into the transistor region to connect with the transistor will further occupy space, resulting in a large lateral space occupied by the gate drive circuit 22 and a large bezel of the display panel 2. In this embodiment, by setting the first clock signal line CKA in the second source-drain layer 223, the lateral space occupied by the clock signal line can be reduced, thereby reducing the bezel of the display panel 2.

[0086] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29As shown, the first type of gate circuit 22a includes a first pull-up control module 311, and the projection of the first clock signal line CKA on the substrate 211 overlaps with the projection of the first pull-up control module 311 on the substrate 211. By making the projection of the first clock signal line CKA on the substrate 211 overlap with the projection of the first pull-up control module 311 on the substrate 211, the first clock signal line does not need to occupy additional space, reducing the space occupied by the gate drive circuit and reducing the bezel of the display panel 2.

[0087] Specifically, such as Figures 8 to 23 , Figures 24 to 29 As shown, the first clock signal line CKA may include a first clock line CKA1, a first clock line CKA2, a first clock line CKA3, and a first clock line CKA4. These four first clock signal lines CKA are cyclically connected every four stages of the first type gate circuit 22a. For example, the first-stage first type gate circuit 22a to the fourth-stage first type gate circuit 22a are respectively connected to the first clock line CKA1, the first clock line CKA2, the first clock line CKA3, and the first clock line CKA4. The fifth-stage first type gate circuit 22a to the eighth-stage first type gate circuit 22a are respectively connected to the first clock line CKA1, the first clock line CKA2, the first clock line CKA3, and the first clock line CKA4. Similarly, the clock signal lines connected to the other stages of the first type gate circuit 22a can be determined.

[0088] Specifically, the first clock line 4 CKA4, the first clock line 3 CKA3, the first clock line 2 CKA2, and the first clock line 1 CKA1 are set sequentially along the first direction.

[0089] Specifically, the above embodiment is illustrated by taking the first clock signal line CKA as having four clock lines, but the embodiments of this application are not limited to this. The first clock signal line CKA may include other numbers of clock lines, such as eight clock lines.

[0090] Specifically, in each of the four stages of the first type gate circuit 22a, the connection point between each stage of the first type gate circuit 22a and the first clock signal line CKA is different.

[0091] In some embodiments, such as Figures 8 to 23 As shown, the second clock signal line CKB is disposed on the second source-drain layer 223. By disposing the second clock signal line CKB on the second source-drain layer 223, the second clock signal line CKB does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate drive circuit 22 and reducing the bezel of the display panel.

[0092] Specifically, it is understood that each clock signal line in the display panel 2 includes multiple clock lines. These multiple clock lines occupy a large space in the first source-drain layer. Furthermore, the multiple clock lines located outside the transistor region and extending into the transistor region to connect with the transistor will further occupy space, resulting in a large lateral space occupied by the gate drive circuit 22 and a large bezel of the display panel 2. In this embodiment, by setting the second clock signal line CKB in the second source-drain layer 223, the lateral space occupied by the clock signal line can be reduced, thereby reducing the bezel of the display panel 2.

[0093] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29 As shown, the first type of gate circuit 22a includes a first pull-up module 312, and the projection of the second clock signal line CKB on the substrate 211 overlaps with the projection of the first pull-up module 312 on the substrate 211. By making the projection of the second clock signal line CKB on the substrate 211 overlap with the projection of the first pull-up module 312 on the substrate 211, the second clock signal line CKB does not need to occupy additional space, and the second clock signal line is easy to connect to the first pull-up module 312, reducing the space occupied by the connection line, reducing the space occupied by the gate driving circuit, and reducing the bezel of the display panel 2.

[0094] Specifically, the second clock signal line CKB includes a first set of sub-lines CKBi and a second set of sub-lines CKBj. The projection of the first set of sub-lines CKBi on the substrate 211 overlaps with the projection of the first pull-up module 312 on the substrate 211.

[0095] Specifically, the second clock signal line CKB may include a second clock first line CKB1, a second clock second line CKB2, a second clock third line CKB3, a second clock fourth line CKB4, a second clock fifth line CKB5, a second clock sixth line CKB6, a second clock seventh line CKB7, and a second clock eighth line CKB8. The second clock first line CKB1, the second clock third line CKB3, the second clock fifth line CKB5, and the second clock seventh line CKB7 form the first group of sub-lines CKBi. The second clock second line CKB2, the second clock fourth line CKB4, the second clock sixth line CKB6, and the second clock eighth line CKB8 form the second group of sub-lines CKBj. The second pull-up transistor T22j of every four stages of the first-class gate circuit 22a is cyclically connected to the first group of sub-lines CKBi, and the third pull-up transistor T23j of every four stages of the first-class gate circuit 22a is cyclically connected to the second group of sub-lines CKBj. For example, the second pull-up transistors of the first-class gate circuit 22a to the fourth-class gate circuit 22a... Transistor T22j is connected to the first line of the second clock (CKB1), the third line of the second clock (CKB3), the fifth line of the second clock (CKB5), and the seventh line of the second clock (CKB7), respectively. The third pull-up transistors T23j of the first-stage first-type gate circuit 22a to the fourth-stage first-type gate circuit 22a are connected to the second line of the second clock (CKB2), the fourth line of the second clock (CKB4), the sixth line of the second clock (CKB6), and the eighth line of the second clock (CKB8), respectively. The second pull-up transistors T22j of the fifth-stage first-type gate circuit 22a to the eighth-stage first-type gate circuit 22a are connected to the first line of the second clock (CKB1), the third line of the second clock (CKB3), the fifth line of the second clock (CKB5), and the seventh line of the second clock (CKB7), respectively. The third pull-up transistors T23j of the fifth-stage first-type gate circuit 22a to the eighth-stage first-type gate circuit 22a are connected to the second line of the second clock (CKB2), the fourth line of the second clock (CKB4), the sixth line of the second clock (CKB6), and the eighth line of the second clock (CKB8), respectively. Similarly, the clock signal lines connected to the other stages of the first-type gate circuit 22a can be determined.

[0096] Specifically, the seventh line of the second clock (CKB7), the fifth line of the second clock (CKB5), the third line of the second clock (CKB3), and the first line of the second clock (CKB1) are set sequentially along the first direction.

[0097] Specifically, the eighth line of the second clock (CKB8), the sixth line of the second clock (CKB6), the fourth line of the second clock (CKB4), and the second line of the second clock (CKB2) are set sequentially along the first direction.

[0098] Specifically, the above embodiment is illustrated by taking the second clock signal line CKB as an example, which includes eight clock lines. However, the embodiments of this application are not limited to this. The second clock signal line CKB may include other numbers of clock lines, such as four clock lines or sixteen clock lines.

[0099] Specifically, in each of the four stages of the first type of gate circuit 22a, the connection point between the second pull-up transistor T22j and the first group of sub-lines CKBi is different.

[0100] Specifically, in each of the four stages of the first type gate circuit 22a, the connection point between the third pull-up transistor T23j and the second group of sub-lines CKBj is different.

[0101] In some embodiments, such as Figures 8 to 23 As shown, the first low-potential signal line VGL1 is disposed on the second source-drain layer 223. By disposing the first low-potential signal line VGL1 on the second source-drain layer 223, the first low-potential signal line VGL1 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0102] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29 As shown, the first type of gate circuit 22a includes a first inverting module 315 and a first pull-up module 312. The first inverting module 315 and the first pull-up module 312 are electrically connected to the first pull-up node Q1[n]. The projection of the first low-potential signal line VGL1 on the substrate 211 is located between the projection of the first inverting module 315 on the substrate 211 and the projection of the first pull-up module 312 on the substrate 211. By positioning the first low-potential signal line between the projection of the first inverting module 315 on the substrate 211 and the projection of the first pull-up module 312 on the substrate 211, the first low-potential signal line VGL1 does not require additional space, and the first low-potential signal line does not affect the normal operation of the first pull-up module.

[0103] In some embodiments, such as Figures 8 to 23 As shown, the second low-potential signal line VGL2 is disposed on the second source-drain layer 223. By disposing the second low-potential signal line VGL2 on the second source-drain layer 223, the second low-potential signal line VGL2 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0104] In some embodiments, such as Figure 5 , Figures 8 to 23 , Figures 24 to 29 As shown, the first type of gate circuit 22a includes a first pull-up module 312, and the projection of the second low-potential signal line VGL2 on the substrate 211 overlaps with the projection of the first pull-up module 312 on the substrate 211. By making the projection of the second low-potential signal line VGL2 on the substrate 211 overlap with the projection of the first pull-up module 312 on the substrate 211, the second low-potential signal line VGL2 does not need to occupy additional space, reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0105] In some embodiments, such as Figures 8 to 23 As shown, the second reset control line VST2 is disposed on the second source-drain layer 223. By disposing the second reset control line VST2 on the second source-drain layer 223, the second reset control line VST2 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate drive circuit 22 and reducing the bezel of the display panel.

[0106] In some embodiments, such as Figure 6 , Figures 8 to 23 , Figures 30 to 35 As shown, the second type of gate circuit 22b includes a second reset module 327, which is electrically connected to the second reset control line VST2. The projection of the second reset control line VST2 on the substrate 211 is located between the projection of the first type of gate circuit 22a on the substrate 211 and the projection of the second reset module 327 on the substrate 211. By positioning the projection of the second reset control line VST2 on the substrate 211 between the projection of the first type of gate circuit 22a on the substrate 211 and the projection of the second reset module 327 on the substrate 211, the second reset control line VST2 does not need to occupy additional lateral space, reducing the lateral space occupied by the gate drive circuit 22, reducing the bezel of the display panel, and the spacing between the second reset control line VST2 and the second reset module 327 is small. The length of the connection line between the second reset control line VST2 and the second reset module 327 is small or even unnecessary, further reducing the space occupied by the second reset control line VST2 and reducing the bezel of the display panel.

[0107] In some embodiments, such as Figures 8 to 23As shown, at least one of the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 is disposed on the second source-drain layer 223. By disposing at least one of the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 on the second source-drain layer 223, the lateral space occupied by the signal lines electrically connected to the gate drive circuit can be reduced, thereby reducing the bezel of the display panel.

[0108] Specifically, compared to the comparison display device where each signal line connected to the gate driving circuit needs to be placed in the first source-drain layer and needs to extend from the trace area to the transistor area, resulting in a large lateral space occupation, the embodiments of this application reduce the width of the first source-drain layer by placing the signal lines connected to the gate driving circuit in the second source-drain layer. Furthermore, the distance between the signal lines placed in the second source-drain layer and the connected transistors can be shortened, thereby reducing the space occupied by the connecting lines, reducing the space occupied by the gate driving circuit, and reducing the bezel of the display panel.

[0109] In some embodiments, such as Figures 8 to 23 As shown, the first high-potential signal line VGH1 is disposed on the second source-drain layer 223. By disposing the first high-potential signal line VGH1 on the second source-drain layer 223, the first high-potential signal line VGH1 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0110] In some embodiments, such as Figure 7 , Figures 8 to 23 , Figures 36 to 41 As shown, the third type of gate circuit 22c includes a third pull-up control module 331. The projection of the first high-potential signal line VGH1 on the substrate 211 overlaps with the projection of the third pull-up control module 331 on the substrate 211. By making the projection of the first high-potential signal line VGH1 on the substrate 211 overlap with the projection of the third pull-up control module 331 on the substrate 211, the first high-potential signal line VGH1 does not need to occupy additional space, reducing the lateral space occupied by the gate driving circuit 22, reducing the bezel of the display panel, and the first high-potential signal line VGH1 can be directly connected to the third pull-up control module, reducing the length of the connecting line, further reducing the occupied space, and reducing the bezel of the display panel.

[0111] In some embodiments, such as Figures 8 to 23As shown, the third clock signal line CKC is disposed on the second source-drain layer 223. By disposing the third clock signal line CKC on the second source-drain layer 223, the third clock signal line CKC does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate drive circuit 22 and reducing the bezel of the display panel.

[0112] Specifically, it is understood that each clock signal line in the display panel 2 includes multiple clock lines. These multiple clock lines occupy a large space in the first source-drain layer. Furthermore, the multiple clock lines located outside the transistor region and extending into the transistor region to connect with the transistors will further occupy space, resulting in a large lateral space occupied by the gate drive circuit 22 and a large bezel of the display panel 2. In this embodiment, by setting the third clock signal line CKC in the second source-drain layer 223, the lateral space occupied by the clock signal lines can be reduced, thereby reducing the bezel of the display panel 2.

[0113] In some embodiments, such as Figure 7 , Figures 8 to 23 , Figures 36 to 41 As shown, the third type of gate circuit 22c includes a third pull-up control module 331. The projection of the third clock signal line CKC on the substrate 211 overlaps with the projection of the third pull-up control module 331 on the substrate 211. By making the projection of the third clock signal line CKC on the substrate 211 overlap with the projection of the third pull-up control module 331 on the substrate 211, the first clock signal line does not need to occupy additional space, reducing the space occupied by the gate drive circuit and reducing the bezel of the display panel 2.

[0114] Specifically, the third clock signal line CKC may include the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3, and the third clock fourth line CKC4. These four third clock signal lines CKC are cyclically connected every four stages of the second-class gate circuit 22b. For example, the first-stage to fourth-stage second-class gate circuit 22b are respectively connected to the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3, and the third clock fourth line CKC4. The fifth-stage to eighth-stage second-class gate circuit 22b are respectively connected to the third clock first line CKC1, the third clock second line CKC2, the third clock third line CKC3, and the third clock fourth line CKC4. Similarly, the clock signal lines connected to other stages of the second-class gate circuit 22b can be determined.

[0115] Specifically, the third clock fourth line CKC4, the third clock third line CKC3, the third clock second line CKC2, and the third clock first line CKC1 are set sequentially along the first direction.

[0116] Specifically, the above embodiment is illustrated by taking the third clock signal line CKC as an example, which includes four clock lines. However, the embodiments of this application are not limited to this. The third clock signal line CKC may include other numbers of clock lines, such as eight clock lines.

[0117] Specifically, in each of the four stages of the second type gate circuit 22b, the connection point between each stage of the second type gate circuit 22b and the third clock signal line CKC is different.

[0118] In some embodiments, such as Figures 8 to 23 As shown, the second high-potential signal line VGH2 is disposed on the second source-drain layer 223. By disposing the second high-potential signal line VGH2 on the second source-drain layer 223, the second high-potential signal line VGH2 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0119] In some embodiments, such as Figure 7 , Figures 8 to 23 , Figures 36 to 41 As shown, the third type of gate circuit 22c includes a third pull-up module 332, which is electrically connected to the second high-potential signal line VGH2. The projection of the second high-potential signal line VGH2 on the substrate 211 overlaps with the projection of the third pull-up module 332 on the substrate 211. By making the projection of the second high-potential signal line VGH2 on the substrate 211 overlap with the projection of the third pull-up module 332 on the substrate 211, the second high-potential signal line VGH2 does not need to occupy additional space, reducing the space occupied by the gate drive circuit and reducing the bezel of the display panel 2. Furthermore, the second high-potential signal line VGH2 can be directly connected to the third pull-up module 332, shortening the length of the connection line or even eliminating the connection line, further reducing the space occupied by the second high-potential signal line VGH2 and reducing the bezel of the display panel.

[0120] In some embodiments, such as Figures 8 to 23 As shown, the third low-potential signal line VGL3 is disposed on the second source-drain layer 223. By disposing the third low-potential signal line VGL3 on the second source-drain layer 223, the third low-potential signal line VGL3 does not need to occupy the lateral space of the first source-drain layer 221, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel.

[0121] In some embodiments, such as Figure 7 , Figures 8 to 23 , Figures 36 to 41As shown, the third type of gate circuit 22c includes a third pull-down module 333, which is electrically connected to the third low-potential signal line VGL3. The projection of the third low-potential signal line VGL3 on the substrate 211 overlaps with the projection of the third pull-down module 333 on the substrate 211. By making the projection of the third low-potential signal line VGL3 on the substrate 211 overlap with the projection of the third pull-down module 333 on the substrate 211, the third low-potential signal line VGL3 does not need to occupy additional space, reducing the space occupied by the gate drive circuit and reducing the bezel of the display panel 2. Furthermore, the third low-potential signal line VGL3 can be directly connected to the third pull-down module 333, shortening the length of the connection line or even eliminating the connection line, further reducing the space occupied by the third low-potential signal line VGL3 and reducing the bezel of the display panel.

[0122] In some embodiments, such as Figures 8 to 23 As shown, the first clock signal line CKA, the second clock signal line CKB, the third clock signal line CKC, the first high-potential signal line VGH1, the second high-potential signal line VGH2, the first low-potential signal line VGL1, the second low-potential signal line VGL2, the third low-potential signal line VGL3, the first reset control line VST1, the second reset control line VST2, and the low-frequency signal line LC are all disposed on the second source-drain layer. By disposing these components on the second source-drain layer, the lateral space occupied by the gate drive circuit can be further reduced, thus reducing the bezel of the display panel.

[0123] Specifically, the second clock signal line CKB includes the first set of sub-lines CKBi and the second set of sub-lines CKBj.

[0124] Specifically, the first reset control line VST1, the low-frequency signal line LC, the first clock signal line CKA, the first low-potential signal line VGL1, the first group of sub-lines CKBi, the second low-potential signal line VGL2, the second reset control line VST2, the second group of sub-lines CKBj, the first high-potential signal line VGH1, the third clock signal line CKC, the second high-potential signal line VGH2, and the third low-potential signal line VGL3 are arranged along the first direction X.

[0125] In some embodiments, such as Figure 5As shown, the first type of gate circuit 22a includes a first pull-up module 312, and the second clock signal line CKB includes a first set of sub-lines CKBi and a second set of sub-lines CKBj. The first pull-up module 312 includes:

[0126] The first pull-up transistor T21j has its first electrode electrically connected to the first clock signal line CKA, and its second electrode electrically connected to the stage transmission signal terminal Cout[n] of the first type of gate circuit 22a of this stage.

[0127] The second pull-up transistor T22j has its first electrode electrically connected to the first group of sub-lines CKBi, and its second electrode electrically connected to the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a.

[0128] The third pull-up transistor T23j has its first electrode electrically connected to the second group of sub-lines CKBj, and its second electrode electrically connected to the first signal output terminal Gn[n] of the first-stage first-type gate circuit 22a. By making the first-stage first-type gate circuit 22a have the first signal output terminals of two-stage first-type gate circuits, the first-stage first-type gate circuit can occupy the space of two-stage first-type gate circuits, thereby shortening the lateral space occupied by the first-type gate circuit and reducing the bezel size.

[0129] Specifically, in the embodiments of this application, the first signal output terminal Gn[m] of another stage of the first type gate circuit 22a can be the first signal output terminal of the next few stages of the first type gate circuit 22a. For example, the first signal output terminal Gn[m] of another stage of the first type gate circuit 22a can be the first signal output terminal of the next stage of the first type gate circuit 22a. Taking n as 3 as an example, m can be 4. However, the embodiments of this application are not limited to this. The first signal output terminal Gn[m] of another stage of the first type gate circuit 22a can be the first signal output terminal of the next two stages of the first type gate circuit 22a or the first signal output terminal of other stages of the first type gate circuit 22a.

[0130] Specifically, it can be understood that, compared to the case where each stage of the first-class gate circuit in a comparative display device has only one first signal output terminal, and each stage of the first-class gate circuit is connected to a corresponding first signal output terminal, the first-class gate circuit in this embodiment has two first signal output terminals. Accordingly, the first-class gate circuit can be shortened by half. Correspondingly, the first signal output terminals connected to each first-class gate circuit can be arranged sequentially. For example, the two first signal output terminals of the first-stage first-class gate circuit can be regarded as the first signal output terminals of the first-stage first-class gate circuit and the second-stage first-class gate circuit in the comparative display device. Similarly, the first signal output terminals of other stages of the first-class gate circuit can be determined.

[0131] Specifically, the gate driving circuit includes multiple transistors (e.g., a first pull-up control transistor and a first pull-up transistor), and the pixel driving circuit includes multiple transistors (e.g., a driving transistor and a switching transistor).

[0132] In some embodiments, the mobility of at least one transistor in the gate driving circuit 22 is greater than the mobility of the transistor in the pixel driving circuit 21; thereby reducing the size of the transistor in the gate driving circuit, thereby reducing the space occupied by the gate driving circuit 22 and reducing the bezel.

[0133] Specifically, when the mobility of at least one transistor in the gate driving circuit 22 is greater than the mobility of the transistor in the pixel driving circuit 21, for example, the mobility of the first inverting transistor in the gate driving circuit 22 is greater than the mobility of the initialization transistor in the pixel driving circuit 21, the embodiments of this application are not limited to this. The mobility of other transistors in the gate driving circuit may be greater than the mobility of the transistors in the pixel driving circuit, or the mobility of multiple transistors in the gate driving circuit may be greater than the mobility of the transistors in the pixel driving circuit.

[0134] Specifically, the active parts of each transistor in the gate driving circuit can be made of the same material, and the active parts of each transistor in the pixel driving circuit can be made of the same material, and the mobility of the active parts of the transistors in the gate driving circuit can be greater than that of the active parts of the transistors in the pixel driving circuit.

[0135] Specifically, the mobility of the active part of the transistor in the gate driving circuit can be greater than 20. For example, the active part of each transistor in the gate driving circuit can be made of Ln-IZO (indium zinc oxide doped with lanthanide elements) or IGZTO (indium gallium zinc tin oxide), and the active part of the transistor in the pixel driving circuit can be made of indium gallium zinc oxide, so that the area of ​​the transistor in the gate driving circuit can be relatively small.

[0136] Specifically, in order to improve the performance of transistors, the area of ​​transistors is generally made larger. For example, when indium gallium zinc oxide is used as the active part material, the channel width of the transistor needs to be 1000 and the length is 5 to meet the electrical requirements of the transistor. In the embodiments of this application, by making the mobility of the transistor in the gate driving circuit greater than that of the transistor in the pixel driving circuit, the area of ​​the transistor can be reduced while still meeting the electrical requirements, reducing the area occupied by the transistor and reducing the bezel of the display panel.

[0137] Meanwhile, to more clearly illustrate the structure of each film layer of the display panel, [the following is provided] Figures 9 to 13 ,like Figure 9 As shown, the positions of each structure within the light-shielding layer 212 and their relative positions can be observed; for example... Figure 10 As shown, the positions of each structure within the active layer 216 and their relative positions can be observed; for example... Figure 11 As shown, the positions of each structure within the first gate layer 218 and their relative positions can be observed; as... Figure 12 As shown, the positions of each structure within the first source / drain layer 221 and their relative positions can be observed; for example... Figure 13 As shown, the positions of each structure within the second source / drain layer 223 and their relative positions can be observed.

[0138] Meanwhile, to illustrate the correspondence between different film layers, the following is provided: Figures 14 to 23 ,like Figure 14 As shown, the relative positional relationship between the light-shielding layer 212 and the active layer 216 can be seen; as Figure 15 As shown, the relative positional relationship between the light-shielding layer 212, the active layer 216, and the first gate layer 218 can be seen; Figure 16 As shown, the relative positions of the light-shielding layer 212, the active layer 216, the first gate layer 218, and the first source / drain layer 221 can be observed; Figure 8 As shown, the relative positions of the light-shielding layer 212, the active layer 216, the first gate layer 218, the first source / drain layer 221, and the second source / drain layer 223 can be observed; Figure 17 As shown, the relative positional relationship between the light-shielding layer 212 and the first via 411 can be seen. The first via 411 refers to the via connecting the first source / drain layer 221 and the light-shielding layer 212, including the via of the buffer layer 213; as shown... Figure 18 As shown, the relative positional relationship between the light-shielding layer 212 and the first source / drain layer 221, and their connection points, can be observed; Figure 19 As shown, the relative positions of the first gate layer 218 and the second via 412 can be seen. The second via 412 refers to the via between the first interlayer insulating layer 219 and the third gate insulating layer 232; as shown... Figure 20 As shown, the relative positions of the first gate layer 218 and the first source / drain layer 221, and their connections, can be observed; Figure 21 As shown, the relative positions of the first source / drain layer 221 and the third via 413 can be seen. The third via 413 refers to the via of the passivation layer 222; as shown... Figure 22 As shown, the relative positions of the first source / drain layer 221, the third via 413, and the fourth via 414 can be seen. The fourth via 414 refers to the via of the first planarization layer 224; as shown... Figure 23 As shown, the relative positions of the first source-drain layer 221 and the second source-drain layer 223 and their connection points can be seen.

[0139] This application addresses the technical problem that current display devices have large bezels due to the large space occupied by the gate circuit of the switching transistor controlling the pixel circuit. It provides some display panels to alleviate the above-mentioned technical problem.

[0140] Specifically, in some comparative display devices, the gate circuit of the switching transistor controlling the pixel circuit includes multiple transistors, each arranged laterally. This results in a large space occupied by each transistor, leading to a large space occupied by the gate circuit of the switching transistor controlling the pixel circuit, and consequently, a large bezel of the display panel. This application provides embodiments that, through designing the arrangement of transistors and wiring in the first type of gate circuit, reduce the space occupied by the first type of gate circuit and thus reduce the bezel of the display panel.

[0141] In some embodiments, the display panel 2 includes multiple rows of pixels 23 and multiple levels of gate driving circuits 22. Each pixel 23 includes a light-emitting device (LED) and a pixel driving circuit 21. Each pixel driving circuit 21 includes a switching transistor (T2). The multiple levels of gate driving circuits 22 are electrically connected to their respective pixel driving circuits 21. Each level of gate driving circuit 22 includes a first type of gate circuit 22a. The first signal output terminal of the first type of gate circuit 22a is electrically connected to the switching transistor (T2). The pixel driving circuits and the first type of gate circuits are arranged along a first direction.

[0142] In some embodiments, such as Figure 5As shown, the first type of gate circuit 22a includes a first pull-up control module 311, a first pull-up module 312, a first pull-down module 313, a first pull-down sustaining module 314, a first inverting module 315, a first negative bias protection module 316, and a first reset module 317. The first pull-up control module 311 and the first pull-up module 312 are electrically connected to the first pull-up node Q1[n] of the first type of gate circuit. The first pull-down module 313 is electrically connected to the first pull-up node Q1[n] and the first signal output terminal Gn[n] of the first type of gate circuit 22a. The first pull-down sustaining module 314 is also electrically connected to the first pull-up node Q1[n] and the first signal output terminal Gn[n] of the first type of gate circuit 22a. Module 314 is electrically connected between the first pull-up node Q1[n] and the first low-potential signal line VGL1 of the display panel; the first inverting module 315 is electrically connected to the first pull-up node Q1[n], the first low-potential signal line VGL1, and the low-frequency signal line LC of the display panel; the first anti-negative bias module 316 is electrically connected between the first high-potential signal line VGH1 of the display panel and the first pull-up node Q1[n]; and the first reset module 317 is electrically connected between the first pull-up node Q1[n] and the first low-potential signal line VGL1.

[0143] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down sustaining module 314, the first inverting module 315, the first anti-negative bias module 316, and the first reset module 317 are arranged along a second direction, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the first pull-up control module 311, the first pull-up module 312, the first pull-down module 313, the first pull-down sustaining module 314, the first inverting module 315, the first anti-negative bias module 316, and the first reset module 317 along the second direction, the lateral space occupied by the first type of gate circuit 22a can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel 2.

[0144] Specifically, compared to the horizontal arrangement of modules in a comparative display device, this embodiment of the application reduces the horizontal space occupied by the first type of gate circuit 22a, reduces the horizontal space occupied by the gate driving circuit 22, and reduces the bezel of the display panel 2 by arranging at least two modules in the first type of gate circuit 22a along the second direction.

[0145] In some embodiments, such as Figure 5 , Figure 24As shown, a portion of the first pull-up control module 311, a portion of the first inverting module 315, the first anti-negative bias module 316, and the first reset module 317 are arranged along the second direction Y. By arranging a portion of the first pull-up control module 311, a portion of the first inverting module 315, the first anti-negative bias module 316, and the first reset module 317 along the second direction Y, the lateral space occupied by the first pull-up control module 311, the first inverting module 315, the first anti-negative bias module 316, and the first reset module 317 can be reduced, the lateral space occupied by the first type of gate circuit 22a can be reduced, the lateral space occupied by the gate drive circuit 22 can be reduced, thereby reducing the bezel of the display panel 2.

[0146] This application provides a display panel that arranges a portion of a first pull-up control module, a portion of a first inverting module, a first anti-negative bias module, and a first reset module along a second direction. By arranging the first pull-up control module, the first inverting module, the first anti-negative bias module, and the first reset module in a vertical spatial arrangement, the horizontal space occupied by the first pull-up control module, the first inverting module, the first anti-negative bias module, and the first reset module is reduced, thereby reducing the horizontal space occupied by the first type of gate circuit, and further reducing the space occupied by the gate driving circuit, and reducing the bezel of the display panel.

[0147] Specifically, such as Figure 24 As shown, a portion of the first inverting module 315, the first reset module 317, the first anti-negative bias module 316, and a portion of the first pull-up control module 311 are arranged along the second direction.

[0148] In some embodiments, such as Figure 5 , Figure 24 As shown, another part of the first pull-up control module 311, another part of the first inverting module 315, and the first pull-down sustaining module 314 are arranged along the second direction Y. By arranging the other part of the first pull-up control module 311, the other part of the first inverting module 315, and the first pull-down sustaining module 314 along the second direction Y, the lateral space occupied by the first type of gate circuit 22a and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the bezel of the display panel 2.

[0149] Specifically, such as Figure 24 As shown, in the second direction Y, the other part of the first inverting module 315, the first pull-down sustaining module 314 and the first pull-up control module 311 are arranged in sequence, with the first pull-down sustaining module 314 located between the first inverting module 315 and the first pull-up control module 311.

[0150] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, another portion of the first pull-up control module 311, another portion of the first inverting module 315, and a portion of the first pull-down module 313 are arranged along the second direction Y, and the first reset module 317, the first pull-down holding module 314, and a portion of the first pull-down module 313 are arranged along the first direction X. By arranging another portion of the first pull-up control module 311, another portion of the first inverting module 315, and a portion of the first pull-down module 313 along the second direction Y, the lateral space occupied by the gate drive circuit 22 can be further reduced, thereby reducing the bezel of the display panel 2.

[0151] Specifically, such as Figure 24 As shown, another part of the first inverting module 315, a part of the first pull-down module 313, and another part of the first pull-up control module 311 are arranged sequentially along the second direction.

[0152] Specifically, such as Figure 24 As shown, a portion of the first inverter module 315 and a portion of the first pull-up control module 311 are arranged along the second direction, and another portion of the first inverter module 315 and another portion of the first pull-up control module 311 are arranged along the second direction.

[0153] In some embodiments, such as Figure 5 , Figure 24 As shown, a portion of the first pull-up module 312 and another portion of the first pull-down module 313 are arranged along the second direction Y. By arranging a portion of the first pull-up module 312 and another portion of the first pull-down module 313 along the second direction Y, the lateral space occupied by the gate drive circuit 22 can be further reduced, thereby reducing the bezel of the display panel 2.

[0154] Specifically, such as Figure 24 As shown, a portion of the first pull-up module 312 and another portion of the first pull-down module 313 are sequentially arranged along the second direction Y.

[0155] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first pull-up control module 311 includes a first pull-up control transistor T11j, a second pull-up control transistor T12j, and a third pull-up control transistor T81j. The gate T11jG of the first pull-up control transistor T11j is electrically connected to the stage output terminal Cout[n-2] of the two-stage first-type gate circuit 22a. The first electrode T11jS of the first pull-up control transistor T11j is electrically connected to the first high-potential signal line VGH1. The second electrode T11jD of the first pull-up control transistor T11j is electrically connected to the first electrode T12jS of the second pull-up control transistor T12j. The gate T12jG of T12j is electrically connected to the stage output terminal Cout[n-2] of the first type gate circuit 22a above. The second electrode T12jD of the second pull-up control transistor T12j is electrically connected to the first pull-up node Q1[n]. The gate T81jG of the third pull-up control transistor T81j is electrically connected to the first high-potential signal line VGH1. The first electrode T81jS of the third pull-up control transistor T81j is electrically connected to the first high-potential signal line VGH1. The second electrode T81jD of the third pull-up control transistor T81j is electrically connected to the second electrode T11jD of the first pull-up control transistor T11j.

[0156] In each stage of the gate drive circuit 22, the first pull-up control transistor T11j and the second pull-up control transistor T12j are arranged sequentially along the second direction, and the first pull-up control transistor T11j and the third pull-up control transistor T81j are arranged sequentially along the first direction. By arranging the first pull-up control transistor T11j and the second pull-up control transistor T12j sequentially along the second direction, the space occupied by the first pull-up control module 311 can be reduced, thereby reducing the bezel of the display panel 2.

[0157] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, the third pull-up control transistor T81j includes a first pull-up control sub-transistor T81j1 and a second pull-up control sub-transistor T81j2. The gate T81j2G and the first electrode T81j2S of the second pull-up control sub-transistor T81j2 are electrically connected to the first high-potential signal line VGH1. The second electrode T81j2D of the second pull-up control sub-transistor T81j2 is electrically connected to the first electrode of the first pull-up control sub-transistor T81j1. The gate T81j1G of the first pull-up control sub-transistor T81j1 is electrically connected to the first high-potential signal line VGH1. The second electrode T81j1D of the first pull-up control sub-transistor T81j1 is electrically connected to the second electrode T11jD of the first pull-up control transistor T11j.

[0158] The first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 are arranged along the second direction. By including the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 in the third pull-up control transistor T81j, the performance of the third pull-up control transistor T81j can be improved. Furthermore, by arranging the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 along the first direction, the lateral area occupied by the third pull-up control transistor T81j can be reduced, thereby reducing the bezel of the display panel 2.

[0159] Specifically, the first pull-up control sub-transistor T81j1 and the second pull-up control sub-transistor T81j2 can be regarded as two independent transistors, or as two sub-transistors in the third pull-up control transistor T81j. Similarly, other sub-transistors can also refer to the above description, and will not be repeated in the following embodiments.

[0160] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected to the signal line. For example, the third pull-up control transistor T81j includes a first pull-up control sub-transistor T81j1 and a second pull-up control sub-transistor T81j2. Since the first electrode T81j2S of the second pull-up control sub-transistor T81j2 is electrically connected to the first high-potential signal line VGH1, the first electrode T81jS of the third pull-up control transistor T81j is the first electrode T81j2S of the second pull-up control sub-transistor T81j2. Similarly, the first electrodes of other transistors can be determined.

[0161] Specifically, the multi-level gate drive circuit 22 includes a multi-level first-type gate circuit 22a. In the first-level first-type gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j can be connected to the start signal line. In the other levels of the first-type gate circuit 22a, the gate T11jG of the first pull-up control transistor T11j and the gate T12jG of the second pull-up control transistor T12j are connected to the first signal output terminals of the two previous levels of the first-type gate circuit 22a. The first electrode T11jS of the first pull-up control transistor T11j and the first electrode T12jS of the second pull-up control transistor T12j are electrically connected to the first high-potential signal line VGH1.

[0162] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first pull-down module 313 includes a first pull-down transistor T31j, a second pull-down transistor T32j, a third pull-down transistor T33j, and a fourth pull-down transistor T41j. The gate T31jG of the first pull-down transistor T31j is electrically connected to the first pull-down node QB1[n] of the first type of gate circuit. The first electrode T31jS of the first pull-down transistor T31j is electrically connected to the first low-potential signal line VGL1. The second electrode T31jD of the first pull-down transistor T31j is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a of this stage. The gate T32jG of the second pull-down transistor T32j is electrically connected to the first pull-down node QB1[n]. The first electrode T32jS of the second pull-down transistor T32j is electrically connected to the second low-potential signal line VGL2 of the display panel. The second electrode T41j of the second pull-down transistor T32j is electrically connected to the first pull-down node QB1[n]. 32jD is electrically connected to the first signal output terminal Gn[m] of another first-class gate circuit 22a. The gate T33jG of the third pull-down transistor T33j is electrically connected to the first pull-down node QB1[n]. The first electrode T33jS of the third pull-down transistor T33j is electrically connected to the second low-potential signal line VGL2. The second electrode T33jD of the third pull-down transistor T33j is electrically connected to the first signal output terminal Gn[n] of the first-class gate circuit 22a of this stage. The gate T41jG of the fourth pull-down transistor T41j is electrically connected to the stage transmission output terminal Cout[n+2] of the next two first-class gate circuits 22a. The first electrode T41jS of the fourth pull-down transistor T41j is electrically connected to the first low-potential signal line VGL1. The second electrode T41jD of the fourth pull-down transistor T41j is electrically connected to the first pull-up node Q1[n].

[0163] The first pull-down transistor T31j and the fourth pull-down transistor T41j are arranged along the second direction, as are the second pull-down transistor T32j and the third pull-down transistor T33j. By arranging the first pull-down transistor T31j and the fourth pull-down transistor T41j, and the second pull-down transistor T32j and the third pull-down transistor T33j, along the second direction, the space occupied by the first pull-down module 313 can be reduced, and the bezel of the display panel 2 can be reduced.

[0164] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the fourth pull-down transistor T41j includes a first pull-down sub-transistor T41j1 and a second pull-down sub-transistor T41j2. The gate T41j2G of the second pull-down sub-transistor T41j2 is electrically connected to the stage transmission output terminal Cout[n+2] of the next two-stage first-type gate circuit 22a. The first electrode T41j2S of the second pull-down sub-transistor T41j2 is electrically connected to the first low-potential signal line VGL1. The second electrode T41j2D of the second pull-down sub-transistor T41j2 is electrically connected to the first electrode T41j1S of the first pull-down sub-transistor T41j1 at the first internal node N1[n]. The gate T41j1G of the first pull-down sub-transistor T41j1 is electrically connected to the stage transmission output terminal Cout[n+2] of the next two-stage first-type gate circuit 22a. The second electrode T41j1D of the first pull-down sub-transistor T41j1 is electrically connected to the first pull-up node Q1[n].

[0165] The first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 are arranged along the second direction. By including the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 in the fourth pull-down transistor T41j, the performance of the fourth pull-down transistor T41j can be improved. Furthermore, the arrangement of the first pull-down sub-transistor T41j1 and the second pull-down sub-transistor T41j2 along the second direction can reduce the lateral area occupied by the fourth pull-down transistor T41j, thereby reducing the bezel of the display panel 2.

[0166] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first inverting module 315 includes a first inverting transistor T51j, a second inverting transistor T52j, a third inverting transistor T53j, a fourth inverting transistor T54j, and a fifth inverting transistor T55j. The gate T51jG and the first electrode T51jS of the first inverting transistor T51j are electrically connected to the low-frequency signal line LC. The second electrode T51jD of the first inverting transistor T51j is electrically connected to the second electrode T52jD of the second inverting transistor T52j. The gate T52jG of the second inverting transistor T52j is electrically connected to the first pull-up node Q1[n]. The first electrode T52jS of the second inverting transistor T52j is electrically connected to the first low-potential signal line VGL1. The gate T53jG of the third inverting transistor T53j is electrically connected to the second electrode T51jD of the first inverting transistor T51j. One electrode T53jS is electrically connected to the low-frequency signal line LC; the second electrode T53jD of the third inverting transistor T53j is electrically connected to the first pull-down node QB1[n]; the gate T54jG of the fourth inverting transistor T54j is electrically connected to the first pull-up node Q1[n]; the first electrode T54jS of the fourth inverting transistor T54j is electrically connected to the first low-potential signal line VGL1; the second electrode T54jD of the fourth inverting transistor T54j is electrically connected to the first pull-down node QB1[n]; the gate T55jG of the fifth inverting transistor T55j is electrically connected to the stage transmission output terminal Cout[n-2] of the first two-stage first-type gate circuit 22a; the first electrode T55jS of the fifth inverting transistor T55j is electrically connected to the first low-potential signal line VGL1; and the second electrode T55jD of the fifth inverting transistor T55j is electrically connected to the first pull-down node QB1[n].

[0167] In this configuration, the first inverting transistor T51j and the second inverting transistor T52j are arranged along the second direction, the third inverting transistor T53j and the fourth inverting transistor T54j are arranged along the second direction, and the second inverting transistor T52j, the fourth inverting transistor T54j and the fifth inverting transistor T55j are arranged along the first direction. By arranging the first inverting transistor T51j and the second inverting transistor T52j along the second direction, and the third inverting transistor T53j and the fourth inverting transistor T54j along the second direction, the lateral space occupied by the first inverting module 315 can be reduced, thereby reducing the bezel of the display panel 2.

[0168] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first inverting transistor T51j includes a first inverting sub-transistor T51j1 and a second inverting sub-transistor T51j2. The gate T51j1G and the first electrode T51j1S of the first inverting sub-transistor T51j1 are electrically connected to the low-frequency signal line LC. The second electrode T51j1D of the first inverting sub-transistor T51j1 is electrically connected to the first electrode of the second inverting sub-transistor T51j2. The gate T51j2G of the second inverting sub-transistor T51j2 is electrically connected to the low-frequency signal line LC. The second electrode T51j2D of the second inverting sub-transistor T51j2 is electrically connected to the second electrode T52jD of the second inverting transistor T52j.

[0169] The first inverting sub-transistor T51j1 and the second inverting sub-transistor T51j2 are arranged along a first direction. By including the first inverting sub-transistor T51j1 and the second inverting sub-transistor T51j2 in the first inverting transistor T51j, the performance of the first inverting transistor T51j can be improved.

[0170] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, the first pull-down sustaining module 314 includes a first pull-down sustaining transistor T42j. The gate T42jG of the first pull-down sustaining transistor T42j is electrically connected to the first pull-down node QB1[n] of the first type of gate circuit. The first electrode T42jS of the first pull-down sustaining transistor T42j is electrically connected to the first low-potential signal line VGL1. The second electrode T42jD of the first pull-down sustaining transistor T42j is electrically connected to the first pull-up node Q1[n].

[0171] In the second direction, the first pull-down holding transistor T42j is disposed between the fourth inverting transistor T54j and the second pull-up control transistor T12j; thereby reducing the lateral space occupied by the first pull-down holding transistor T42j disposed between the fourth inverting transistor T54j and the second pull-up control transistor T12j, and reducing the bezel of the display panel 2.

[0172] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first pull-down sustaining transistor T42j includes a first pull-down sustaining sub-transistor T42j1 and a second pull-down sustaining sub-transistor T42j2. The gate T42j2G of the second pull-down sustaining sub-transistor T42j2 is electrically connected to the first pull-down node QB1[n]. The first electrode T42j2S of the second pull-down sustaining sub-transistor T42j2 is electrically connected to the first low-potential signal line VGL1. The second electrode T42j2D of the second pull-down sustaining sub-transistor T42j2 is electrically connected to the first electrode T42j1S of the first pull-down sustaining sub-transistor T42j1 at the first internal node N1[n]. The gate T42j1G of the first pull-down sustaining sub-transistor T42j1 is electrically connected to the first pull-down node QB1[n]. The second electrode of the first pull-down sustaining sub-transistor T42j1 is electrically connected to the first pull-up node Q1[n].

[0173] The first pull-down sustaining sub-transistor T42j1 and the second pull-down sustaining sub-transistor T42j2 are arranged along a second direction. By including the first pull-down sustaining sub-transistor T42j1 and the second pull-down sustaining sub-transistor T42j2 in the first pull-down sustaining transistor T42j, the performance of the first pull-down sustaining transistor T42j can be improved. Furthermore, the arrangement of the first pull-down sustaining sub-transistor T42j1 and the second pull-down sustaining sub-transistor T42j2 along the second direction can reduce the lateral space occupied by the first pull-down sustaining transistor T42j, thereby reducing the bezel of the display panel 2.

[0174] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, the first reset module 317 includes a first reset transistor T43j, the gate T43jG of the first reset transistor T43j is electrically connected to the first reset control line VST1 of the display panel, the first electrode T43jS of the first reset transistor T43j is electrically connected to the first low potential signal line VGL1, and the second electrode T43jD of the first reset transistor T43j is electrically connected to the first pull-up node Q1[n].

[0175] The first reset transistor T43j is disposed between the second inverter transistor T52j and the third pull-up control transistor T81j. By disposing the first reset transistor T43j between the second inverter transistor T52j and the third pull-up control transistor T81j, the lateral space occupied by the first reset transistor T43j, the second inverter transistor T52j, and the third pull-up control transistor T81j is reduced, thereby reducing the bezel of the display panel 2.

[0176] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first reset transistor T43j includes a first reset sub-transistor T43j1 and a second reset sub-transistor T43j2. The gate T43j1G of the second reset sub-transistor T43j2 is electrically connected to the first reset control line VST1. The first electrode of the second reset sub-transistor T43j2 is electrically connected to the first low-potential signal line VGL1. The second electrode T43j1D of the first reset sub-transistor T43j1 and the first electrode T43j1S of the first reset sub-transistor T43j1 are electrically connected to the first internal node N1[n]. The gate T43j1G of the first reset sub-transistor T43j1 is electrically connected to the first reset control line VST1. The second electrode T43j1D of the first reset sub-transistor T43j1 is electrically connected to the first pull-up node Q1[n].

[0177] The first reset transistor T43j1 and the second reset transistor T43j2 are arranged along the second direction. By including the first reset transistor T43j1 and the second reset transistor T43j2, the performance of the first reset transistor T43j can be improved. Furthermore, the arrangement of the first reset transistor T43j1 and the second reset transistor T43j2 along the second direction can reduce the lateral space occupied by the first reset transistor T43j and reduce the bezel of the display panel 2.

[0178] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, the first anti-negative bias module 316 includes a first anti-negative bias transistor T71j, the gate T71jG of the first anti-negative bias transistor T71j is electrically connected to the first pull-up node Q1[n], the first electrode T71jS of the first anti-negative bias transistor T71j is electrically connected to the first high-potential signal line VGH1, and the second electrode T71jD of the first anti-negative bias transistor T71j is electrically connected to the first internal node N1[n].

[0179] The first anti-negative bias transistor T71j is disposed along the second direction between the first reset transistor T43j and the third pull-up control transistor T81j. By disposing the first anti-negative bias transistor T71j along the second direction between the first reset transistor T43j and the third pull-up control transistor T81j, the lateral area occupied by the first anti-negative bias module 316 can be reduced, thus reducing the bezel of the display panel 2.

[0180] In some embodiments, such as Figure 5 , Figures 24 to 29As shown, the first anti-negative bias transistor T71j includes a first anti-negative bias sub-transistor T71j1 and a second anti-negative bias sub-transistor T71j2. The gate T71j2G of the second anti-negative bias sub-transistor T71j2 is electrically connected to the first pull-up node Q1[n]. The first electrode T71j2S of the second anti-negative bias sub-transistor T71j2 is electrically connected to the first high-potential signal line. The second electrode T71j2D of the second anti-negative bias sub-transistor T71j2 is electrically connected to the first electrode of the first anti-negative bias sub-transistor T71j1. The gate T71j1G of the first anti-negative bias sub-transistor T71j1 is electrically connected to the first pull-up node Q1[n]. The second electrode T71j1D of the first anti-negative bias sub-transistor T71j1 is electrically connected to the first internal node N1[n].

[0181] The first anti-negative bias transistor T71j1 and the second anti-negative bias transistor T71j2 are arranged along the second direction. By including the first anti-negative bias transistor T71j1 and the second anti-negative bias transistor T71j2 in the first anti-negative bias transistor T71j, the performance of the first anti-negative bias transistor T71j can be improved. Furthermore, the arrangement of the first anti-negative bias transistor T71j1 and the second anti-negative bias transistor T71j2 along the second direction can reduce the lateral space occupied by the first anti-negative bias transistor T71j and reduce the bezel of the display panel 2.

[0182] In some embodiments, such as Figure 5 , Figure 8 , Figures 24 to 29As shown, the second clock signal line CKB includes a first set of sub-lines CKBi and a second set of sub-lines CKBj. The first pull-up module 312 includes a first pull-up transistor T21j, a second pull-up transistor T22j, and a third pull-up transistor T23j. The gate T21jG of the first pull-up transistor T21j is electrically connected to the first pull-up node Q1[n]. The first electrode T21jS of the first pull-up transistor T21j is electrically connected to the first clock signal line CKA. The second electrode T21jD of the first pull-up transistor T21j is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a. The gate T22jG of the second pull-up transistor T22j is electrically connected to the first type of gate circuit 22a. A pull-up node Q1[n] is electrically connected; the first electrode T22jS of the second pull-up transistor T22j is electrically connected to the first group of sub-lines CKBi; the second electrode T22jD of the second pull-up transistor T22j is electrically connected to the first signal output terminal Gn[m] of another stage of the first type of gate circuit 22a; the gate T23jG of the third pull-up transistor T23j is electrically connected to the first pull-up node Q1[n]; the first electrode T23jS of the third pull-up transistor T23j is electrically connected to the second group of sub-lines CKBj; and the second electrode T23jD of the third pull-up transistor T23j is electrically connected to the first signal output terminal Gn[n] of the first type of gate circuit 22a of this stage.

[0183] In this configuration, the first pull-up transistor T21j and the second pull-down transistor T32j are arranged along the second direction Y, the second pull-up transistor T22j and the third pull-up transistor T23j are arranged along the second direction Y, and the first pull-up transistor T21j and the second pull-up transistor T22j are arranged along the first direction X. By arranging the first pull-up transistor T21j and the second pull-down transistor T32j along the second direction Y, and the second pull-up transistor T22j and the third pull-up transistor T23j along the second direction Y, the lateral area occupied by the first pull-down module and the first pull-up module can be reduced, thus reducing the bezel of the display panel 2.

[0184] In some embodiments, such as Figure 5 , Figures 24 to 29 As shown, the first inverting transistor T51j, the second inverting transistor T52j, the first reset transistor T43j, the first anti-negative bias transistor T71j, and the third pull-up control transistor T81j are arranged along the second direction Y.

[0185] The third inverting transistor T53j, the fourth inverting transistor T54j, the fourth pull-down transistor T42j, the second pull-up control transistor T12j, and the first pull-up control transistor T11j are arranged along the second direction;

[0186] The fifth inverting transistor T55j, the first pull-down transistor T31j, the fourth pull-down transistor T41j, the second pull-up control transistor T12j, and the first pull-up control transistor T11j are arranged along the second direction Y;

[0187] The second inverting transistor T52j, the fourth inverting transistor T54j, the fifth inverting transistor T55j, the first pull-up transistor T21j, and the second pull-up transistor T22j are arranged along the first direction X; this allows different transistors to be arranged along the second direction, reducing the lateral space occupied by the first type of gate circuit and reducing the bezel of the display panel.

[0188] In some embodiments, such as Figure 5 As shown, the first type of gate circuit 22a also includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the first pull-up node Q1[n], and the other plate of the first capacitor C1 is electrically connected to the stage output terminal Cout[n] of the first type of gate circuit 22a.

[0189] Specifically, the first capacitor includes a first plate and a second plate. The first plate of the first capacitor includes a first part of the first plate and a second part of the first plate.

[0190] In some embodiments, such as Figure 24 , Figure 25 As shown, the display panel 2 includes a light-shielding layer 212, which includes a first light-shielding connection line LS1, a second light-shielding connection line LS2, the stage transmission output terminal Cout[n] of the first type gate circuit 22a of this stage, and the first part C1a1 of the first plate C1a of the first capacitor C1.

[0191] In some embodiments, such as Figure 24 , Figure 26As shown, the display panel 2 includes an active layer 216, which includes the active portion T11jA of a first pull-up control transistor T11j, the active portion T12jA of a second pull-up control transistor T12j, the active portion T81jA of a third pull-up control transistor T81j, the active portion T21jA of a first pull-up transistor T21j, the active portion T22jA of a second pull-up transistor T22j, the active portion T23jA of a third pull-up transistor T23j, the active portion T31jA of a first pull-down transistor T31j, the active portion T32jA of a second pull-down transistor T32j, and a third pull-down transistor... The active portion T33jA of transistor T33j, the active portion T41jA of fourth pull-down transistor T41j, the active portion T42jA of first pull-down holding transistor T42j, the active portion T51jA of first inverting transistor T51j, the active portion T52jA of second inverting transistor T52j, the active portion T53jA of third inverting transistor T53j, the active portion T54jA of fourth inverting transistor T54j, the active portion T55jA of fifth inverting transistor T55j, the active portion T43jA of first reset transistor T43j, and the active portion T71jA of first anti-negative bias transistor T71j;

[0192] The active portion T51jA of the first inverting transistor T51j, the active portion T52jA of the second inverting transistor T52j, the active portion T43jA of the first reset transistor T43j, the active portion T71jA of the first anti-negative bias transistor T71j, and the active portion T81jA of the third pull-up control transistor T81j are arranged sequentially along the second direction Y.

[0193] The active portions T53jA of the third inverting transistor T53j, T54jA of the fourth inverting transistor T54j, T42jA of the first pull-down holding transistor T42j, T12jA of the second pull-up control transistor T12j, and T11jA of the first pull-up control transistor T11j are arranged sequentially along the second direction Y.

[0194] The active portion T55jA of the fifth inverting transistor T55j, the active portion T31jA of the first pull-down transistor T31j, the active portion T41jA of the fourth pull-down transistor T41j, the active portion T12jA of the second pull-up control transistor T12j, and the active portion T11jA of the first pull-up control transistor T11j are arranged sequentially along the second direction Y.

[0195] The active portion T21jA of the first pull-up transistor T21j, the active portion T33jA of the third pull-down transistor T33j, and the active portion T32jA of the second pull-down transistor T32j are arranged sequentially along the second direction;

[0196] The active portion T22jA of the second pull-up transistor T22j and the active portion T23jA of the third pull-up transistor T23j are arranged sequentially along the second direction;

[0197] The active portion T52jA of the second inverting transistor T52j, the active portion T54jA of the fourth inverting transistor T54j, the active portion T55jA of the fifth inverting transistor T55j, the active portion T21jA of the first pull-up transistor T21j, and the active portion T22jA of the second pull-up transistor T22j are arranged sequentially along the first direction.

[0198] Specifically, such as Figure 26 As shown, the active portion T81jA of the third pull-up control transistor T81j includes the active portion T81j1A of the first pull-up control sub-transistor T81j1 and the active portion T81j2A of the second pull-up control sub-transistor T81j2. The active portion T81j1A of the first pull-up control sub-transistor T81j1 and the active portion T81j2A of the second pull-up control sub-transistor T81j2 are arranged sequentially along the second direction.

[0199] Specifically, such as Figure 26 As shown, the active portion T41jA of the fourth pull-down transistor T41j includes the active portion T41j1A of the first pull-down sub-transistor T41j1 and the active portion T41j2A of the second pull-down sub-transistor T41j2, which are arranged along a second direction.

[0200] Specifically, such as Figure 26 As shown, the active portion T42jA of the first pull-down sustaining transistor T42j includes the active portion T42j1A of the first pull-down sustaining sub-transistor T42j1 and the active portion T42j2A of the second pull-down sustaining sub-transistor T42j2. The active portion T42j1A of the first pull-down sustaining sub-transistor T42j1 and the active portion T42j2A of the second pull-down sustaining sub-transistor T42j2 are arranged along a second direction.

[0201] Specifically, such as Figure 26 As shown, the active portion T43jA of the first reset transistor T43j includes the active portion T43j1A of the first reset sub-transistor T43j1 and the active portion T43j1A of the second reset sub-transistor T43j2. The active portions T43j1A of the first reset sub-transistor T43j1 and the active portions T43j1A of the second reset sub-transistor T43j2 are arranged along a second direction.

[0202] Specifically, such as Figure 26As shown, the active portion T51jA of the first inverting transistor T51j includes the active portion T51j1A of the first inverting sub-transistor T51j1 and the active portion T51j2A of the second inverting sub-transistor T51j2. The active portion T51j1A of the first inverting sub-transistor T51j1 and the active portion T51j2A of the second inverting sub-transistor T51j2 are arranged along a first direction.

[0203] Specifically, such as Figure 26 As shown, the active portion T71jA of the first anti-negative bias transistor T71j includes the active portion T71j1A of the first anti-negative bias transistor T71j1 and the active portion T71j2A of the second anti-negative bias transistor T71j2. The active portion T71j1A of the first anti-negative bias transistor T71j1 and the active portion T71j2A of the second anti-negative bias transistor T71j2 are arranged along a first direction.

[0204] In some embodiments, such as Figure 24 , Figure 27 As shown, the display panel 2 includes a first gate layer 218, which includes the gate T11jG of a first pull-up control transistor T11j, the gate T12jG of a second pull-up control transistor T12j, the gate T81jG of a third pull-up control transistor T81j, the gate T21jG of a first pull-up transistor T21j, the gate T22jG of a second pull-up transistor T22j, the gate T23jG of a third pull-up transistor T23j, the gate T31jG of a first pull-down transistor T31j, the gate T32jG of a second pull-down transistor T32j, and the gate of a third pull-down transistor T33j. T33jG, the gate of the fourth pull-down transistor T41j, the gate of the first pull-down holding transistor T42j, the gate of the first inverting transistor T51j, the gate of the second inverting transistor T52j, the gate of the third inverting transistor T53j, the gate of the fourth inverting transistor T54j, the gate of the fifth inverting transistor T55j, the gate of the first reset transistor T43j, the gate of the first anti-negative bias transistor T71j, the second plate C1b of the first capacitor C1, and the first gate connection line LE1;

[0205] The gates T51jG of the first inverting transistor T51j, T52jG of the second inverting transistor T52j, T43jG of the first reset transistor T43j, T71jG of the first anti-negative bias transistor T71j, and T81jG of the third pull-up control transistor T81j are arranged along the first direction Y.

[0206] The gates T53jG of the third inverting transistor T53j, T54jG of the fourth inverting transistor T54j, T42jG of the first pull-down holding transistor T42j, T12jG of the second pull-up control transistor T12j, and T11jG of the first pull-up control transistor T11j are arranged along the second direction Y.

[0207] The gate T55jG of the fifth inverting transistor T55j, the gate T31jG of the first pull-down transistor T31j, the gate T41jG of the fourth pull-down transistor T41j, the gate T12jG of the second pull-up control transistor T12j, and the gate T11jG of the first pull-up control transistor T11j are arranged along the second direction Y.

[0208] The gate T21jG of the first pull-up transistor T21j, a portion of the second plate C1b of the first capacitor C1, the gate T33jG of the third pull-down transistor T33j, and the gate T32jG of the second pull-down transistor T32j are sequentially arranged along the second direction Y.

[0209] The gates T22jG of the second pull-up transistor T22j and T23jG of the third pull-up transistor T23j are sequentially arranged along the second direction Y.

[0210] The gate T52jG of the second inverting transistor T52j, the gate T54jG of the fourth inverting transistor T54j, the gate T55jG of the fifth inverting transistor T55j, the gate T21jG of the first pull-up transistor T21j, another part of the second plate C1b of the first capacitor C1, and the gate T22jG of the second pull-up transistor T22j are arranged sequentially along the first direction X.

[0211] Specifically, such as Figure 27 As shown, the gate T81jG of the third pull-up control transistor T81j includes the gate T81j1G of the first pull-up control sub-transistor T81j1 and the gate T81j2G of the second pull-up control sub-transistor T81j2. The gate T81j1G of the first pull-up control sub-transistor T81j1 and the gate T81j2G of the second pull-up control sub-transistor T81j2 are arranged sequentially along the second direction.

[0212] Specifically, such as Figure 27 As shown, the gate T41jG of the fourth pull-down transistor T41j includes the gate T41j1G of the first pull-down sub-transistor T41j1 and the gate T41j2G of the second pull-down sub-transistor T41j2, and the gate T41j1G of the first pull-down sub-transistor T41j1 and the gate T41j2G of the second pull-down sub-transistor T41j2 are arranged along the second direction.

[0213] Specifically, such as Figure 27As shown, the gate T42jG of the first pull-down sustaining transistor T42j includes the gate T42j1G of the first pull-down sustaining sub-transistor T42j1 and the gate T42j2G of the second pull-down sustaining sub-transistor T42j2. The gate T42j1G of the first pull-down sustaining sub-transistor T42j1 and the gate T42j2G of the second pull-down sustaining sub-transistor T42j2 are arranged along a second direction.

[0214] Specifically, such as Figure 27 As shown, the gate T43jG of the first reset transistor T43j includes the gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2. The gate T43j1G of the first reset sub-transistor T43j1 and the gate T43j1G of the second reset sub-transistor T43j2 are arranged along a second direction.

[0215] Specifically, such as Figure 27 As shown, the gate T51jG of the first inverting transistor T51j includes the gate T51j1G of the first inverting sub-transistor T51j1 and the gate T51j2G of the second inverting sub-transistor T51j2. The gate T51j1G of the first inverting sub-transistor T51j1 and the gate T51j2G of the second inverting sub-transistor T51j2 are arranged along a first direction.

[0216] Specifically, such as Figure 27 As shown, the gate T71jG of the first anti-negative bias transistor T71j includes the gate T71j1G of the first anti-negative bias transistor T71j1 and the gate T71j2G of the second anti-negative bias transistor T71j2. The gate T71j1G of the first anti-negative bias transistor T71j1 and the gate T71j2G of the second anti-negative bias transistor T71j2 are arranged along a first direction.

[0217] In some embodiments, such as Figure 24 , Figure 28As shown, the display panel 2 includes a first source-drain layer 221, which includes the first electrode T11jS of the first pull-up control transistor T11j, the first electrode T12jS of the second pull-up control transistor T12j, the first electrode T81jS of the third pull-up control transistor T81j, the first electrode T21jS of the first pull-up transistor T21j, the first electrode T22jS of the second pull-up transistor T22j, the first electrode T23jS of the third pull-up transistor T23j, the first electrode T31jS of the first pull-down transistor T31j, the first electrode T32jS of the second pull-down transistor T32j, and the first electrode T33j of the third pull-down transistor T33j. The first electrode T33jS, the first electrode T41jS of the fourth pull-down transistor T41j, the first electrode T42jS of the first pull-down holding transistor T42j, the first electrode T51jS of the first inverting transistor T51j, the first electrode T52jS of the second inverting transistor T52j, the first electrode T53jS of the third inverting transistor T53j, the first electrode T54jS of the fourth inverting transistor T54j, the first electrode T55jS of the fifth inverting transistor T55j, the first electrode T43jS of the first reset transistor T43j, the first electrode T71jS of the first anti-negative bias transistor T71j, and the second electrode T of the first pull-up control transistor T11j 11jD, the second electrode of the second pull-up control transistor T12j, the second electrode of the third pull-up control transistor T81j, the second electrode of the first pull-up transistor T21j, the second electrode of the second pull-up transistor T22j, the second electrode of the third pull-up transistor T23j, the second electrode of the first pull-down transistor T31j, the second electrode of the second pull-down transistor T32j, the second electrode of the third pull-down transistor T33j, the second electrode of the fourth pull-down transistor T41j, and the second electrode of the first pull-down sustaining transistor T42j. The second electrode T51jD of the first inverting transistor T51j, the second electrode T52jD of the second inverting transistor T52j, the second electrode T53jD of the third inverting transistor T53j, the second electrode T54jD of the fourth inverting transistor T54j, the second electrode T55jD of the fifth inverting transistor T55j, the second electrode T43jD of the first reset transistor T43j, the second electrode T71jD of the first anti-negative bias transistor T71j, the second part C1a2 of the first plate C1a of the first capacitor C1, the first source connection line LD1, the second source connection line LD2, the third source connection line LD3, the fourth source connection line LD4, and the fifth source connection line LD5;

[0218] The first electrode T51jS of the first inverting transistor T51j, the first electrode T52jS of the second inverting transistor T52j, the first electrode T43jS of the first reset transistor T43j, the first electrode T71jS of the first anti-negative bias transistor T71j, and the first electrode T81jS of the third pull-up control transistor T81j are arranged sequentially along the second direction Y.

[0219] The first electrode T53jS of the third inverting transistor T53j, the first electrode T54jS of the fourth inverting transistor T54j, the first electrode T42jS of the first pull-down holding transistor T42j, the first electrode T12jS of the second pull-up control transistor T12j, and the first electrode T11jS of the first pull-up control transistor T11j are sequentially arranged along the second direction Y.

[0220] The first electrode T55jS of the fifth inverting transistor T55j, the first electrode T31jS of the first pull-down transistor T31j, the first electrode T41jS of the fourth pull-down transistor T41j, the first electrode T12jS of the second pull-up control transistor T12j, and the first electrode T11jS of the first pull-up control transistor T11j are sequentially arranged along the second direction Y.

[0221] The first electrode T21jS of the first pull-up transistor T21j, the first electrode T33jS of the third pull-down transistor T33j, and the first electrode T32jS of the second pull-down transistor T32j are sequentially arranged along the second direction Y.

[0222] The first electrode T22jS of the second pull-up transistor T22j and the first electrode T23jS of the third pull-up transistor T23j are sequentially arranged along the second direction Y.

[0223] The first electrode T52jS of the second inverting transistor T52j, the first electrode T54jS of the fourth inverting transistor T54j, the first electrode T55jS of the fifth inverting transistor T55j, the first electrode T21jS of the first pull-up transistor T21j, and the first electrode T22j of the second pull-up transistor T22j are arranged sequentially along the first direction.

[0224] The second source connection line LD2 connects the gate T55jG of the fifth inverting transistor T55j to the stage transmission signal terminal Cout[n-2] of the upper two-stage first-type gate circuit 22a. The third source connection line LD3 connects the gate T32jG of the second pull-down transistor T32j to the first shielding connection line LS1. The first shielding connection line LS1 connects the second electrode T55jD of the fifth inverting transistor T55j. The fourth source connection line LD4 connects the gate T41jG of the fourth pull-down transistor T41j to the stage transmission signal terminal Cout[n+2] of the lower two-stage first-type gate circuit 22a. The second shielding connection line LS2 connects the first electrode T55jS of the fourth inverting transistor T54j and the first electrode T31jS of the first pull-down transistor T31j.

[0225] Specifically, in the circuit diagrams of this application embodiment, to illustrate the connection relationship of each transistor, each transistor has a gate, a first electrode, and a second electrode. However, in actual design, to reduce the space occupied by the transistors, the electrodes of some transistors may be formed using the same structure. For example, the first electrode of the first pull-up control sub-transistor T81j1 and the second electrode T81j2D of the second pull-up control sub-transistor T81j2 may be formed using the same structure. Therefore, the second electrode T81j2D of the second pull-up control sub-transistor T81j2 can be identified in the diagram. It can be understood that this structure is also the first electrode of the first pull-up control sub-transistor T81j1. Similarly, the structure of the electrodes of other transistors can be determined.

[0226] Specifically, such as Figures 24 to 29 As shown, the first part C1a1 of the first plate C1a of the first capacitor C1 is connected to the second part C1a2 of the first plate C1a of the first capacitor C1.

[0227] Specifically, such as Figures 24 to 29 As shown, the first plate of the first capacitor C1 includes a first part of the first plate of the first capacitor C1 and a second part of the first plate of the first capacitor C1.

[0228] Specifically, such as Figure 28 As shown, the first source-drain layer 221 includes a first electrode of a first pull-up control sub-transistor T81j1, a second electrode of the first pull-up control sub-transistor T81j1 T81j1D, a first electrode of a second pull-up control sub-transistor T81j2 T81j2S, and a second electrode of the second pull-up control sub-transistor T81j2 T81j2D. The first electrode of the second pull-up control sub-transistor T81j2 T81j2S, the second electrode of the second pull-up control sub-transistor T81j2 T81j2D, and the second electrode of the first pull-up control sub-transistor T81j1 T81j1D are arranged sequentially along a second direction.

[0229] Specifically, such as Figure 28 As shown, the first source-drain layer 221 includes a first electrode T41j1S of the first pull-down sub-tube T41j1, a second electrode T41j1D of the first pull-down sub-tube T41j1, a first electrode T41j2S of the second pull-down sub-tube T41j2, and a second electrode T41j2D of the second pull-down sub-tube T41j2. The second electrode T41j2D of the second pull-down sub-tube T41j2, the first electrode T41j2S of the second pull-down sub-tube T41j2, and the second electrode T41j1D of the first pull-down sub-tube T41j1 are arranged sequentially along the second direction.

[0230] Specifically, such as Figure 28 As shown, the first source-drain layer 221 includes a first electrode T42j1S of the first pull-down sustaining sub-transistor T42j1, a second electrode of the first pull-down sustaining sub-transistor T42j1, a first electrode T42j2S of the second pull-down sustaining sub-transistor T42j2, and a second electrode T42j2D of the second pull-down sustaining sub-transistor T42j2. The second electrode T42j2D of the second pull-down sustaining sub-transistor T42j2, the first electrode T42j2S of the second pull-down sustaining sub-transistor T42j2, and the first electrode T42j1S of the first pull-down sustaining sub-transistor T42j1 are arranged sequentially along the second direction.

[0231] Specifically, such as Figure 28 As shown, the first source-drain layer 221 includes a first electrode T43j1S of the first reset transistor T43j1, a second electrode T43j1D of the first reset transistor T43j1, a first electrode of the second reset transistor T43j2, and a second electrode T43j1D of the second reset transistor T43j2. The second electrode T43j1D of the second reset transistor T43j2, the first electrode of the second reset transistor T43j2, and the second electrode T43j1D of the first reset transistor T43j1 are arranged sequentially along the second direction.

[0232] Specifically, such as Figure 28 As shown, the first source-drain layer 221 includes a first electrode T51j1S of the first inverting sub-transistor T51j1, a second electrode T51j1D of the first inverting sub-transistor T51j1, a first electrode of the second inverting sub-transistor T51j2, and a second electrode T51j2D of the second inverting sub-transistor T51j2. The first electrode T51j1S of the first inverting sub-transistor T51j1, the second electrode T51j1D of the first inverting sub-transistor T51j1, and the second electrode T51j2D of the second inverting sub-transistor T51j2 are arranged sequentially along a first direction.

[0233] Specifically, such as Figure 28As shown, the first source-drain layer 221 includes a first electrode of the first anti-negative bias transistor T71j1, a second electrode of the first anti-negative bias transistor T71j1 T71j1D, a first electrode of the second anti-negative bias transistor T71j2 T71j2S, and a second electrode of the second anti-negative bias transistor T71j2 T71j2D. The first electrode of the second anti-negative bias transistor T71j2 T71j2S, the second electrode of the second anti-negative bias transistor T71j2 T71j2D, and the second electrode of the first anti-negative bias transistor T71j1 T71j1D are arranged sequentially along a first direction.

[0234] In some embodiments, such as Figure 24 , Figure 29 As shown, the second clock signal line CKB includes a first set of sub-lines CKB1 and a second set of sub-lines CKBj. The display panel 2 includes a second source-drain layer 223, which includes a first reset control line VST1, a low-frequency control line LC, a first clock signal line CKA, a first low-potential signal line VGL1, a second clock signal line CKB, and a second low-potential signal line VGL2.

[0235] The first reset control line VST1, the low frequency control line LC, the first clock signal line CKA, the first low potential signal line VGL1, the first group of sub-lines CKBi, the second low potential signal line VGL2, and the second group of sub-lines CKBj are arranged along the first direction X;

[0236] The first reset control line VST1 is connected to the gate T43jG of the first reset transistor T43j through the first source connection line LD1. The second low-potential signal line VGL2 is connected to the first gate connection line LE1 through the fifth source connection line LD5. The first gate connection line LE1 is connected to the first electrode T32jS of the second pull-down transistor T32j.

[0237] In some embodiments, such as Figure 6 , Figure 30As shown, the second type of gate circuit 22b includes a second pull-up control module 321, a second pull-up module 322, a second pull-down module 323, a second pull-down sustaining module 324, a second inverting module 325, a second negative bias prevention module 326, and a second reset module 327. The second pull-up control module 321 and the second pull-up module 322 are electrically connected to the second pull-up node Q2[n]. The second pull-down module 323 is electrically connected to the second pull-up node Q2[n] and the second signal output terminal INI[n] of the second type of gate circuit 22b. The second pull-down sustaining module 324 is electrically connected between the second pull-up node Q2[n] and the second low-potential signal line VGL2; the second inverting module 325 is electrically connected to the second pull-up node Q2[n], the second low-potential signal line VGL2, and the low-frequency signal line LC; the second anti-negative bias module 326 is electrically connected between the first high-potential signal line VGH1 and the second pull-up node Q2[n]; and the second reset module 327 is electrically connected between the second pull-up node Q2[n] and the second low-potential signal line VGL2.

[0238] In some embodiments, such as Figure 6 , Figure 30 As shown, at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down sustaining module 324, the second inverting module 325, the second anti-negative bias module 326, and the second reset module 327 are arranged along a second direction, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the second pull-up control module 321, the second pull-up module 322, the second pull-down module 323, the second pull-down sustaining module 324, the second inverting module 325, the second anti-negative bias module 326, and the second reset module 327 along the second direction, the lateral space occupied by the second type of gate circuit 22b can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel 2.

[0239] Specifically, compared to the horizontal arrangement of modules in a comparative display device, this embodiment of the application reduces the horizontal space occupied by the second type of gate circuit 22b and the horizontal space occupied by the gate driving circuit 22 by arranging at least two modules in the second type of gate circuit 22b along the second direction, thereby reducing the bezel of the display panel 2.

[0240] In some embodiments, such as Figure 6 , Figure 30As shown, a portion of the second pull-up control module 321, a portion of the second inverting module 325, the second anti-negative bias module 326, and the second reset module 327 are arranged along the second direction Y. By arranging a portion of the second pull-up control module 321, a portion of the second inverting module 325, the second anti-negative bias module 326, and the second reset module 327 along the second direction Y, the lateral space occupied by the second pull-up control module 321, the second inverting module 325, the second anti-negative bias module 326, and the second reset module 327 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, the lateral space occupied by the gate drive circuit 22 can be reduced, thereby reducing the bezel of the display panel 2.

[0241] Specifically, such as Figure 30 As shown, in the second direction, a portion of the second inverting module 325, the second reset module 327, the second anti-negative bias module 326, and a portion of the second pull-up control module 321 are arranged along the second direction Y.

[0242] In some embodiments, such as Figure 6 , Figure 30 As shown, another part of the second pull-up control module 321, another part of the second inverting module 325, and the second pull-down sustaining module 324 are arranged along the second direction Y. By arranging the other part of the second pull-up control module 321, the other part of the second inverting module 325, and the second pull-down sustaining module 324 along the second direction Y, the lateral space occupied by the second pull-up control module 321, the second inverting module 325, and the second pull-down sustaining module 324 can be reduced, the lateral space occupied by the second type of gate circuit 22b can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the bezel of the display panel 2.

[0243] Specifically, such as Figure 30 As shown, another part of the second pull-up control module 321, the second pull-down maintenance module 324, and the other part of the second inverting module 325 are arranged sequentially along the second direction Y.

[0244] In some embodiments, such as Figure 6 , Figure 30 As shown, another part of the second pull-up control module 321, another part of the second inverting module 325, and the second pull-down module 323 are arranged along the second direction Y, and the second reset module 327, the second pull-down maintenance module 324, a part of the second pull-down module 323, and the second pull-up module 322 are arranged along the first direction X.

[0245] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second pull-up control module 321 includes a fourth pull-up control transistor T11i, a fifth pull-up control transistor T12i, and a sixth pull-up control transistor T81i. The gate T11iG of the fourth pull-up control transistor T11i is electrically connected to the second signal output terminal INI[n-2] of the upper two-stage second-type gate circuit 22b. The first electrode T11iS of the fourth pull-up control transistor T11i is electrically connected to the first high-potential signal line VGH1. The second electrode T11iD of the fourth pull-up control transistor T11i is electrically connected to the first electrode T12iS of the fifth pull-up control transistor T12i. The fifth pull-up control transistor... The gate T12iG of T12i is electrically connected to the second signal output terminal INI[n-2] of the second type gate circuit 22b of the two previous stages. The second electrode T12iD of the fifth pull-up control transistor T12i is electrically connected to the second pull-up node Q2[n]. The gate T81iG of the sixth pull-up control transistor T81i is electrically connected to the first high-potential signal line VGH1. The first electrode T81iS of the sixth pull-up control transistor T81i is electrically connected to the first high-potential signal line VGH1. The second electrode T81iD of the sixth pull-up control transistor T81i is electrically connected to the second electrode T11iD of the fourth pull-up control transistor T11i.

[0246] The fourth pull-up control transistor T11i and the fifth pull-up control transistor T12i are arranged along the second direction Y, and the sixth pull-up control transistor T81i is arranged along the first direction X. By arranging the fourth pull-up control transistor T11i and the fifth pull-up control transistor T12i along the second direction Y, the space occupied by the second pull-up control module 321 can be reduced, thereby reducing the bezel of the display panel 2.

[0247] In some embodiments, such as Figure 6 , Figures 30 to 35As shown, the sixth pull-up control transistor T81i includes a third pull-up control sub-transistor T81i1 and a fourth pull-up control sub-transistor T81i2. The gate T81i2G and the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 are electrically connected to the first high-potential signal line VGH1. The second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is electrically connected to the first electrode of the third pull-up control sub-transistor T81i1. The gate T81i1G of the third pull-up control sub-transistor T81i1 is electrically connected to the first high-potential signal line VGH1. The second electrode T81i1D of the third pull-up control sub-transistor T81i1 is electrically connected to the second electrode T11iD of the fourth pull-up control transistor T11i.

[0248] The third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 are arranged along the second direction. By including the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 in the sixth pull-up control transistor T81i, the performance of the sixth pull-up control transistor T81i can be improved. Furthermore, by arranging the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 along the first direction, the lateral area occupied by the sixth pull-up control transistor T81i can be reduced, thereby reducing the bezel of the display panel 2.

[0249] Specifically, the third pull-up control sub-transistor T81i1 and the fourth pull-up control sub-transistor T81i2 can be regarded as two independent transistors, or as two sub-transistors in the sixth pull-up control transistor T81i, and so on; other sub-transistors can also refer to the above description, and will not be repeated in the following embodiments.

[0250] Specifically, when a transistor has multiple sub-transistors, the first electrode of the transistor is the electrode connected to the signal line. For example, the sixth pull-up control transistor T81i includes a third pull-up control sub-transistor T81i1 and a fourth pull-up control sub-transistor T81i2. Since the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2 is electrically connected to the first high-potential signal line VGH1, the first electrode T81iS of the sixth pull-up control transistor T81i is the first electrode T81i2S of the fourth pull-up control sub-transistor T81i2. Similarly, the first electrodes of other transistors can be determined.

[0251] Specifically, the multi-level gate drive circuit 22 includes a multi-level second-type gate circuit 22b. In the first-level second-type gate circuit 22b, the gate T11iG of the fourth pull-up control transistor T11i can be connected to the start signal line. In the other levels of the second-type gate circuit 22b, the gate T11iG of the fourth pull-up control transistor T11i and the gate T12iG of the fifth pull-up control transistor T12i are electrically connected to the second signal output terminal INI[n-2] of the two previous levels of the second-type gate circuit 22b. The first electrode T11iS of the fourth pull-up control transistor T11i and the first electrode T12iS of the fifth pull-up control transistor T12i are electrically connected to the first high-potential signal line VGH1.

[0252] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second pull-down module 323 includes a fifth pull-down transistor T31i and a sixth pull-down transistor T41i. The gate T31iG of the fifth pull-down transistor T31i is electrically connected to the second pull-down node QB2[n]. The first electrode T31iS of the fifth pull-down transistor T31i is electrically connected to the second low-potential signal line VGL2. The second electrode T31iD of the fifth pull-down transistor T31i is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage. The gate T41iG of the sixth pull-down transistor T41i is electrically connected to the second signal output terminal INI[n+2] of the second type gate circuit 22b of the next two stages. The first electrode T41iS of the sixth pull-down transistor T41i is connected to the second low-potential signal line VGL2. The second electrode T41iD of the sixth pull-down transistor T41i is electrically connected to the second pull-up node Q2[n].

[0253] The fifth pull-down transistor T31i and the sixth pull-down transistor T41i are arranged along the second direction Y. By arranging the fifth pull-down transistor T31i and the sixth pull-down transistor T41i along the second direction, the space occupied by the second pull-down module 323 can be reduced, and the bezel of the display panel 2 can be reduced.

[0254] In some embodiments, such as Figure 6 , Figures 30 to 35As shown, the sixth pull-down transistor T41i includes a third pull-down sub-transistor T41i1 and a fourth pull-down sub-transistor T41i2. The gate T41i2G of the fourth pull-down sub-transistor T41i2 is electrically connected to the second signal output terminal INI[n+2] of the next two-stage second-type gate circuit 22b. The first electrode T41i2S of the fourth pull-down sub-transistor T41i2 is electrically connected to the second low-potential signal line VGL2. The second electrode T41i2D of the fourth pull-down sub-transistor T41i2 is electrically connected to the first electrode T41i1S of the third pull-down sub-transistor T41i1 at the second internal node N2[n]. The gate T41i1G of the third pull-down sub-transistor T41i1 is electrically connected to the second signal output terminal INI[n+2] of the next two-stage second-type gate circuit 22b. The second electrode T41i1D of the third pull-down sub-transistor T41i1 is electrically connected to the second pull-up node Q2[n].

[0255] The third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 are arranged along the second direction Y. By including the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 in the sixth pull-down transistor T41i, the performance of the sixth pull-down transistor T41i can be improved. Furthermore, the arrangement of the third pull-down sub-transistor T41i1 and the fourth pull-down sub-transistor T41i2 along the second direction can reduce the lateral area occupied by the sixth pull-down transistor T41i, thereby reducing the bezel of the display panel 2.

[0256] In some embodiments, such as Figure 6 , Figures 30 to 35As shown, the second inverting module 325 includes a sixth inverting transistor T51i, a seventh inverting transistor T52i, an eighth inverting transistor T53i, a ninth inverting transistor T54i, and a tenth inverting transistor T55i. The gate T51iG and the first electrode T51iS of the sixth inverting transistor T51i are electrically connected to the low-frequency signal line LC. The second electrode T51iD of the sixth inverting transistor T51i is electrically connected to the second electrode T52iD of the seventh inverting transistor T52i. The gate T52iG of the seventh inverting transistor T52i is electrically connected to the second pull-up node Q2[n]. The first electrode T52iS of the seventh inverting transistor T52i is electrically connected to the second low-potential signal line VGL2. The gate T53iG of the eighth inverting transistor T53i is electrically connected to the second electrode T51iD of the sixth inverting transistor T51i. The first electrode T51iS of the eighth inverting transistor T54i is electrically connected to the second low-potential signal line VGL2. Electrode T53iS is electrically connected to the low-frequency signal line LC. The second electrode T53iD of the eighth inverting transistor T53i is electrically connected to the second pull-down node QB2[n]. The gate T54iG of the ninth inverting transistor T54i is electrically connected to the second pull-up node Q2[n]. The first electrode T54iS of the ninth inverting transistor T54i is electrically connected to the second low-potential signal line VGL2. The second electrode T54iD of the ninth inverting transistor T54i is electrically connected to the second pull-down node QB2[n]. The gate T55iG of the tenth inverting transistor T55i is electrically connected to the second signal output terminal INI[n-2] of the upper two-stage second-class gate circuit 22b. The first electrode T55iS of the tenth inverting transistor T55i is electrically connected to the second low-potential signal line VGL2. The second electrode T55iD of the tenth inverting transistor T55i is electrically connected to the second pull-down node QB2[n].

[0257] The sixth inverting transistor T51i and the seventh inverting transistor T52i are arranged along the second direction Y, the eighth inverting transistor T53i and the ninth inverting transistor T54i are arranged along the second direction Y, and the sixth inverting transistor T51i, the eighth inverting transistor T53i and the tenth inverting transistor T55i are arranged along the first direction X. By arranging the sixth inverting transistor T51i and the seventh inverting transistor T52i along the second direction, and the eighth inverting transistor T53i and the ninth inverting transistor T54i along the second direction, the lateral space occupied by the second inverting module 325 can be reduced, thereby reducing the bezel of the display panel 2.

[0258] In some embodiments, such as Figure 6 , Figures 30 to 35As shown, the sixth inverting transistor T51i includes a third inverting sub-transistor T51i1 and a fourth inverting sub-transistor T51i2. The gate T51i1G and the first electrode T51i1S of the third inverting sub-transistor T51i1 are electrically connected to the low-frequency signal line LC. The second electrode T51i1D of the third inverting sub-transistor T51i1 is electrically connected to the first electrode of the fourth inverting sub-transistor T51i2. The gate T51i2G of the fourth inverting sub-transistor T51i2 is electrically connected to the low-frequency signal line LC. The second electrode T51i2D of the fourth inverting sub-transistor T51i2 is electrically connected to the second electrode T52iD of the seventh inverting transistor T52i.

[0259] The third inverting sub-transistor T51i1 and the fourth inverting sub-transistor T51i2 are arranged along the first direction X. By including the third inverting sub-transistor T51i1 and the fourth inverting sub-transistor T51i2 in the sixth inverting transistor T51i, the performance of the sixth inverting transistor T51i can be improved.

[0260] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the sixth inverting transistor T51i and the sixth pull-up control transistor T81i are arranged along the second direction Y, the eighth inverting transistor T53i and the fifth pull-up control transistor T12i are arranged along the second direction Y, and the tenth inverting transistor T55i and the fifth pull-down transistor T31i are arranged along the second direction Y. This reduces the lateral space occupied by the second inverting module 325, the second pull-up control module 321, and the second pull-down module 323, thus reducing the bezel of the display panel 2.

[0261] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second pull-down sustaining module 324 includes a second pull-down sustaining transistor T42i. The gate T42iG of the second pull-down sustaining transistor T42i is electrically connected to the second pull-down node QB2[n]. The first electrode T42iS of the second pull-down sustaining transistor T42i is electrically connected to the second low-potential signal line VGL2. The second electrode T42iD of the second pull-down sustaining transistor T42i is electrically connected to the second pull-up node Q2[n].

[0262] In the second direction, the second pull-down holding transistor T42i is disposed between the ninth inverting transistor T54i and the fifth pull-up control transistor T12i. This reduces the lateral space occupied by the second pull-down holding transistor T42i, the ninth inverting transistor T54i, and the fifth pull-up control transistor T12i, thereby reducing the bezel of the display panel 2.

[0263] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second pull-down sustaining transistor T42i includes a third pull-down sustaining sub-transistor T42i1 and a fourth pull-down sustaining sub-transistor T42i2. The gate T42i2G of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the second pull-down node QB2[n]. The first electrode T42i2S of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the second low-potential signal line VGL2. The second electrode T42i2D of the fourth pull-down sustaining sub-transistor T42i2 is electrically connected to the first electrode T42i1S of the third pull-down sustaining sub-transistor T42i1 at the second internal node N2[n]. The gate of the third pull-down sustaining sub-transistor T42i1 is electrically connected to the second pull-down node QB2[n]. The second electrode of the third pull-down sustaining sub-transistor T42i1 is electrically connected to the second pull-up node Q2[n].

[0264] The third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 are arranged along the second direction Y. By including the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 in the second pull-down sustaining transistor T42i, the performance of the second pull-down sustaining transistor T42i can be improved. Furthermore, the arrangement of the third pull-down sustaining sub-transistor T42i1 and the fourth pull-down sustaining sub-transistor T42i2 along the second direction can reduce the lateral space occupied by the second pull-down sustaining transistor T42i, thereby reducing the bezel of the display panel 2.

[0265] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second reset module 327 includes a second reset transistor T43i. The gate T43iG of the second reset transistor T43i is electrically connected to the second reset control line VST2. The first electrode T43iS of the second reset transistor T43i is electrically connected to the second low potential signal line VGL2. The second electrode T43iD of the second reset transistor T43i is electrically connected to the second pull-up node Q2[n].

[0266] In the second direction Y, the second reset transistor T43i is disposed on the side of the seventh inverter transistor T52i away from the sixth inverter transistor T51i. By disposing the second reset transistor T43i on the side of the seventh inverter transistor T52i away from the sixth inverter transistor T51i, the lateral space occupied by the second reset transistor T43i and the second inverter module 325 is reduced, thereby reducing the bezel of the display panel 2, and the second reset transistor T43i is easier to connect to the second reset control line VST2.

[0267] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second reset transistor T43i includes a third reset sub-transistor T43i1 and a fourth reset sub-transistor T43i2. The gate T43i1G of the fourth reset sub-transistor T43i2 is electrically connected to the second reset control line VST2. The first electrode of the fourth reset sub-transistor T43i2 is electrically connected to the second low-potential signal line VGL2. The second electrode T43i1D of the third reset sub-transistor T43i1 and the first electrode T43i1S of the third reset sub-transistor T43i1 are electrically connected to the second internal node N2[n]. The gate T43i1G of the third reset sub-transistor T43i1 is electrically connected to the second reset control line VST2. The second electrode T43i1D of the third reset sub-transistor T43i1 is electrically connected to the second pull-up node Q2[n].

[0268] The third reset transistor T43i1 and the fourth reset transistor T43i2 are arranged along the second direction. By including the third reset transistor T43i1 and the fourth reset transistor T43i2 in the second reset transistor T43i, the performance of the second reset transistor T43i can be improved. Furthermore, the arrangement of the third reset transistor T43i1 and the fourth reset transistor T43i2 along the second direction can reduce the lateral space occupied by the second reset transistor T43i, thereby reducing the bezel of the display panel 2.

[0269] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second anti-negative bias module 326 includes a second anti-negative bias transistor T61i. The gate T61iG of the second anti-negative bias transistor T61i is electrically connected to the second pull-up node Q2[n]. The first electrode T61iS of the second anti-negative bias transistor T61i is electrically connected to the first high-potential signal line VGH1. The second electrode T61iD of the second anti-negative bias transistor T61i is electrically connected to the second internal node N2[n].

[0270] The second anti-negative bias transistor T61i is disposed along the second direction Y between the seventh inverting transistor T52i and the sixth pull-up control transistor T81i. By disposing the second anti-negative bias transistor T61i along the second direction Y between the seventh inverting transistor T52i and the sixth pull-up control transistor T81i, the lateral area occupied by the second anti-negative bias module 326 can be reduced, thus reducing the bezel of the display panel 2.

[0271] In some embodiments, such as Figure 6 , Figures 30 to 35As shown, the second anti-negative bias transistor T61i includes a third anti-negative bias transistor T61i1 and a fourth anti-negative bias transistor T61i2. The gate T61i2G of the fourth anti-negative bias transistor T61i2 is electrically connected to the second pull-up node Q2[n]. The first electrode T61i2S of the fourth anti-negative bias transistor T61i2 is electrically connected to the first high-potential signal line. The second electrode T61i2D of the fourth anti-negative bias transistor T61i2 is electrically connected to the first electrode of the third anti-negative bias transistor T61i1. The gate T61i1G of the third anti-negative bias transistor T61i1 is electrically connected to the second pull-up node Q2[n]. The second electrode T61i1D of the third anti-negative bias transistor T61i1 is electrically connected to the second internal node N2[n].

[0272] The third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 are arranged along the second direction. By including the third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 in the second anti-negative bias transistor T61i, the performance of the second anti-negative bias transistor T61i can be improved. Furthermore, the arrangement of the third anti-negative bias transistor T61i1 and the fourth anti-negative bias transistor T61i2 along the second direction can reduce the lateral space occupied by the second anti-negative bias transistor T61i, thereby reducing the bezel of the display panel 2.

[0273] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second pull-up module 322 includes a fourth pull-up transistor T21i. The gate T21iG of the fourth pull-up transistor T21i is electrically connected to the second pull-up node Q2[n]. The first electrode T21iS of the fourth pull-up transistor T21i is electrically connected to the third clock signal line CKC. The second electrode T21iD of the fourth pull-up transistor T21i is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage.

[0274] The fourth pull-up transistor T21i and the tenth inverting transistor T55i are arranged along the first direction X.

[0275] In some embodiments, such as Figure 6 , Figures 30 to 35 As shown, the second type of gate circuit 22b also includes a second capacitor C2. One plate of the second capacitor C2 is electrically connected to the second pull-up node Q2[n], and the other plate of the second capacitor C2 is electrically connected to the second signal output terminal INI[n] of the second type of gate circuit 22b.

[0276] Specifically, the second capacitor C2 includes a first plate C2a and a second plate C2b. The first plate C2a of the second capacitor C2 includes a first part C2a1 and a second part C2a2.

[0277] In some embodiments, such as Figure 30 , Figure 31 As shown, the display panel 2 includes a light-shielding layer 212, which includes a third light-shielding connection line LS3, a second signal output terminal INI[n] of the second type gate circuit 22b, and a first part C2a1 of the first plate C2a of the second capacitor C2, which are arranged sequentially along the first direction X.

[0278] In some embodiments, such as Figure 30 , Figure 32 As shown, the display panel 2 includes an active layer 216, which includes the active portion T11iA of the fourth pull-up control transistor T11i, the active portion T12iA of the fifth pull-up control transistor T12i, the active portion T81iA of the sixth pull-up control transistor T81i, the active portion T21iA of the fourth pull-up transistor T21i, the active portion T31iA of the fifth pull-down transistor T31i, the active portion T41iA of the sixth pull-down transistor T41i, and the second pull-down transistor... The active portion T42iA of transistor T42i, the active portion T51iA of sixth inverting transistor T51i, the active portion T52iA of seventh inverting transistor T52i, the active portion T53iA of eighth inverting transistor T53i, the active portion T54iA of ninth inverting transistor T54i, the active portion T55iA of tenth inverting transistor T55i, the active portion T43iA of second reset transistor T43i, and the active portion T61iA of second anti-negative bias transistor T61i;

[0279] The active portion T51iA of the sixth inverting transistor T51i, the active portion T52iA of the seventh inverting transistor T52i, the active portion T61iA of the second anti-negative bias transistor T61i, and the active portion T81iA of the sixth pull-up control transistor T81i are arranged sequentially along the second direction Y.

[0280] The active portion T51iA of the sixth inverting transistor T51i, the active portion T52iA of the seventh inverting transistor T52i, and the active portion T43iA of the second reset transistor T43i are arranged sequentially along the second direction Y.

[0281] The active portions T53iA of the eighth inverting transistor T53i, T54iA of the ninth inverting transistor T54i, T42iA of the second pull-down holding transistor T42i, T12iA of the fifth pull-up control transistor T12i, and T11iA of the fourth pull-up control transistor T11i are arranged sequentially along the second direction Y.

[0282] The active portion T55iA of the tenth inverting transistor T55i, the active portion T31iA of the fifth pull-down transistor T31i, the active portion T41iA of the sixth pull-down transistor T41i, the active portion T12iA of the fifth pull-up control transistor T12i, and the active portion T11iA of the fourth pull-up control transistor T11i are arranged sequentially along the second direction;

[0283] The active portion T51iA of the sixth inverting transistor T51i, the active portion T53iA of the eighth inverting transistor T53i, the active portion T55iA of the tenth inverting transistor T55i, and the active portion T21iA of the fourth pull-up transistor T21i are arranged sequentially along the first direction X.

[0284] Specifically, such as Figure 32 As shown, the active portion T81iA of the sixth pull-up control transistor T81i includes the active portion T81i1A of the third pull-up control sub-transistor T81i1 and the active portion T81i2A of the fourth pull-up control sub-transistor T81i2. The active portion T81i1A of the third pull-up control sub-transistor T81i1 and the active portion T81i2A of the fourth pull-up control sub-transistor T81i2 are arranged sequentially along the second direction.

[0285] Specifically, such as Figure 32 As shown, the active portion T41iA of the sixth pull-down transistor T41i includes the active portion T41i1A of the third pull-down sub-transistor T41i1 and the active portion T41i2A of the fourth pull-down sub-transistor T41i2, which are arranged along the second direction.

[0286] Specifically, such as Figure 32 As shown, the active portion T42iA of the second pull-down sustaining transistor T42i includes the active portion of the third pull-down sustaining sub-transistor T42i1 and the active portion T42i2A of the fourth pull-down sustaining sub-transistor T42i2, which are arranged along a second direction.

[0287] Specifically, such as Figure 32As shown, the active portion T43iA of the second reset transistor T43i includes the active portion T43i1A of the third reset sub-transistor T43i1 and the active portion T43i1A of the fourth reset sub-transistor T43i2. The active portion T43i1A of the third reset sub-transistor T43i1 and the active portion T43i1A of the fourth reset sub-transistor T43i2 are arranged along the second direction.

[0288] Specifically, such as Figure 32 As shown, the active portion T51iA of the sixth inverting transistor T51i includes the active portion T51i1A of the third inverting sub-transistor T51i1 and the active portion T51i2A of the fourth inverting sub-transistor T51i2, which are arranged along a first direction.

[0289] Specifically, such as Figure 32 As shown, the active portion T61iA of the second anti-negative bias transistor T61i includes the active portion T61i1A of the third anti-negative bias transistor T61i1 and the active portion T61i2A of the fourth anti-negative bias transistor T61i2. The active portion T61i1A of the third anti-negative bias transistor T61i1 and the active portion T61i2A of the fourth anti-negative bias transistor T61i2 are arranged along the second direction.

[0290] In some embodiments, such as Figure 30 , Figure 33 As shown, the display panel 2 includes a gate layer 218, which includes the gate T11iG of a fourth pull-up control transistor T11i, the gate T12iG of a fifth pull-up control transistor T12i, the gate T81iG of a sixth pull-up control transistor T81i, the gate T21iG of a fourth pull-up transistor T21i, the gate T31iG of a fifth pull-down transistor T31i, the gate T41iG of a sixth pull-down transistor T41i, and a second pull-down sustaining transistor T4. The gate T42iG of the second transistor, the gate T51iG of the sixth inverting transistor, the gate T52iG of the seventh inverting transistor, the gate T53iG of the eighth inverting transistor, the gate T54iG of the ninth inverting transistor, the gate T55iG of the tenth inverting transistor, the gate T43iG of the second reset transistor, the gate T61iG of the second anti-negative bias transistor, and the second plate C2b of the second capacitor C2.

[0291] The gates T51iG of the sixth inverting transistor T51i, T52iG of the seventh inverting transistor T52i, T61iG of the second anti-negative bias transistor T61i, and T81iG of the sixth pull-up control transistor T81i are arranged sequentially along the second direction Y.

[0292] The gate T51iG of the sixth inverting transistor T51i, the gate T52iG of the seventh inverting transistor T52i, and the gate T43iG of the second reset transistor T43i are arranged sequentially along the second direction Y.

[0293] The gates T53iG of the eighth inverting transistor T53i, T54iG of the ninth inverting transistor T54i, T42iG of the second pull-down holding transistor T42i, T12iG of the fifth pull-up control transistor T12i, and T11iG of the fourth pull-up control transistor T11i are arranged sequentially along the second direction Y.

[0294] The gate T55iG of the tenth inverting transistor T55i, the gate T31iG of the fifth pull-down transistor T31i, the gate T41iG of the sixth pull-down transistor T41i, the gate T12iG of the fifth pull-up control transistor T12i, and the gate T11iG of the fourth pull-up control transistor T11i are arranged sequentially along the second direction.

[0295] The gate T11iG of the fourth pull-up transistor T11i and a portion of the second plate C2b of the second capacitor C2 are sequentially arranged along the second direction Y.

[0296] The gate T51iG of the sixth inverting transistor T51i, the gate T53iG of the eighth inverting transistor T53i, the gate T55iG of the tenth inverting transistor T55i, the gate T21iG of the fourth pull-up transistor T21i, and another part of the second plate C2b of the second capacitor C2 are arranged sequentially along the first direction X.

[0297] Specifically, such as Figure 33 As shown, the gate T81iG of the sixth pull-up control transistor T81i includes the gate T81i1G of the third pull-up control sub-transistor T81i1 and the gate T81i2G of the fourth pull-up control sub-transistor T81i2. The gate T81i1G of the third pull-up control sub-transistor T81i1 and the gate T81i2G of the fourth pull-up control sub-transistor T81i2 are arranged sequentially along the second direction.

[0298] Specifically, such as Figure 33 As shown, the gate T41iG of the sixth pull-down transistor T41i includes the gate T41i1G of the third pull-down sub-transistor T41i1 and the gate T41i2G of the fourth pull-down sub-transistor T41i2, and the gate T41i1G of the third pull-down sub-transistor T41i1 and the gate T41i2G of the fourth pull-down sub-transistor T41i2 are arranged along the second direction.

[0299] Specifically, such as Figure 33As shown, the gate T42iG of the second pull-down sustaining transistor T42i includes the gate of the third pull-down sustaining sub-transistor T42i1 and the gate T42i2G of the fourth pull-down sustaining sub-transistor T42i2, and the gate of the third pull-down sustaining sub-transistor T42i1 and the gate T42i2G of the fourth pull-down sustaining sub-transistor T42i2 are arranged along the second direction.

[0300] Specifically, such as Figure 33 As shown, the gate T43iG of the second reset transistor T43i includes the gate T43i1G of the third reset sub-transistor T43i1 and the gate T43i1G of the fourth reset sub-transistor T43i2, and the gate T43i1G of the third reset sub-transistor T43i1 and the gate T43i1G of the fourth reset sub-transistor T43i2 are arranged along the second direction.

[0301] Specifically, such as Figure 33 As shown, the gate T51iG of the sixth inverting transistor T51i includes the gate T51i1G of the third inverting sub-transistor T51i1 and the gate T51i2G of the fourth inverting sub-transistor T51i2, and the gate T51i1G of the third inverting sub-transistor T51i1 and the gate T51i2G of the fourth inverting sub-transistor T51i2 are arranged along a first direction.

[0302] Specifically, such as Figure 33 As shown, the gate T61iG of the second anti-negative bias transistor T61i includes the gate T61i1G of the third anti-negative bias transistor T61i1 and the gate T61i2G of the fourth anti-negative bias transistor T61i2, and the gate T61i1G of the third anti-negative bias transistor T61i1 and the gate T61i2G of the fourth anti-negative bias transistor T61i2 are arranged along the second direction.

[0303] In some embodiments, such as Figure 30 , Figure 34As shown, the display panel 2 includes a first source-drain layer 221, which includes the first electrode T11iS of the fourth pull-up control transistor T11i, the first electrode T12iS of the fifth pull-up control transistor T12i, the first electrode T81iS of the sixth pull-up control transistor T81i, the first electrode T21iS of the fourth pull-up transistor T21i, the first electrode T31iS of the fifth pull-down transistor T31i, the first electrode T41iS of the sixth pull-down transistor T41i, and a second pull-down sustaining crystal. The first electrode T42iS of transistor T42i, the first electrode T51iS of sixth inverting transistor T51i, the first electrode T52iS of seventh inverting transistor T52i, the first electrode T53iS of eighth inverting transistor T53i, the first electrode T54iS of ninth inverting transistor T54i, the first electrode T55iS of tenth inverting transistor T55i, the first electrode T43iS of second reset transistor T43i, the first electrode T61iS of second anti-negative bias transistor T61i, and the fourth pull-up control transistor. The second electrode of T11i is T11iD, the second electrode of the fifth pull-up control transistor T12i is T12iD, the second electrode of the sixth pull-up control transistor T81i is T81iD, the second electrode of the fourth pull-up transistor T21i is T21iD, the second electrode of the fifth pull-down transistor T31i is T31iD, the second electrode of the sixth pull-down transistor T41i is T41iD, the second electrode of the second pull-down holding transistor T42i is T42iD, the second electrode of the sixth inverting transistor T51i is T51iD, and the seventh inverting crystal... The second electrode T52iD of transistor T52i, the second electrode T53iD of eighth inverting transistor T53i, the second electrode T54iD of ninth inverting transistor T54i, the second electrode T55iD of tenth inverting transistor T55i, the second electrode T43iD of second reset transistor T43i, the second electrode T61iD of second anti-negative bias transistor T61i, the second part C2a2 of the first plate C2a of second capacitor C2, the sixth source connection line LD6, the seventh source connection line LD7 and the eighth source connection line LD8;

[0304] The first electrode T51iS of the sixth inverting transistor T51i, the first electrode T52iS of the seventh inverting transistor T52i, the first electrode T61iS of the second anti-negative bias transistor T61i, and the first electrode T81iS of the sixth pull-up control transistor T81i are arranged sequentially along the second direction Y.

[0305] The first electrode T51iS of the sixth inverting transistor T51i, the first electrode T52iS of the seventh inverting transistor T52i, and the first electrode T43iS of the second reset transistor T43i are arranged sequentially along the second direction Y.

[0306] The first electrode T53iS of the eighth inverting transistor T53i, the first electrode T54iS of the ninth inverting transistor T54i, the first electrode T42iS of the second pull-down holding transistor T42i, the first electrode T12iS of the fifth pull-up control transistor T12i, and the first electrode T11iS of the fourth pull-up control transistor T11i are arranged sequentially along the second direction Y.

[0307] The first electrode T55iS of the tenth inverting transistor T55i, the first electrode T31iS of the fifth pull-down transistor T31i, the first electrode T41iS of the sixth pull-down transistor T41i, the first electrode T12iS of the fifth pull-up control transistor T12i, and the first electrode T11iS of the fourth pull-up control transistor T11i are arranged sequentially along the second direction.

[0308] The first electrode T51iS of the sixth inverting transistor T51i, the first electrode T53iS of the eighth inverting transistor T53i, the first electrode T55iS of the tenth inverting transistor T55i, and the first electrode T21iS of the fourth pull-up transistor T21i are arranged sequentially along the first direction X.

[0309] The third shielding connection line LS3 connects the first electrode T41iS of the sixth pull-down transistor T41i and the first electrode T55iS of the tenth inverting transistor T55i. The seventh source connection line LD7 connects the gate T55iG of the tenth inverting transistor T55i and the second signal output terminal INI[n-2] of the upper two-stage second-type gate circuit 22b. The eighth source connection line LD8 connects the gate T41iG of the sixth pull-down transistor T41i and the second signal output terminal INI[n+2] of the lower two-stage second-type gate circuit 22b.

[0310] Specifically, in the circuit diagrams of this application embodiment, each transistor has a gate, a first electrode, and a second electrode to illustrate the connection relationship. However, in actual design, to reduce the space occupied by the transistors, the electrodes of some transistors may be formed using the same structure. For example, the first electrode of the third pull-up control sub-transistor T81i1 and the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 may be formed using the same structure. Therefore, only the second electrode T81i2D of the fourth pull-up control sub-transistor T81i2 is shown in the diagram. It can be understood that this structure is also the first electrode of the third pull-up control sub-transistor T81i1. Similarly, the structure of the electrodes of other transistors can be determined.

[0311] Specifically, such as Figures 30 to 35 As shown, the first part C2a1 of the first plate C2a of the second capacitor C2 is connected to the second part C2a2 of the first plate C2a of the second capacitor C2.

[0312] Specifically, such as Figure 34 As shown, the first source-drain layer 221 includes a first electrode of the third pull-up control sub-tube T81i1, a second electrode T81i1D of the third pull-up control sub-tube T81i1, a first electrode T81i2S of the fourth pull-up control sub-tube T81i2, and a second electrode T81i2D of the fourth pull-up control sub-tube T81i2. The first electrode T81i2S of the fourth pull-up control sub-tube T81i2, the second electrode T81i2D of the fourth pull-up control sub-tube T81i2, and the second electrode T81i1D of the third pull-up control sub-tube T81i1 are arranged sequentially along the second direction Y.

[0313] Specifically, such as Figure 34 As shown, the first source-drain layer 221 includes the first electrode of the third pull-down sub-tube T41i1, the second electrode T41i1D of the third pull-down sub-tube T41i1, the first electrode T41i2S of the fourth pull-down sub-tube T41i2, and the second electrode T41i2D of the fourth pull-down sub-tube T41i2. The first electrode T41i2S of the fourth pull-down sub-tube T41i2, the second electrode T41i2D of the fourth pull-down sub-tube T41i2, and the second electrode T41i1D of the third pull-down sub-tube T41i1 are arranged sequentially along the second direction Y.

[0314] Specifically, such as Figure 34 As shown, the first source-drain layer 221 includes a first electrode of the third pull-down sustaining sub-transistor T42i1, a second electrode of the third pull-down sustaining sub-transistor T42i1 T42i1D, a first electrode of the fourth pull-down sustaining sub-transistor T42i2 T42i2S, and a second electrode of the fourth pull-down sustaining sub-transistor T42i2 T42i2D. The first electrode of the fourth pull-down sustaining sub-transistor T42i2 T42i2S, the second electrode of the fourth pull-down sustaining sub-transistor T42i2 T42i2D, and the second electrode of the third pull-down sustaining sub-transistor T42i1 T42i1D are arranged sequentially along the second direction Y.

[0315] Specifically, such as Figure 34 As shown, the first source-drain layer 221 includes the first electrode of the third reset transistor T43i1, the second electrode T43i1D of the third reset transistor T43i1, the first electrode T43i2S of the fourth reset transistor T43i2, and the second electrode T43i1D of the fourth reset transistor T43i2. The first electrode T43i2S of the fourth reset transistor T43i2, the second electrode T43i1D of the fourth reset transistor T43i2, and the second electrode T43i1D of the third reset transistor T43i1 are arranged sequentially along the second direction Y.

[0316] Specifically, such as Figure 34As shown, the first source-drain layer 221 includes the first electrode T51i1S of the third inverting sub-transistor T51i1, the second electrode T51i1D of the third inverting sub-transistor T51i1, the first electrode of the fourth inverting sub-transistor T51i2, and the second electrode T51i2D of the fourth inverting sub-transistor T51i2. The first electrode T51i1S of the third inverting sub-transistor T51i1, the second electrode T51i1D of the third inverting sub-transistor T51i1, and the second electrode T51i2D of the fourth inverting sub-transistor T51i2 are arranged sequentially along the first direction X.

[0317] Specifically, such as Figure 34 As shown, the first source-drain layer 221 includes the first electrode of the third anti-negative bias tube T61i1, the second electrode T61i1D of the third anti-negative bias tube T61i1, the first electrode T61i2S of the fourth anti-negative bias tube T61i2, and the second electrode T61i2D of the fourth anti-negative bias tube T61i2. The first electrode T61i2S of the fourth anti-negative bias tube T61i2, the second electrode T61i2D of the fourth anti-negative bias tube T61i2, and the second electrode T61i1D of the third anti-negative bias tube T61i1 are arranged sequentially along the second direction Y.

[0318] In some embodiments, such as Figure 30 , Figure 35 As shown, the second clock signal line CKB includes a first group of sub-lines CKB1 and a second group of sub-lines CKBj. The display panel 2 includes a second source-drain layer 223. The second source-drain layer 223 includes a second reset control line VST2 and a second group of sub-lines CKBj arranged sequentially along the first direction X.

[0319] The second reset control line VST2 is connected to the gate T43iG of the second reset transistor T43i through the sixth source connection line LD6.

[0320] In some embodiments, such as Figure 7As shown, the third type of gate circuit 22c includes a third pull-up control module 331, a third pull-up module 332, a third pull-down module 333, a third pull-down sustaining module 334, a third inverting module 335, and a third anti-negative bias module 336. The third pull-up control module 331 and the third pull-up module 332 are electrically connected to the third pull-up node Q3[n] of the third type of gate circuit. The third pull-down module 333 is electrically connected to the third pull-up node Q3[n] and the third signal output terminal REF[n] of the third type of gate circuit 22c. The third pull-down sustaining module 334 is electrically connected to the third pull-up node Q3[n]. The third inverting module 335 is electrically connected to the third pull-up node Q3[n], the first high-potential signal line VGH1 of the display panel, the second low-potential signal line VGL2, the first signal output terminal Gn[n-1] of the previous stage first type gate circuit 22a, the second signal output terminal INI[n] of the current stage second type gate circuit 22b, and the second signal output terminal INI[n+1] of the next stage second type gate circuit 22b; the third anti-negative bias module 336 is electrically connected between the first high-potential signal line VGH1 and the third pull-up node Q3[n].

[0321] In some embodiments, such as Figure 7 , Figure 36 As shown, at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down sustaining module 334, the third inverting module 335, and the third anti-negative bias module 336 are arranged along the second direction, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By arranging at least two of the third pull-up control module 331, the third pull-up module 332, the third pull-down module 333, the third pull-down sustaining module 334, the third inverting module 335, and the third anti-negative bias module 336 along the second direction, the lateral space occupied by the third type of gate circuit 22c can be shortened, thereby reducing the lateral space occupied by the gate driving circuit 22 and reducing the bezel of the display panel 2.

[0322] Specifically, compared to the horizontal arrangement of modules in a comparative display device, this embodiment of the application reduces the horizontal space occupied by the third type of gate circuit 22c, reduces the horizontal space occupied by the gate driving circuit 22, and reduces the bezel of the display panel 2 by arranging at least two modules in the third type of gate circuit 22c along the second direction.

[0323] In some embodiments, such as Figure 7 , Figure 36As shown, a portion of the third inverter module 335 and the third pull-up control module 331 are arranged along the second direction Y. By arranging a portion of the third inverter module 335 and the third pull-up control module 331 along the second direction, the lateral space occupied by a portion of the third inverter module 335 and the third pull-up control module 331 can be reduced, as can the lateral space occupied by the third type of gate circuit 22c and the lateral space occupied by the gate drive circuit 22, thereby reducing the bezel of the display panel 2.

[0324] Specifically, such as Figure 36 As shown, in the second direction, a portion of the third inverting module 335 is located above the third pull-up control module 331.

[0325] In some embodiments, such as Figure 7 , Figure 36 As shown, another portion of the third inverting module 335, a portion of the third pull-down sustaining module 334, and a portion of the third pull-down module 333 are arranged along the second direction Y. By arranging the other portion of the third inverting module 335, the third pull-down sustaining module 334, and a portion of the third pull-down module 333 along the second direction Y, the lateral space occupied by the other portion of the third inverting module 335, the third pull-down sustaining module 334, and the third pull-down module 333 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the bezel of the display panel 2.

[0326] Specifically, such as Figure 36 As shown, it can be seen that in the second direction, another part of the third inverting module 335, the third pull-down maintaining module 334, and a part of the third pull-down module 333 are arranged sequentially along the second direction Y.

[0327] In some embodiments, such as Figure 7 , Figure 36 As shown, the third pull-up module 332 and the third anti-negative bias module 336 are arranged along the second direction Y;

[0328] Another portion of the third inverting module 335, the third pull-up module 332, and the third pull-down module 333 are arranged along the first direction X. By arranging the third pull-up module 332 and the third anti-negative bias module 336 along the second direction Y, the lateral space occupied by the third pull-up module 332 and the third anti-negative bias module 336 can be reduced, the lateral space occupied by the third type of gate circuit 22c can be reduced, and the lateral space occupied by the gate driving circuit 22 can be reduced, thereby reducing the bezel of the display panel 2.

[0329] Specifically, such as Figure 36 As shown, in the second direction, the third pull-up module 332 is located above the third anti-negative bias module 336.

[0330] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third inverting module 335 includes an eleventh inverting transistor T51r, a twelfth inverting transistor T52r, a thirteenth inverting transistor T53r, a fourteenth inverting transistor T54r, a fifteenth inverting transistor T55r, and a sixteenth inverting transistor T56r. The gate T51rG of the eleventh inverting transistor T51r and the first electrode T51rS of the eleventh inverting transistor T51r are electrically connected to the first signal output terminal Gn[n-1] of the previous stage first type gate circuit 22a. The second electrode T51rD of the eleventh inverting transistor T51r is connected to the twelfth inverting transistor T56r. The second electrode T52rD of transistor T52r is electrically connected. The gate T52rG of the twelfth inverting transistor T52r is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage. The first electrode T52rS of the twelfth inverting transistor T52r is electrically connected to the second low-potential signal line VGL2. The gate T53rG of the thirteenth inverting transistor T53r is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r. The first electrode T53rS of the thirteenth inverting transistor T53r is connected to the first high-potential signal line VG. H1 is electrically connected. The gate T54rG of the fourteenth inverting transistor T54r is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r. The first electrode T54rS of the fourteenth inverting transistor T54r is electrically connected to the first high-potential signal line VGH1. The second electrode T54rD of the fourteenth inverting transistor T54r is electrically connected to the third pull-down node QB3[n]. The gate T55rG of the fifteenth inverting transistor T55r is electrically connected to the third pull-up node Q3[n]. The first electrode T5 of the fifteenth inverting transistor T55r is electrically connected to the third pull-up node Q3[n]. 5rS is electrically connected to the second low-potential signal line VGL2, and the second electrode of the fifteenth inverting transistor T55r is electrically connected to the third pull-down node QB3[n]. The gate T56rG of the sixteenth inverting transistor T56r is electrically connected to the second signal output terminal INI[n+1] of the next stage second type gate circuit 22b. The first electrode T56rS of the sixteenth inverting transistor T56r is electrically connected to the second low-potential signal line VGL2, and the second electrode T56rD of the sixteenth inverting transistor T56r is electrically connected to the third pull-down node QB3[n].

[0331] The eleventh inverter transistor T51r, the thirteenth inverter transistor T53r, and the twelfth inverter transistor T52r are arranged along the first direction, the eleventh inverter transistor T51r, the thirteenth inverter transistor T53r, and the fourteenth inverter transistor T54r are arranged along the second direction, and the twelfth inverter transistor T52r, the sixteenth inverter transistor T56r, and the fifteenth inverter transistor T55r are arranged along the second direction Y. This arrangement can reduce the lateral space occupied by the third inverter module 335, thereby reducing the bezel of the display panel 2.

[0332] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the eleventh inverting transistor T51r includes a fifth inverting sub-transistor T51r1 and a sixth inverting sub-transistor T51r2. The gate T51r1G and the first electrode T51r1S of the fifth inverting sub-transistor T51r1 are electrically connected to the first signal output terminal Gn[n-1] of the previous stage first-class gate circuit 22a. The second electrode T51r1D of the fifth inverting sub-transistor T51r1 is electrically connected to the first electrode of the sixth inverting sub-transistor T51r2. The gate T51r2G of the sixth inverting sub-transistor T51r2 is electrically connected to the first signal output terminal Gn[n-1] of the previous stage first-class gate circuit 22a. The second electrode T51r2D of the sixth inverting sub-transistor T51r2 is electrically connected to the second electrode T52rD of the twelfth inverting transistor T52r.

[0333] The fifth inverting sub-transistor T51r1 and the sixth inverting sub-transistor T51r2 are arranged along a first direction. By including the fifth inverting sub-transistor T51r1 and the sixth inverting sub-transistor T51r2 in the eleventh inverting transistor T51r, the performance of the eleventh inverting transistor T51r can be improved.

[0334] In some embodiments, such as Figure 7 , Figures 36 to 41As shown, the twelfth inverting transistor T52r includes a seventh inverting sub-transistor T52r1 and an eighth inverting sub-transistor T52r2. The gate T52r1G and the first electrode T52r1S of the seventh inverting sub-transistor T52r1 are electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage. The second electrode T52r1D of the seventh inverting sub-transistor T52r1 is electrically connected to the first electrode T52r2S of the eighth inverting sub-transistor T52r2. The gate T52r2G of the eighth inverting sub-transistor T52r2 is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage. The second electrode T52r2D of the eighth inverting sub-transistor T52r2 is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r.

[0335] The seventh inverting sub-transistor T52r1 and the eighth inverting sub-transistor T52r2 are arranged along the first direction X. By including the seventh inverting sub-transistor T52r1 and the eighth inverting sub-transistor T52r2 in the twelfth inverting transistor T52r, the performance of the twelfth inverting transistor T52r can be improved.

[0336] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third pull-up control module 331 includes a seventh pull-up control transistor T11r and an eighth pull-up control transistor T12r. The gate T11rG of the seventh pull-up control transistor T11r is electrically connected to the second signal output terminal INI[n+1] of the next-stage second-type gate circuit 22b. The first electrode T11rS of the seventh pull-up control transistor T11r is electrically connected to the first high-potential signal line VGH1. The second electrode T11rD of the seventh pull-up control transistor T11r is electrically connected to the first electrode T12rS of the eighth pull-up control transistor T12r. The gate T12rG of the eighth pull-up control transistor T12r is electrically connected to the second signal output terminal INI[n+1] of the next-stage second-type gate circuit 22b. The second electrode T12rD of the eighth pull-up control transistor T12r is electrically connected to the third pull-up node Q3[n].

[0337] The fourteenth inverter transistor T54r, the eighth pull-up control transistor T12r, and the seventh pull-up control transistor T11r are arranged along the second direction Y. By arranging the fourteenth inverter transistor T54r, the eighth pull-up control transistor T12r, and the seventh pull-up control transistor T11r along the second direction Y, the lateral space occupied by the third inverter module 335 and the third pull-up control module 331 can be reduced, thereby reducing the bezel of the display panel 2.

[0338] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third pull-down module 333 includes a seventh pull-down transistor T31r and an eighth pull-down transistor T41r. The gate T31rG of the seventh pull-down transistor T31r is electrically connected to the third pull-down node QB3[n]. The first electrode T31rS of the seventh pull-down transistor T31r is electrically connected to the third low-potential signal line VGL3 of the display panel. The second electrode T31rD of the seventh pull-down transistor T31r is electrically connected to the third signal output terminal REF[n] of the third type gate circuit 22c of this stage. The gate T41rG of the eighth pull-down transistor T41r is electrically connected to the first signal output terminal of the first type gate circuit 22a of the previous stage. The first electrode T41rS of the eighth pull-down transistor T41r is connected to the second low-potential signal line VGL2. The second electrode T41rD of the eighth pull-down transistor T41r is electrically connected to the third pull-up node Q3[n].

[0339] The eighth pull-down transistor T41r and the fifteenth inverter transistor T55r are arranged along the second direction Y. By arranging the eighth pull-down transistor T41r and the fifteenth inverter transistor T55r along the second direction Y, the space occupied by the third pull-down module 333 and the third inverter module 335 can be reduced, and the bezel of the display panel 2 can be reduced.

[0340] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the eighth pull-down transistor T41r includes a fifth pull-down sub-transistor T41r1 and a sixth pull-down sub-transistor T41r2. The gate T41r1G of the fifth pull-down sub-transistor T41r1 is electrically connected to the first signal output terminal of the first type of gate circuit 22a of the previous stage. The first electrode T41r1S of the fifth pull-down sub-transistor T41r1 is electrically connected to the second low-potential signal line VGL2. The second electrode T41r1D of the fifth pull-down sub-transistor T41r1 and the first electrode of the sixth pull-down sub-transistor T41r2 are electrically connected to the third internal node N3[n] of the third type of gate circuit. The gate T41r2G of the sixth pull-down sub-transistor T41r2 is electrically connected to the first signal output terminal of the first type of gate circuit 22a of the previous stage. The second electrode T41r2D of the sixth pull-down sub-transistor T41r2 is electrically connected to the third pull-up node Q3[n].

[0341] The fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 are arranged along the second direction. By including the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 in the eighth pull-down transistor T41r, the performance of the eighth pull-down transistor T41r can be improved. Furthermore, the arrangement of the fifth pull-down sub-transistor T41r1 and the sixth pull-down sub-transistor T41r2 along the second direction can reduce the lateral area occupied by the eighth pull-down transistor T41r, thereby reducing the bezel of the display panel 2.

[0342] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third pull-down sustaining module 334 includes a third pull-down sustaining transistor T42r. The gate T42rG of the third pull-down sustaining transistor T42r is electrically connected to the third pull-down node QB3[n]. The first electrode T42rS of the third pull-down sustaining transistor T42r is electrically connected to the second low-potential signal line VGL2. The second electrode T42rD of the third pull-down sustaining transistor T42r is electrically connected to the third pull-up node Q3[n].

[0343] In the second direction Y, the third pull-down holding transistor T42r is disposed between the fifteenth inverting transistor T55r and the eighth pull-down transistor T41r; thereby reducing the lateral space occupied by the third pull-down holding transistor T42r, the fifteenth inverting transistor T55r and the eighth pull-down transistor T41r, and reducing the bezel of the display panel 2.

[0344] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third pull-down sustaining transistor T42r includes a fifth pull-down sustaining sub-transistor T42r1 and a sixth pull-down sustaining sub-transistor T42r2. The gate T42r2G of the sixth pull-down sustaining sub-transistor T42r2 is electrically connected to the third pull-down node QB3[n]. The first electrode T42r2S of the sixth pull-down sustaining sub-transistor T42r2 is electrically connected to the second low-potential signal line VGL2. The second electrode T42r2D of the sixth pull-down sustaining sub-transistor T42r2 is electrically connected to the first electrode T42r1S of the fifth pull-down sustaining sub-transistor T42r1 at the third internal node N3[n]. The gate T42r1G of the fifth pull-down sustaining sub-transistor T42r1 is electrically connected to the third pull-down node QB3[n]. The second electrode T42r1D of the fifth pull-down sustaining sub-transistor T42r1 is electrically connected to the third pull-up node Q3[n].

[0345] The fifth pull-down sustaining sub-transistor T42r1 and the sixth pull-down sustaining sub-transistor T42r2 are arranged along the second direction. By including the fifth pull-down sustaining sub-transistor T42r1 and the sixth pull-down sustaining sub-transistor T42r2 in the third pull-down sustaining transistor T42r, the performance of the third pull-down sustaining transistor T42r can be improved. Furthermore, the arrangement of the fifth pull-down sustaining sub-transistor T42r1 and the sixth pull-down sustaining sub-transistor T42r2 along the second direction can reduce the lateral space occupied by the third pull-down sustaining transistor T42r, thereby reducing the bezel of the display panel 2.

[0346] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third anti-negative bias module 336 includes a third anti-negative bias transistor T61r. The gate T61rG of the third anti-negative bias transistor T61r is electrically connected to the third pull-up node Q3[n]. The first electrode T61rS of the third anti-negative bias transistor T61r is electrically connected to the first high-potential signal line VGH1. The second electrode T61rD of the third anti-negative bias transistor T61r is electrically connected to the third internal node N3[n].

[0347] The third anti-negative bias transistor T61r is disposed along the first direction X on the side of the eighth pull-down transistor T41r away from the seventh pull-up control transistor T11r.

[0348] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third anti-negative bias transistor T61r includes a fifth anti-negative bias sub-transistor T61r1 and a sixth anti-negative bias sub-transistor T61r2. The gate T61r2G of the sixth anti-negative bias sub-transistor T61r2 is electrically connected to the third pull-up node Q3[n]. The first electrode T61r2S of the sixth anti-negative bias sub-transistor T61r2 is electrically connected to the first high-potential signal line. The second electrode T61r2D of the sixth anti-negative bias sub-transistor T61r2 is electrically connected to the first electrode of the fifth anti-negative bias sub-transistor T61r1. The gate T61r1G of the fifth anti-negative bias sub-transistor T61r1 is electrically connected to the third pull-up node Q3[n]. The second electrode T61r1D of the fifth anti-negative bias sub-transistor T61r1 is electrically connected to the third internal node N3[n].

[0349] The fifth anti-negative bias transistor T61r1 and the sixth anti-negative bias transistor T61r2 are arranged along the second direction. By including the fifth anti-negative bias transistor T61r1 and the sixth anti-negative bias transistor T61r2 in the third anti-negative bias transistor T61r, the performance of the third anti-negative bias transistor T61r can be improved. Furthermore, the arrangement of the fifth anti-negative bias transistor T61r1 and the sixth anti-negative bias transistor T61r2 along the second direction can reduce the lateral space occupied by the third anti-negative bias transistor T61r, thereby reducing the bezel of the display panel 2.

[0350] In some embodiments, such as Figure 7 , Figures 36 to 41 As shown, the third pull-up module 332 includes a fifth pull-up transistor T21r. The gate T21rG of the fifth pull-up transistor T21r is electrically connected to the third pull-up node Q3[n]. The first electrode T21rS of the fifth pull-up transistor T21r is electrically connected to the second high-potential signal line VGH2 of the display panel. The second electrode T21rD of the fifth pull-up transistor T21r is electrically connected to the third signal output terminal REF[n] of the third type gate circuit 22c of this stage.

[0351] The fifth pull-up transistor T21r and the third anti-negative bias transistor T61r are arranged along the second direction; thereby reducing the horizontal space occupied by the fifth pull-up transistor T21r and the third anti-negative bias transistor T61r, and reducing the bezel of the display panel 2.

[0352] In some embodiments, such as Figure 7 As shown, the third type of gate circuit 22c also includes a third capacitor C3. One plate of the third capacitor C3 is electrically connected to the third pull-up node Q3[n], and the other plate of the third capacitor C3 is electrically connected to the third signal output terminal REF[n] of the third type of gate circuit 22c.

[0353] Specifically, the third capacitor C3 includes a first plate C3a and a second plate C3b. The first plate C3a includes a first part C3a1 and a second part C3a2.

[0354] In some embodiments, such as Figure 7 As shown, the third type of gate circuit 22c also includes a fourth capacitor C4. One plate of the fourth capacitor C4 is electrically connected to the first high-potential signal line VGH1, and the other plate of the fourth capacitor C4 is electrically connected to the second electrode T51rD of the eleventh inverting transistor T51r.

[0355] Specifically, the fourth capacitor C4 includes the first plate C4a and the second plate C4b of the fourth capacitor C4.

[0356] In some embodiments, such as Figure 36 , Figure 37 As shown, the display panel 2 includes a light-shielding layer 212, which includes a first part C3a1 of the first plate C3a of the third capacitor C3, a first part C4a1 of the first plate C4a of the fourth capacitor C4, a fourth light-shielding connection line LS4, a fifth light-shielding connection line LS5, and a first signal output terminal Gn[n-1] of the previous first-level first-type gate circuit 22a.

[0357] The first portion C4a1 of the first plate C4a of the fourth capacitor C4, the fourth shielding connection line LS4, the first signal output terminal Gn[n-1] of the previous first type gate circuit 22a, and the first portion C3a1 of the first plate C3a of the third capacitor C3 are arranged along the first direction X; the fourth shielding connection line LS4 and the fifth shielding connection line LS5 are arranged along the second direction Y.

[0358] In some embodiments, such as Figure 36 , Figure 38 As shown, the display panel 2 includes an active layer 216, which includes the active portion T11rA of the seventh pull-up control transistor T11r, the active portion T12rA of the eighth pull-up control transistor T12r, the active portion T21rA of the fifth pull-up transistor T21r, the active portion T31rA of the seventh pull-down transistor T31r, the active portion T41rA of the eighth pull-down transistor T41r, and the active portion T4 of the third pull-down sustaining transistor T42r. 2rA, the active part T51rA of the eleventh inverting transistor T51r, the active part T52rA of the twelfth inverting transistor T52r, the active part T53rA of the thirteenth inverting transistor T53r, the active part T54rA of the fourteenth inverting transistor T54r, the active part T55rA of the fifteenth inverting transistor T55r, the active part T56rA of the sixteenth inverting transistor T56r, and the active part T61rA of the third anti-negative bias transistor T61r;

[0359] The active portions T51rA of the eleventh inverting transistor T51r and T53rA of the thirteenth inverting transistor T53r are arranged sequentially along the second direction Y with the active portions T54rA of the fourteenth inverting transistor T54r, the active portion T11rA of the seventh pull-up control transistor T11r, and the active portion T12rA of the eighth pull-up control transistor T12r.

[0360] The active portions T52rA of the twelfth inverting transistor T52r, T56rA of the sixteenth inverting transistor T56r, T55rA of the fifteenth inverting transistor T55r, T42rA of the third pull-down holding transistor T42r, and T41rA of the eighth pull-down transistor T41r are arranged sequentially along the second direction Y.

[0361] The active portion T21rA of the fifth pull-up transistor T21r and the active portion T61rA of the third anti-negative bias transistor T61r are arranged sequentially along the second direction Y.

[0362] The active portion T51rA of the eleventh inverting transistor T51r, the active portion T53rA of the thirteenth inverting transistor T53r, the active portion T52rA of the twelfth inverting transistor T52r, the active portion T21rA of the fifth pull-up transistor T21r, and the active portion T31rA of the seventh pull-down transistor T31r are arranged sequentially along the first direction X.

[0363] Specifically, such as Figure 38 As shown, the active portion T41rA of the eighth pull-down transistor T41r includes the active portion T41r1A of the fifth pull-down sub-transistor T41r1 and the active portion T41r2A of the sixth pull-down sub-transistor T41r2, which are arranged along the second direction.

[0364] Specifically, such as Figure 38 As shown, the active portion of the fifth pull-down sustaining transistor includes the active portion T42r1A of the fifth pull-down sustaining sub-transistor T42r1 and the active portion T42r2A of the sixth pull-down sustaining sub-transistor T42r2. The active portion T42r1A of the fifth pull-down sustaining sub-transistor T42r1 and the active portion T42r2A of the sixth pull-down sustaining sub-transistor T42r2 are arranged along the second direction.

[0365] Specifically, such as Figure 38 As shown, the active portion T51rA of the eleventh inverting transistor T51r includes the active portion T51r1A of the fifth inverting sub-transistor T51r1 and the active portion T51r2A of the sixth inverting sub-transistor T51r2. The active portion T51r1A of the fifth inverting sub-transistor T51r1 and the active portion T51r2A of the sixth inverting sub-transistor T51r2 are arranged along a first direction.

[0366] Specifically, such as Figure 38As shown, the active portion T52rA of the twelfth inverting transistor T52r includes the active portion T52r1A of the seventh inverting sub-transistor T52r1 and the active portion T52r2A of the eighth inverting sub-transistor T52r2, which are arranged along a first direction.

[0367] Specifically, such as Figure 38 As shown, the active portion T61rA of the third anti-negative bias transistor T61r includes the active portion T61r1A of the fifth anti-negative bias transistor T61r1 and the active portion T61r2A of the sixth anti-negative bias transistor T61r2. The active portion T61r1A of the fifth anti-negative bias transistor T61r1 and the active portion T61r2A of the sixth anti-negative bias transistor T61r2 are arranged along the second direction.

[0368] In some embodiments, such as Figure 36 , Figure 39 As shown, the display panel 2 includes a first gate layer 218, which includes the gate T11rG of the seventh pull-up control transistor T11r, the gate T12rG of the eighth pull-up control transistor T12r, the gate T21rG of the fifth pull-up transistor T21r, the gate T31rG of the seventh pull-down transistor T31r, the gate T41rG of the eighth pull-down transistor T41r, the gate T42rG of the third pull-down sustaining transistor T42r, and the eleventh inverting transistor T11rG. Gate T51rG of 51r, gate T52rG of the twelfth inverting transistor T52r, gate T53rG of the thirteenth inverting transistor T53r, gate T54rG of the fourteenth inverting transistor T54r, gate T55rG of the fifteenth inverting transistor T55r, gate T56rG of the sixteenth inverting transistor T56r, gate T61rG of the third anti-negative bias transistor T61r, second plate C3b of the third capacitor C3, and second plate C4b of the fourth capacitor C4;

[0369] The gates T51rG of the eleventh inverting transistor T51r and the gates T53rG of the thirteenth inverting transistor T53r are arranged sequentially along the second direction Y with the gates T54rG of the fourteenth inverting transistor T54r, the gate T11rG of the seventh pull-up control transistor T11r, and the gate T12rG of the eighth pull-up control transistor T12r.

[0370] The gates T52rG of the twelfth inverting transistor T52r, T56rG of the sixteenth inverting transistor T56r, T55rG of the fifteenth inverting transistor T55r, T42rG of the third pull-down holding transistor T42r, and T41rG of the eighth pull-down transistor T41r are arranged sequentially along the second direction Y.

[0371] The gate T21rG of the fifth pull-up transistor T21r, the gate T61rG of the third anti-negative bias transistor T61r, and a portion of the second plate C3b of the third capacitor C3 are sequentially arranged along the second direction Y.

[0372] The gate T53rG of the thirteenth inverting transistor T53r and the second plate C4b of the fourth capacitor C4 are arranged sequentially along the second direction Y.

[0373] The gate T31rG of the seventh pull-down transistor T31r and a portion of the second plate C3b of the third capacitor C3 are sequentially arranged along the second direction Y.

[0374] The gates T51rG of the eleventh inverting transistor T51r, T53rG of the thirteenth inverting transistor T53r, T52rG of the twelfth inverting transistor T52r, T21rG of the fifth pull-up transistor T21r, and T31rG of the seventh pull-down transistor T31r are sequentially arranged along the first direction X.

[0375] Specifically, such as Figure 39 As shown, the gate T41rG of the eighth pull-down transistor T41r includes the gate T41r1G of the fifth pull-down sub-transistor T41r1 and the gate T41r2G of the sixth pull-down sub-transistor T41r2, which are arranged along the second direction.

[0376] Specifically, such as Figure 39 As shown, the gate of the fifth pull-down sustaining transistor includes the gate T42r1G of the fifth pull-down sustaining sub-transistor T42r1 and the gate T42r2G of the sixth pull-down sustaining sub-transistor T42r2, which are arranged along the second direction.

[0377] Specifically, such as Figure 39 As shown, the gate T51rG of the eleventh inverting transistor T51r includes the gate T51r1G of the fifth inverting sub-transistor T51r1 and the gate T51r2G of the sixth inverting sub-transistor T51r2, and the gate T51r1G of the fifth inverting sub-transistor T51r1 and the gate T51r2G of the sixth inverting sub-transistor T51r2 are arranged along a first direction.

[0378] Specifically, such as Figure 39As shown, the gate T52rG of the twelfth inverting transistor T52r includes the gate T52r1G of the seventh inverting sub-transistor T52r1 and the gate T52r2G of the eighth inverting sub-transistor T52r2, which are arranged along a first direction.

[0379] Specifically, such as Figure 39 As shown, the gate T61rG of the third anti-negative bias transistor T61r includes the gate T61r1G of the fifth anti-negative bias transistor T61r1 and the gate T61r2G of the sixth anti-negative bias transistor T61r2, and the gate T61r1G of the fifth anti-negative bias transistor T61r1 and the gate T61r2G of the sixth anti-negative bias transistor T61r2 are arranged along a first direction.

[0380] In some embodiments, Figure 36 , Figure 40As shown, the display panel 2 includes a first source-drain layer 221, which includes the first electrode T11rS of the seventh pull-up control transistor T11r, the first electrode T12rS of the eighth pull-up control transistor T12r, the first electrode T21rS of the fifth pull-up transistor T21r, the first electrode T31rS of the seventh pull-down transistor T31r, the first electrode T41rS of the eighth pull-down transistor T41r, and the first electrode T42r of the third pull-down sustaining transistor T42r. S, the first electrode of the eleventh inverter transistor T51r, T51rS; the first electrode of the twelfth inverter transistor T52r, T52rS; the first electrode of the thirteenth inverter transistor T53r, T53rS; the first electrode of the fourteenth inverter transistor T54r, T54rS; the first electrode of the fifteenth inverter transistor T55r, T55rS; the first electrode of the sixteenth inverter transistor T56r, T56rS; the first electrode of the third anti-negative bias transistor T61r, T61rS; the seventh pull-up control transistor. The second electrode T11rD of T11r, the second electrode T12rD of the eighth pull-up control transistor T12r, the second electrode T21rD of the fifth pull-up transistor T21r, the second electrode T31rD of the seventh pull-down transistor T31r, the second electrode T41rD of the eighth pull-down transistor T41r, the second electrode T42rD of the third pull-down sustaining transistor T42r, the second electrode T51rD of the eleventh inverting transistor T51r, and the second electrode T52r of the twelfth inverting transistor T52r. 2rD, the second electrode of the thirteenth inverting transistor T53r, the second electrode of the fourteenth inverting transistor T54r, the second electrode of the fifteenth inverting transistor T55r, the second electrode of the sixteenth inverting transistor T56r, the second electrode of the third anti-negative bias transistor T61r, the second part of the first plate C3a of the third capacitor C3 (C3a2), the second part of the first plate C4a of the fourth capacitor C4 (C4a2), and the ninth source connection line LD9;

[0381] The first electrode T51rS of the eleventh inverting transistor T51r, the first electrode T53rS of the thirteenth inverting transistor T53r, the first electrode T54rS of the fourteenth inverting transistor T54r, the first electrode T11rS of the seventh pull-up control transistor T11r, and the first electrode T12rS of the eighth pull-up control transistor T12r are arranged sequentially along the second direction Y.

[0382] The first electrode T52rS of the twelfth inverting transistor T52r, the first electrode T56rS of the sixteenth inverting transistor T56r, the first electrode T55rS of the fifteenth inverting transistor T55r, the first electrode T42rS of the third pull-down holding transistor T42r, and the first electrode T41rS of the eighth pull-down transistor T41r are arranged sequentially along the second direction Y.

[0383] The first electrode T21rS of the fifth pull-up transistor T21r and the first electrode T61rS of the third anti-negative bias transistor T61r are sequentially arranged along the second direction Y.

[0384] The first electrode T51rS of the eleventh inverting transistor T51r, the first electrode T53rS of the thirteenth inverting transistor T53r, the first electrode T52rS of the twelfth inverting transistor T52r, the first electrode T21rS of the fifth pull-up transistor T21r, and the first electrode T31rS of the seventh pull-down transistor T31r are arranged sequentially along the first direction X.

[0385] The fourth shielding connection line LS4 connects the first electrode T41rS of the eighth pull-down transistor T41r and the first electrode T55rS of the fifteenth inverting transistor T55r; the fifth shielding connection line LS5 connects the first electrode T11rS of the seventh pull-up control transistor T11r and the first electrode T61rS of the third anti-negative bias transistor T61r; the ninth source connection line LD9 connects the gate T41rG of the eighth pull-down transistor T41r and the first signal output terminal Gn[n-1] of the previous stage first type gate circuit 22a.

[0386] Specifically, in the circuit diagrams of the embodiments of this application, each transistor has a gate, a first electrode, and a second electrode to illustrate the connection relationship of each transistor. However, in actual design, in order to reduce the space occupied by the transistors, the electrodes of some transistors will be formed using the same structure. It can be understood that this structure can be regarded as the electrodes of two transistors. Similarly, the structure of the electrodes of other transistors can be determined.

[0387] Specifically, such as Figures 36 to 41 As shown, the first part C3a1 of the first plate C3a of the third capacitor C3 is connected to the second part C3a2 of the first plate C3a of the third capacitor C3.

[0388] Specifically, such as Figures 36 to 41 As shown, the first part C4a1 of the first plate C4a of the fourth capacitor C4 is connected to the second part C4a2 of the first plate C4a of the fourth capacitor C4.

[0389] Specifically, such as Figure 40As shown, the first source-drain layer 221 includes the first electrode T41r1S of the fifth pull-down sub-tube T41r1, the second electrode T41r1D of the fifth pull-down sub-tube T41r1, the first electrode of the sixth pull-down sub-tube T41r2, and the second electrode T41r2D of the sixth pull-down sub-tube T41r2. The first electrode T41r1S of the fifth pull-down sub-tube T41r1, the second electrode T41r1D of the fifth pull-down sub-tube T41r1, and the second electrode T41r2D of the sixth pull-down sub-tube T41r2 are arranged sequentially along the second direction.

[0390] Specifically, such as Figure 40 As shown, the first source-drain layer 221 includes the first electrode of the fifth pull-down sustaining sub-transistor T42r1, the second electrode T42r1D of the fifth pull-down sustaining sub-transistor T42r1, the first electrode T42r2S of the sixth pull-down sustaining sub-transistor T42r2, and the second electrode T42r2D of the sixth pull-down sustaining sub-transistor T42r2. The first electrode T42r2S of the sixth pull-down sustaining sub-transistor T42r2, the second electrode T42r2D of the sixth pull-down sustaining sub-transistor T42r2, and the second electrode T42r1D of the fifth pull-down sustaining sub-transistor T42r1 are arranged sequentially along the second direction.

[0391] Specifically, such as Figure 40 As shown, the first source-drain layer 221 includes the first electrode T51r1S of the fifth inverting sub-transistor T51r1, the second electrode T51r1D of the fifth inverting sub-transistor T51r1, the first electrode of the sixth inverting sub-transistor T51r2, and the second electrode T51r2D of the sixth inverting sub-transistor T51r2. The first electrode T51r1S of the fifth inverting sub-transistor T51r1, the second electrode T51r1D of the fifth inverting sub-transistor T51r1, and the second electrode T51r2D of the sixth inverting sub-transistor T51r2 are arranged sequentially along a first direction.

[0392] Specifically, such as Figure 40 As shown, the first source-drain layer 221 includes the first electrode T52r1S of the seventh inverting sub-transistor T52r1, the second electrode T52r1D of the seventh inverting sub-transistor T52r1, the first electrode of the eighth inverting sub-transistor T52r2, and the second electrode T52r2D of the eighth inverting sub-transistor T52r2. The first electrode T52r1S of the seventh inverting sub-transistor T52r1, the second electrode T52r1D of the seventh inverting sub-transistor T52r1, and the second electrode T52r2D of the eighth inverting sub-transistor T52r2 are arranged sequentially along a first direction.

[0393] Specifically, such as Figure 40As shown, the first source-drain layer 221 includes the first electrode of the fifth anti-negative bias tube T61r1, the second electrode T61r1D of the fifth anti-negative bias tube T61r1, the first electrode T61r2S of the sixth anti-negative bias tube T61r2, and the second electrode T61r2D of the sixth anti-negative bias tube T61r2. The second electrode T61r1D of the fifth anti-negative bias tube T61r1, the second electrode T61r2D of the sixth anti-negative bias tube T61r2, and the first electrode T61r2S of the sixth anti-negative bias tube T61r2 are arranged sequentially along the second direction.

[0394] In some embodiments, such as Figure 36 , Figure 41 As shown, the display panel 2 includes a second source-drain layer 223, which includes a first high-potential signal line VGH1, a third clock signal line CKC, a second high-potential signal line VGH2, and a third low-potential signal line VGL3 arranged sequentially along the first direction X.

[0395] Specifically, the signals output on the first low-potential signal line VGL1, the second low-potential signal line VGL2, and the third low-potential signal line VGL3 can be different.

[0396] Specifically, the output signals on the first high-potential signal line VGH1 and the second high-potential signal line VGH2 can be different.

[0397] Specifically, in the embodiments of this application, the first signal output terminal Gn[m] of another stage of the first type gate circuit 22a can be the first signal output terminal of the next few stages of the first type gate circuit 22a. For example, the first signal output terminal Gn[m] of another stage of the first type gate circuit 22a can be the first signal output terminal of the next stage of the first type gate circuit 22a. Taking n as 3 as an example, m can be 4. However, the embodiments of this application are not limited to this. The first signal output terminal Gn[m] of another stage of the first type gate circuit 22a can be the first signal output terminal of the next two stages of the first type gate circuit 22a or the first signal output terminal of other stages of the first type gate circuit 22a.

[0398] Specifically, the above embodiments are illustrated using the example of some transistors including two sub-transistors, but the embodiments of this application are not limited to this, and each transistor may include only one sub-transistor.

[0399] Specifically, such as Figure 4 As shown, Figure 4The present invention provides a pixel driving circuit 21 for a display panel 2. The pixel driving circuit 21 includes a driving transistor T1, a switching transistor T2, a reset transistor T3 and an initialization transistor T4. The driving transistor T1, the switching transistor T2 and the reset transistor T3 are connected to a first pixel node g, and the driving transistor T1 and the initialization transistor T4 are connected to a second pixel node s.

[0400] Specifically, the gate of the switching transistor T2 is electrically connected to the first signal output terminal Gn[n] of the first type gate circuit 22a of this stage; the gate of the initialization transistor T4 is electrically connected to the second signal output terminal INI[n] of the second type gate circuit 22b of this stage; and the gate of the reset transistor T3 is electrically connected to the third signal output terminal REF[n] of the third type gate circuit 22c of this stage. By electrically connecting the gates of the switching transistor, the initialization transistor, and the reset transistor to the first signal output terminal Gn[n] of the first type gate circuit 22a, the second signal output terminal INI[n] of the second type gate circuit 22b, and the third signal output terminal REF[n] of the third type gate circuit 22c of this stage, respectively, signals can be input to the pixel driving circuit 21 through the gate driving circuit 22, enabling the pixel driving circuit 21 to operate normally.

[0401] Specifically, such as Figure 2 As shown, the display panel 2 also includes a light-emitting device (LED). The gate of the driving transistor T1 is connected to the first node g, the first electrode of the driving transistor T1 is connected to the high-potential power supply line VDD, the second electrode of the driving transistor T1 is connected to the second node s, the first electrode of the switching transistor T2 is connected to the data line Vdata, the second electrode of the switching transistor T2 is connected to the first node g, the first electrode of the reset transistor T3 is connected to the reference line Vref, the second electrode of the reset transistor T3 is connected to the first node g, the first electrode of the initialization transistor T4 is connected to the initialization signal line Vini, the second electrode of the initialization transistor T4 is connected to the positive terminal of the light-emitting device (LED), and the negative terminal of the light-emitting device (LED) is connected to the low-potential power supply line VSS.

[0402] Specifically, it can be understood that the display panel 2 includes multiple rows of sub-pixels, and a corresponding multi-row pixel driving circuit 21 is set to drive each sub-pixel. A corresponding multi-level gate driving circuit 22 is also set, and each level of gate driving circuit 22 can be connected to one or two rows of pixel driving circuits 21.

[0403] Specifically, in the gate driving circuit 22 of this application embodiment, each transistor can be an N-type transistor or a P-type transistor. Similarly, in the pixel driving circuit 21 of this application embodiment, each transistor can be an N-type transistor or a P-type transistor.

[0404] Specifically, in the gate driving circuit 22 of this application embodiment, the active portion of each transistor can be formed using an active layer 216. In the pixel driving circuit 21 of this application embodiment, the active portion of each transistor can be formed using a semiconductor layer 214, or it can be partially formed using a semiconductor layer 214 and partially formed using an active layer 216.

[0405] Specifically, the first electrode can be the source and the second electrode can be the drain; or the first electrode can be the drain and the second electrode can be the source.

[0406] Specifically, the above embodiments have provided a detailed description of the display panel 2 from aspects such as circuit, timing, and transistor design. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the first reset control line is disposed on the second source-drain layer, and the low-frequency signal line is disposed on the second source-drain layer.

[0407] Meanwhile, this application provides a display device, which includes a display panel 2 as described in any of the above embodiments.

[0408] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0409] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0410] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0411] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Multiple rows of pixels, each pixel including a light-emitting device and a pixel driving circuit including a switching transistor; A multi-stage gate driving circuit is electrically connected to the corresponding pixel driving circuit. Each stage of the gate driving circuit includes a first type of gate circuit. The first signal output terminal of the first type of gate circuit is electrically connected to the switching transistor. The first type of gate circuit includes a first pull-up control module, a first pull-up module, a first pull-down module, a first pull-down sustaining module, a first inverting module, a first anti-negative bias module, and a first reset module. The first pull-up control module and the first pull-up module are electrically connected to the first pull-up node of the first type of gate circuit. The first pull-down module is electrically connected to the first pull-up node and the first signal output terminal of the first type of gate circuit at this stage. The first pull-down sustaining module is electrically connected between the first pull-up node and the first low-potential signal line of the display panel. The first inverting module is electrically connected to the first pull-up node, the first low-potential signal line, and the low-frequency signal line of the display panel. The first anti-negative bias module is electrically connected between the first high-potential signal line of the display panel and the first pull-up node. The first reset module is electrically connected between the first pull-up node and the first low-potential signal line. The pixel driving circuit and the first type of gate circuit are arranged along a first direction, and a part of the first pull-up control module, a part of the first inverting module, the first anti-negative bias module and the first reset module are arranged along a second direction. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The first inverting module and the first pull-down sustaining module are electrically connected to the first pull-down node. The first inverting module is configured to invert the potentials of the first pull-up node and the first pull-down node. The first negative bias protection module is electrically connected to the first pull-down module, the first pull-down sustaining module, and the first reset module to the first internal node. The first negative bias protection module is configured to be controlled by the signal of the first pull-up node and output the signal of the first high-potential signal line to the first internal node. The first internal node acts on the transistors in the first pull-down module, the first pull-down sustaining module, and the first reset module to prevent leakage when the threshold voltage of the transistors is negatively biased.

2. The display panel according to claim 1, characterized in that, Another part of the first pull-up control module, another part of the first inverting module, and the first pull-down sustaining module are arranged along the second direction.

3. The display panel according to claim 2, characterized in that, Another part of the first pull-up control module, another part of the first inverting module, and a part of the first pull-down module are arranged along the second direction, and the first reset module, the first pull-down maintenance module, and a part of the first pull-down module are arranged along the first direction.

4. The display panel according to claim 3, characterized in that, A portion of the first pull-up module and another portion of the first pull-down module are positioned along the second direction.

5. The display panel according to claim 1, characterized in that, The first pull-up control module includes a first pull-up control transistor, a second pull-up control transistor, and a third pull-up control transistor. The gate of the first pull-up control transistor is electrically connected to the stage output terminal of the two previous first-type gate circuits. The first electrode of the first pull-up control transistor is electrically connected to the first high-potential signal line. The second electrode of the first pull-up control transistor is electrically connected to the first electrode of the second pull-up control transistor. The gate of the second pull-up control transistor is electrically connected to the stage output terminal of the two previous first-type gate circuits. The second electrode of the second pull-up control transistor is electrically connected to the first pull-up node. The gate of the third pull-up control transistor is electrically connected to the first high-potential signal line. The first electrode of the third pull-up control transistor is electrically connected to the first high-potential signal line. The second electrode of the third pull-up control transistor is electrically connected to the second electrode of the first pull-up control transistor. In each stage of the gate drive circuit, the first pull-up control transistor and the second pull-up control transistor are arranged sequentially along the second direction, and the first pull-up control transistor and the third pull-up control transistor are arranged sequentially along the first direction.

6. The display panel according to claim 5, characterized in that, The third pull-up control transistor includes a first pull-up control sub-transistor and a second pull-up control sub-transistor. The gate and first electrode of the second pull-up control sub-transistor are electrically connected to the first high-potential signal line. The second electrode of the second pull-up control sub-transistor is electrically connected to the first electrode of the first pull-up control sub-transistor. The gate of the first pull-up control sub-transistor is electrically connected to the first high-potential signal line. The second electrode of the first pull-up control sub-transistor is electrically connected to the second electrode of the first pull-up control transistor. The first pull-up control sub-tube and the second pull-up control sub-tube are arranged along the second direction.

7. The display panel according to claim 5, characterized in that, The first pull-down module includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor. The gate of the first pull-down transistor is electrically connected to the first pull-down node of the first type of gate circuit. The first electrode of the first pull-down transistor is electrically connected to the first low-potential signal line. The second electrode of the first pull-down transistor is electrically connected to the stage output terminal of the first type of gate circuit. The gate of the second pull-down transistor is electrically connected to the first pull-down node. The first electrode of the second pull-down transistor is electrically connected to the second low-potential signal line of the display panel. The electrode is electrically connected to the first signal output terminal of another first-type gate circuit. The gate of the third pull-down transistor is electrically connected to the first pull-down node. The first electrode of the third pull-down transistor is electrically connected to the second low-potential signal line. The second electrode of the third pull-down transistor is electrically connected to the first signal output terminal of the first-type gate circuit of this stage. The gate of the fourth pull-down transistor is electrically connected to the stage output terminal of the next two first-type gate circuits. The first electrode of the fourth pull-down transistor is electrically connected to the first low-potential signal line. The second electrode of the fourth pull-down transistor is electrically connected to the first pull-up node. The first pull-down transistor and the fourth pull-down transistor are arranged along the second direction, and the second pull-down transistor and the third pull-down transistor are arranged along the second direction.

8. The display panel according to claim 7, characterized in that, The fourth pull-down transistor includes a first pull-down sub-transistor and a second pull-down sub-transistor. The gate of the second pull-down sub-transistor is electrically connected to the stage output terminal of the next two stages of the first type of gate circuit. The first electrode of the second pull-down sub-transistor is electrically connected to the first low-potential signal line. The second electrode of the second pull-down sub-transistor is electrically connected to the first electrode of the first pull-down sub-transistor at a first internal node. The gate of the first pull-down sub-transistor is electrically connected to the stage output terminal of the next two stages of the first type of gate circuit. The second electrode of the first pull-down sub-transistor is electrically connected to the first pull-up node. The first pull-down sub-tube and the second pull-down sub-tube are arranged along the second direction.

9. The display panel according to claim 7, characterized in that, The first inverting module includes a first inverting transistor, a second inverting transistor, a third inverting transistor, a fourth inverting transistor, and a fifth inverting transistor. The gate and first electrode of the first inverting transistor are electrically connected to a low-frequency signal line. The second electrode of the first inverting transistor is electrically connected to the second electrode of the second inverting transistor. The gate of the second inverting transistor is electrically connected to the first pull-up node. The first electrode of the second inverting transistor is electrically connected to the first low-potential signal line. The gate of the third inverting transistor is electrically connected to the second electrode of the first inverting transistor. One electrode is electrically connected to the low-frequency signal line; the second electrode of the third inverting transistor is electrically connected to the first pull-down node; the gate of the fourth inverting transistor is electrically connected to the first pull-up node; the first electrode of the fourth inverting transistor is electrically connected to the first low-potential signal line; the second electrode of the fourth inverting transistor is electrically connected to the first pull-down node; the gate of the fifth inverting transistor is electrically connected to the stage output terminal of the two-stage first-type gate circuit; the first electrode of the fifth inverting transistor is electrically connected to the first low-potential signal line; and the second electrode of the fifth inverting transistor is electrically connected to the first pull-down node. The first and second inverting transistors are arranged along the second direction, the third and fourth inverting transistors are arranged along the second direction, and the first and third inverting transistors are arranged along the first direction.

10. The display panel according to claim 9, characterized in that, The first inverting transistor includes a first inverting sub-transistor and a second inverting sub-transistor. The gate of the first inverting sub-transistor and the first electrode of the first inverting sub-transistor are electrically connected to the low-frequency signal line. The second electrode of the first inverting sub-transistor is electrically connected to the first electrode of the second inverting sub-transistor. The gate of the second inverting sub-transistor is electrically connected to the low-frequency signal line. The second electrode of the second inverting sub-transistor is electrically connected to the second electrode of the second inverting transistor. The first inverting sub-tube and the second inverting sub-tube are arranged along a first direction.

11. The display panel according to claim 9, characterized in that, The first pull-down sustaining module includes a first pull-down sustaining transistor, the gate of the first pull-down sustaining transistor is electrically connected to a first pull-down node, the first electrode of the first pull-down sustaining transistor is electrically connected to the first low-potential signal line, and the second electrode of the first pull-down sustaining transistor is electrically connected to the first pull-up node. In the second direction, the first pull-down holding transistor is disposed between the fourth inverting transistor and the second pull-up control transistor.

12. The display panel according to claim 11, characterized in that, The first pull-down sustaining transistor includes a first pull-down sustaining sub-transistor and a second pull-down sustaining sub-transistor. The gate of the second pull-down sustaining sub-transistor is electrically connected to the first pull-down node. The first electrode of the second pull-down sustaining sub-transistor is electrically connected to the first low-potential signal line. The second electrode of the second pull-down sustaining sub-transistor is electrically connected to the first electrode of the first pull-down sustaining sub-transistor at a first internal node. The gate of the first pull-down sustaining sub-transistor is electrically connected to the first pull-down node. The second electrode of the first pull-down sustaining sub-transistor is electrically connected to the first pull-up node. The first pull-down support sub-tube and the second pull-down support sub-tube are arranged along the second direction.

13. The display panel according to claim 11, characterized in that, The first reset module includes a first reset transistor, the gate of the first reset transistor is electrically connected to the first reset control line of the display panel, the first electrode of the first reset transistor is electrically connected to the first low-potential signal line, and the second electrode of the first reset transistor is electrically connected to the first pull-up node. The first reset transistor is disposed between the second inverting transistor and the third pull-up control transistor.

14. The display panel according to claim 13, characterized in that, The first reset transistor includes a first reset sub-transistor and a second reset sub-transistor. The gate of the second reset sub-transistor is electrically connected to the first reset control line. The first electrode of the second reset sub-transistor is electrically connected to the first low-potential signal line. The second electrode of the first reset sub-transistor is electrically connected to the first electrode of the first reset sub-transistor at a first internal node. The gate of the first reset sub-transistor is electrically connected to the first reset control line. The second electrode of the first reset sub-transistor is electrically connected to the first pull-up node. The first reset tube and the second reset tube are arranged along the second direction.

15. The display panel according to claim 13, characterized in that, The first negative bias protection module includes a first negative bias protection transistor, the gate of the first negative bias protection transistor is electrically connected to the first pull-up node, the first electrode of the first negative bias protection transistor is electrically connected to the first high-potential signal line, and the second electrode of the first negative bias protection transistor is electrically connected to the first internal node. The first anti-negative bias transistor is disposed along the second direction between the first reset transistor and the third pull-up control transistor.

16. The display panel according to claim 15, characterized in that, The first anti-negative bias transistor includes a first anti-negative bias sub-transistor and a second anti-negative bias sub-transistor. The gate of the second anti-negative bias sub-transistor is electrically connected to the first pull-up node. The first electrode of the second anti-negative bias sub-transistor is electrically connected to the first high-potential signal line. The second electrode of the second anti-negative bias sub-transistor is electrically connected to the first electrode of the first anti-negative bias sub-transistor. The gate of the first anti-negative bias sub-transistor is electrically connected to the first pull-up node. The second electrode of the first anti-negative bias sub-transistor is electrically connected to the first internal node. The first anti-negative deviation tube and the second anti-negative deviation tube are arranged along the second direction.

17. The display panel according to claim 15, characterized in that, The display panel includes a first clock signal line and a second clock signal line. The second clock signal line includes a first group of sub-lines and a second group of sub-lines. The first pull-up module includes a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor. The gate of the first pull-up transistor is electrically connected to the first pull-up node. The first electrode of the first pull-up transistor is electrically connected to the first clock signal line. The second electrode of the first pull-up transistor is electrically connected to the stage output terminal of the first type gate circuit of this stage. The gate of the second pull-up transistor is electrically connected to the first pull-up node. The first electrode of the second pull-up transistor is electrically connected to the first group of sub-lines. The second electrode of the second pull-up transistor is electrically connected to the first signal output terminal of another type of gate circuit of this stage. The gate of the third pull-up transistor is electrically connected to the first pull-up node. The first electrode of the third pull-up transistor is electrically connected to the second group of sub-lines. The second electrode of the third pull-up transistor is electrically connected to the first signal output terminal of the first type gate circuit of this stage. Wherein, the first pull-up transistor and the second pull-down transistor are arranged along the second direction, the second pull-up transistor and the third pull-up transistor are arranged along the second direction, and the first pull-up transistor and the second pull-up transistor are arranged along the first direction.

18. The display panel according to claim 17, characterized in that, The first inverting transistor, the second inverting transistor, the first reset transistor, the first anti-negative bias transistor, and the third pull-up control transistor are arranged along the second direction; The third inverting transistor, the fourth inverting transistor, the first pull-down sustaining transistor, the second pull-up control transistor, and the first pull-up control transistor are arranged along the second direction; The fifth inverting transistor, the first pull-down transistor, the fourth pull-down transistor, the second pull-up control transistor, and the first pull-up control transistor are arranged along the second direction; The second inverting transistor, the fourth inverting transistor, the fifth inverting transistor, the first pull-up transistor, and the second pull-up transistor are arranged along the first direction.

19. The display panel according to claim 18, characterized in that, The first type of gate circuit further includes a first capacitor, one plate of which is electrically connected to a first pull-up node, and the other plate of which is electrically connected to the stage output terminal of the first type of gate circuit.

20. The display panel according to claim 19, characterized in that, The display panel includes a light-shielding layer, which includes a first light-shielding connection line, a second light-shielding connection line, a stage transmission output terminal of the first type of gate circuit, and a first portion of the first plate of the first capacitor.

21. The display panel according to claim 20, characterized in that, The display panel includes an active layer, which includes an active portion of a first pull-up control transistor, an active portion of a second pull-up control transistor, an active portion of a third pull-up control transistor, an active portion of a first pull-up transistor, an active portion of a second pull-up transistor, an active portion of a third pull-up transistor, an active portion of a first pull-down transistor, an active portion of a second pull-down transistor, an active portion of a third pull-down transistor, an active portion of a fourth pull-down transistor, an active portion of a first pull-down holding transistor, an active portion of a first inverting transistor, an active portion of a second inverting transistor, an active portion of a third inverting transistor, an active portion of a fourth inverting transistor, an active portion of a fifth inverting transistor, an active portion of a first reset transistor, and an active portion of a first anti-negative bias transistor. The active portion of the first inverting transistor, the active portion of the second inverting transistor, the active portion of the first reset transistor, the active portion of the first anti-negative bias transistor, and the active portion of the third pull-up control transistor are arranged sequentially along the second direction. The active portion of the third inverting transistor, the active portion of the fourth inverting transistor, the active portion of the first pull-down holding transistor, the active portion of the second pull-up control transistor, and the active portion of the first pull-up control transistor are arranged sequentially along the second direction. The active portion of the fifth inverting transistor, the active portion of the first pull-down transistor, the active portion of the fourth pull-down transistor, the active portion of the second pull-up control transistor, and the active portion of the first pull-up control transistor are arranged sequentially along the second direction. The active portion of the first pull-up transistor, the active portion of the third pull-down transistor, and the active portion of the second pull-down transistor are arranged sequentially along the second direction; The active portion of the second pull-up transistor and the active portion of the third pull-up transistor are arranged sequentially along the second direction; The active portions of the second inverting transistor, the fourth inverting transistor, the fifth inverting transistor, the first pull-up transistor, and the second pull-up transistor are arranged sequentially along a first direction.

22. The display panel according to claim 21, characterized in that, The display panel includes a first gate layer, which includes the gate of a first pull-up control transistor, the gate of a second pull-up control transistor, the gate of a third pull-up control transistor, the gate of a first pull-up transistor, the gate of a second pull-up transistor, the gate of a third pull-up transistor, the gate of a first pull-down transistor, the gate of a second pull-down transistor, the gate of a third pull-down transistor, the gate of a fourth pull-down transistor, the gate of a first pull-down holding transistor, the gate of a first inverting transistor, the gate of a second inverting transistor, the gate of a third inverting transistor, the gate of a fourth inverting transistor, the gate of a fifth inverting transistor, the gate of a first reset transistor, the gate of a first anti-negative bias transistor, and a first gate connection line. The gates of the first inverting transistor, the second inverting transistor, the first reset transistor, the first anti-negative bias transistor, and the third pull-up control transistor are arranged sequentially along the second direction. The gates of the third inverting transistor, the fourth inverting transistor, the first pull-down holding transistor, the second pull-up control transistor, and the first pull-up control transistor are arranged sequentially along the second direction. The gates of the fifth inverting transistor, the first pull-down transistor, the fourth pull-down transistor, the second pull-up control transistor, and the first pull-up control transistor are arranged sequentially along the second direction. The gate of the first pull-up transistor, a portion of the second plate of the first capacitor, the gate of the third pull-down transistor, and the gate of the second pull-down transistor are arranged sequentially along the second direction; The gates of the second pull-up transistor and the third pull-up transistor are arranged sequentially along the second direction; The gate of the second inverting transistor, the gate of the fourth inverting transistor, the gate of the fifth inverting transistor, the gate of the first pull-up transistor, another part of the second plate of the first capacitor, and the gate of the second pull-up transistor are arranged sequentially along the first direction.

23. The display panel according to claim 22, characterized in that, The display panel includes a first source-drain layer, which includes a first electrode of a first pull-up control transistor, a first electrode of a second pull-up control transistor, a first electrode of a third pull-up control transistor, a first electrode of a first pull-up transistor, a first electrode of a second pull-up transistor, a first electrode of a third pull-up transistor, a first electrode of a first pull-down transistor, a first electrode of a second pull-down transistor, a first electrode of a third pull-down transistor, a first electrode of a fourth pull-down transistor, a first electrode of a first pull-down holding transistor, a first electrode of a first inverting transistor, a first electrode of a second inverting transistor, a first electrode of a third inverting transistor, a first electrode of a fourth inverting transistor, a first electrode of a fifth inverting transistor, a first electrode of a first reset transistor, a first electrode of a first anti-negative bias transistor, and a second electrode of a first pull-up control transistor. Electrode, second electrode of the second pull-up control transistor, second electrode of the third pull-up control transistor, second electrode of the first pull-up transistor, second electrode of the second pull-up transistor, second electrode of the third pull-up transistor, second electrode of the first pull-down transistor, second electrode of the second pull-down transistor, second electrode of the third pull-down transistor, second electrode of the fourth pull-down transistor, second electrode of the first pull-down holding transistor, second electrode of the first inverting transistor, second electrode of the second inverting transistor, second electrode of the third inverting transistor, second electrode of the fourth inverting transistor, second electrode of the fifth inverting transistor, second electrode of the first reset transistor, second electrode of the first anti-negative bias transistor, second portion of the first plate of the first capacitor, first source connection line, second source connection line, third source connection line, fourth source connection line, fifth source connection line; The first electrode of the first inverting transistor, the first electrode of the second inverting transistor, the first electrode of the first reset transistor, the first electrode of the first anti-negative bias transistor, and the first electrode of the third pull-up control transistor are arranged sequentially along the second direction. The first electrode of the third inverting transistor, the first electrode of the fourth inverting transistor, the first electrode of the first pull-down holding transistor, the first electrode of the second pull-up control transistor, and the first electrode of the first pull-up control transistor are arranged sequentially along the second direction; The first electrode of the fifth inverting transistor, the first electrode of the first pull-down transistor, the first electrode of the fourth pull-down transistor, the first electrode of the second pull-up control transistor, and the first electrode of the first pull-up control transistor are arranged sequentially along the second direction; The first electrode of the first pull-up transistor, the first electrode of the third pull-down transistor, and the first electrode of the second pull-down transistor are arranged sequentially along the second direction; The first electrode of the second pull-up transistor and the first electrode of the third pull-up transistor are arranged sequentially along the second direction; The first electrode of the second inverting transistor, the first electrode of the fourth inverting transistor, the first electrode of the fifth inverting transistor, the first electrode of the first pull-up transistor, and the first electrode of the second pull-up transistor are arranged sequentially along the first direction; The second source connection line connects the gate of the fifth inverting transistor to the stage transmission signal terminal of the two preceding first-type gate circuits. The third source connection line connects the gate of the second pull-down transistor to the first shielding connection line. The first shielding connection line connects the second electrode of the fifth inverting transistor. The fourth source connection line connects the gate of the fourth pull-down transistor to the stage transmission signal terminal of the two preceding first-type gate circuits. The second shielding connection line connects the first electrode of the fourth inverting transistor to the first electrode of the first pull-down transistor.

24. The display panel according to claim 23, characterized in that, The second clock signal line includes a first set of sub-lines and a second set of sub-lines. The display panel includes a second source-drain layer, which includes a first reset control line, a low-frequency control line, a first clock signal line, a first low-potential signal line, a second clock signal line, and a second low-potential signal line. The first reset control line, the low-frequency control line, the first clock signal line, the first low-potential signal line, the first group of sub-lines, the second low-potential signal line, and the second group of sub-lines are arranged along the first direction; The first reset control line is connected to the gate of the first reset transistor through the first source connection line, the second low-potential signal line is connected to the first gate connection line through the fifth source connection line, and the first gate connection line is connected to the first electrode of the second pull-down transistor.

25. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 24.

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