A dynamic response analysis method for phase-locked loop of island microgrid under distorted voltage

Abstract

The present invention discloses a method for analyzing the dynamic response of a phase-locked loop (PLL) under distorted voltage of an island microgrid, comprising: the phase-locked loop under distorted voltage has a PLL model, the stability margin, dynamic response and anti-interference capability of the PLL model are analyzed, and steady-state performance parameters under distorted voltage are obtained, thereby providing a theoretical basis for timely phase and frequency locking of the grid when a fault occurs in the island microgrid.

Description

Technical Field

[0001] The present invention belongs to the technical field of power grids, and in particular relates to a method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid. Background Art

[0002] With power shortages and development constraints facing islands, a new form of island power grid, the island microgrid, has emerged, leveraging the coordinated control and efficient interaction of power generation, storage, and loads. Based on the island's available energy resources, the island microgrid is a miniature power system designed for island applications and consists of various power generation and supply systems, energy storage equipment, and power electronics.

[0003] Due to the diversity of both the power supply and consumption sides within the system, island microgrids require a large number of power electronic devices, such as transformers, converters, and inverters, to uniformly manage, control, and distribute the power within the system. This inevitably introduces various harmonics into the grid, causing severe voltage distortion. Furthermore, the inverter's on-grid and off-grid switching, coupled with the uncertainty of green energy and the pulsed power characteristics of high-power loads, can further cause grid frequency fluctuations, significantly reducing grid power quality and increasing the difficulty of grid connection control.

[0004] If the island microgrid is connected to the grid, and the voltage frequency and phase of the island microgrid are not synchronized with the main grid, or the voltage frequency and phase of the power consumption side and the power supply side of the island microgrid are not synchronized, the island microgrid cannot be connected to the grid and operate normally. At the same time, the voltage asynchrony will cause a huge voltage drop on both sides of the grid, thereby forming a huge impact current, burning the circuit and destroying the entire power grid system, which requires further improvement. Summary of the Invention

[0005] The present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid, which can analyze the dynamic response of the phase-locked loop under distorted voltage and obtain steady-state performance parameters that can be quickly analyzed under distorted voltage.

[0006] To solve the above problems, the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid, comprising: the phase-locked loop under distorted voltage has a PLL model, and the stability margin, dynamic response, and anti-interference capability of the PLL model are analyzed to obtain steady-state performance parameters under distorted voltage.

[0008] In an optional embodiment of the present invention, the stability margin analysis of the PLL model includes:

[0009] The open-loop transfer function of the PLL model is designed to be

[0010] Among them, ω z is the turning frequency, and ω z =k i / k p ;

[0011] Based on the above formula (1), the PLL phase margin PM is:

[0012] PM=φ z +φ p (2);

[0013] in, And the crossing frequency

[0014] For PM to ω c When we take the partial derivative and make the result zero, we get:

[0015]

[0016] At the same time, the combination of formula (2) can be obtained:

[0017]

[0018] From formula (4), we can get that when ω p and ω z When is a fixed value, When , the PM of PLL is the largest;

[0019] Among them, let ω p =g 2 ω z , g is a constant, and from formula (4) we can get:

[0020]

[0021] From formula (5), the parameters of PLL are g and ω c Determine, combine equations (2) and (5) to get:

[0022]

[0023] When the phase margin of the function curve in equation (6) is selected between 45° and 70°, the stability of the PLL is better, and at this time g∈(2.4,5.6); when g=3.5, PM=58.11.

[0024] In an optional embodiment of the present invention, the dynamic response analysis of the PLL model includes: performing relevant parameter design to obtain the minimum settling time when the phase or frequency jump occurs; combining equations (1) and (5), the PLL open-loop transfer function is:

[0025] From formula (7), we can get the PLL open-loop transfer function G OL (s) is a second-order function with two poles at the origin, so the PLL can lock the phase information without error when the phase changes or the frequency jumps;

[0026] The error transfer function is

[0027] Assuming g = 2ζ + 1, the above formula can be simplified to:

[0028] When the phase changes suddenly (Δθ), the error signal is transformed into:

[0029]

[0030] Similarly, when the frequency jumps (Δω), the error signal is transformed into:

[0031]

[0032] In the time domain, equations (10) and (11) are expressed as follows:

[0033]

[0034]

[0035] From Equations (12) and (13), it can be seen that when the phase changes suddenly or the frequency jumps, the dynamic response of the PLL is related to the crossover frequency ωc under any damping coefficient ζ: c The larger the value, the faster the dynamic response speed of the PLL; c When the value is larger, the anti-interference ability of PLL will decrease, so when selecting ω c When using the CMOS, it is necessary to balance the dynamic response speed and anti-interference ability;

[0036] In the dynamic response of the PLL to phase mutations and frequency jumps when ζ is different, the PLL's response should strike a balance between response speed and overshoot. When ζ is small, the PLL's dynamic response speed is fast but the overshoot is large; conversely, the dynamic response speed is slow but the overshoot is small. The damping coefficient ζ can be selected in the range of 0.6 to 1. At this time, the PLL's dynamic response speed is fast and the overshoot is within the appropriate range. At the same time, ζ has little effect on the PLL's anti-interference ability.

[0037] In an optional embodiment of the present invention, the PLL model anti-interference ability analysis includes: c The selection of is analyzed to make the PLL have better anti-interference ability;

[0038] When using a notch filter, the open-loop transfer function of the PLL has an upper bandwidth BWOL In order to make the passband of PLL not affected by the notch filter, we select ω c ,ω c It should be far away from the notch frequency, generally selected at 1 / 4 to 1 / 5 of the notch frequency, such as 2π·20 to 2π·25rad / s;

[0039] The disturbance closed-loop transfer function of the PLL is designed as:

[0040]

[0041] Assume ζ = 0.707, g = 3.5, V +1 =1, at this time, PLL is different at ω c In the Bode diagram of the perturbation transfer function and the open-loop transfer function, for ω c The perturbation transfer function of the PLL with a constant is the same as the open-loop transfer function at ω c When ω>ω, the amplitude characteristics of the two are the same; when ω>ω c When the attenuation of the two is almost the same; at the required ω c The open-loop function can be used to replace the disturbance function for relevant calculations.

[0042] In an optional embodiment of the present invention, the PLL model anti-interference capability analysis includes: OL (s) Amplitude characteristic analysis, ω d is the lowest disturbance frequency, atten ωd is the attenuation value of the lowest disturbance frequency;

[0043]

[0044] ω p =gω c Bring in:

[0045] From this we can get:

[0046] From formula (17), we can get ω c According to the pre-set suitable atten ωd For a fixed d =6ω=2π·300rad / s, let ω c =2π·25rad / s, g=3.5, atten ωd =-32.29dB, which can meet the PLL requirements, ω c It can be set to 2π·25rad / s;

[0047] ω c The design values ​​of , ζ and g are as follows: ω c=2π·25rad / s, ζ=0.707, g=3.5, from which the parameters of the PLL can be further designed. Cutoff frequency ω p =gω c =2π·87.5rad / s.

[0048] Compared with the prior art, an embodiment of the present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid, which has the following beneficial effects: a method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid, comprising: the phase-locked loop under distorted voltage has a PLL model, and the stability margin, dynamic response and anti-interference capability of the PLL model are analyzed to obtain steady-state performance parameters under distorted voltage, providing a theoretical basis for timely phase and frequency locking of the grid when a fault occurs in the island microgrid. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 This is a function curve diagram of PM with respect to g provided in an embodiment of the present application.

[0051] Figure 2 Schematic diagram of the dynamic response of the PLL with different ζ values ​​and phase mutations provided in the embodiment of the present application.

[0052] Figure 3 Schematic diagram of PLL dynamic response and frequency hopping when ζ is different provided in an embodiment of the present application.

[0053] Figure 4 Schematic diagram of the open-loop transfer function and disturbance closed-loop transfer function curves of the PLL model provided in an embodiment of the present application.

[0054] Figure 5 Different embodiments of the present invention provide c Bode diagram of the open-loop transfer function of the PLL model under

[0055] Figure 6 G provided in the embodiment of this application OL (s) Amplitude characteristic diagram. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0057] An embodiment of the present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid, comprising the following steps: the phase-locked loop under distorted voltage has a PLL model, the stability margin, dynamic response, and anti-interference capability of the PLL model are analyzed, and steady-state performance parameters under distorted voltage are obtained.

[0058] Example 1

[0059] The stability margin analysis of the PLL model includes:

[0060] The open-loop transfer function of the PLL model is designed to be

[0061] Among them, ω z is the turning frequency, and ω z =k i / k p ;

[0062] Based on the above formula (1), the PLL phase margin PM is PM = φ z +φ p (2);

[0063] in, And the crossing frequency

[0064] For PM to ω c When we find the partial derivative and make the result zero, we get

[0065] At the same time, the combination of formula (2) can be obtained:

[0066] From formula (4), we can get that when ω p and ω z When is a fixed value, When , the PM of PLL is the largest;

[0067] Among them, let ω p =g 2 ω z , g is a constant, and from formula (4) we can get:

[0068]

[0069] From formula (5), the parameters of PLL are g and ωc Determine, and combine formula (2) and formula (5) to get:

[0070] like Figure 1 As shown in the figure, when the phase margin of the function curve of equation (6) is selected between 45° and 70°, the stability of the PLL is better, and at this time g∈(2.4,5.6); when g=3.5, PM=58.11.

[0071] Example 2

[0072] The dynamic response analysis of the PLL model includes the design of relevant parameters to minimize the settling time when the phase or frequency jump occurs, as follows:

[0073] Combining equations (1) and (5), we can obtain the PLL open-loop transfer function:

[0074]

[0075] From formula (7), we can get the PLL open-loop transfer function G OL (s) is a second-order function with two poles at the origin, so the PLL can lock the phase information without error when the phase changes or the frequency jumps;

[0076] The error transfer function is:

[0077]

[0078] Assuming g = 2ζ + 1, the above formula can be simplified to:

[0079]

[0080] When the phase changes suddenly (Δθ), the error signal is transformed into:

[0081]

[0082] Similarly, when the frequency jumps (Δω), the error signal is transformed into:

[0083]

[0084] In the time domain, equations (10) and (11) are expressed as follows:

[0085]

[0086] From equations (12) and (13), it can be seen that when the phase changes suddenly or the frequency jumps, the dynamic response of the PLL is the same as the crossover frequency ω under any damping coefficient ζ. c Related:c The larger the value, the faster the dynamic response of the PLL; however, c When the value is larger, the anti-interference ability of PLL will decrease, so when selecting ω c When designing a system, it is necessary to balance the dynamic response speed and anti-interference ability.

[0087] like Figure 2 and Figure 3 As shown in the figure, when ζ is different, the PLL's dynamic response to phase mutation and frequency jump should be balanced between response speed and overshoot. When ζ is small, the PLL's dynamic response speed is fast but the overshoot is large. On the contrary, the dynamic response speed is slow but the overshoot is small. The damping coefficient ζ can be selected in the range of 0.6 to 1. At this time, the PLL's dynamic response speed is fast and the overshoot is within the appropriate range. At the same time, ζ has little effect on the PLL's anti-interference ability.

[0088] Example 3

[0089] The PLL model anti-interference ability analysis includes: c The selection of is analyzed to make the PLL have better anti-interference ability;

[0090] When using a notch filter, the open-loop transfer function of the PLL has an upper bandwidth BW OL In order to make the passband of PLL not affected by the notch filter, we select ω c ,ω c It should be far away from the notch frequency, generally selected at 1 / 4 to 1 / 5 of the notch frequency, such as 2π·20 to 2π·25rad / s;

[0091] The disturbance closed-loop transfer function of the PLL is designed as:

[0092]

[0093] like Figure 4 and Figure 5 As shown, let ζ=0.707, g=3.5, V +1 =1, at this time, PLL is different at ω c In the Bode diagram of the perturbation transfer function and the open-loop transfer function, for ω c The perturbation transfer function of the PLL with a constant is the same as the open-loop transfer function at ω c When ω>ω, the amplitude characteristics of the two are the same; when ω>ω c When the attenuation of the two is almost the same; at the required ω c The open-loop function can be used to replace the disturbance function for relevant calculations.

[0094] PLL model anti-interference ability analysis includes: G OL (s) Amplitude characteristics analysis, such as Figure 6 As shown, in GOL (s) amplitude characteristic diagram, ω d is the lowest disturbance frequency, atten ωd is the attenuation value of the lowest disturbance frequency.

[0095]

[0096] ω p =gω c Bring in:

[0097] From this we can get

[0098] From formula (3.42), we can get ω c According to the pre-set suitable atten ωd is fixed. d =6ω=2π·300rad / s. Let ω c =2π·25rad / s, g=3.5, atten ωd =-32.29dB, which can meet the PLL requirements, ω c It can be set to 2π·25rad / s.

[0099] ω c The design values ​​of , ζ and g are as follows: ω c =2π·25rad / s, ζ=0.707, g=3.5. From this, the parameters of the PLL can be further designed. Cutoff frequency ω p =gω c =2π·87.5rad / s.

[0100] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an island microgrid, characterized in that: include: The phase-locked loop has a PLL model under distorted voltage. The stability margin, dynamic response and anti-interference capability of the PLL model are analyzed to obtain the steady-state performance parameters under distorted voltage. The stability margin analysis of the PLL model includes: The open-loop transfer function of the PLL model is designed to be Among them, ω z is the turning frequency, and ω z =k i / k p , k p is the proportional coefficient of the controller, k i is the integral coefficient of the PLL controller; Based on the above formula (1), the PLL phase margin PM is: PM=φ z +φ p (2); in, And the crossing frequency For PM to ω c When we take the partial derivative and make the result zero, we get: At the same time, combining equation (2) we can get: From formula (4), we can get that when ω p and ω z When is a fixed value, When , the PM of PLL is the largest, and ωp is the pole cutoff frequency of the PLL open-loop transfer function; Among them, let ω p =g 2 ω z , g is a constant, and from formula (4) we can get: oh p =gω c (5); From formula (5), the parameters of PLL are g and ω c Determine, combine equations (2) and (5) to get: When the phase margin of the function curve in equation (6) is selected between 45° and 70°, the stability of the PLL is better. In this case, g∈(2.4,5.6); when g=3.5, PM=58.11; The dynamic response analysis of the PLL model includes: designing relevant parameters to obtain the minimum settling time when the phase changes or the frequency jumps; combining equations (1) and (5), the PLL open-loop transfer function is: From formula (7), we can get the PLL open-loop transfer function G OL (s) is a second-order function with two poles at the origin, so the PLL can lock the phase information without error when the phase changes or the frequency jumps; The error transfer function is Assuming g = 2ζ + 1, the above formula can be simplified to: When the phase changes suddenly (Δθ), the error signal is transformed into: Similarly, when the frequency jumps (Δω), the error signal is transformed into: In the time domain, equations (10) and (11) are expressed as follows: From equations (12) and (13), it can be seen that when the phase changes suddenly or the frequency jumps, the dynamic response of the PLL is the same as the crossover frequency ω under any damping coefficient ζ. c Related: c The larger the value, the faster the dynamic response speed of the PLL; c When the value is larger, the anti-interference ability of PLL will decrease, so when selecting ω c When using the CMOS, it is necessary to balance the dynamic response speed and anti-interference ability; When the PLL dynamically responds to phase changes and frequency jumps at different ζ values, the PLL's response should strike a balance between response speed and overshoot. When ζ is small, the PLL's dynamic response speed is fast but the overshoot is large; conversely, the dynamic response speed is slow but the overshoot is small. The damping coefficient ζ is selected in the range of 0.6 to 1, at which point the PLL's dynamic response speed is fast and the overshoot is within an appropriate range, while ζ has little effect on the PLL's anti-interference ability. The PLL model anti-interference ability analysis includes: c The selection of is analyzed to make the PLL have better anti-interference ability; When using a notch filter, the open-loop transfer function of the PLL has an upper bandwidth BW OL In order to make the passband of PLL not affected by the notch filter, we select ω c ,ω c It should be far away from the notch frequency, generally selected at 1 / 4 to 1 / 5 of the notch frequency, such as 2π·20 to 2π·25rad / s; The disturbance closed-loop transfer function of the PLL is designed as: Assume ζ = 0.707, V +1 =1, at this time, PLL is different at ω c In the Bode diagram of the perturbation transfer function and the open-loop transfer function, for ω c The perturbation transfer function of the PLL with a constant is the same as the open-loop transfer function at ω c When ω>ω, the amplitude characteristics of the two are the same; when ω>ω c When the attenuation of the two is almost the same; at the required ω c The open-loop function can be used to replace the disturbance function for relevant calculations; PLL model anti-interference ability analysis includes: G OL (s) Amplitude characteristics analysis, ω d is the lowest disturbance frequency, atten ωd is the attenuation value of the lowest disturbance frequency; ω p =gω c Bring in: From this we can get: From formula (17), we can get ω c According to the pre-set suitable atten ωd For a fixed d =6ω=2π·300rad / s, let ω c =2π·25rad / s, g=3.5, atten ωd =-32.29dB, which can meet the PLL requirements, ω c It can be set to 2π·25rad / s; ω c The design values ​​of , ζ and g are as follows: ω c =2π·25rad / s, ζ=0.707, from which the parameters of the PLL can be further designed. Cutoff frequency ω p =gω c =2π·87.5rad / s.

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