A method for updating pulse switch parameters, an electronic device, a medium

Abstract

The present invention discloses a method for updating pulse switch parameters, an electronic device, and a medium, including: setting a reference value for the switch period; obtaining the current switch period, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; respectively determining the first action and the second action according to the first duty cycle of the first PWM signal and the second duty cycle of the second PWM signal, and setting the first flag bit; when the first flag bit is detected, timing is performed by a cyclic timer to update the switch period, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave under the current switch period; after the update is completed, the first flag bit is set, and the cyclic timer is cleared.

Description

Technical Field

[0001] The present application relates to the field of power electronics control technology, and particularly to a method for updating pulse switch parameters, an electronic device, and a medium. Background Art

[0002] Pulse Width Modulation (PWM) is a technology for controlling analog output by adjusting the pulse width of a digital signal. Its core principle is to use a square wave with a fixed frequency as the carrier wave, and change the average voltage or power of the signal by adjusting the duration of the high level (duty cycle) within each period. For example, when the duty cycle is 50%, the output average voltage is half of the power supply voltage. Currently, especially in variable-frequency PWM control systems, the pulse width modulation technology has been widely applied, and how to reasonably configure and apply the PWM module is crucial for variable-frequency control.

[0003] Chinese Patent CN111146927A discloses a method for updating variable-frequency PWM control switch parameters, a PWM control method, and a PWM controller. This method solves the problem of incorrect pulses in timing by adding an intermediate value, first updating to the intermediate value of the switch parameters, and then updating from the intermediate value of the switch parameters to the switch parameters to be updated after one sampling calculation period. However, this method can only solve the situation of incorrect pulses caused by deviations in the execution time of the chip, and cannot effectively solve the situation of incorrect pulses caused by other reasons.

[0004] In the prior art, in variable-frequency interleaved PWM applications, problems such as Figure 1 shown in the similar incorrect pulse problem occur. Chinese Patent CN117938130A discloses a method for updating PWM control switch parameters, as Figure 2 shown. That is, the first duty cycle of the first PWM signal is updated at the time point corresponding to the peak of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle, and the second duty cycle of the second PWM signal and the switching cycle PRD are updated at the time point corresponding to the valley of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle; thus, the abnormal pulse widths of the first PWM signal and the second PWM signal output are avoided. When the relevant device needs to change frequency, whether the period of the PWM wave is increased or decreased, no incorrect pulse width will occur.

[0005] However, when adjusting the pulse width by the PWM control switch parameter update method disclosed in Chinese Patent CN117938130A, that is, updating the first duty cycle of the first PWM signal at the time point corresponding to the peak of the triangular carrier wave in the current switching cycle, and updating the second duty cycle of the second PWM signal and the switching cycle PRD at the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle, it will cause the actual switch update speed to be slow. Specifically, to update the first duty cycle of the first PWM signal, it is necessary to wait until the carrier counter of the PWM wave runs to the time point corresponding to the peak of the triangular carrier wave in the next cycle before the value can be written into the active register to successfully update.

[0006] At the same time, when adjusting the pulse width by the PWM control switch parameter update method disclosed in Chinese Patent CN117938130A, that is, updating the first duty cycle of the first PWM signal at the time point corresponding to the peak of the triangular carrier wave in the current switching cycle, and updating the second duty cycle of the second PWM signal and the switching cycle PRD at the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle, if the switching cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal are not fully updated, it is easy to appear as Figure 3 the non-target level shown. Especially when the duty cycle exceeds 50%, due to the random loading of the switching cycle PRD, the first duty cycle of the first PWM signal, the second duty cycle of the second PWM signal, the first action of the first PWM signal, and the second action of the second PWM signal, the effect is worse, and error pulses are extremely likely to appear. Specifically, the second duty cycle of the second PWM signal is obtained by subtracting the first duty cycle of the first PWM signal from the switching cycle PRD. When the switching cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal change greatly, the second duty cycle of the second PWM signal should become very small. However, due to the problem of the program execution timing, such as executing the instruction to update the switching cycle PRD first at the zero crossing point and not having time to execute the instruction to update the second duty cycle of the second PWM signal, the system still executes the original second duty cycle of the second PWM signal at the zero crossing point. Since the value of the original second duty cycle of the second PWM signal is very large, it is easy to cause a high level with a duty cycle higher than 50%. Therefore, in variable frequency applications, this solution is extremely likely to cause system instability problems, resulting in abnormal operation of power electronic devices. And due to the limitations of the method, corresponding actions cannot be performed by reasonably planning the action register, and pulses exceeding 50% cannot be controlled. Summary of the Invention

[0007] Aiming at the deficiencies of the prior art, embodiments of the present invention provide a pulse switch parameter update method, an electronic device, and a medium.

[0008] In a first aspect, an embodiment of the present invention provides a method for updating pulse switch parameters. The method is applied to an enhanced pulse width modulation module, which includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated based on the first PWM signal and the second PWM signal; the method specifically includes the following steps:

[0009] Set a reference value for the switching period;

[0010] Obtain the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determine the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determine the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and set the first flag bit.

[0011] When the first flag bit is detected, use a cycle timer to time and update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, set the first flag bit and clear the cycle timer.

[0012] In a second aspect, an embodiment of the present invention provides a PWM control switch parameter update system. The system is applied to an enhanced pulse width modulation module, which includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated based on the first PWM signal and the second PWM signal; the system includes:

[0013] A setting module for setting a reference value for the switching period;

[0014] An obtaining module for obtaining the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determining the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determining the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and setting the first flag bit.

[0015] An update module, configured to, when detecting a first flag bit, time through a cyclic timer to update a switching period PRD, a duty cycle of a first PWM signal, a duty cycle of a second PWM signal, a first action corresponding to the first PWM signal, and a second action corresponding to the second PWM signal at a next target time point; wherein, the target time point is the time point corresponding to the trough of a triangular carrier wave of a carrier counter of a PWM wave in a current switching period; after the update is completed, set the first flag bit and clear the cyclic timer.

[0016] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, the memory is coupled to the processor; wherein, the memory is used to store program data, and the processor is used to execute the program data to implement the above-mentioned pulse switching parameter update method.

[0017] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above-mentioned pulse switching parameter update method is implemented.

[0018] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the above-mentioned pulse switching parameter update method is implemented.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] The present invention provides a pulse switching parameter update method, which, when detecting a first flag bit, times through a cyclic timer to update a switching period PRD, a duty cycle of a first PWM signal, a duty cycle of a second PWM signal, a first action corresponding to the first PWM signal, and a second action corresponding to the second PWM signal at a next target time point; wherein, the target time point is the time point corresponding to the trough of a triangular carrier wave of a carrier counter of a PWM wave in a current switching period; after the update is completed, set the first flag bit and clear the cyclic timer; thereby avoiding abnormal pulses and solving the problem caused by insufficient update of the duty cycle, and at the same time solving the problem of slow actual switching update speed. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a waveform diagram of a PWM wave during the update process of PWM control switch parameters in related technologies;

[0023] Figure 2 A waveform diagram of a PWM wave during another PWM control switch parameter update process in the related art;

[0024] Figure 3 A waveform diagram of a PWM wave during another PWM control switch parameter update process in the related art;

[0025] Figure 4 A waveform diagram of a PWM wave during a PWM control switch parameter update process provided by an embodiment of the present invention;

[0026] Figure 5 A flow chart of a pulse switch parameter updating method provided by an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of the structure of an enhanced pulse width modulation module provided by an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of the operation of an enhanced pulse width modulation module provided by an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] It should be noted that, in the absence of conflict, the features in the following embodiments and implementations may be combined with each other.

[0032] This embodiment provides a PWM control circuit. The PWM control circuit outputs two PWM signals, namely a first PWM signal and a second PWM signal, wherein the first PWM signal and the second PWM signal are interlaced and modulated, and the rising edge of the first PWM signal precedes the rising edge of the second PWM signal by a preset angle, that is, a dynamic phase offset is established between the first PWM signal and the second PWM signal, that is, the trigger edge of the first PWM signal is set ahead of the second PWM signal by a phase angle through the phase offset modulation technology. The PWM control circuit has a dynamic phase compensation mechanism, which can adjust the duty cycle phase parameters and the working cycle duration in real time, so that the phase and period of the output PWM signal can be dynamically changed, and the output waveform can be reconstructed online.

[0033] Further, the PWM control circuit includes a period register containing a PWM period value, a comparator, an action limiter, and a PWM counter. The period register is used to set the periods of the first PWM signal and the second PWM signal. Specifically, the period register uses a shadow register mechanism to store the reference period value T_base of the two PWM signals, automatically loads the pre-stored period parameters when the count value is equal to 0, updates the period accuracy up to ±1.5 ns, and at the same time, this period register supports an asynchronous update mode. The comparator is used to compare the PWM period value with the PWM count value to provide a key comparison result for subsequent operations. The action limiter is used to receive the comparison value output by the comparator, compare the comparison value with the count value, and limit the PWM signal, effectively limit the PWM signal according to the comparison result, ensure that the PWM signal fluctuates within a reasonable range. It is particularly noteworthy that when the PWM count value is zero, at this time, it is necessary to update the PWM period value, and at the same time, reset the duty cycles of the first PWM signal and the second PWM signal, and also accurately and orderly update the actions corresponding to the first PWM signal and the second PWM signal. Thereby ensuring that the entire PWM control circuit can operate continuously, stably, and efficiently, accurately output the PWM signal that meets the expectations, and thus achieve precise control of related devices or systems.

[0034] This embodiment provides an enhanced pulse width modulation module. Figure 6 is a schematic structural diagram of an enhanced pulse width modulation module of this embodiment, as Figure 6 and Figure 7 shown, the enhanced pulse width modulation module includes: a time reference sub-module 01, a comparison function sub-module 02, and an action limiting sub-module 03.

[0035] Among them, the time reference sub-module 01 includes a time reference register, and the time reference register includes a current register and a mapping register. The comparison function sub-module 02 includes a first comparison register and a second comparison register; the first comparison register is a CMPA register (Compare Accumulator A), the second comparison register is a CMPB register (Compare Accumulator B), the CMPA register includes a CMPA current register and a CMPA mapping register, and the CMPB register includes a CMPB current register and a CMPB mapping register. The action limiting sub-module 03 includes a first action limiting register and a second action limiting register; the first action limiting register is an AQA register, and the second action limiting register is an AQB register.

[0036] In the embodiments of the present application, by reasonably planning the switching action value, the modulation of the duty cycle can be made wider, that is, a pulse width with a duty cycle exceeding 50% can be modulated. As Figure 4 The illustrated example is a schematic diagram of the modulation of a pulse width with a duty cycle less than 50% to a pulse width with a duty cycle greater than 50%.

[0037] Specifically, in this example, when controlling a duty cycle less than 50%, the A channel (i.e., the first PWM signal) drives to generate a rising edge of the drive at point C, and generates a falling edge of the drive when the counter counts up to the first duty cycle CMPA_Old point of the old first PWM signal. The B channel (i.e., the second PWM signal) drives to generate a rising edge of the drive at point B, and generates a falling edge of the drive when the counter counts down to the second duty cycle CMPB_Old point of the old second PWM signal. When controlling a duty cycle greater than 50%, the A channel drives to generate a rising edge of the drive at point C, and generates a falling edge of the drive when the counter counts down to the first duty cycle CMPA_New point of the new first PWM signal. The B channel drives to generate a rising edge of the drive at point B, and generates a falling edge of the drive when the counter counts up to the second duty cycle CMPB_New point of the new second PWM signal.

[0038] In some examples, due to the lack of a well-planned update strategy, when controlling a duty cycle exceeding 50%, such as when switching from a duty cycle exceeding 50% to a duty cycle less than 50%, at this time the duty cycle should become very small, but due to the problem of the program execution timing, such as executing the instruction for updating the switching period PRD at the zero crossing point and not having time to execute the instruction for updating the first duty cycle of the first PWM signal and the first action of the first PWM signal, it is easy to have a high level with a duty cycle higher than 50% for a long time.

[0039] Similarly, if the instruction for updating the switching period PRD is executed first at the zero crossing point and there is no time to execute the instruction for updating the second duty cycle of the second PWM signal and the second action of the second PWM signal, it is also easy to have a high level with a duty cycle higher than 50%.

[0040] Moreover, when controlling a duty cycle exceeding 50%, such as when switching from a duty cycle exceeding 50% to a duty cycle less than 50% and the first and second PWM signals need to be updated simultaneously, since the action registers have priorities, they cannot be updated simultaneously, so a certain PWM signal is prone to having a high level with a duty cycle higher than 50% for a long time.

[0041] To solve the above problems, based on the action update strategy mentioned above, this example proposes the switching cycle PRD of the switching cycle, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal, and sets the update flag after determining the first action of the first PWM signal and the second action of the second PWM signal according to the duty cycle. Then, a loop is written near the zero crossing point, that is, point C, and the above parameters are fully loaded in the loop, which is a new method.

[0042] As Figure 5 shown, this embodiment provides a method for updating pulse switch parameters. The method is applied to an enhanced pulse width modulation module. By continuously updating the value of the mapped register in the comparison register, and in the existing flyback quasi-resonant control technology, calculating the new switching cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal, and setting the update flag after determining the first action of the first PWM signal and the second action of the second PWM signal according to the duty cycle. Then, a loop is written near the zero crossing point, and the above parameters are fully loaded in the loop to ensure that the value in the mapped register is loaded into the current register. Among them, the enhanced pulse width modulation module includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal. A PWM wave is generated according to the first PWM signal and the second PWM signal. The method for updating pulse switch parameters includes the following steps:

[0043] Step S1, set the switching cycle reference value.

[0044] Specifically, the enhanced pulse width modulation module includes a time reference sub-module. Among them, the time reference sub-module includes a time reference period register and a time reference counter. The time reference period register includes a current register and a mapped register. The value in the current register is used as the switching cycle reference value to complete the initialization.

[0045] Step S2, obtain the current switching cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determine the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determine the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and set the first flag.

[0046] Step S3: When the first flag bit is detected, use a cycle timer to time and update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point C; wherein, the target time point C is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, set the first flag bit and clear the cycle timer.

[0047] Specifically, as Figure 4 shown, in the first coordinate system, the abscissa represents time and the ordinate represents the value of the carrier counter; as Figure 4 shown in Channel A of Figure 4 it shows a schematic diagram of the first PWM signal; as shown in Channel B of

[0048] it shows a schematic diagram of the second PWM signal. Set the current switching period as the old switching period PRD_Old, set the current duty cycle of the first PWM signal as the first duty cycle CMPA_Old of the old first PWM signal, set the current duty cycle of the second PWM signal as the second duty cycle CMPB_Old of the old second PWM signal, the current action of the first PWM signal as the first action AQA_Old corresponding to the old first PWM signal, set the current action of the second PWM signal as the second action AQB_Old corresponding to the old second PWM signal, set the new period calculated by the anti-resonant quasi-resonant as the new switching period PRD_New, set the new duty cycle of the first PWM signal as the first duty cycle CMA_New of the new first PWM signal, set the current duty cycle of the second PWM signal as the second duty cycle CMB_New of the new second PWM signal, set the new action of the first PWM signal as the first action AQA_New corresponding to the new first PWM signal, set the current action of the second PWM signal as the second action AQB_New corresponding to the new second PWM signal. When the time base counter is equal to zero, theoretically, the updated normal operation can update the period value PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the action of the first PWM signal, or the action of the second PWM signal at any time point A, B, or C. Among them, time points A and B are the time points corresponding to the peaks of the triangular carrier wave, and time point C is the time point corresponding to the trough of the triangular carrier wave.In this embodiment, through the above steps S1 to S3, the cycle value PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the operation of the first PWM signal, and the operation of the second PWM signal are uniformly and fully updated at the target time point C. By adjusting the update order of the switch parameters, this embodiment ensures that no error pulses are generated during the frequency conversion process and guarantees that there are no abnormalities in the PWM output drive after the update. Specifically, when the flyback quasi-resonant control calculates a new set of updated switch cycle values, for the switch cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal, after determining the first operation of the first PWM signal and the second operation of the second PWM signal based on the duty cycle, the flag bit is set. When the first flag bit is detected and the switch cycle is updated at the next C time point, the cycle timer is entered, and at the same time, the switch cycle PRD, the duty cycle of the first PWM signal, and the duty cycle of the second PWM signal are updated. And the operation of the first PWM signal and the operation of the second PWM signal are sequentially updated. After the full update is completed, the first flag bit is set, and the cycle timer is cleared. The C time point is the time point corresponding to the trough of the triangular carrier wave of the PWM wave carrier counter under the current switch cycle. At this time, the second duty cycle of the new second PWM signal should be equal to the switch cycle PRD minus the first duty cycle of the first PWM signal, thus naturally avoiding the problems caused by abnormal pulses and insufficient update of the duty cycle. And at the time point corresponding to the trough of the triangular carrier wave of the PWM wave carrier counter under the current switch cycle, the switch cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal are fully updated simultaneously, avoiding the problem of "to update the first duty cycle of the first PWM signal, it is necessary to wait until the time point corresponding to the peak of the triangular carrier wave of the next cycle of the PWM wave carrier counter to write the value into the active register to successfully update", so the actual switch update speed will be faster. And due to the full update of the AQ register within the loop, the problem of "the high level exceeding the control expected duty cycle and thus exceeding the control expectation due to the failure to update the action register in time caused by the sequential update of the AQ register" is avoided.

[0049] Of course, in some of these embodiments, the enhanced pulse width modulation module is a DSP, a CPU, or a microcontroller. The enhanced pulse width modulation module adopts an up-down counting mode to generate a symmetric triangular carrier wave. Further, the triangular carrier wave is an isosceles triangular wave.

[0050] In some of these embodiments, the pulse switch parameter update method further includes: while the duty cycle of the second PWM signal is updated, the current switch cycle value is set to the switch cycle reference value at the second time point. That is, when the value of the PWM wave carrier counter is zero, that is, at the time point corresponding to the trough of the triangular carrier wave of the PWM wave carrier counter under the current switch cycle, the current switch cycle value is set to the switch cycle reference value to complete the frequency conversion.

[0051] On the other hand, an embodiment of the present invention also provides a PWM control switch parameter update system, which is applied to an enhanced pulse width modulation module. The enhanced pulse width modulation module includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated according to the first PWM signal and the second PWM signal; the system includes:

[0052] A setting module for setting a reference value of the switching period;

[0053] An acquisition module for acquiring the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; judging the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, judging the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and setting the first flag bit;

[0054] An update module for, when detecting the first flag bit, timing through a cycle timer to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, set the first flag bit and clear the cycle timer.

[0055] Regarding the system in the above embodiment, the specific manners of operations performed by each module have been described in detail in the embodiment related to the method, and will not be elaborated herein.

[0056] For the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can be referred to the partial description of the method embodiment. The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative work.

[0057] Correspondingly, the present application also provides an electronic device, including: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the pulse switch parameter update method as described above. As Figure 8As shown, it is a hardware structure diagram of any device with data processing capabilities where the pulse switch parameter update method provided by the embodiment of the present invention is located. Besides Figure 8 the shown processor, memory, and network interface, any device with data processing capabilities where the device in the embodiment is located usually includes other hardware according to the actual functions of the device with data processing capabilities, which will not be elaborated here.

[0058] Correspondingly, the present application also provides a computer-readable storage medium, on which computer instructions are stored. When the instructions are executed by a processor, the pulse switch parameter update method as described above is implemented. The computer-readable storage medium may be an internal storage unit of any device with data processing capabilities described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium may also be an external storage device, such as a plug-in hard disk, a Smart Media Card (SMC), an SD card, a Flash Card, etc. equipped on the device. Further, the computer-readable storage medium may also include both an internal storage unit of any device with data processing capabilities and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the device with data processing capabilities, and may also be used to temporarily store the data that has been output or will be output.

[0059] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily think of other implementation schemes of the present application. The present application aims to cover any variations, uses, or adaptive changes of the present application, and these variations, uses, or adaptive changes follow the general principles of the present application and include common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary.

[0060] It should be understood that the present application is not limited to the precise structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A method for updating pulse switch parameters, characterized in that, The method is applied to an enhanced pulse width modulation module, which includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated based on the first PWM signal and the second PWM signal; the method specifically includes the following steps: Set the reference value of the switching period; Obtain the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determine the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determine the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and set the first flag bit; When the first flag bit is detected, use a cycle timer to time and update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave under the current switching period; after the update is completed, set the first flag bit and clear the cycle timer; Among them, the process of determining the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal and the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal includes: When controlling with a duty cycle less than 50%, the first PWM signal generates a rising edge of the drive at the target time point and a falling edge of the drive when the counter counts up to the first duty cycle CMPA_Old point of the old first PWM signal; the second PWM signal generates a rising edge of the drive at the second time point and a falling edge of the drive when the counter counts down to the second duty cycle CMPB_Old point of the old second PWM signal, and the second time point is the time point corresponding to the peak of the triangular carrier wave of the carrier counter of the PWM wave under the current switching period; When controlling with a duty cycle greater than 50%, the first PWM signal generates a rising edge of the drive at the target time point and a falling edge of the drive when the counter counts down to the first duty cycle CMPA_New point of the new first PWM signal; the second PWM signal generates a rising edge of the drive at the second time point and a falling edge of the drive when the counter counts up to the second duty cycle CMPB_New point of the new second PWM signal, and the second time point is the time point corresponding to the peak of the triangular carrier wave of the carrier counter of the PWM wave under the current switching period.

2. The method for updating pulse switch parameters according to claim 1, wherein The process of setting the reference value of the switching period includes: The enhanced pulse width modulation module includes a time reference sub-module; the time reference sub-module includes a time reference period register and a time reference counter, and the time reference period register includes a current register and a mapping register; Take the value in the current register as the reference value of the switching period.

3. A method for updating pulse switch parameters according to claim 1, characterized in that The process of obtaining the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal includes: Calculate the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal by the flyback quasi-resonant control method.

4. A method for updating pulse switch parameters according to claim 1, characterized in that, The pulse switch parameter update method further includes: After updating the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal, the updated duty cycle of the second PWM signal is equal to the difference between the switching period PRD and the duty cycle of the first PWM signal.

5. A PWM control switch parameter update system, characterized in that For implementing the pulse switch parameter update method described in any one of the above claims 1-4, the system is applied to an enhanced pulse width modulation module, and the enhanced pulse width modulation module includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; Generate a PWM wave according to the first PWM signal and the second PWM signal; the system includes: A setting module for setting a switching period reference value; An acquisition module for acquiring the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; judging the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, judging the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and setting the first flag bit; An update module for, when detecting the first flag bit, timing through a cycle timer to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, set the first flag bit and clear the cycle timer.

6. An electronic device, comprising a memory and a processor, characterized in that, The memory is coupled to the processor; wherein, the memory is used to store program data, and the processor is used to execute the program data to implement the pulse switch parameter update method described in any one of the above claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the pulse switch parameter update method described in any one of claims 1-4.

8. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, it implements the pulse switch parameter update method described in any one of claims 1-4.

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