Integrated circuit device and manufacturing method thereof

Abstract

An integrated circuit device and a method of manufacturing the same are provided, the integrated circuit device including: a substrate including a memory cell region and a peripheral circuit region around the memory cell region; a cell transistor in the memory cell region; a peripheral circuit transistor in the peripheral circuit region; a capacitor structure including a lower electrode on the cell transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stack plate structure covering the capacitor structure; and an interlayer insulating film covering the stacked plate structure in the memory cell region and covering the peripheral circuit transistor in the peripheral circuit region, in which the stacked plate structure includes: a first plate layer including doped silicon germanium (SiGe); an intermediate layer conformally covering the first plate layer and including a metal silicide (MxSiy) including a metal (M); and a second plate layer conformally covering the intermediate layer and including a metal (M) in the metal silicide.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit devices, and more particularly to integrated circuit devices including capacitors and methods of manufacturing integrated circuit devices. Background Art

[0002] With the rapid development of miniaturized semiconductor processing technologies, due to the accelerated high integration of integrated circuit devices, the area of a unit cell decreases. Accordingly, the area that a capacitor can occupy within a unit cell also decreases. For example, as the integration degree of an integrated circuit device such as a dynamic random access memory (DRAM) increases, the area of a unit cell decreases, and conversely, the capacitance required thereof remains constant or increases. Accordingly, a structure is needed that can overcome the spatial limitation and design rule limitation in a capacitor, increase capacitance, and maintain desired electrical characteristics. Summary of the Invention

[0003] An integrated circuit device is provided that uses a stacked plate structure in a dynamic random access memory (DRAM) including a stacked plate structure on a capacitor structure to have improved electrical characteristics and product reliability, in which an intermediate layer is inserted between a doped silicon germanium layer and a tungsten plate layer in the stacked plate structure.

[0004] A method of manufacturing an integrated circuit device is further provided that uses a stacked plate structure in a dynamic random access memory (DRAM) including a stacked plate structure on a capacitor structure to manufacture an integrated circuit device having improved electrical characteristics and product reliability, in which an intermediate layer is inserted between a doped silicon germanium layer and a tungsten plate layer in the stacked plate structure.

[0005] According to an aspect of the present disclosure, an integrated circuit device includes: a substrate including a memory cell region and a peripheral circuit region around the memory cell region; a cell transistor in the memory cell region; a peripheral circuit transistor in the peripheral circuit region; a capacitor structure including a lower electrode on the cell transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; and an interlayer insulating film covering the stacked plate structure in the memory cell region and covering the peripheral circuit transistor in the peripheral circuit region, wherein the stacked plate structure includes: a first plate layer including doped silicon germanium (SiGe); an intermediate layer conformally covering the first plate layer and including a metal silicide (M x Si y ) including a metal (M) in the metal silicide; and a second plate layer conformally covering the intermediate layer and including the metal (M) in the metal silicide.

[0006] According to one aspect of the present disclosure, an integrated circuit device includes: a substrate including a memory cell region and a peripheral circuit region surrounding the memory cell region; cell transistors in the memory cell region; peripheral circuit transistors in the peripheral circuit region; a capacitor structure including a lower electrode on the cell transistors, a dielectric film on the surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; and an interlayer insulating film covering the stacked plate structure in the memory cell region and covering the peripheral circuit transistors in the peripheral circuit region, wherein the stacked plate structure includes: a first plate layer containing doped silicon germanium (SiGe); a second plate layer containing a metal (M); and a first intermediate layer containing metal silicide (M x Si y ) and a second intermediate layer containing metal silicon nitride (M x Si y N), wherein the first intermediate layer and the second intermediate layer are between the first plate layer and the second plate layer.

[0007] According to one aspect of the present disclosure, an integrated circuit device includes: cell transistors in a memory cell region of the integrated circuit device; a capacitor structure including a lower electrode on the cell transistors, a dielectric film on the surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; an interlayer insulating film covering the stacked plate structure; and a metal contact connected to the stacked plate structure and penetrating the interlayer insulating film, wherein the stacked plate structure includes: a first plate layer containing doped silicon germanium (SiGe); an intermediate layer conformally covering the first plate layer and containing one selected from tungsten silicide (WSi x ) and tungsten silicon nitride (WSi x N y ); and a second plate layer conformally covering the intermediate layer and containing tungsten (W).

[0008] The objectives of the present disclosure are not limited to the above-mentioned objectives, and those skilled in the art will clearly understand other objectives not mentioned above from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Through the following description in conjunction with the drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent, wherein:

[0010] Figure 1 is a layout diagram showing an integrated circuit device according to an embodiment;

[0011] Figure 2 is Figure 1 an enlarged view of part A1 of

[0012] Figure 3 is Figure 2 a cross-sectional view taken along line B1 - B1' of the integrated circuit device of

[0013] Figure 4 is Figure 3 an enlarged view of a part of CX1;

[0014] Figure 5 is a cross-sectional view showing an integrated circuit device according to an embodiment;

[0015] Figure 6 is Figure 5 an enlarged view of a part of CX2;

[0016] Figure 7 is a layout view showing an integrated circuit device according to an embodiment;

[0017] Figure 8 is Figure 7 a cross-sectional view of the integrated circuit device taken along line C1-C1';

[0018] Figure 9 is a flowchart showing a method of manufacturing an integrated circuit device according to an embodiment;

[0019] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 and Figure 19 are cross-sectional views showing a method of manufacturing an integrated circuit device according to an embodiment; and

[0020] Figure 20 is a configuration diagram showing a system including an integrated circuit device according to an embodiment. Detailed Embodiments

[0021] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0022] In the following description, the same reference numerals throughout the specification refer to the same elements. As used herein, a plurality of "units", "modules", "components", and "blocks" may be implemented as a single component, or a single "unit", "module", "component", and "block" may include a plurality of components.

[0023] It will be understood that when an element is referred to as being "connected" to another element, it can be directly or indirectly connected to the other element.

[0024] Furthermore, when a part "includes" or "contains" an element, unless there is a specific description to the contrary, the part may further include other elements without excluding other elements.

[0025] Throughout the description, when an element is "on" another element, this includes not only when the element is in contact with the other element, but also when there is another element between the two elements.

[0026] Here, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" mean "only a", "only b", "only c", "both a and b", "both a and c", "both b and c", and "all of a, b, and c".

[0027] It will be understood that although terms such as first, second, third, etc. may be used herein to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0028] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise.

[0029] Regarding any method or process described herein, for ease of description, identification codes may be used, but are not intended to indicate the order of each step or operation. Each step or operation may be implemented in an order different from that shown, unless the context clearly indicates otherwise. One or more steps or operations may be omitted, unless the context of the present disclosure clearly indicates otherwise.

[0030] Figure 1 is a layout diagram showing an integrated circuit device, Figure 2 is Figure 1 an enlarged view of part A1 of Figure 3 is Figure 2 a cross-sectional view taken along line B1 - B1' of the integrated circuit device of Figure 4 is Figure 3 an enlarged view of part CX1 of

[0031] Referring together to Figures 1 to 4 , the integrated circuit device 10 may include a substrate 110, and the substrate 110 includes a memory cell area MCA and a peripheral circuit area PCA.

[0032] The memory cell area MCA may be an array area of volatile memory cells of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may be a core area or a peripheral circuit area of the DRAM device. For example, the peripheral circuit area PCA may include peripheral circuit transistors PG for transmitting signals and / or power to a memory cell array included in the memory cell area MCA.

[0033] In one or more embodiments, the peripheral circuit transistors PG may configure various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, a data input / output circuit, etc.

[0034] A device isolation trench 112T may be formed in a substrate 110, and a device isolation film 112 may be formed in the device isolation trench 112T. The device isolation film 112 may include silicon oxide, silicon nitride, or a combination thereof. Through the device isolation film 112, a plurality of first active regions AC1 may be defined in the substrate 110 in a memory cell region MCA, and a second active region AC2 may be defined in the substrate 110 in a peripheral circuit region PCA.

[0035] In the memory cell region MCA, each of the plurality of first active regions AC1 may be arranged to have a major axis in a diagonal direction with respect to a first horizontal direction X and a second horizontal direction Y. A plurality of word lines WL may cross the plurality of first active regions AC1 and extend parallel to each other in the first horizontal direction X. A plurality of bit lines BL may extend on the plurality of word lines WL parallel to each other in the second horizontal direction Y. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 through a plurality of direct contacts DC.

[0036] A plurality of blocking contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of blocking contacts BC may be arranged in a row in the first horizontal direction X and the second horizontal direction Y. A plurality of landing pads LP may be formed on the plurality of blocking contacts BC. The plurality of blocking contacts BC and the plurality of landing pads LP may connect a lower electrode 181 of a capacitor structure 180 formed on the plurality of bit lines BL to the first active region AC1. Each of the plurality of landing pads LP may be arranged such that a part thereof overlaps the blocking contact BC in a vertical direction Z.

[0037] The substrate 110 may be a silicon (Si)-containing wafer. In one or more embodiments, the substrate 110 may be a wafer including a semiconductor element (such as germanium (Ge)) or a compound semiconductor (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The substrate 110 may have a silicon-on-insulator (SOI) structure. In addition, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure.

[0038] A plurality of direct contacts DC may be formed in a plurality of direct contact holes DCH of the substrate 110. The plurality of direct contacts DC may be connected to the plurality of first active regions AC1. Each of the plurality of direct contacts DC may include doped polysilicon. For example, each of the plurality of direct contacts DC may include polysilicon containing a relatively high concentration of impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb).

[0039] A plurality of bit lines BL may longitudinally extend along a second horizontal direction Y on a substrate 110 and a plurality of direct contacts DC. Each of the plurality of bit lines BL may be connected to a first active region AC1 through a direct contact DC. Each of the plurality of bit lines BL may include a lower conductive pattern 132A, an intermediate conductive pattern 134A, and an upper conductive pattern 136A sequentially stacked on the substrate 110. The lower conductive pattern 132A may include doped polysilicon. Each of the intermediate conductive pattern 134A and the upper conductive pattern 136A may include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In one or more embodiments, the intermediate conductive pattern 134A may include TiN, TiSiN, or a combination thereof, and the upper conductive pattern 136A may include tungsten.

[0040] The plurality of bit lines BL may be covered with a plurality of capping layers 140A. The plurality of capping layers 140A may extend on the plurality of bit lines BL in the second horizontal direction Y. Spacers 150A may be disposed on two sidewalls of each of the plurality of bit lines BL. The spacers 150A may extend on two sidewalls of each of the plurality of bit lines BL in the second horizontal direction Y, and a part of each spacer 150A may extend into the interior of the direct contact hole DCH to cover each of the two sidewalls of the direct contact DC.

[0041] The direct contact DC may be formed within a direct contact hole DCH formed in the substrate 110 and extend to a level higher than the upper surface of the substrate 110. For example, the upper surface of the direct contact DC may be disposed at the same level as the upper surface of the lower conductive pattern 132A, and the upper surface of the direct contact DC may contact the bottom surface of the intermediate conductive pattern 134A. In addition, the bottom surface of the direct contact DC may be disposed at a level lower than the upper surface of the substrate 110.

[0042] A plurality of insulating fences and a plurality of conductive plugs 152 may be arranged in a row between the plurality of bit lines BL along the second horizontal direction Y. The plurality of conductive plugs 152 may longitudinally extend in a vertical direction Z from a recessed space RS formed in the substrate 110. Two sidewalls of each of the plurality of conductive plugs 152 in the second horizontal direction Y may be insulated from each other by the plurality of insulating fences. The plurality of conductive plugs 152 may configure a plurality of barrier contacts BC.

[0043] A plurality of landing pads LP may be formed above the plurality of conductive plugs 152. A metal silicide film may be further disposed between the plurality of conductive plugs 152 and the plurality of landing pads LP. The metal silicide film may include cobalt silicide, nickel silicide, or manganese silicide. Each of the plurality of landing pads LP may include a conduction blocking film 162A and a landing pad conductive layer 164A. The conduction blocking film 162A may include Ti, TiN, or a combination thereof. The landing pad conductive layer 164A may include a metal, a metal nitride, conductive polysilicon, or a combination thereof. Each of the plurality of landing pads LP may have an island shape in a plan view. The plurality of landing pads LP may be electrically insulated from each other by an insulating pattern 166 surrounding the plurality of landing pads LP.

[0044] In the peripheral circuit area PCA, peripheral circuit transistors PG may be disposed in the second active area AC2. The peripheral circuit transistors PG may include a gate dielectric film 116, a gate electrode PGS, and a gate capping pattern 140B sequentially stacked in the second active area AC2.

[0045] The gate dielectric film 116 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material having a dielectric constant higher than that of silicon oxide. The gate electrode PGS may include a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B. The constituent materials of the lower conductive pattern 132B, the intermediate conductive pattern 134B, and the upper conductive pattern 136B may be the same as the constituent materials of the lower conductive pattern 132A, the intermediate conductive pattern 134A, and the upper conductive pattern 136A included in the bit line BL in the memory cell area MCA, respectively. In addition, the gate capping pattern 140B may include silicon nitride.

[0046] In one or more embodiments, both sidewalls of the gate electrode PGS may be covered with gate spacers 150B. Each gate spacer 150B may include silicon oxide, silicon nitride, or a combination thereof.

[0047] The peripheral circuit transistors PG may be covered with a first insulating film 142. A second insulating film 144 may be disposed on the first insulating film 142. In the peripheral circuit area PCA, a contact plug CP may be formed in a contact hole CPH vertically penetrating the first insulating film 142 and the second insulating film 144. The contact plug CP may include a conduction blocking film 162B and a landing pad conductive layer 164B, similar to the plurality of landing pads LP formed in the memory cell area MCA.

[0048] In the memory cell area MCA, an upper insulating pattern 170 may be disposed on the insulating pattern 166. The upper insulating pattern 170 may include a material having an etching selectivity with respect to the second insulating film 144 and the insulating pattern 166. For example, the upper insulating pattern 170 may include silicon nitride.

[0049] In the memory cell area MCA, the capacitor structure 180 may be disposed on the upper insulating pattern 170. The capacitor structure 180 may include a plurality of lower electrodes 181, a capacitor dielectric film 183, and an upper electrode 185.

[0050] The plurality of lower electrodes 181 may extend along the vertical direction Z on the plurality of landing pads LP. The bottom portions of the plurality of lower electrodes 181 may be disposed within the opening portions of the upper insulating pattern 170. The support layer SPT may be disposed on the sidewalls of the plurality of lower electrodes 181. The support layer SPT may maintain a constant distance between two adjacent lower electrodes 181 and prevent the plurality of lower electrodes 181 from tilting or falling. The plurality of support layers SPT may be formed at different levels in the vertical direction Z on the sidewalls of the plurality of lower electrodes 181.

[0051] The capacitor dielectric film 183 may be disposed on the plurality of lower electrodes 181. The capacitor dielectric film 183 may extend from the sidewalls of the plurality of lower electrodes 181 to the upper and bottom surfaces of the support layer SPT and may extend onto the upper insulating pattern 170.

[0052] The upper electrode 185 may be disposed on the capacitor dielectric film 183. The upper electrode 185 may be disposed to completely cover the capacitor dielectric film 183 and may cover the plurality of lower electrodes 181 with the capacitor dielectric film 183 therebetween.

[0053] In one or more embodiments, each of the plurality of lower electrodes 181 and the upper electrode 185 may include at least one selected from metals (such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W)), conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN)), and conductive metal oxides (such as iridium oxide (IrO 2 )), ruthenium oxide (RuO 2 )), and strontium ruthenium oxide (SrRuO 3 ))).

[0054] In one or more embodiments, the capacitor dielectric film 183 may include at least one of zirconium oxide, hafnium oxide, titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanate, barium strontium titanate, scandium oxide, and lanthanide oxides.

[0055] The capacitor structure 180 may be formed only in the memory cell area MCA. That is, the capacitor structure 180 may not be formed in the peripheral circuit area PCA.

[0056] In the integrated circuit device 10 of the present disclosure, the stacked plate structure 190 may be arranged along the surface of the capacitor structure 180 having the above shape. Due to the large step difference between the memory cell area MCA and the peripheral circuit area PCA, the surface of the stacked plate structure 190 may include a flat upper surface and vertical sidewalls.

[0057] The stacked plate structure 190 may include a first plate layer 191, an intermediate layer 193 conformally covering the first plate layer 191, and a second plate layer 195 conformally covering the intermediate layer 193.

[0058] The first plate layer 191 may include a doped semiconductor material. In one or more embodiments, the first plate layer 191 may include silicon germanium (SiGe) doped with p-type impurities. Here, the p-type impurities may be, for example, boron (B), gallium (Ga), indium (In), etc. In addition, the first plate layer 191 may be in a crystalline state. The thickness of the first plate layer 191 may be about to about However, it is not limited thereto.

[0059] The intermediate layer 193 may include metal silicide (M x Si y ) or metal silicon nitride (M x Si y N z ). That is, the intermediate layer 193 may include any one selected from metal silicide (M x Si y ) and metal silicon nitride (M x Si y N z ). In one or more embodiments, the metal (M) may be tungsten (W). In this case, the intermediate layer 193 may include one selected from tungsten silicide (WSi x ) and tungsten silicon nitride (WSi x N y ), but it is not limited thereto.

[0060] The intermediate layer 193 may be in an amorphous state, or the intermediate layer 193 may be configured to have an amorphous state in most (more than 50%) of its regions and only a crystalline state in its local regions. That is, the main crystal structure of the intermediate layer 193 may be an amorphous structure. The thickness of the intermediate layer 193 may be about to about However, it is not limited thereto.

[0061] In addition, in the metal silicide (M x Si y ) or metal silicon nitride (M x Si y Nz ) In this case, the concentration of silicon (Si) can be from about 1 wt% to about 20 wt%. That is, by adjusting the concentration of silicon (Si), the sheet resistance of the intermediate layer 193 can be configured to satisfy from about 1 ohm to about 100 ohm, and the work function of the intermediate layer 193 can be configured to satisfy from about 4.4 eV to about 4.8 eV. However, the physical properties of the intermediate layer 193 are not limited to the above values.

[0062] The second plate layer 195 can have a plate shape made of the metal (M) included in the intermediate layer 193. In one or more embodiments, the metal (M) can be tungsten (W). In addition, the second plate layer 195 can be in a crystalline state. The thickness of the second plate layer 195 can be from about to about However, it is not limited thereto.

[0063] In the integrated circuit device 10 of the present disclosure, the shape of the stacked plate structure 190 is described in detail as follows.

[0064] In one or more embodiments, the surface roughness of the first plate layer 191 at the surface in contact with the intermediate layer 193 can be greater than the surface roughness of the second plate layer 195 at the surface in contact with the intermediate layer 193 (for example, see Figure 4 ) of the display area CX1. That is, the intermediate layer 193 can be formed to fill the relatively rough surface of the first plate layer 191, so that the surface of the second plate layer 195 can be formed to be relatively smooth. This characteristic may be due to the fact that the intermediate layer 193 is in an amorphous state, and the intermediate layer 193 is made of a material including both silicon (Si) included in the first plate layer 191 and the metal (M) included in the second plate layer 195.

[0065] In one or more embodiments, the sidewall of the first plate layer 191 can be completely covered by the intermediate layer 193, most of the sidewalls of the intermediate layer 193 can be in contact with the second plate layer 195, but a part of the lower region of the sidewall of the intermediate layer 193 can be in contact with the interlayer insulating film 210 to be described below. This characteristic may be attributed to the manufacturing process in which a part of the intermediate layer 193 and a part of the second plate layer 195 are dry-etched together.

[0066] In one or more embodiments, the thickness of the second plate layer 195 formed on the upper surface of the intermediate layer 193 in the vertical direction Z can be greater than the width of the second plate layer 195 formed on the sidewall of the intermediate layer 193 in the first horizontal direction X. This feature may be attributed to the fact that the forming method of the second plate layer 195 is a physical vapor deposition (PVD) process.

[0067] The interlayer insulating film 210 may be arranged to cover both the memory cell area MCA and the peripheral circuit area PCA. The interlayer insulating film 210 may have different thicknesses in the vertical direction Z in each area to cover the step difference according to the presence or absence of the capacitor structure 180 and the stacked plate structure 190 in the memory cell area MCA and the peripheral circuit area PCA.

[0068] In the memory cell area MCA, a plurality of metal contacts 220 penetrating the interlayer insulating film 210 and extending in the vertical direction Z may be arranged. The bottom portions of the plurality of metal contacts 220 may be electrically connected to the first plate layer 191 by contacting the first plate layer 191. That is, the bottom portions of the plurality of metal contacts 220 may be electrically connected to the upper electrode 185 of the capacitor structure 180 through the first plate layer 191. Each of the plurality of metal contacts 220 may include a conductive barrier film 222 and a contact conductive layer 224.

[0069] In one or more embodiments, the plurality of metal contacts 220 may sequentially penetrate the second plate layer 195 and the intermediate layer 193. In addition, the level of the lowermost surface of the plurality of metal contacts 220 may be arranged to be lower than the level of the uppermost surface of the first plate layer 191 and higher than the level of the uppermost surface of the upper electrode 185.

[0070] In the peripheral circuit area PCA, a peripheral circuit contact 230 penetrating the interlayer insulating film 210 and extending in the vertical direction Z may be arranged. The bottom portion of the peripheral circuit contact 230 may contact a contact pad, which is the upper portion of the contact plug CP. That is, the peripheral circuit contact 230 may be electrically connected to the peripheral circuit transistor PG through the contact plug CP. Similar to the plurality of metal contacts 220 formed in the memory cell area MCA, the peripheral circuit contact 230 may include a conductive barrier film 222 and a contact conductive layer 224.

[0071] In one or more embodiments, the level of the lowermost surface of the peripheral circuit contact 230 may be arranged to be substantially the same as the level of the lowermost surface of the first plate layer 191 and the level of the lowermost surface of the intermediate layer 193, and arranged to be lower than the level of the lowermost surface of the second plate layer 195.

[0072] In a device similar to the integrated circuit device 10, in order to ensure the sensing margin in the capacitor structure 180, a doped silicon germanium (SiGe) layer and a tungsten (W) plate layer may be formed and used together.

[0073] However, since the space between the doped silicon germanium (SiGe) layer and the tungsten (W) plate layer is a junction of heterogeneous materials, the interface resistance between the doped silicon germanium (SiGe) layer and the tungsten (W) plate layer is quite large. In addition, due to the surface roughness of the doped silicon germanium (SiGe) layer, its interface condition is poor and its adhesion strength is reduced, thus introducing potential points for tearing of the tungsten (W) plate layer. Furthermore, since the doped silicon germanium (SiGe) layer and the tungsten (W) plate layer are usually crystalline materials in the existing design, hydrogen (H) generated during the manufacturing process of the integrated circuit device may easily penetrate the grain boundaries, resulting in defects in the electrical characteristics of the capacitor structure similar to capacitor structure 180.

[0074] The present disclosure solves this problem by forming the intermediate layer 193 to include one selected from tungsten silicide (WSi x ) and tungsten silicon nitride (WSi x N y ), and being inserted between the first plate layer 191 including doped silicon germanium (SiGe) and the second plate layer 195 including tungsten (W).

[0075] That is, the intermediate layer 193 according to the embodiment includes both silicon (Si) contained in the first plate layer 191 and metal (M) contained in the second plate layer 195. Therefore, the intermediate layer 193 can be used as an adhesive layer between the first plate layer 191 and the second plate layer 195, and can also significantly reduce the interface resistance that appears between heterogeneous materials.

[0076] In addition, most or all regions of the intermediate layer 193 may include amorphous materials, and the amorphous materials do not have grain boundaries; therefore, the paths through which hydrogen (H) may move may be blocked. That is, the intermediate layer 193 can be used as a hydrogen (H) barrier layer.

[0077] Ultimately, by using the stacked plate structure 190 in a DRAM including the stacked plate structure 190 on the capacitor structure 180, the integrated circuit device 10 according to the embodiment can have improved electrical characteristics and product reliability, where the intermediate layer 193 is inserted between the first plate layer 191 of the doped silicon germanium (SiGe) layer and the second plate layer 195 of the tungsten (W) plate layer.

[0078] Figure 5 is a cross-sectional view showing an integrated circuit device according to another embodiment, Figure 6 is Figure 5 an enlarged view of a partial CX2 of

[0079] Hereinafter, most of the components constituting the integrated circuit device 20 and the materials of its components described below are the same as those referred to above Figures 1 to 4Those described are substantially the same or similar. Therefore, for ease of explanation, the following description mainly focuses on the differences between the integrated circuit device 20 and the integrated circuit device 10.

[0080] Referring together to Figure 5 and Figure 6 , the integrated circuit device 20 may include a substrate 110, and the substrate 110 includes a memory cell area MCA and a peripheral circuit area PCA.

[0081] In the integrated circuit device 20 of the present disclosure, the stacked plate structure 190A may be disposed along the surface of the capacitor structure 180. Due to the large step difference between the memory cell area MCA and the peripheral circuit area PCA, the surface of the stacked plate structure 190A may include a flat upper surface and a vertical sidewall.

[0082] The stacked plate structure 190A may include a first plate layer 191, a first intermediate layer 193A conformally covering the first plate layer 191, a second intermediate layer 193B conformally covering the first intermediate layer 193A, and a second plate layer 195 conformally covering the second intermediate layer 193B.

[0083] The first plate layer 191 may include p-type doped silicon germanium (SiGe). The thickness of the first plate layer 191 may be about to about However, it is not limited thereto.

[0084] In one or more embodiments, the first intermediate layer 193A may include metal silicide (M x Si y ), and the second intermediate layer 193B may include metal silicon nitride (M x Si y N z ). For example, the metal (M) may be tungsten (W). In this case, the first intermediate layer 193A may include tungsten silicide (WSi x ), and the second intermediate layer 193B may include tungsten silicon nitride (WSi x N y ), but the present disclosure is not limited thereto.

[0085] Here, the thickness AT of the first intermediate layer 193A may be less than the thickness BT of the second intermediate layer 193B. This is because the tungsten silicon nitride (WSi x N y ) forming the second intermediate layer 193B can more effectively block the penetration of hydrogen (H) generated during the manufacturing process of the integrated circuit device 20. Therefore, increasing the thickness BT of the second intermediate layer 193B can effectively improve the electrical characteristics of the integrated circuit device 20.

[0086] In another embodiment, the first intermediate layer 193A may include metal silicon nitride (M x Si y N z ), and the second intermediate layer 193B may include metal silicide (M x Si y ). In this case, different from the embodiment Figure 6 shown, the thickness AT of the first intermediate layer 193A may be greater than the thickness BT of the second intermediate layer 193B. The reason is the same as that explained above.

[0087] Each of the first intermediate layer 193A and the second intermediate layer 193B may be in an amorphous state, or the first intermediate layer 193A and the second intermediate layer 193B may be configured to have an amorphous state in most (more than 50%) of their regions and only have a crystalline state in their local regions. That is, the main crystal structure of each of the first intermediate layer 193A and the second intermediate layer 193B may be in an amorphous state.

[0088] In addition, in the metal silicide (M x Si y ) or metal silicon nitride (M x Si y N z ) respectively constituting the first intermediate layer 193A and the second intermediate layer 193B, the concentration of silicon (Si) may be about 1 wt% to about 20 wt%, but the present disclosure is not limited thereto.

[0089] The second plate layer 195 may include the metal (M) included in the first intermediate layer 193A and the second intermediate layer 193B. In addition, the second plate layer 195 may be in a crystalline state. The thickness of the second plate layer 195 may be about to about However, it is not limited thereto.

[0090] In the integrated circuit device 20 of the present disclosure, the shape of the stacked plate structure 190A is described in detail as follows.

[0091] In one or more embodiments, the surface roughness of the first plate layer 191 at the surface in contact with the first intermediate layer 193A may be greater than the surface roughness of the second plate layer 195 at the surface in contact with the second intermediate layer 193B. That is, the first intermediate layer 193A may be formed to fill the relatively rough surface of the first plate layer 191, and the surface of the second plate layer 195 may be formed to be relatively smooth (see, for example, the Figure 6) This characteristic may be attributed to each of the first intermediate layer 193A and the second intermediate layer 193B being in an amorphous state, and the first intermediate layer 193A and the second intermediate layer 193B including materials containing both silicon (Si) included in the first plate layer 191 and metal (M) included in the second plate layer 195.

[0092] In one or more embodiments, the sidewalls of the first plate layer 191 may be completely covered by the first intermediate layer 193A. Most of the sidewalls of the first intermediate layer 193A may be in contact with the second intermediate layer 193B, but a part of the lower region of the sidewalls of the first intermediate layer 193A may be in contact with the interlayer insulating film 210. In addition, most of the sidewalls of the second intermediate layer 193B may be in contact with the second plate layer 195, but a part of the lower region of the sidewalls of the second intermediate layer 193B may be in contact with the interlayer insulating film 210.

[0093] In one or more embodiments, the thickness of the second plate layer 195 formed on the upper surface of the second intermediate layer 193B in the vertical direction Z may be greater than the width of the second plate layer 195 formed on the sidewalls of the second intermediate layer 193B in the first horizontal direction X.

[0094] Finally, the integrated circuit device 20 according to the embodiment may have improved electrical characteristics and product reliability by using the stacked plate structure 190A in a DRAM including the stacked plate structure 190A on the capacitor structure 180, wherein the first intermediate layer 193A and the second intermediate layer 193B are inserted between the first plate layer 191 of the doped silicon germanium (SiGe) layer and the second plate layer 195 of the tungsten (W) plate layer.

[0095] Figure 7 is a layout diagram showing an integrated circuit device according to another embodiment, Figure 8 is along Figure 7 a cross-sectional view of the integrated circuit device taken along line C1-C1' of.

[0096] Hereinafter, most of the components constituting the integrated circuit device 30 described below and the materials of the components are basically the same as or similar to those described above with reference to Figures 1 to 4 Therefore, for ease of explanation, the following description focuses on the differences between the integrated circuit device 30 and the integrated circuit device 10.

[0097] Referring together to Figure 7 and Figure 8 , the integrated circuit device 30 may include a plurality of conductive lines 320, a channel layer 330, a gate electrode layer 340, a gate insulating layer 350, and a capacitor structure 180 disposed in the memory cell area MCA of the substrate 110.

[0098] The integrated circuit device 30 of the present disclosure may be a memory device including vertical-channel transistors, which may be referred to as a structure in which the channel length of the channel layer 330 extends from the substrate 110 in the vertical direction Z.

[0099] The lower insulating layer 312 may be disposed on the substrate 110, and a plurality of wires 320 may be disposed on the lower insulating layer 312 to be spaced apart from each other in the first horizontal direction X and extend in the second horizontal direction Y. A plurality of first insulating patterns 322 may be disposed on the lower insulating layer 312 to fill the spaces between the plurality of wires 320. The plurality of wires 320 may respectively correspond to the bit lines BL of the integrated circuit device 30.

[0100] In one or more embodiments, the plurality of wires 320 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The plurality of wires 320 may include a single layer or multiple layers, and each layer includes the above materials. In other embodiments, the plurality of wires 320 may include two-dimensional materials, and the two-dimensional materials may include, for example, graphene, carbon nanotubes, nanosheets, or a combination thereof.

[0101] The channel layer 330 may be disposed in an island shape on the plurality of wires 320 to be spaced apart from each other in the first horizontal direction X and the second horizontal direction Y. The channel layer 330 may have a first width in the first horizontal direction X and a first height in the vertical direction Z, and the first height may be greater than the first width. The bottom portion of the channel layer 330 may be used as a first source / drain region, the upper portion of the channel layer 330 may be used as a second source / drain region, and the portion of the channel layer 330 between the first source / drain region and the second source / drain region may be used as a channel region.

[0102] The gate electrode layer 340 may surround the sidewalls of the channel layer 330 and extend along the first horizontal direction X. In a plan view, the gate electrode layer 340 may be a fully surrounding gate type that surrounds all the sidewalls of the channel layer 330 (e.g., all four sidewalls). The gate electrode layer 340 may correspond to the word line WL of the integrated circuit device 30.

[0103] In other embodiments, the gate electrode layer 340 may be a double-gate type and may include, for example, a first sub-gate electrode facing the first sidewall of the channel layer 330 and a second sub-gate electrode facing the second sidewall opposite to the first sidewall of the channel layer 330. In other embodiments, the gate electrode layer 340 may be a single-gate type that only covers the first sidewall of the channel layer 330 and extends in the first horizontal direction X.

[0104] The gate electrode layer 340 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0105] The gate insulating layer 350 may surround the sidewalls of the channel layer 330 and may be disposed between the channel layer 330 and the gate electrode layer 340. In one or more embodiments, the gate insulating layer 350 may include silicon oxide, silicon nitride, a high-k dielectric material, or a combination thereof.

[0106] The first buried insulating layer 342 surrounding the lower sidewalls of the channel layer 330 may be disposed on the plurality of first insulating patterns 322, and the second buried insulating layer 344 surrounding the lower sidewalls of the channel layer 330 and covering the gate electrode layer 340 may be disposed on the first buried insulating layer 342.

[0107] The capacitor contact 360 may be disposed above the channel layer 330. The capacitor contacts 360 may be arranged to overlap the channel layer 330 in the vertical direction Z and may be arranged in a matrix form so as to be spaced apart from each other in the first horizontal direction X and the second horizontal direction Y. The upper insulating layer 362 may be disposed on the second buried insulating layer 344 so as to surround the sidewalls of the capacitor contacts 360.

[0108] In the integrated circuit device 30 of the present disclosure, the upper insulating pattern 170 may be disposed on the upper insulating layer 362, and the capacitor structure 180 may be disposed on the upper insulating pattern 170. In addition, the stacked plate structure 190 may be disposed along the surface of the capacitor structure 180. Here, the stacked plate structure 190 may include a first plate layer 191, an intermediate layer 193 conformally covering the first plate layer 191, and a second plate layer 195 conformally covering the intermediate layer 193.

[0109] Figure 9 is a flowchart showing a method of manufacturing an integrated circuit device according to an embodiment.

[0110] Referring to Figure 9 , the method S10 of manufacturing an integrated circuit device may include the process sequence of the first to eighth operations S110 to S180.

[0111] When a certain embodiment may be implemented in a different manner, a specific process sequence may be performed in a manner different from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the described order.

[0112] The method S10 for manufacturing an integrated circuit device according to the present disclosure may include: a first operation S110 of forming cell transistors in a memory cell region and forming peripheral circuit transistors and contact plugs connected to the peripheral circuit transistors in a peripheral circuit region; a second operation S120 of forming capacitor structures on the plurality of cell transistors; a third operation S130 of conformally forming a first plate layer covering the capacitor structures in the memory cell region; a fourth operation S140 of conformally forming an intermediate layer covering the first plate layer in the memory cell region and covering the contact plugs in the peripheral circuit region; a fifth operation S150 of conformally forming a second plate layer covering the intermediate layer; a sixth operation S160 of exposing the contact plugs by removing a part of the second plate layer and a part of the intermediate layer in the peripheral circuit region; a seventh operation S170 of conformally covering an interlayer insulating film of the second plate layer and the contact plugs; and an eighth operation S180 of forming a plurality of metal contacts connected to the first plate layer in the memory cell region and peripheral circuit contacts connected to the contact plugs in the peripheral circuit region.

[0113] The following refers to Figures 10 to 19 The technical features of each of the first to eighth operations S110 to S180 are described in detail.

[0114] Figures 10 to 19 is a cross-sectional view showing a method for manufacturing an integrated circuit device according to an embodiment in a process sequence.

[0115] Referring to Figure 10 , a plurality of device isolation trenches 112T and a plurality of device isolation films 112 may be formed in a substrate 110 having a memory cell region MCA and a peripheral circuit region PCA.

[0116] Through the plurality of device isolation films 112, a plurality of first active regions AC1 may be defined in the memory cell region MCA of the substrate 110, and a second active region AC2 may be defined in the peripheral circuit region PCA of the substrate 110. Next, a gate dielectric film 116 may be formed on the substrate 110 in the peripheral circuit region PCA.

[0117] Then, a direct contact hole DCH exposing the first active region AC1 may be formed by removing a part of the substrate 110, and a direct contact DC may be formed in the direct contact hole DCH. Next, a bit line BL and an insulating capping layer 140A may be formed on the direct contact DC, and a gate electrode PGS and a gate capping pattern 140B may be formed on the gate dielectric film 116. Then, a gate spacer 150B may be formed on the sidewall of the gate electrode PGS, and a first insulating film 142 covering the gate electrode PGS may be formed.

[0118] Next, spacers 150A can be formed on bit lines BL and the insulating cover layer 140A in the memory cell area MCA, and a plurality of insulating fences can be formed between the plurality of bit lines BL. Then, a part of the substrate 110 at the bottom of the contact space arranged between the plurality of bit lines BL and the plurality of insulating fences can be removed to form a plurality of recessed spaces RS exposing the first active region AC1 between the plurality of bit lines BL. Next, a plurality of conductive plugs 152 can be formed to fill a part of the contact space between the plurality of bit lines BL while filling the plurality of recessed spaces RS.

[0119] Then, a plurality of contact holes CPH exposing the second active region AC2 can be formed by etching the first insulating film 142 in the peripheral circuit area PCA.

[0120] Next, a plurality of landing pads LP each including a conduction blocking film 162A and a landing pad conductive layer 164A can be formed in the memory cell area MCA, and a plurality of contact plugs CP each including a conduction blocking film 162B and a landing pad conductive layer 164B can be formed in the peripheral circuit area PCA. Then, an insulating pattern 166 surrounding the sidewalls of the plurality of landing pads LP and a second insulating film 144 covering the sidewalls of the contact plugs CP can be formed.

[0121] Referring to Figure 11 , in the memory cell area MCA, a mold structure including a plurality of mold layers sequentially arranged on the upper insulating pattern 170 can be formed.

[0122] A support layer SPT can be selectively formed between and on the plurality of mold layers.

[0123] Then, a mask pattern can be formed on the mold structure, an opening part penetrating the mold structure can be formed by using the mask pattern as an etching mask, and a lower electrode 181 can be formed in the opening part.

[0124] Next, the upper insulating pattern 170, the lower electrode 181, and the support layer SPT can be formed by removing the mold structure.

[0125] Referring to Figure 12 , a capacitor dielectric film 183 can be formed on the upper insulating pattern 170, the lower electrode 181, and the support layer SPT.

[0126] Specifically, the capacitor dielectric film 183 can be formed on the plurality of lower electrodes 181 in the memory cell area MCA. The capacitor dielectric film 183 can extend from the sidewalls of the plurality of lower electrodes 181 to the upper surface and the bottom surface of the support layer SPT, and can extend onto the upper insulating pattern 170.

[0127] Then, an upper electrode 185 can be formed on the capacitor dielectric film 183. The upper electrode 185 can be formed to completely cover the capacitor dielectric film 183 and can be formed to cover a plurality of lower electrodes 181, with the capacitor dielectric film 183 therebetween.

[0128] In this way, a capacitor structure 180 including the lower electrode 181, the capacitor dielectric film 183, and the upper electrode 185 can be formed.

[0129] Referring to Figure 13 , a first plate layer 191 can be formed in the memory cell area MCA to cover the capacitor structure 180.

[0130] The first plate layer 191 can be formed by doping silicon germanium (SiGe) with a p-type impurity. The p-type impurity can be, for example, boron (B), gallium (Ga), indium (In), etc. In addition, the first plate layer 191 can be in a crystalline state. The thickness of the first plate layer 191 can be about to about However, it is not limited thereto.

[0131] Referring to Figure 14 , an intermediate layer 193 can be conformally formed to cover the first plate layer 191 in the memory cell area MCA and the contact plug CP in the peripheral circuit area PCA.

[0132] The intermediate layer 193 can include metal silicide (M x Si y ) or metal silicon nitride (M x Si y N z ). In one or more embodiments, the metal (M) can be tungsten (W). In this case, the intermediate layer 193 can include one selected from tungsten silicide (WSi x ) and tungsten silicon nitride (WSi x N y ). When the intermediate layer 193 includes tungsten silicon nitride (WSi x N y ), nitrogen (N) can be included in the intermediate layer 193 through a plasma nitridation process.

[0133] Here, the intermediate layer 193 can be in an amorphous state, or the intermediate layer 193 can be configured to have an amorphous state in most (more than 50%) of its regions and only have a crystalline state in its local regions. The thickness of the intermediate layer 193 can be about to about However, it is not limited thereto.

[0134] Referring to Figure 15 , a second plate layer 195 can be formed to conformally cover the intermediate layer 193.

[0135] The second plate layer 195 may be formed to include a metal (M) included in the intermediate layer 193. In one or more embodiments, the metal (M) may be tungsten (W). Further, the second plate layer 195 may be formed to have a crystalline state. The thickness of the second plate layer 195 may be formed to range from about to about However, it is not limited thereto.

[0136] In one or more embodiments, the thickness of the second plate layer 195 formed on the upper surface of the intermediate layer 193 in the vertical direction Z may be greater than the width of the second plate layer 195 formed on the sidewall of the intermediate layer 193 in the first horizontal direction X. This characteristic may be attributed to the fact that the formation method of the second plate layer 195 is a PVD process.

[0137] Referring to Figure 16 , by using the mask pattern MP as an etching mask to etch a part of the intermediate layer 193 and the second plate layer 195 in the peripheral circuit area PCA, the contact pads of each of the plurality of contact plugs CP can be exposed.

[0138] The etching may be a dry etching process. The dry etching process may be performed as a process of etching a part of the intermediate layer 193 and the second plate layer 195 in the peripheral circuit area PCA but reducing the etching of the plurality of contact plugs CP and the second insulating film 144.

[0139] Specifically, the outermost sidewall of the intermediate layer 193, the outermost sidewall of the second plate layer 195, and the outermost sidewall of the mask pattern MP may be coplanar in the vertical direction Z. After the dry etching process, the mask pattern MP may be removed in an ashing and stripping process.

[0140] Accordingly, the sidewall of the first plate layer 191 may be completely covered by the intermediate layer 193, and most of the sidewalls of the intermediate layer 193 may be in contact with the second plate layer 195, but a part of the lower region of the sidewall of the intermediate layer 193 may be exposed to the outside. This characteristic may be attributed to the manufacturing process in which a part of the intermediate layer 193 and a part of the second plate layer 195 are dry-etched together.

[0141] Referring to Figure 17 , an interlayer insulating film 210 may be formed to conformally cover the intermediate layer 193, the second plate layer 195, and the plurality of contact plugs CP.

[0142] The interlayer insulating film 210 may be formed to cover both the memory cell area MCA and the peripheral circuit area PCA. Specifically, the interlayer insulating film 210 may have different thicknesses in the vertical direction Z in each region to cover the step difference according to the presence or absence of the capacitor structure 180 and the stacked plate structure 190 in the memory cell area MCA and the peripheral circuit area PCA.

[0143] Referring to Figure 18 , a plurality of metal contact holes 220H penetrating the interlayer insulating film 210 can be formed in the memory cell region MCA, and peripheral circuit contact holes 230H penetrating the interlayer insulating film 210 can be formed in the peripheral circuit region PCA.

[0144] Specifically, the plurality of metal contact holes 220H can expose the inside of the first plate layer 191 by penetrating the interlayer insulating film 210, the second plate layer 195, and the intermediate layer 193, and the peripheral circuit contact holes 230H can expose the uppermost surface of the contact pad of the contact plug CP by penetrating the interlayer insulating film 210.

[0145] Referring to Figure 19 , a conductive barrier film 222 that conformally covers the inner sidewalls of the plurality of metal contact holes 220H and the inner sidewalls of the peripheral circuit contact holes 230H can be formed.

[0146] Specifically, the conductive barrier film 222 can be continuously and conformally formed on the memory cell region MCA and the peripheral circuit region PCA. The conductive barrier film 222 can include Ti, TiN, or a combination thereof, but is not limited thereto.

[0147] Referring again to Figure 3 , a contact conductive layer 224 filling the plurality of metal contact holes 220H and the peripheral circuit contact holes 230H can be formed, and the upper portions of the contact conductive layer 224 and the conductive barrier film 222 can be polished to form a plurality of metal contacts 220 and peripheral circuit contacts 230.

[0148] Figure 20 is a configuration diagram showing a system including an integrated circuit device according to an embodiment.

[0149] Referring to Figure 20 , the system 1000 can include a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050.

[0150] The system 1000 can be a mobile system or a system that transmits or receives information. In one or more embodiments, the mobile system can be a portable computer, a netbook, a mobile phone, a digital music player, or a memory card.

[0151] The controller 1010 is configured to control the execution programs in the system 1000 and can include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0152] The input / output device 1020 can be used to input or output data of the system 1000. The system 1000 can be connected to an external device, such as a personal computer or a network, by using the input / output device 1020, and can exchange data with the external device. The input / output device 1020 can be, for example, a touch screen, a touch pad, a keyboard, or a display device.

[0153] The storage device 1030 can store the operation data of the controller 1010 or store the data processed by the controller 1010. The storage device 1030 can include any one of the integrated circuit devices 10, 20, and 30 according to the above embodiments.

[0154] The interface 1040 can be a data transmission path between the system 1000 and an external device. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 can communicate with each other through the bus 1050.

[0155] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

[0156] Cross-reference to related applications

[0157] This application is based on and claims priority to Korean Patent Application No. 10-2023-0178047, filed with the Korean Intellectual Property Office on December 8, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device comprising: A substrate including a memory cell region and a peripheral circuit region around the memory cell region; a cell transistor in the memory cell region; a peripheral circuit transistor in the peripheral circuit region; a capacitor structure including a lower electrode on the unit transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; as well as an interlayer insulating film covering the stacked plate structure in the memory cell region and covering the peripheral circuit transistor in the peripheral circuit region, The stacked plate structure comprises: a first plate layer including doped silicon germanium (SiGe); The intermediate layer conformally covers the first plate layer and includes a metal silicide (M) containing a metal (M) x Si y );as well as A second plate layer conformally covers the intermediate layer and includes the metal (M) in the metal silicide.

2. The integrated circuit device according to claim 1, wherein at least a portion of the intermediate layer is in an amorphous state, and Each of the first ply and the second ply is in a crystalline state.

3. The integrated circuit device according to claim 1, wherein the thickness of the first plate layer is to The thickness of the intermediate layer is to The thickness of the second board layer is to 4. The integrated circuit device according to claim 1, wherein: The metal silicide (M x Si y ) includes a silicon (Si) concentration ranging from 1 wt % to 20 wt %.

5. The integrated circuit device according to claim 1, wherein the first plate layer is doped with p-type impurities, and The metal (M) includes tungsten (W). 6 . The integrated circuit device according to claim 1 , wherein a surface roughness of a surface of the first plate layer in contact with the intermediate layer is greater than a surface roughness of a surface of the second plate layer in contact with the intermediate layer.

7. The integrated circuit device according to claim 1, wherein the side wall of the first board layer is completely covered by the middle layer, wherein a portion of the side wall of the intermediate layer is in contact with the second board layer, and The side wall of the intermediate layer except the portion in contact with the second plate layer is in contact with the interlayer insulating film.

8. The integrated circuit device of claim 1, wherein a vertical thickness of a first portion of the second plate layer formed on an upper surface of the intermediate layer is greater than a horizontal width of a second portion of the second plate layer formed on a sidewall of the intermediate layer.

9. The integrated circuit device according to claim 1, further comprising: a metal contact connected to the stacked plate structure and penetrating the interlayer insulating film in the memory cell region; as well as A peripheral circuit contact is connected to the peripheral circuit transistor and penetrates the interlayer insulating film in the peripheral circuit region.

10. The integrated circuit device according to claim 9, in, The metal contact sequentially penetrates the second plate layer and the middle layer, wherein the level of the lowermost surface of the metal contact is lower than the level of the uppermost surface of the first plate layer and higher than the level of the uppermost surface of the upper electrode, and The level of the lowermost surface of the peripheral circuit contact is substantially the same as the level of the lowermost surface of the first board layer and the level of the lowermost surface of the intermediate layer, and is lower than the level of the lowermost surface of the second board layer.

11. An integrated circuit device comprising: A substrate including a memory cell region and a peripheral circuit region around the memory cell region; a cell transistor in the memory cell region; a peripheral circuit transistor in the peripheral circuit region; a capacitor structure including a lower electrode on the unit transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; as well as an interlayer insulating film covering the stacked plate structure in the memory cell region and covering the peripheral circuit transistor in the peripheral circuit region, The stacked plate structure comprises: a first slab layer comprising doped silicon germanium (SiGe); a second sheet layer comprising a metal (M); as well as Contains metal silicide (M x Si y ) and a first intermediate layer comprising metal silicon nitride (M x Si y N) a second intermediate layer, wherein the first intermediate layer and the second intermediate layer are between the first board layer and the second board layer.

12. The integrated circuit device according to claim 11, wherein each of the first ply and the second ply is in a crystalline state, and At least a portion of each of the first intermediate layer and the second intermediate layer is in an amorphous state.

13. The integrated circuit device according to claim 11, wherein: The thickness of the first intermediate layer is smaller than the thickness of the second intermediate layer.

14. The integrated circuit device according to claim 11, wherein: The first board layer is in direct contact with the first intermediate layer, and the second board layer is in direct contact with the second intermediate layer.

15. The integrated circuit device according to claim 11, wherein: The first board layer is in direct contact with the second intermediate layer, and the second board layer is in direct contact with the first intermediate layer.

16. An integrated circuit device comprising: a cell transistor in a memory cell region of the integrated circuit device; a capacitor structure including a lower electrode on the unit transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; an interlayer insulating film covering the stacked plate structure; as well as a metal contact connected to the stacked plate structure and penetrating the interlayer insulating film, The stacked plate structure comprises: a first plate layer comprising doped silicon germanium (SiGe); The intermediate layer conformally covers the first plate layer and comprises tungsten silicide (WSi x ) and tungsten silicon nitride (WSi x N y ) The second plate layer conformally covers the intermediate layer and comprises tungsten (W).

17. The integrated circuit device according to claim 16, wherein: The intermediate layer includes a material in an amorphous state, or a material layer in which more than 50% of its area is in an amorphous state and includes partial crystallization.

18. The integrated circuit device according to claim 16, wherein: The intermediate layer contains silicon (Si) at a concentration ranging from 1 wt % to 20 wt %.

19. The integrated circuit device according to claim 18, wherein: The sheet resistance of the intermediate layer is in the range of 1 ohm to 100 ohm.

20. The integrated circuit device according to claim 19, wherein: The work function of the intermediate layer is in the range of 4.4 eV to 4.8 eV.

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