Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and electronic equipment. The semiconductor structure comprises a substrate; the word lines are arranged on the substrate and extend in the direction perpendicular to the substrate; the multiple layers of memory cell arrays are arranged in the direction perpendicular to the substrate, each layer of memory cell array comprises multiple active channels arranged in the first direction, the multiple active channels are arranged at intervals in the extending direction of the word lines, and the active channels cover part of the circumferential faces of the word lines; the at least one first active region is arranged on one side of the active channel in the second direction and is connected with the active channel; the at least one second active region is arranged on the other side of the active channel in the second direction relative to the at least one first active region and is connected with the active channel; in the first direction, the size of the active channel is larger than at least one of the size of the part, connected with the active channel, of the first active region and the size of the part, connected with the active channel, of the second active region, and the yield and the electrical performance of the semiconductor structure are improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, the industry has proposed various semiconductor structure designs and process optimizations to meet the requirements of current products. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure, a manufacturing method thereof, and an electronic device.

[0005] In a first aspect, the present application provides a semiconductor structure, including:

[0006] A substrate;

[0007] A word line disposed on the substrate and extending in a direction perpendicular to the substrate;

[0008] A multi-layer memory cell array disposed in a direction perpendicular to the substrate. Each layer of the memory cell array includes a plurality of active channels arranged in a first direction; the plurality of active channels are spaced apart along the extending direction of the word line, and a part of the peripheral surface of the word line is covered by the active channels;

[0009] At least one first active region disposed on one side of the active channel in a second direction and connected to the active channel. The first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction;

[0010] At least one second active region disposed on the other side of the active channel in the second direction relative to at least one first active region and connected to the active channel;

[0011] Along the first direction, the size of the active channel is greater than at least one of the size of the part of the first active region connected to the active channel and the size of the part of the second active region connected to the active channel.

[0012] Optionally, along the direction perpendicular to the substrate, the plurality of first active regions are spaced apart, and the plurality of first active regions are connected to the same active channel.

[0013] Optionally, along a direction perpendicular to the substrate, the multiple first active regions and the multiple active channels are connected in one-to-one correspondence.

[0014] Optionally, the word line includes a main body portion extending along a direction perpendicular to the substrate and a partition portion provided on the peripheral surface of the main body portion. The partition portions are arranged at intervals along a direction perpendicular to the substrate, and the partition portions are provided between the first active regions adjacent along a direction perpendicular to the substrate and / or between the second active regions adjacent along a direction perpendicular to the substrate.

[0015] Optionally, each layer of the memory cell array further includes:

[0016] A capacitor, the capacitor including a first electrode, a dielectric layer, and a second electrode. The first electrode includes a partial structure of the first active region, the dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the dielectric layer.

[0017] Optionally, the second active region includes a main body portion and a connection portion. The main body portion extends along the first direction, and the connection portion connects the main body portion and the active channel.

[0018] Optionally, the multiple word lines are arranged at intervals along the first direction. A plurality of connection portions are provided on a side of the second active region close to the active channel, and the multiple connection portions are arranged at intervals along the first direction.

[0019] Optionally, along the first direction, the size of the active channel is greater than the size of the connection portion.

[0020] Optionally, it further includes:

[0021] A protective layer and a gate insulating layer. The gate insulating layer, the protective layer, and the active channel are sequentially provided along a direction away from the word line.

[0022] In a second aspect, the present application provides an electronic device including the semiconductor structure as described in the first aspect.

[0023] In a third aspect, the present application provides a method for manufacturing a semiconductor structure, including the following steps:

[0024] Providing a substrate, forming a stacked structure on the substrate. The stacked structure includes a functional layer and a sacrificial layer. The functional layer includes at least one active material layer. Along a direction perpendicular to the substrate, the functional layer and the sacrificial layer are alternately arranged;

[0025] Patterning the stacked structure, and the active material layer forms an initial active layer;

[0026] Form at least one channel trench that penetrates the stacked structure in a direction perpendicular to the substrate, and the channel trench divides the initial active layer into a first active region and a second active region;

[0027] Form a semiconductor layer and a word line in sequence in the channel trench;

[0028] Etch away at least part of the sacrificial layer and part of the semiconductor layer, and divide the semiconductor layer into multiple active channels, and the multiple active channels are arranged at intervals in a direction perpendicular to the substrate.

[0029] Optionally, after forming at least one channel trench, the manufacturing method of the semiconductor structure further includes the following steps:

[0030] Remove part of the functional layer or part of the sacrificial layer exposed by the channel trench, and form a recess on the sidewall of the channel trench, and the recess is recessed in a direction parallel to the substrate and away from the channel trench;

[0031] The word line includes a main body portion extending in the stacking direction of the stacked structure and a partition portion provided on the peripheral surface of the main body portion. The partition portions are arranged at intervals in the stacking direction of the stacked structure, and the partition portions are filled in the recesses, and the partition portions are formed between the first active regions adjacent in the stacking direction of the stacked structure and / or between the second active regions adjacent in the stacking direction of the stacked structure.

[0032] Optionally, along the stacking direction of the stacked structure, the functional layer includes the active material layer and the dielectric layer arranged alternately.

[0033] Optionally, the manufacturing method of the semiconductor structure further includes the following steps:

[0034] Remove part of the dielectric layer to expose part of the sidewall of the first active region covered by the dielectric layer;

[0035] Form a dielectric layer that covers the exposed sidewall of the first active region;

[0036] Form a second electrode that covers the dielectric layer, and use the part of the structure of the first active region covered by the dielectric layer as the first electrode, and the second electrode, the dielectric layer and the first electrode form a capacitor.

[0037] Optionally, the second active region extends in a first direction, a connection portion is formed on a side of the second active region close to the channel trench, and the second active region is connected to the active channel through the connection portion, and the first direction is parallel to the substrate.

[0038] Optionally, along the first direction, the size of the active channel is greater than at least one of the size of the first active region and the size of the connection portion.

[0039] Optionally, at least part of the sacrificial layer is etched away, and etching away part of the semiconductor layer includes:

[0040] A first through hole is formed between adjacent word lines, and the first through hole exposes a part of the top surface of the substrate;

[0041] Based on the first through hole, the sacrificial layer and the semiconductor layer are etched until the semiconductor layer located between the adjacent functional layers is removed.

[0042] Optionally, the manufacturing method further includes the following steps:

[0043] A protective layer and a gate insulating layer are formed, and the gate insulating layer, the protective layer, and the semiconductor layer are sequentially arranged in a direction away from the word line.

[0044] The semiconductor structure, its manufacturing method, and the electronic device of the present application have the following beneficial effects:

[0045] In the semiconductor structure of the present application, there is no conductive film layer remaining from the manufacturing process between adjacent active channels, which can avoid or reduce the parasitic transistor problem between adjacent transistors in the semiconductor structure, improve the response speed of the semiconductor structure, and improve the electrical performance of the semiconductor structure;

[0046] In the semiconductor structure of the present application, by changing the in-plane size relationship of the source region (S) / drain region (D) and the channel, the channel length can be increased, the short-channel effect can be reduced, and at the same time, damage to the channel during the process can be avoided.

[0047] In the manufacturing method of the semiconductor structure of the present application, by adjusting the stacking rule of the stacked structure and arranging a sacrificial layer between adjacent functional layers, the semiconductor layer connected to the sacrificial layer can be exposed by removing the sacrificial layer, so as to remove the semiconductor layer connected to the sacrificial layer, and the entire semiconductor layer is divided into independently arranged active channels, avoiding the generation of parasitic channels due to the remaining semiconductor layer between adjacent transistors. This method can effectively simplify the processing technology, increase the process critical window value, reduce the process difficulty, and improve the product yield. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 Flow chart of a method for fabricating a semiconductor structure provided in some embodiments.

[0050] Figure 2 Schematic structural diagram of a stacked structure formed on a substrate shown in some embodiments.

[0051] Figure 3 For some embodiments, shown along the Figure 2 Cross-sectional view perpendicular to the substrate taken along line A-A in.

[0052] Figure 4 Top view after patterning the stacked structure to form an initial active layer in some embodiments.

[0053] Figure 5 Top view after forming a support layer in some embodiments.

[0054] Figure 6 Top view after forming a channel trench in some embodiments.

[0055] Figure 7 For some embodiments, shown along the Figure 6 Cross-sectional view perpendicular to the substrate taken along line B-B in.

[0056] Figure 8 For some embodiments, shown along the Figure 6 Cross-sectional view perpendicular to the substrate taken along line B-B after forming a recess.

[0057] Figure 9 For some embodiments, shown along the Figure 6 Cross-sectional view perpendicular to the substrate taken along line B-B after forming a semiconductor layer.

[0058] Figure 10 For some embodiments, shown along the Figure 6 Cross-sectional view perpendicular to the substrate taken along line B-B after forming a protective layer.

[0059] Figure 11 For some embodiments, shown along the Figure 6 Cross-sectional view perpendicular to the substrate taken along line B-B after forming a word line.

[0060] Figure 12 For some embodiments, shown along the Figure 6 Cross-sectional view perpendicular to the substrate taken along line C-C after forming a word line.

[0061] Figure 13 Top view after forming a first via hole shown in some embodiments.

[0062] Figure 14 A cross-sectional view perpendicular to the substrate taken along the C-C line after the formation of the first via hole as shown in some embodiments. Figure 6

[0063] Figure 15 A cross-sectional view perpendicular to the substrate taken along the C-C line after the formation of a plurality of active channels as shown in some embodiments. Figure 6

[0064] Figure 16 A cross-sectional view perpendicular to the substrate taken along the B-B line after the formation of a plurality of active channels as shown in some embodiments. Figure 6

[0065] Figure 17 A cross-sectional view perpendicular to the substrate taken along the B-B line after the formation of the insulating layer as shown in some embodiments. Figure 6

[0066] Figure 18 A schematic structural diagram after the formation of the first trench as shown in some embodiments.

[0067] Figure 19 A cross-sectional view perpendicular to the substrate taken along the B-B line after the formation of the first trench as shown in some embodiments. Figure 6

[0068] Figure 20 A cross-sectional view perpendicular to the substrate taken along the B-B line after removing a part of the dielectric layer as shown in some embodiments. Figure 6

[0069] Figure 21 A cross-sectional view perpendicular to the substrate taken along the B-B line after the formation of the capacitor as shown in some embodiments. Figure 6

[0070] Figure 22 A schematic structural diagram after the formation of the capacitor as shown in some embodiments.

[0071] Figure 23 For Figure 22 A schematic structural diagram after omitting the support layer.

[0072] Figure 24 A cross-sectional view perpendicular to the substrate taken along the A-A line of the stacked structure as shown in some embodiments. Figure 2

[0073] Figure 25 A cross-sectional view perpendicular to the substrate taken along the A-A line of the stacked structure as shown in some embodiments. Figure 2 ​​​​​​​​​

[0074] Figure 26 A vertical cross-sectional view perpendicular to the substrate taken along line B-B after forming a capacitor in some embodiments. Figure 6 after forming a capacitor.

[0075] Figure 27 A vertical cross-sectional view perpendicular to the substrate taken along line D-D after forming a capacitor. Figure 26 after forming a capacitor.

[0076] Figure 28 A top view of a semiconductor structure provided in some embodiments.

[0077] Figure 29 A vertical cross-sectional view perpendicular to the substrate taken along line B-B of a semiconductor structure provided in some embodiments. Figure 28 after forming a capacitor.

[0078] Figure 30 A vertical cross-sectional view perpendicular to the substrate taken along line C-C of a semiconductor structure provided in some embodiments. Figure 28 after forming a capacitor.

[0079] Description of reference numerals:

[0080] 10. Substrate; 100. Memory cell array; 01. Capacitance region; 20. Stacked structure; 21. Sacrificial layer; 22. Functional layer; 23. Active material layer; 130. Body portion; 230. Connection portion; 123. First active region; 223. Second active region; 231. First active material layer; 232. Second active material layer; 24. Dielectric layer; 241. First dielectric layer; 242. Second dielectric layer; 243. Third dielectric layer; 31. Channel trench; 311. Depression; 32. First via; 25. Initial active layer; 251. First part; 252. Second part; 33. First trench; 40. Active channel; 41. Semiconductor layer; 50. Word line; 150. Body portion; 250. Partition portion; 51. Gate insulating layer; 52. Gate; 53. Protective layer; 60. Isolation layer; 61. Insulating layer; 70. Capacitor; 71. First electrode; 72. Dielectric layer; 73. Second electrode; 731. First sub-electrode of the second electrode; 732. Second sub-electrode of the second electrode;

[0081] MCT. Transistor;

[0082] D1. First direction; D2. Second direction. Detailed implementation manners

[0083] To facilitate the understanding of the present application, the present application will be described more comprehensively with reference to the relevant accompanying drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of the present application herein are for the purpose of describing specific embodiments only and are not intended to limit the present application.

[0085] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0086] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0087] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components, and / or groups thereof are not precluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0088] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, such that variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques.

[0089] Please refer to Figure 1 , the present application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0090] Step S110: Provide a substrate, and form a stacked structure on the substrate, the stacked structure including a functional layer and a sacrificial layer, the functional layer including at least one active material layer, and the functional layer and the sacrificial layer being alternately arranged in a direction perpendicular to the substrate.

[0091] Referring to Figure 2 as shown, the material of the substrate 10 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as group III-V compounds like gallium arsenide, etc.

[0092] A stacked structure 20 is formed on a substrate 10. The stacked structure 20 includes a functional layer 22 and a sacrificial layer 21 vertically stacked on the substrate 10. The functional layer 22 includes at least one active material layer 23. Along the stacking direction of the stacked structure 20, the active material layer 23 and the sacrificial layer 21 are arranged at intervals, and / or the active material layer 23 is arranged at intervals between adjacent sacrificial layers 21.

[0093] The sacrificial layer 21 and the functional layer 22 of the stacked structure 20 can be alternately stacked in 2 to 1024 layers or more. For example, the sacrificial layer 21 and the functional layer 22 can be alternately stacked in 48 layers, 64 layers, 128 layers, 256 layers or 512 layers, etc.

[0094] In some embodiments, along the stacking direction of the stacked structure 20, the functional layer 22 includes a dielectric layer 24 and an active material layer 23 alternately arranged between adjacent sacrificial layers 21. Exemplarily, referring to Figure 3 As shown, the functional layer 22 can include a three-layer structure. Along the stacking direction of the stacked structure 20, the functional layer 22 can include a first dielectric layer 241, an active material layer 23, and a second dielectric layer 242 arranged in sequence. The active material layer 23 is arranged between the first dielectric layer 241 and the second dielectric layer 242, and the active material layer 23 is separated from the sacrificial layer 21 by the first dielectric layer 241 or the second dielectric layer 242.

[0095] Or, referring to Figure 24 As shown, the functional layer 22 can include a first active material layer 231, a dielectric layer 24, and a second active material layer 232 arranged in sequence. The dielectric layer 24 separates the first active material layer 231 and the second active material layer 232. The first active material layer 231 and the second active material layer 232 are respectively connected to the sacrificial layer 21 at the top layer of the functional layer 22 or to the sacrificial layer 21 at the bottom layer of the functional layer 22.

[0096] Or, referring to Figure 25 As shown, the functional layer 22 can include a four-layer or five-layer structure, and the dielectric layer 24 and the active material layer 23 are alternately arranged between adjacent sacrificial layers 21.

[0097] Among them, the material of the sacrificial layer 21 can include silicon nitride or silicon oxynitride; the material of the dielectric layer 24 can include silicon oxide; the material of the active material layer 23 can include a conductive metal or a doped semiconductor material. For example, the material of the active material layer 23 can include aluminum (Al) or aluminum alloy material, tungsten (W) or tungsten alloy material, titanium (Ti) or titanium alloy material, etc. Or, the material of the active material layer 23 can include a P-type conductive doped semiconductor material or an N-type conductive doped semiconductor material.

[0098] Next, referring to Figure 2 、 Figure 3, taking the functional layer 22 including a first dielectric layer 241, an active material layer 23, and a second dielectric layer 242 arranged in sequence as an example, the following implementation manners can be adopted to form the stacked structure 20 on the substrate 10:

[0099] Any one of the deposition processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or sputtering can be selected to alternately deposit dielectric materials and active materials to form the first dielectric layer 241, the active material layer 23, and the second dielectric layer 242, thereby forming the functional layer 22.

[0100] Then, any one of the above deposition processes can be selected to deposit and form the sacrificial layer 21. Repeat the steps of forming the functional layer 22 and the sacrificial layer 21 to form the stacked structure 20 on the substrate 10.

[0101] It can be understood that, in order to avoid subsequent process damage or contamination of the substrate 10, before forming the sacrificial layer 21 or the functional layer 22, a dielectric layer 24 is first deposited on the substrate 10 to prevent the substrate 10 from being exposed to the process environment and causing electrical degradation of the substrate 10.

[0102] Step S120: Pattern the stacked structure, and the active material layer forms an initial active layer.

[0103] Refer to Figure 2 , Figure 3 , on the top surface of the stacked structure 20, a first mask layer (not shown in the figure) is formed, and the stacked structure 20 is patterned according to the first mask layer, and a part of the stacked structure 20 is etched away. Refer to Figure 4 As shown, the remaining active material layer 23 after etching forms the initial active layer 25. The initial active layer 25 includes a first part 251 extending along the second direction D2 and a second part 252 extending along a first direction D1 different from the second direction D2. The first direction D1 and the second direction D2 are both parallel to the substrate 10, and the first direction D1 and the second direction D2 intersect.

[0104] For example, the included angle between the first direction D1 and the second direction D2 can be 30°, 45°, 60°, 90°, 120°, or 150°. In some embodiments, the included angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 are perpendicularly intersecting.

[0105] Then, as Figure 5 shown, refer to Figure 2 , Figure 3 , Figure 4, a support layer 60 is formed by deposition. The support layer 60 fills the removed part of the stacked structure 20, and the top surface of the support layer 60 is flush with the top surface of the stacked structure 20. The material of the support layer 60 is selected as a dielectric material having a high etching selectivity with respect to the dielectric layer 24. For example, the material of the support layer 60 may include at least one of silicon nitride or silicon oxynitride.

[0106] Step S130: Form at least one channel trench. The channel trench penetrates the stacked structure in a direction perpendicular to the substrate, and the channel trench divides the initial active layer into a first active region and a second active region.

[0107] As Figure 6 shown, referring to Figure 2 , Figure 3 , Figure 5 , a second mask layer (not shown in the figure) is formed on the top surfaces of the stacked structure 20 and the support layer 60. The second mask layer is defined with a pattern for forming the channel trench 31. The stacked structure 20 and the support layer 60 are etched according to the second mask layer until the top surface of the substrate 10 is exposed. Referring to Figure 7 shown, at least one channel trench 31 is formed. The channel trench 31 penetrates the stacked structure 20 in the stacking direction of the stacked structure 20.

[0108] In some embodiments, at least one channel trench 31 is arranged along a first direction D1, and the first direction D1 is located in a plane parallel to the substrate 10.

[0109] At least one channel trench 31 divides the initial active layer 25 into a first active region 123 and a second active region 223 that are oppositely arranged on both sides of the channel trench 31 along a second direction D2. Wherein, the width of the channel trench 31 in the first direction D1 is greater than the width of the first active region 123 in the first direction D1 and the width of the part of the second active region 223 connected to the channel trench 31 in the first direction D1. That is, along the first direction D1, both sides of the channel trench 31 extend into the support layer 60.

[0110] Step S140: A semiconductor layer and a word line are sequentially formed in the channel trench.

[0111] First, a semiconductor layer 41 is formed in the channel trench 31. As Figure 9 shown, referring to Figure 7 , any one of chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process or sputtering deposition process can be selected to deposit and form the semiconductor layer 41. The semiconductor layer 41 covers the bottom wall, side walls of the channel trench 31, as well as the top surface of the stacked structure 20 and the top surface of the support layer 60. The material of the semiconductor layer 41 may include indium gallium zinc oxide (IGZO).

[0112] In some embodiments, after forming the semiconductor layer 41 and before forming the word line 50, the following steps are further performed:

[0113] Step S140-1: Form a protective layer and a gate insulating layer. The gate insulating layer, the protective layer, and the semiconductor layer are sequentially arranged in a direction away from the word line.

[0114] As Figure 10 shown, referring to Figure 9 , after forming the semiconductor layer 41, any one of chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, or sputtering deposition process can be selected to deposit and form the protective layer 53. The protective layer 53 covers the surface of the semiconductor layer 41. As shown in Figure 11 , the protective layer 53 separates the semiconductor layer 41 from the word line 50 formed in the subsequent steps, avoiding the gate insulating layer 51 being etched and damaged in the subsequent step of etching the semiconductor layer 41 connected to the sacrificial layer 21 (which will be described in detail in the subsequent embodiments), thus affecting the structural integrity and electrical performance of the word line 50.

[0115] The material of the protective layer 53 is selected as a dielectric material that can achieve a high etching selectivity ratio with the material of the sacrificial layer 21. For example, the material of the protective layer 53 may include silicon oxide.

[0116] Then, the gate insulating layer 51 is formed. As shown in Figure 11 , Figure 12 , referring to Figure 10 , any one of chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, or sputtering deposition process can be selected to deposit a high-K dielectric constant (HighK) material to form the gate insulating layer 51. The gate insulating layer 51 covers the semiconductor layer 41.

[0117] Among them, the material of the gate insulating layer 51 may include hafnium materials such as hafnium or hafnium compounds. For example, the material of the gate insulating layer 51 may include one or more of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO).

[0118] Next, as shown in Figure 11 , Figure 12 , referring to Figure 10 , any one of the above deposition processes can be used to deposit a gate material layer in the channel trench 31, and a plurality of gates 52 spaced apart in a direction perpendicular to the substrate 10 are formed in the channel trench 31. The material of the gate 52 may include tungsten or tungsten compounds.

[0119] Etch away the gate material layer and the gate insulating layer 51 located on the top surface of the stacked structure 20 in sequence, and form a word line 50 in the channel trench 31. The word line 50 includes a plurality of gates 52 arranged at intervals along a direction perpendicular to the substrate 10.

[0120] Step S150: Etch away at least part of the sacrificial layer, etch away part of the semiconductor layer, and divide the semiconductor layer into a plurality of active channels, and the plurality of active channels are arranged at intervals along a direction perpendicular to the substrate.

[0121] Among them, referring to Figure 11 、 Figure 12 , in some embodiments, the direction perpendicular to the substrate 10 is the upward direction from the substrate 10.

[0122] In some embodiments, etching away at least part of the sacrificial layer and etching away part of the semiconductor layer include the following steps:

[0123] Step S151: Form a first through hole between adjacent word lines, and the first through hole exposes the part of the top surface.

[0124] First, as Figure 13 、 Figure 14 shown, form a third mask layer (not shown in the figure) on the top surfaces of the stacked structure 20 and the support layer 60. The third mask layer is defined with a pattern for forming the first through hole 32, and the third mask layer exposes a part of the top surface of the support layer 60 located around the word line 50.

[0125] Then, as Figure 13 、 Figure 14 shown, etch the support layer 60 based on the third mask layer to form a first through hole 32 penetrating through the support layer 60. The first through hole 32 exposes a part of the top surface of the substrate 10 or extends into the substrate 10. The first through hole 32 is disposed close to the word line 50, and the groove wall of the first through hole 32 exposes a part of the structure of each sacrificial layer 21 connected to the word line 50.

[0126] Along the first direction D1, the first through hole 32 is formed between two adjacent channel trenches 31, and the first through hole 32 and the channel trench 31 are independently disposed in the orthographic projection formed on the substrate 10.

[0127] Step S152: Etch the sacrificial layer and the semiconductor layer based on the first through hole until the semiconductor layer located between adjacent functional layers is removed.

[0128] As Figure 15 、 Figure 16 shown, referring to Figure 11 、 Figure 12 、 Figure 13 、 Figure 14, an anisotropic etching process is used to etch the support layer 60 exposed by the first through hole 32 until the first through hole 32 exposes the stacked structure 20. The sacrificial layer 21 exposed by the first through hole 32 is etched, and the sacrificial layer 21 around the channel groove 31 is etched and removed in the horizontal direction. After the semiconductor layer 41 connected to the sacrificial layer 21 is exposed, the semiconductor layer 41 is continuously etched until the semiconductor layer 41 connected to the sacrificial layer 21 is completely removed. Refer to Figure 15 , Figure 16 , the entire semiconductor layer 41 is divided into multiple independently arranged active channels 40. The multiple active channels 40 are arranged at intervals in a direction perpendicular to the substrate 10. The multiple active channels 40 and the multiple functional layers 22 are arranged in one-to-one correspondence, and each active channel 40 is connected to the corresponding functional layer 22.

[0129] In some embodiments, the etching process for etching the sacrificial layer 21 has a high etching selectivity with respect to the dielectric layer 24 and the active material layer 23, avoiding the consumption of the dielectric layer 24 or the active material layer 23 during the process of etching the sacrificial layer 21 and affecting the integrity of the structure and performance of the finally formed semiconductor structure.

[0130] Refer to Figure 16 As shown, a transistor MCT is formed at the node where the word line 50 is connected to the first active region 123 and the second active region 223. In some embodiments, the materials of the first active region 123 and the second active region 223 include metal materials. The first active region 123, the second active region 223, and the part of the word line 50 covered by the active channel 40 directly form the transistor MCT. The part of the first active region 123 close to the word line 50 forms the source or drain of the transistor MCT, the part of the second active region 223 close to the word line 50 forms the drain or source of the transistor MCT, and the part of the word line 50 covered by the active channel 40 serves as the gate 52 of the transistor MCT. The gates 52 of the multiple transistors MCT are connected to the word line 50.

[0131] In other embodiments, the materials of the first active region 123 and the second active region 223 include doped semiconductor materials. After the first active region 123 and the second active region 223 are formed, an ion implantation process is used to implant conductive ions (which can be P-type conductive ions or N-type conductive ions) into the side of the first active region 123 close to the word line 50 to form a first doped region (not labeled in the figure).

[0132] Then, an ion implantation process is used to implant conductive ions (which can be conductive ions of N-type conductive type or P-type conductive type) into the side of the second active region 223 close to the word line 50 to form a second doped region (not labeled in the figure). The first doped region serves as the source or drain of the transistor MCT, the second doped region serves as the drain or source of the transistor MCT, and the part of the word line 50 covered by the active channel 40 serves as the gate 52 of the transistor MCT. The gates 52 of multiple transistors MCT are connected to the word line 50.

[0133] In some embodiments, after cutting the semiconductor layer 41 into multiple independently arranged active channels 40, the following steps are further performed: depositing an insulating material to form an insulating layer 61, and the insulating layer 61 fills the gaps between the functional layers 22 and the first through holes 32.

[0134] The manufacturing method of the semiconductor structure of the above embodiments adjusts the stacking rule of the stacked structure, sets a sacrificial layer between adjacent functional layers, removes the sacrificial layer to expose the semiconductor layer connected to the sacrificial layer, and then removes the semiconductor layer connected to the sacrificial layer, dividing the entire semiconductor layer into independently arranged active channels, avoiding the formation of parasitic transistors (a parasitic transistor refers to a transistor with a parasitic channel) by the remaining semiconductor layer between adjacent transistors, avoiding the existence of parasitic channels between adjacent transistors, and being able to improve the response speed of the semiconductor structure and avoid response delay.

[0135] The manufacturing method of the semiconductor structure of the above embodiments increases the process window for removing the semiconductor layer by setting the sacrificial layer, reduces the difficulty of process operations and control for removing the semiconductor layer between adjacent transistors, has no complicated lithography-etching steps, reduces the requirements for equipment and process stability, greatly reduces the process cost and improves the yield rate.

[0136] At the same time, in the manufacturing method of the semiconductor structure of the above embodiments, during the manufacturing process, the active channels are covered by the surrounding active material layers and dielectric layers, which can avoid damaging the active channels during the manufacturing process and further improve the yield rate and electrical performance of the semiconductor structure.

[0137] In some embodiments, after forming at least one channel trench in step S130, the manufacturing method of the semiconductor structure further includes the following steps:

[0138] Step S1301: Remove the exposed part of the functional layer or part of the sacrificial layer exposed by the channel trench, and form a recess on the sidewall of the channel trench. The recess is recessed in a direction parallel to the substrate and away from the channel trench.

[0139] As Figure 8As shown, the groove walls of the channel groove 31 expose a part of the functional layer 22 (including a part of the dielectric layer 24 and a part of the active material layer 23), and the groove walls of the channel groove 31 also expose a part of the sacrificial layer 21.

[0140] In some embodiments, the following implementation is adopted to form the recess 311:

[0141] As Figure 8 shown, referring to Figure 7 , after the channel groove 31 is formed, the stacked structure 20 is etched based on the channel groove 31, the functional layer 22 (dielectric layer 24 or active material layer 23) exposed by the sidewalls of the channel groove 300 is etched, or the sacrificial layer 21 exposed by the sidewalls of the channel groove 300 is etched to form the recess 311.

[0142] For example, in some examples, referring to Figure 8 shown, a suitable etching process can be selected to etch the sacrificial layer 21 exposed by the channel groove 31. The etching process has a high etching selectivity with respect to the dielectric layer 24 and the active material layer 23. Part of the sacrificial layer 21 is etched away to form the recess 311 on the sidewalls of the channel groove 300, and the recess 311 is recessed into the sacrificial layer 21. That is, after this step of processing, the groove width of the channel groove 31 in the sacrificial layer 21 is greater than the groove width of the channel groove 31 in the dielectric layer 24 and the groove width of the channel groove 31 in the active material layer 23.

[0143] In other examples, which are not shown in the drawings in this example, a suitable etching process can be selected to etch the dielectric layer 24 exposed by the channel groove 31. The etching process has a high etching selectivity with respect to the sacrificial layer 21 and the active material layer 23. Part of the dielectric layer 24 is etched away to form the recess 311 on the sidewalls of the channel groove 300, and the recess 311 is recessed into the dielectric layer 24. That is, after this step of processing, the groove width of the channel groove 31 in the dielectric layer 24 is greater than the groove width of the channel groove 31 in the sacrificial layer 21 and the groove width of the channel groove 31 in the active material layer 23.

[0144] In some embodiments, when the semiconductor layer 41 is formed, the semiconductor layer 41 covers the groove walls of the channel groove 31 and the groove walls of the recess 311. Referring to Figure 12 , when the word line 50 is formed, the gate insulating layer 51 covers the semiconductor layer 41, and the word line 50 covers the gate insulating layer 51 and fills the unfilled areas of the channel groove 31 and the unfilled areas of the recess 311.

[0145] In some embodiments, referring to Figure 12, the formed word line 50 includes a main body portion 150 extending along the stacking direction of the stacked structure 20 and a partition portion 250 disposed on the circumferential surface of the main body portion 150. The partition portions 250 are spaced along the stacking direction of the stacked structure 20. The partition portions 250 are filled in the recessed portions 311. The partition portions 250 are formed between the first active regions 123 adjacent along the stacking direction of the stacked structure 20 and / or between the second active regions 223 adjacent along the stacking direction of the stacked structure 20.

[0147] In some embodiments, referring to Figure 6 as shown, at least one channel trench 31 is spaced along the first direction D1. The second active regions 223 formed by patterning the stacked structure 20 extend along the first direction D1. A connecting portion 230 is formed on a side of the second active region 223 close to the channel trench 31. The second active region 223 is connected to the active channel 40 through the connecting portion 230. The first direction D1 is parallel to the substrate 10.

[0148] Exemplarily, in step S120, a plurality of channel trenches 31 arranged at intervals along the first direction D1 are formed in the stacked structure 20, so that the formed plurality of word lines 50 are arranged at intervals along the first direction D1. During the process of patterning the stacked structure 20, it is defined that the second active regions 223 extend along the first direction D1, and a plurality of connecting portions 230 are formed on a side of the second active regions 223 close to the word lines 50. Along the first direction D1, the plurality of connecting portions 230 and the plurality of word lines 50 are arranged correspondingly. Each connecting portion 230 is connected to the active channel 40 and is connected to the word line 50 through the active channel 40. It can be understood that a transistor MCT is formed at the node where the word line 50 is connected to the first active region 123 and the second active region 223. Part of the structure of the first active region 123 or part of the structure of the second active region 223, the connecting portion 230, and the part of the word line 50 covered by the active channel 40 serve as the gate 52, jointly constituting the transistor MCT.

[0149] In some embodiments, along the first direction D1, the size of the active channel 40 is greater than at least one of the sizes of the first active region 123 and the connecting portion 230.

[0150] For example, the size of the active channel 40 is greater than the size of the first active region 123; or, the size of the active channel 40 is greater than the size of the connecting portion 230; or, the size of the active channel 40 can be greater than the sizes of both the first active region 123 and the connecting portion 230 at the same time.

[0151] Referring to Figure 6As shown, the stacked structure 20 is patterned according to the fact that the size of the active channel 40 in the first direction D1 is greater than the size of the first active region 123 or the connecting portion 230. Exemplarily, the size of the active channel 40 in the first direction D1 is the first width d1. By controlling the patterning process, d1 is made much larger than the size d2 of the formed first active region 123 and the connecting portion 230 in the first direction D1, thereby increasing the channel length of the transistor MCT. When further reducing the AA size, the short-channel effect of the transistor MCT can be avoided. At the same time, the process of preferentially forming the first active region 123 and the second active region 223 can avoid damaging the active channel 40 by this process, ensuring the integrity of the structure and performance of the active channel 40.

[0152] According to an exemplary embodiment, some embodiments include all the steps of the above embodiments. Some embodiments are different from the above embodiments in that, after forming the semiconductor layer and before forming the word line, the following steps are further included:

[0153] According to some embodiments, including all the steps of the above embodiments, after patterning the stacked structure, the following steps are further included:

[0154] Step S160: Remove part of the dielectric layer to expose part of the sidewalls of the first active region covered by the dielectric layer.

[0155] In some embodiments, the following implementation manners can be adopted to remove part of the dielectric layer to expose part of the sidewalls of the first active region covered by the dielectric layer:

[0156] Step S161: Define a capacitor region, etch and remove the support layer located in the capacitor region to form a first trench, and the first trench exposes the substrate.

[0157] Refer to Figure 18 、 Figure 19 As shown, a fourth mask layer (not shown in the figure) is formed on the top surface of the support layer 60. The capacitor region 01 is defined according to the layout and structure of the word line 50 and the layout and structure of the first active region 123 or the second active region 223 (refer to Figure 13 ), and the pattern of the capacitor region 01 (refer to Figure 18 ) is defined on the fourth mask layer. Refer to Figure 18 , when defining the capacitor region 01, along the second direction D2, the capacitor region 01 is defined on one side of the first active region 123.

[0158] Then, according to the fourth mask layer, the support layer 60 located in the capacitor region 01 (refer to Figure 18 ) is etched and removed, and in the capacitor region 01 (refer to Figure 18)Form a first trench 33, the first trench 33 exposes a partial structure of one end of the first active region 123 away from the word line 50, and the first trench 33 also exposes a partial structure of the dielectric layer 24 connected to the first active region 123.

[0159] Step S162: Etch the stacked structure based on the first trench to remove a part of the dielectric layer.

[0160] As Figure 20 shown, refer to Figure 19 , use an anisotropic etching process to etch the dielectric layer 24 exposed by the first trench 33, expose all sidewalls of one end of the first active region 123 away from the word line 20, and increase the contact area between the dielectric layer 72 (refer to Figure 21 or Figure 29 ) formed subsequently and the first active region 123, which is beneficial to improving the storage capacity of the formed capacitor 70 (refer to Figure 21 or Figure 29 ).

[0161] Step S170: Form a dielectric layer, and the dielectric layer covers the exposed sidewalls of the first active region.

[0162] Refer to Figure 21 shown, deposit and form a dielectric layer 72 through an atomic layer deposition process, and the dielectric layer 72 uniformly covers the exposed sidewalls of the first active region 123.

[0163] The material of the dielectric layer 72 may include at least one of strontium titanate (SrTiO 3 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), or hafnium oxide (HfO 2 ).

[0164] Step S180: Form a second electrode, the second electrode covers the dielectric layer, use the partial structure of the first active region covered by the dielectric layer as the first electrode, and the second electrode, the dielectric layer, and the first electrode form a capacitor.

[0165] Refer to Figure 22 , Figure 29 shown, use the partial structure of the first active region 123 covered by the dielectric layer 72 as the first electrode 71, and each first electrode 71, the dielectric layer 72 on its surface, and the second electrode 73 form a capacitor 70 in the capacitance region 01. The capacitor 70 is arranged on one side of the word line 50, and the capacitor 70 and the word line 50 are separated by the dielectric layer 24 reserved by etching to avoid short - circuiting between the capacitor 70 and the word line 50.

[0166] In some embodiments, the second electrode 73 can be formed by the following implementation method: Refer to Figure 21, first, an atomic layer deposition process can be employed to deposit and form a first sub-electrode 731 of the second electrode, and the first sub-electrode 731 of the second electrode covers the surface of the dielectric layer 72.

[0167] The material of the first sub-electrode 731 of the second electrode may include a high melting point metal, such as at least one of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and / or molybdenum (Mo); or, the material of the first sub-electrode 731 of the second electrode may further include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0168] Then, referring to Figure 22 , Figure 23 , Figure 29 , a second sub-electrode 732 of the second electrode can be re-formed by any one of chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process or sputtering. The second sub-electrode 732 of the second electrode covers the surface of the first sub-electrode 731 of the second electrode and fills the unfilled regions between the first sub-electrodes 731 of the second electrode and the unfilled regions of the first trench 33 (refer to Figure 19 ).

[0169] The material of the second sub-electrode 732 of the second electrode may include a semiconductor material doped with conductive ions or a conductive metal. For example, the material of the second sub-electrode 732 of the second electrode may include single crystal silicon or polycrystalline silicon, and the material of the second sub-electrode 732 of the second electrode may also include at least one of metal tungsten, cobalt, titanium, and / or nickel.

[0170] It can be understood that when the semiconductor structure is in a working state, the first sub-electrode 731 of the second electrode and the second sub-electrode 732 of the second electrode jointly serve as the second electrode 73 of the capacitor 70.

[0171] In some embodiments, after the capacitor 70 is formed, an insulating material is deposited to fill the gap between the capacitors 70 to avoid short-circuiting of adjacent capacitors 70 and also reduce the coupling capacitance of the capacitors 70. The insulating material and the support layer 60 jointly support the semiconductor structure.

[0172] According to an exemplary embodiment, the difference between some embodiments and the above embodiments is that in step S110, as Figure 24 shown, along the stacking direction of the stacked structure 20, the functional layer 22 includes a first active material layer 231, a dielectric layer 24, and a second active material layer 232 arranged in sequence.

[0173] As Figure 26 , Figure 27 shown, according to Figure 24A semiconductor structure formed by the stacked structure 20 shown, on one side of each active channel 40, it is connected to two first active regions 123, on the other side of each active channel 40, it is connected to two second active regions 223, in the region of the same active channel 40, the regions where the two first active regions 123, the two second active regions 223 and the word line 50 intersect form two transistors MCT.

[0174] According to Figure 24 A semiconductor structure formed by the stacked structure 20 shown, each active channel 40 is connected to two first active regions 123 and two second active regions 223. One end of the two first active regions 123 far from the word line 50 serves as the first electrode 71 of the capacitor 70. The formed capacitor 70 is a cup-shaped capacitor, which increases the proportion of the first electrode 71 in the capacitor 70, increases the storage area of the dielectric layer 72 and the first electrode 71, and further improves the storage capacity of the capacitor 70. The 2T1C structure formed by the capacitor 70 and the two transistors MCT further improves the integration density of the semiconductor structure.

[0175] According to an exemplary embodiment, the difference between some embodiments and the above embodiments is that in step S110, as shown in 25, along the stacking direction of the stacked structure 20, the functional layer 22 includes a first dielectric layer 241, a first active material layer 231, a second dielectric layer 242, a second active material layer 232, and a third dielectric layer 243 arranged in sequence.

[0176] According to Figure 25 The semiconductor structure formed by the stacked structure 20 shown and the above embodiments according to Figure 24 The semiconductor structure formed by the stacked structure 20 shown is the same. As Figure 26 、 Figure 27 shown, on one side of each active channel 40, it is connected to two first active regions 123, on the other side of each active channel 40, it is connected to two second active regions 223. The capacitor 70 is a cup-shaped capacitor, and the capacitor 70 and the two transistors MCT form a 2T1C structure.

[0177] Referring to Figure 25 the stacked structure 20 shown, the first active material layer 231 in the functional layer 22 is separated from the sacrificial layer 21 by the first dielectric layer 241, and the second active material layer 232 is separated from the sacrificial layer 21 by the third dielectric layer 243, avoiding direct contact between the first active material layer 231, the second active material layer 232 and the sacrificial layer 21, and avoiding damage to the first active material layer 231 and the second active material layer 232 during the manufacturing process by the etching process, ensuring the integrity of the structure and performance of the formed semiconductor structure.

[0178] Some embodiments provide a semiconductor structure, such as Figure 28 、 Figure 29, Figure 30 As shown in reference to Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 26 , some semiconductor structures of some embodiments include a substrate 10, a word line 50, a multi-layer memory cell array 100 disposed in a direction perpendicular to the substrate 10, at least one first active region 123, and at least one second active region 223. The word line 50 is disposed on the substrate 10 and extends in a direction perpendicular to the substrate 10. Each layer of the memory cell array 100 includes a plurality of active channels 40 arranged in a first direction D1. The plurality of active channels 40 are spaced apart along the extending direction of the word line 50. The active channels 40 cover a partial circumferential surface of the word line 50. At least one first active region 123 is disposed on one side of the active channels 40 in a second direction D2 and is connected to the active channels 40. The first direction D1 and the second direction D2 are both parallel to the substrate 10, and the first direction D1 and the second direction D2 intersect. At least one second active region 223 is disposed on the other side of the active channels 40 in the second direction D2 relative to at least one first active region 123 and is connected to the active channels 40. Along the first direction D1, the size of the active channels 40 is greater than at least one of the size of the portion of the first active region 123 connected to the active channels 40 and the size of the portion of the second active region 223 connected to the active channels 40.

[0179] Wherein, the included angle between the first direction D1 and the second direction D2 can be 30°, 45°, 60°, 90°, 120° or 150°. In some embodiments, the included angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 are perpendicularly intersecting.

[0180] Referring to Figure 28 , Figure 29 , Figure 30 As shown, a transistor MCT is formed at the node where the word line 50 is connected to the first active region 123 and the second active region 223. The partial structure of the first active region 123 close to the word line 50 forms the source or drain of the transistor MCT. The partial structure of the second active region 223 close to the word line 50 forms the drain or source of the transistor MCT. The partial word line 50 covered by the active channels 40 serves as the gate 52 of the transistor MCT. The gates 52 of the plurality of transistors MCT are connected to the word line 50.

[0181] For the semiconductor structure provided by some embodiments, the plurality of active channels 40 covering the same word line 50 are independently disposed, and there is no conductive film layer with process residues between adjacent active channels 40. Thus, the parasitic capacitance between adjacent transistors of the semiconductor structure can be avoided or reduced, the response speed of the semiconductor structure can be improved, response delay can be avoided, and the yield and electrical performance of the semiconductor structure can be improved.

[0182] In some embodiments, such as Figure 28 , Figure 29 , Figure 30 shown, referring to Figure 22 , Figure 23 , Figure 26 , in a direction perpendicular to the substrate 10, a plurality of first active regions 123 are arranged at intervals, and the plurality of first active regions 123 are connected to the same active channel 40. Two or more adjacent first active regions 123 are connected to the same active channel 40.

[0183] For example, one side of each active channel 40 is connected to two first active regions 123, the other side of each active channel 40 is connected to two second active regions 223, and in the region where each active channel 40 is located, the first active region 123, the second active region 223, and a part of the word line 50 covered by the active channel 40 together form a transistor MCT.

[0184] That is, the region of each active channel 40 forms two transistors MCT, improving the integration degree of the semiconductor structure. It can be understood that the number of the first active regions 123 and the second active regions 223 connected to the active channel 40 can be adjusted adaptively. For example, the active channel 40 can also be connected to three or more first active regions 123 and three or more second active regions 223.

[0185] In some embodiments, referring to Figure 22 , Figure 26 , Figure 27 , Figure 29 , Figure 30 , in a direction perpendicular to the substrate 10, a plurality of first active regions 123 and a plurality of active channels 40 are connected in one-to-one correspondence. Two adjacent first active regions 123 are respectively connected to two adjacent active channels 40 in one-to-one correspondence.

[0186] In some embodiments, referring to Figure 12 shown, the word line 50 includes a main body portion 150 extending in a direction perpendicular to the substrate 10 and a partition portion 250 provided on the peripheral surface of the main body portion 150. The partition portions 250 are arranged at intervals in a direction perpendicular to the substrate 10, and the partition portions 250 are provided between the first active regions 123 adjacent in a direction perpendicular to the substrate 10 and / or between the second active regions 223 adjacent in a direction perpendicular to the substrate 10.

[0187] In some examples, along a direction perpendicular to the substrate 10, the partition portion 250 of the word line 50 is disposed between adjacent first active regions 123 or between adjacent second active regions 223. The partition portion 250 may be in contact connection with a part of the bottom surface or a part of the top surface of the first active region 123, and the partition portion 250 may also be in contact connection with a part of the bottom surface or a part of the top surface of the second active region 223.

[0188] In some examples, along a direction perpendicular to the substrate 10, the partition portion 250 of the word line 50 is disposed between adjacent first active regions 123 or between adjacent second active regions 223. The partition portion 250 is spaced apart from the first active region 123 above it and the first active region 123 below it, and the partition portion 250 is spaced apart from the second active region 223 above it and the second active region 223 below it.

[0189] In some other embodiments, the partition portions 250 are spaced apart along a direction perpendicular to the substrate 10, and the partition portions 250 are in contact connection with the first active region 123 and the second active region 223.

[0190] The partition portion 250 of the word line 50 is in contact connection with the first active region 123 and the second active region 223 on both sides of the word line 50, that is, the width of the word line 50 located between the first active region 123 and the second active region 223 is greater than the width of the main body portion 150.

[0191] In some embodiments, referring to Figure 21 、 Figure 22 、 Figure 23 、 Figure 26 、 Figure 28 、 Figure 29 、 Figure 30 as shown, each layer of the memory cell array 100 further includes a capacitor 70. The capacitor 70 includes a first electrode 71, a dielectric layer 72, and a second electrode 73. The first electrode 71 includes a partial structure of the first active region 123. The dielectric layer 72 covers the surface of the first electrode 71, and the second electrode 73 covers the surface of the dielectric layer 72.

[0192] In some embodiments, the second electrode 73 includes a second electrode first sub - electrode 731 and a second electrode second sub - electrode 732. The second electrode first sub - electrode 731 covers the surface of the dielectric layer 72, and the second electrode first sub - electrode 731 encloses a closed figure. The second electrode second sub - electrode 732 covers the second electrode first sub - electrode 731 and fills the closed figure.

[0193] When the semiconductor structure is in a working state, the second electrode first sub - electrode 731 and the second electrode second sub - electrode 732 jointly serve as the second electrode 73 of the capacitor 70.

[0194] In some embodiments, referring to Figure 18 , the second active region 223 includes a body portion 130 and a connecting portion 230. The body portion 130 extends along the first direction D1, and the connecting portion 230 connects the body portion 130 and the active channel 40.

[0195] In some embodiments, referring to Figure 18 , a plurality of word lines 50 are arranged at intervals along the first direction D1. A plurality of connecting portions 230 are provided on a side of the second active region 223 close to the active channel 40, and the plurality of connecting portions 230 are arranged at intervals along the first direction D1.

[0196] The plurality of connecting portions 230 and the plurality of active channels 40 are arranged in one-to-one correspondence, and the second active region 223 is connected to the corresponding active channel 40 through the connecting portion 230.

[0197] In some embodiments, referring to Figure 18 , along the first direction D1, the size of the active channel 40 is larger than the size of the connecting portion 230.

[0198] In some embodiments, referring to Figure 29 , Figure 22 or Figure 26 as shown. The semiconductor structure further includes a protective layer 53 and a gate insulating layer 51. The gate insulating layer 51, the protective layer 53, and the active channel 40 are sequentially arranged in a direction away from the word line 50.

[0199] The protective layer 53 covers the bottom wall and the side wall of the word line 50. The gate insulating layer 51 covers the protective layer 53, and the active channel 40 is separated by the gate insulating layer 51, the protective layer 53, and the word line 50.

[0200] For the semiconductor structure of the present application, by changing the in-plane dimensional relationship between the source region (S) / drain region (D) and the channel, the channel length can be increased, the short-channel effect can be reduced, and at the same time, the damage to the channel during the process can be avoided.

[0201] Some embodiments provide a memory, which includes the semiconductor structure in the above embodiments. The memory in some embodiments may be a Dynamic Random Access Memory (DRAM). However, the memory in some embodiments may also be a Static Random-Access Memory (SRAM), a flash EPROM, a Ferroelectric Random-Access Memory (FRAM), a Magnetic Random-Access Memory (MRAM), a Phase change Random-Access Memory (PRAM), etc.

[0202] Some embodiments provide an electronic device, which includes the memory or semiconductor structure in the above embodiments. The electronic device may be a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0203] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0204] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate; a word line disposed on the substrate and extending in a direction perpendicular to the substrate; a multi-level memory cell array disposed in a direction perpendicular to the substrate, each layer of the memory cell array including a plurality of active channels arranged in a first direction; the plurality of active channels are spaced apart along the extension direction of the word line, and the active channels cover a partial circumference of the word line; at least one first active region disposed on one side of the active channel in a second direction and connected to the active channel, the first direction and the second direction both being parallel to the substrate and the first direction and the second direction intersecting; at least one second active region disposed on the other side of the active channel in the second direction relative to the at least one first active region and connected to the active channel; along the first direction, the size of the active channel is greater than at least one of the size of the portion of the first active region connected to the active channel and the size of the portion of the second active region connected to the active channel.

2. The semiconductor structure according to claim 1, characterized in that, along the direction perpendicular to the substrate, the plurality of first active regions are spaced apart, and the plurality of first active regions are connected to the same active channel.

3. The semiconductor structure according to claim 1, characterized in that, along the direction perpendicular to the substrate, the plurality of first active regions are connected to the plurality of active channels one by one.

4. The semiconductor structure according to claim 1, characterized in that, the word line includes a main body portion extending in a direction perpendicular to the substrate and a partition portion disposed on the circumferential surface of the main body portion, the partition portions are spaced apart along the direction perpendicular to the substrate, and the partition portions are disposed between the first active regions adjacent in the direction perpendicular to the substrate and / or between the second active regions adjacent in the direction perpendicular to the substrate.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, each layer of the memory cell array further includes: a capacitor, the capacitor including a first electrode, a dielectric layer, and a second electrode, the first electrode including a partial structure of the first active region, the dielectric layer covering the surface of the first electrode, and the second electrode covering the surface of the dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, the second active region includes a main body portion and a connecting portion, the main body portion extends in the first direction, and the connecting portion connects the main body portion and the active channel.

7. The semiconductor structure according to claim 6, characterized in that, the plurality of word lines are arranged at intervals along the first direction, a plurality of connecting portions are provided on a side of the second active region close to the active channel, and the plurality of connecting portions are arranged at intervals along the first direction.

8. The semiconductor structure according to claim 7, characterized in that, along the first direction, the size of the active channel is greater than the size of the connecting portion.

9. The semiconductor structure according to claim 1, characterized in that, further comprising: A protective layer and a gate insulating layer, wherein the gate insulating layer, the protective layer, and the active channel are sequentially arranged in a direction away from the word line.

10. An electronic device, characterized in that, it includes the semiconductor structure according to any one of claims 1-9.

11. A method for manufacturing a semiconductor structure, characterized in that, it includes the following steps: Providing a substrate, forming a stacked structure on the substrate, the stacked structure including a functional layer and a sacrificial layer, the functional layer including at least one active material layer, and the functional layer and the sacrificial layer being alternately arranged in a direction perpendicular to the substrate; Patterning the stacked structure, and the active material layer forms an initial active layer; Forming at least one channel trench, the channel trench penetrating the stacked structure in a direction perpendicular to the substrate, and the channel trench dividing the initial active layer into a first active region and a second active region; Sequentially forming a semiconductor layer and a word line in the channel trench; Etching away at least part of the sacrificial layer and etching away part of the semiconductor layer to divide the semiconductor layer into a plurality of active channels, and the plurality of active channels are arranged at intervals in a direction perpendicular to the substrate.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, after forming at least one channel trench, the method for manufacturing the semiconductor structure further includes the following steps: Removing part of the functional layer or part of the sacrificial layer exposed by the channel trench, and forming a recess on the sidewall of the channel trench, the recess being recessed in a direction parallel to the substrate and away from the channel trench; The word line includes a main body portion extending in the stacking direction of the stacked structure and a partition portion provided on the peripheral surface of the main body portion, the partition portions being arranged at intervals in the stacking direction of the stacked structure, the partition portions being filled in the recess, and the partition portions being formed between the first active regions adjacent in the stacking direction of the stacked structure and / or between the second active regions adjacent in the stacking direction of the stacked structure.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, along the stacking direction of the stacked structure, the functional layer includes the active material layer and the dielectric layer alternately arranged.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, the method for manufacturing the semiconductor structure further includes the following steps: Removing part of the dielectric layer to expose part of the sidewall of the first active region covered by the dielectric layer; Forming a dielectric layer, the dielectric layer covering the exposed sidewall of the first active region; Forming a second electrode, the second electrode covering the dielectric layer, using the partial structure of the first active region covered by the dielectric layer as a first electrode, and the second electrode, the dielectric layer, and the first electrode form a capacitor.

15. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The second active region extends along a first direction, a connecting portion is formed on a side of the second active region close to the channel trench, the second active region is connected to the active channel through the connecting portion, and the first direction is parallel to the substrate.

16. The manufacturing method of the semiconductor structure according to claim 15, wherein, along the first direction, the size of the active channel is greater than at least one of the size of the first active region and the size of the connecting portion.

17. The manufacturing method of the semiconductor structure according to claim 11, wherein, etching to remove at least part of the sacrificial layer and etching to remove part of the semiconductor layer includes: forming a first through hole between adjacent word lines, the first through hole exposing a partial top surface of the substrate; etching the sacrificial layer and the semiconductor layer based on the first through hole until the semiconductor layer located between the adjacent functional layers is removed.

18. The manufacturing method of the semiconductor structure according to claim 17, wherein, the manufacturing method further includes the following steps: forming a protective layer and a gate insulating layer, the gate insulating layer, the protective layer and the semiconductor layer are sequentially arranged in a direction away from the word line.

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