Display device

Abstract

The display device includes: an inorganic insulating layer having a groove surrounding a pixel region; a first thin film transistor in a first pixel region of the substrate; a second thin film transistor in a second pixel region of the substrate; a first electrode layer overlapping a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor; an organic material layer disposed in the groove; a data line extending over the organic material layer in a second direction; and a first connection line extending across the organic material layer in the first direction, disposed between the first electrode layer and the data line, and overlapping the first electrode layer.

Description

[0001] This application is a divisional application of the patent application with application number 202011446984.8 and title "Display Device" filed on December 9, 2020.

[0002] Cross-reference to related applications

[0003] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0176140, filed on December 27, 2019, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Technical field

[0004] One or more embodiments relate to a foldable display device that can be folded or bent. Background art

[0005] Display devices have been used for various purposes. As the thickness and weight of display devices have decreased, the range of utilization of display devices has increased. In addition to flat display devices, research has been conducted on flexible display devices (such as foldable display devices, rollable display devices, etc.).

[0006] It is to be understood that this background art section is partly intended to provide a useful background for understanding the technology. However, this background art section may also include ideas, concepts, or understandings that were not known or understood by those skilled in the relevant art before the effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] One or more embodiments may include a high-resolution display device that can be flexible while being robust against external shocks. However, the above technical features are exemplary, and the scope of the present disclosure is not limited thereto.

[0008] Additional aspects will be partly set forth in the following description, and partly will be apparent from the description, or may be learned by practicing the embodiments presented in the present disclosure.

[0009] According to an embodiment, a display device may include: a substrate including a display area including display elements, the display area including a pixel area, each of the pixel areas may include a first pixel area and a second pixel area that may be adjacent to each other in a first direction; an inorganic insulating layer including a groove surrounding the pixel area; and a first thin film transistor including a first semiconductor layer on the substrate in the first pixel area and a first gate electrode on the first semiconductor layer. The display device may include a second thin film transistor including a second semiconductor layer on the substrate in the second pixel area and a second gate electrode on the second semiconductor layer. The display device may include: a first electrode layer disposed on the first gate electrode and overlapping with the first gate electrode and the second gate electrode; an organic material layer disposed in the groove; a data line extending across the organic material layer in a second direction; and a first connection line extending across the organic material layer in the first direction, disposed between the first electrode layer and the data line, and overlapping with the first electrode layer.

[0010] The first semiconductor layer and the second semiconductor layer may be symmetric with respect to a boundary line between the first pixel area and the second pixel area.

[0011] The inorganic insulating layer may include an inorganic pattern corresponding to the pixel area, and the organic material layer may be disposed between the inorganic patterns and may include holes corresponding to the inorganic patterns.

[0012] The data line may overlap at least a part of the first connection line.

[0013] The display device may further include a power line extending across the organic material layer in a direction substantially parallel to the data line. The power line and the data line may be disposed on the same layer. The first connection line may be electrically connected to the first electrode layer, and the power line may be electrically connected to the first connection line.

[0014] The display device may further include a node electrode disposed between the first electrode layer and the first connection line. The node electrode may include one end electrically connected to the first gate electrode and the other end electrically connected to the first semiconductor layer.

[0015] The first connection line may overlap one end of the node electrode, and the one end of the node electrode overlapping with the first connection line may overlap with the first electrode layer.

[0016] The display device may further include a second connection line extending across the organic material layer in a direction substantially parallel to the first connection line, wherein the second connection line and the first connection line may be disposed on the same layer, and in a plan view, at least a part of the second connection line may be disposed between the data line and the other end of the node electrode.

[0017] The voltage applied to the first connection line may be different from the voltage applied to the second connection line.

[0018] Each of the display elements may include a pixel electrode, a counter electrode facing the pixel electrode, and an emission layer disposed between the pixel electrode and the counter electrode, wherein at least two organic insulating layers may be disposed between the data line and the pixel electrode.

[0019] The pixel electrode may overlap with the organic material layer.

[0020] The slots in the first row and the slots in the second row adjacent to the first row may be offset from each other by up to a first pixel region.

[0021] According to another embodiment, a display device may include: a substrate including a first pixel region and a second pixel region adjacent to the first pixel region in a first direction; a first driving thin film transistor in the first pixel region of the substrate; a second driving thin film transistor in the second pixel region of the substrate; a first electrode layer overlapping with a first gate electrode of the first driving thin film transistor and a second gate electrode of the second driving thin film transistor, the first electrode layer being disposed on the first gate electrode and the second gate electrode; a data line extending in a second direction in the first pixel region; a first connection line extending in the first direction, disposed between the first electrode layer and the data line, and overlapping with the first electrode layer; and an inorganic insulating layer disposed between the substrate and the first connection line and including slots surrounding the first pixel region and the second pixel region, wherein an organic material may be filled in the slots.

[0022] The display device may further include a third driving thin film transistor in a third pixel region adjacent to the first pixel region in the first direction, and a second electrode layer disposed on and overlapping with a third gate electrode of the third driving thin film transistor, wherein a slot may be disposed between the first driving thin film transistor and the third driving thin film transistor, and the first connection line may electrically connect to the first electrode layer and the second electrode layer across the slot.

[0023] The display device may further include a first switching thin film transistor in the first pixel region, and a node electrode disposed between the first electrode layer and the first connection line. The node electrode may include one end electrically connected to the first gate electrode of the first driving thin film transistor, and the other end connected to the semiconductor layer of the first switching thin film transistor.

[0024] The first connection line may overlap with one end of the node electrode, and the one end of the node electrode overlapping with the first connection line may overlap with the first electrode layer.

[0025] The display device may further include a second connection line extending substantially parallel to the first connection line, wherein the first connection line and the second connection line may be disposed on the same layer, and in a plan view, at least a portion of the second connection line may be disposed between the data line and the other end of the node electrode.

[0026] The display device may further include: a second switching thin film transistor in the first pixel region, the second switching thin film transistor including one end of a semiconductor layer electrically connected to the first switching thin film transistor and the other end electrically connected to the second connection line; and a conductive layer electrically connected to the semiconductor layer of the second switching thin film transistor and overlapping the semiconductor layer between the two channel regions of the second switching thin film transistor, wherein the conductive layer and the node electrode may be disposed on the same layer.

[0027] The display device may further include: a third switching thin film transistor in the first pixel region, the third switching thin film transistor being electrically connected to the first driving thin film transistor and the organic light emitting diode; a fourth switching thin film transistor in a fourth pixel region adjacent to the first pixel region in a second direction; and a third connection line extending in the second direction, wherein a groove may be provided between the third switching thin film transistor and the fourth switching thin film transistor, and the third connection line may cross the groove and be electrically connected to the semiconductor layer of the third switching thin film transistor and the semiconductor layer of the fourth switching thin film transistor.

[0028] The display device may further include a display element in the first pixel region, the display element including a pixel electrode and a counter electrode facing the pixel electrode, wherein at least two organic insulating layers may be provided between the data line and the pixel electrode.

[0029] The pixel electrode may overlap the groove. Description of the Drawings

[0030] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1A and Figure 1B is a schematic perspective view of a display device in an unfolded state according to an embodiment;

[0032] Figure 2A and Figure 2B is a schematic cross-sectional view of a display device in a folded state according to an embodiment;

[0033] Figure 3A and Figure 3B is a schematic cross-sectional view of a display device according to an embodiment;

[0034] Figure 4is a schematic equivalent circuit diagram of a pixel in a display panel according to an embodiment;

[0035] Figure 5 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to an embodiment;

[0036] Figures 6A to 6I is showing according to the layer Figure 5 a schematic plan view of the elements (such as thin film transistors, capacitors, and pixel electrodes) shown in;

[0037] Figures 7 to 9 is a schematic cross-sectional view of a pixel taken along the Figure 5 lines I-I', II-II', and III-III';

[0038] Figure 10 is a schematic plan view showing the relationship between a pixel region and connection lines according to an embodiment;

[0039] Figure 11 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to another embodiment;

[0040] Figure 12A is Figure 11 a partially enlarged schematic diagram of the left capacitor of; Figure 12B is along Figure 12A a schematic cross-sectional view of the left capacitor taken along the line IV-IV';

[0041] Figure 13 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to another embodiment;

[0042] Figures 14A to 14H is showing according to the layer Figure 13 a schematic plan view of the elements (such as thin film transistors, capacitors, and pixel electrodes) shown in;

[0043] Figure 15 is along Figure 13 a schematic cross-sectional view of a pixel taken along the lines V-V', VI-VI', and VII-VII';

[0044] Figure 16 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to another embodiment;

[0045] Figures 17A to 17F is showing according to the layer Figure 16 a schematic plan view of the elements (such as thin film transistors, capacitors, and pixel electrodes) shown in;

[0046] Figures 18 to 20 is a schematic cross-sectional view of pixels taken along lines VIII-VIII', IX-IX', and X-X' of Figure 16 ;

[0047] Figure 21 is a schematic cross-sectional view of a display device according to an embodiment;

[0048] Figure 22 is a schematic diagram showing the relationship between the black matrix of Figure 21 and the emission region; and

[0049] Figure 23 is a schematic diagram showing the relationship between the color filter of Figure 21 and the emission region. DETAILED DESCRIPTION

[0050] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only by referring to the figures to explain the described aspects.

[0051] Although terms such as "first," "second," etc. may be used to describe various elements, such elements are not limited to the above terms. The above terms are only used to distinguish one element from another.

[0052] Expressions used in the singular form encompass the plural form unless they have a clearly different meaning in the context.

[0053] It is to be understood that terms such as "comprising," "having," and "including" are intended to indicate the presence of features, numbers, steps, actions, elements, components, or combinations thereof disclosed herein, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, elements, components, or combinations thereof may exist or may be added.

[0054] It will be understood that when a layer, region, or element is referred to as being "formed on" another layer, region, or element, it may be directly or indirectly formed on the other layer, region, or element. For example, intermediate layers, regions, or elements may be present.

[0055] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the drawings may be arbitrarily illustrated for ease of explanation, the following embodiments are not limited thereto.

[0056] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or". Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or a variation thereof. The phrase "at least one of A and B" means A, B, or A and B.

[0057] The line "extends in a first direction or a second direction" can mean extending in a zigzag or in a curve in the first direction or the second direction, as well as extending straight in the first direction or the second direction.

[0058] The phrase "in a plan view" can mean observing the target part from the top, and the phrase "in a cross-sectional view" can mean observing the cross-section of the target part that can be vertically cut from a lateral direction. As will be understood by those of ordinary skill in the art, as used herein, the first element "overlapping" the second element can mean that the first element can be located on, above, below, facing, or covering the second element.

[0059] "About" as used herein includes the recited value and means within an acceptable deviation range of the specific value determined by those of ordinary skill in the art in view of the measurement being discussed and the error associated with a particular quantity of the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the recited value.

[0060] In cases where an embodiment can be implemented differently, the specific process order can be carried out differently from the described order. For example, two consecutively described processes can be carried out substantially simultaneously, or in an order opposite to the described order.

[0061] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in a common dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and will not be interpreted in an ideal or overly formal sense unless expressly defined in the specification.

[0062] Figure 1A and Figure 1B is a schematic perspective view of an unfolded display device according to an embodiment. Figure 2A and Figure 2B is a schematic cross-sectional view of a folded display device according to an embodiment. Figure 3Aand Figure 3B is a cross-sectional view of a display device according to an embodiment.

[0063] The display device according to an embodiment may be foldable or bendable. The display device may be provided in various shapes. For example, it may have a rectangular plate shape having two pairs of sides that are substantially parallel to each other. In the case where the display device is provided in a rectangular plate shape, one pair of sides may be longer than the other pair. In this embodiment, for ease of description, the display device has a rectangular shape having a pair of long sides and a pair of short sides. The direction in which the short sides extend is denoted as a first direction D1, the direction in which the long sides extend is denoted as a second direction D2, and the direction perpendicular to the extending directions of the long sides and the short sides is denoted as a third direction D3.

[0064] The display device according to an embodiment is not limited to the above examples and may have various shapes. For example, the display device may be provided in various shapes (e.g., a closed polygon shape including straight edges, a circular shape or an elliptical shape including curved edges, a semi-circular shape or a semi-elliptical shape including straight edges and curved edges, etc.). In an embodiment, in the case where the display device has straight edges, at least some of the corners in each shape may have curves. For example, in the case where the display device has a rectangular shape, the points where adjacent straight lines meet each other may be replaced with curves having curvature. For example, the vertex portion of the rectangular shape may include curved edges that connect to the opposite ends of two adjacent straight edges and have curvature. Here, the curvature may vary according to the position of the vertex. For example, the curvature may change according to the starting position of the curve and the length of the curve.

[0065] Referring to Figure 1A 、 Figure 1B 、 Figure 2A and Figure 2B , the display device may include a display panel 10. The display panel 10 may include a display area DA and a peripheral area PA on an outer portion of the display area DA. The display area DA may be an area where pixels PX may be arranged to display an image. The peripheral area PA surrounds the display area DA and may be a non-display area where pixels may not be arranged.

[0066] Various electronic devices (such as a printed circuit board, etc.) may be electrically attached to the peripheral area PA, and voltage lines for supplying power to drive display elements, etc. may be in the peripheral area PA. For example, a scan driver for supplying a scan signal to each of the pixels PX, a data driver for supplying a data signal to each pixel PX, supply lines (clock signal lines, carry signal lines, drive voltage lines, etc.) for supplying signals input to the scan driver and the data driver, a main power line, etc. may be in the peripheral area PA.

[0067] The display panel 10 can be at least partially flexible and can be folded at the flexible part. For example, the display panel 10 can include a foldable region FA and non-foldable regions NFA1 and NFA2. The foldable region FA can be flexible and foldable. The non-foldable regions NFA1 and NFA2 can be provided on at least one side of the foldable region FA and can be non-foldable. In the present disclosure, for ease of description, a region that is not foldable can be referred to as a non-foldable region, but one or more embodiments are not limited thereto, and the expression "non-foldable" can represent a case where the region has less flexibility than the foldable region FA, a case where the region can be flexible but not foldable, and a case where the region can be rigid rather than flexible. The display panel 10 can display an image on a display region DA in the foldable region FA and the non-foldable regions NFA (NFA1 and NFA2).

[0068] In Figure 1A , for ease of description, the first non-foldable region NFA1 and the second non-foldable region NFA2 have similar areas to each other, and one foldable region FA can be between the first non-foldable region NFA1 and the second non-foldable region NFA2, but one or more embodiments are not limited thereto. For example, the first non-foldable region NFA1 and the second non-foldable region NFA2 can have different areas from each other. In addition, as Figure 1B shown, one or more foldable regions FA can be provided. The non-foldable regions NFA1, NFA2, and NFA3 are spaced apart from each other, and there are foldable regions FA1 and FA2 between them. Each of the foldable regions FA, FA1, and FA2 can be folded relative to a fold line FL, FL1, or FL2, and each of the fold lines FL, FL1, and FL2 can be provided as multiple lines. The fold lines FL, FL1, and FL2 can be respectively provided in the foldable regions FA, FA1, and FA2 in a first direction D1. The foldable regions FA, FA1, and FA2 extend in the first direction D1, and thus, the display panel 10 can be folded at the foldable regions FA, FA1, and FA2.

[0069] In Figure 1A and Figure 1BIn it, the folding lines FL, FL1, and FL2 extend across the centers of the foldable regions FA, FA1, and FA2, and each of the foldable regions FA, FA1, and FA2 can be symmetric with respect to the folding lines FL, FL1, or FL2. However, one or more embodiments are not limited thereto. For example, the folding lines FL, FL1, and FL2 can be provided asymmetrically in the foldable regions FA, FA1, and FA2. The foldable regions FA, FA1, and FA2 and the folding lines FL, FL1, and FL2 of the foldable regions FA, FA1, and FA2 can overlap with the region on the display panel 10 where an image is displayed, and when the display panel 10 is folded, the region where the image is displayed can be folded.

[0070] In another embodiment, the display panel 10 can exactly correspond to the foldable regions FA, FA1, and FA2. For example, when the display device is rollable, the display panel 10 can exactly correspond to the foldable regions FA, FA1, and FA2.

[0071] The display panel 10 can be unfolded flat as shown in Figure 1A and Figure 1B In an embodiment, the display panel 10 can be folded as shown in Figure 2A and thus, the display region DA can be folded with respect to the folding line FL such that the opposite sides of the display region DA face each other. In another embodiment, the display panel 10 can be folded with respect to the folding line FL as shown in Figure 2B and thus, the display region DA can face outward. Here, the term "fold" means that the original shape can not be fixed but can be transformed into another form, and includes folding, bending, or curling along one or more specific lines (such as the folding line FL). Therefore, in the embodiments of the present disclosure, the display region DA can be folded such that the surfaces of the two non-foldable regions NFA1 and NFA2 face each other substantially parallel to each other, but one or more embodiments are not limited thereto, and the display region DA can be folded such that the two non-foldable regions NFA1 and NFA2 form a specific angle (e.g., an acute angle or an obtuse angle) with the foldable region FA therebetween.

[0072] Referring to Figure 3A , the display device 1 can include an optical function layer 50 on the display panel 10, and the optical function layer 50 and the display panel 10 can be covered by a window 60. The window 60 can be bonded to the elements below it (such as the optical function layer 50) through an optically transparent adhesive OCA. The display device 1 can be provided in various electronic devices (such as mobile phones, tablet PCs, laptop computers, smart watches, etc.). As shown in Figure 3B , the display device 1 can further include an input sensing layer 40 between the display panel 10 and the optical function layer 50.

[0073] The input sensing layer 40 may obtain coordinate information generated according to an external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes (e.g., touch electrodes) and signal lines (e.g., traces) connected to the sensing electrodes. In an embodiment, the input sensing layer 40 may be on the display panel 10 (e.g., directly on the display panel 10). That the input sensing layer 40 is on the display panel 10 (e.g., directly on the display panel 10) means that no additional adhesive material layer may be provided between the input sensing layer 40 and the display panel 10, and elements of the input sensing layer 40 may be patterned on the display panel 10 (e.g., directly patterned). In another embodiment, the input sensing layer 40 may be obtained by a process separate from that of the display panel 10 and may be bonded to the display panel 10 via a transparent adhesive material layer or the like.

[0074] The optical function layer 50 may include a structure of a black matrix and color filters. The color filters may be arranged in consideration of the color of light emitted from each of the pixels in the display panel 10. The optical function layer 50 may be used as an antireflection layer that reduces the reflectance of light (e.g., external light) incident on the display panel 10 from the outside via the window 60.

[0075] The window 60 may cover and protect the optical function layer 50, the input sensing layer 40, and / or the display panel 10. The window 60 may be on the display panel 10 with no intermediate polarization layer between the display panel 10 and the window 60. According to this embodiment, a foldable display device (which may be foldable while having a function of preventing external light reflection) may be implemented by including the optical function layer 50 (which includes color filters) instead of a rigid polarization layer (e.g., a retarder and a polarizer) and / or by including a planarization layer containing an organic insulating layer in the display panel 10.

[0076] The window 60 may be provided to be larger than the input sensing layer 40, the optical function layer 50, and the display panel 10, and thus, one side of the window 60 may protrude more than one side of the input sensing layer 40, the optical function layer 50, and the display panel 10. The window 60 may include a transparent material. The window 60 may be flexible. For example, the window 60 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate (CAP), etc., or a combination thereof. The window 60 may be coupled to the input sensing layer 40 and the optical function layer 50 by using a transparent adhesive material layer or the like. The window 60 may include a light-transmitting region 61 that may correspond to the display area DA and a light-blocking region 62 that may correspond to the peripheral area PA.

[0077] Figure 4 It is a schematic equivalent circuit diagram of a pixel PX in a display panel according to an embodiment.

[0078] Reference Figure 4 , the pixel PX may include signal lines SL1, SL2, SL3, EL and DL, an initialization voltage line VIL, and a power supply voltage line PL. In another embodiment, at least one of the signal lines SL1, SL2, SL3, EL and DL, the initialization voltage line VIL, and / or the power supply voltage line PL may be shared by adjacent pixels.

[0079] The signal lines may include a first scan line SL1 configured to transmit a first scan signal GW, a second scan line SL2 configured to transmit a second scan signal GI, a third scan line SL3 configured to transmit a third scan signal GB, an emission control line EL configured to transmit a light emission control signal EM, and a data line DL configured to transmit a data signal DATA. The third scan line SL3 may be the second scan line SL2 of a different (e.g., the next) row, and the third scan signal GB may be the second scan signal GI of a different (e.g., the next) row.

[0080] The power supply voltage line PL may be configured to transmit a first power supply voltage ELVDD to the first transistor T1, and the initialization voltage line VIL may be configured to transmit an initialization voltage VINT to the pixel PX for initializing the first transistor T1 and the organic light emitting diode OLED.

[0081] The pixel circuit PC of the pixel PX may include first to seventh transistors T1 to T7 and a capacitor Cst. The first to seventh transistors T1 to T7 may each include a thin film transistor.

[0082] The first transistor T1 may be electrically connected to the power supply voltage line PL via the fifth transistor T5 and may be electrically connected to the organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 may act as a driving transistor and may receive a data signal DATA to provide a driving current Ioled to the organic light emitting diode OLED according to the switching operation of the second transistor T2.

[0083] The second transistor T2 may be electrically connected to the first scan line SL1 and the data line DL and may be turned on according to the first scan signal GW transmitted through the first scan line SL1 to perform a switching operation for transmitting the data signal DATA that may be transmitted through the data line DL to the node N.

[0084] The third transistor T3 can be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3 can be turned on according to the first scan signal GW transmitted through the first scan line SL1 to diode-connect the first transistor T1.

[0085] The fourth transistor T4 can be turned on according to the second scan signal GI transmitted through the second scan line SL2 and can be configured to transfer the initialization voltage VINT from the initialization voltage line VIL to the gate electrode of the first transistor T1 to initialize the gate voltage of the first transistor T1.

[0086] The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on according to the emission control signal EM transmitted through the emission control line EL to form a current path, and the driving current Ioled flows through this current path from the power supply voltage line PL to the organic light-emitting diode OLED.

[0087] The seventh transistor T7 can be turned on according to the third scan signal GB transmitted through the third scan line SL3 and can be configured to transfer the initialization voltage VINT from the initialization voltage line VIL to the organic light-emitting diode OLED to initialize the organic light-emitting diode OLED. The seventh transistor T7 can be omitted.

[0088] In Figure 4 the fourth transistor T4 can be electrically connected to the second scan line SL2, and the seventh transistor T7 can be electrically connected to the third scan line SL3. In another embodiment, the seventh transistor T7 and the fourth transistor T4 can be electrically connected to the second scan line SL2.

[0089] The capacitor Cst can be electrically connected to the power supply voltage line PL and the gate electrode of the first transistor T1 to store and hold the voltage corresponding to the difference between the voltages at the opposite ends to hold the voltage applied to the gate electrode of the first transistor T1.

[0090] The organic light-emitting diode OLED can include a pixel electrode and a counter electrode, and the counter electrode can receive the second power supply voltage ELVSS. The organic light-emitting diode OLED can receive the driving current Ioled from the first transistor T1 to emit light and thus can display an image.

[0091] Figure 5 is a schematic diagram showing the positions of thin-film transistors and capacitors in each of two adjacent pixels according to an embodiment. Figures 6A to 6I is showing by layer Figure 5 a schematic plan view of the elements (such as thin-film transistors, capacitors, and pixel electrodes) shown in Figures 7 to 9 is along Figure 5Schematic cross-sectional view of pixels intercepted by lines I-I', II-II', and III-III'.

[0092] Reference Figures 5 to 9 , according to an embodiment, the display panel 10 may include a substrate 100, pixels PX on the substrate 100, and a packaging layer 400.

[0093] An inorganic insulating layer including a trench GV between pixel regions PXA and an organic material layer 180 filling the trench GV may be on the substrate 100. Connecting lines 151 to 156 may be on the organic material layer 180 on the substrate 100, and the connecting lines 151 to 156 may cross the organic material layer 180 in a first direction D1 and / or a second direction D2.

[0094] The pixel region PXA may be a region where a pair of pixels PX may be arranged, and may include a first pixel region SPA1 on the left side and a second pixel region SPA2 on the right side. Hereinafter, the pixels in the first pixel region SPA1 may be referred to as first pixels PXL, and the pixels in the second pixel region SPA2 may be referred to as second pixels PXR. The pixel circuits of the first pixels PXL in the first pixel region SPA1 and the pixel circuits of the second pixels PXR in the second pixel region SPA2 may be symmetric to each other based on a virtual boundary line BL that may divide the pixel region PXA. Figures 5 to 6I A part of adjacent pixel regions PXA is further shown.

[0095] Figures 6A to 6I Each of them shows the arrangement of lines, electrodes, semiconductor layers, etc. on the same layer, and an insulating layer may be located Figures 6A to 6I between the layers shown in. Hereinafter, reference will be made to Figures 5 to 9 together for description.

[0096] The substrate 100 may include various materials, such as metal materials, plastic materials, etc., or a combination thereof. In an embodiment, the substrate 100 may include a flexible substrate. As Figures 7 to 9As shown, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104, which may be stacked on top of each other in sequence. The first base layer 101 and the second base layer 103 may each include a polymer resin. For example, the first base layer 101 and the second base layer 103 may each include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate (CAP), etc., or a combination thereof. The above polymer resins may be transparent. The first barrier layer 102 and the second barrier layer 104 may prevent the penetration of external impurities and may each have a single-layer or multi-layer structure including an inorganic material (such as silicon nitride and / or silicon oxide).

[0097] The buffer layer 110 may be on the second barrier layer 104 of the substrate 100. The buffer layer 110 may block impurities or moisture that may penetrate through the substrate 100. The buffer layer 110 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure.

[0098] For each pixel region PXA, the semiconductor layer ACT may be on the buffer layer 110. The semiconductor layer ACT may include a first semiconductor layer ACT1 in the first pixel region SPA1 and a second semiconductor layer ACT2 in the second pixel region SPA2. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be connected to each other. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be provided integrally with each other. In Figure 6A the part between the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be denoted as the third semiconductor layer ACT3. The semiconductor layer ACT in the pixel region PXA may be separated from the semiconductor layer ACT in another pixel region PXA by a groove GV therebetween.

[0099] The semiconductor layer ACT may include amorphous silicon, polycrystalline silicon, an organic semiconductor material, or a combination thereof. Each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may have various curved shapes, where the semiconductor layer ACTa of the first transistor T1, the semiconductor layer ACTb of the second transistor T2, the semiconductor layer ACTc of the third transistor T3, the semiconductor layer ACTd of the fourth transistor T4, the semiconductor layer ACTe of the fifth transistor T5, the semiconductor layer ACTf of the sixth transistor T6, and the semiconductor layer ACTg of the seventh transistor T7 may be connected to each other.

[0100] As Figure 6AAs shown, each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include a channel region 131a of the first transistor T1, a channel region 131b of the second transistor T2, channel regions 131c1 and 131c2 of the third transistor T3, channel regions 131d1 and 131d2 of the fourth transistor T4, a channel region 131e of the fifth transistor T5, a channel region 131f of the sixth transistor T6, and a channel region 131g of the seventh transistor T7. For example, the channel region in each of the first transistor T1 to the seventh transistor T7 may be a part of the semiconductor layer ACT. Since the channel region 131a of the first transistor T1 may be curved and elongated, the driving range of the gate voltage applied to the gate electrode can be increased. The channel region 131a of the first transistor T1 may have various shapes, for example, 'S', 'M', 'W', etc.

[0101] The semiconductor layer of each of the first transistor T1 to the seventh transistor T7 may include a source region and a drain region at opposite sides of the channel region. As Figure 6A shown, each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include a source region 176a and a drain region 177a of the first transistor T1, a source region 176b and a drain region 177b of the second transistor T2, a source region 176c and a drain region 177c of the third transistor T3, a source region 176d and a drain region 177d of the fourth transistor T4, a source region 176e and a drain region 177e of the fifth transistor T5, a source region 176f and a drain region 177f of the sixth transistor T6, and a source region 176g and a drain region 177g of the seventh transistor T7. In some cases, the source region and the drain region may be interpreted as the source electrode and the drain electrode of the transistor. For example, the source electrode and the drain electrode of the first transistor T1 may respectively correspond to Figure 6A the source region 176a and the drain region 177a doped with impurities around the channel region 131a in the semiconductor layer ACT as shown. According to the embodiment, the positions of the source region and the drain region may be changed.

[0102] The source region 176a of the first transistor T1 can be connected to the drain region 177b of the second transistor T2 and the source region 176e of the fifth transistor T5. The drain region 177a of the first transistor T1 can be connected to the source region 176c of the third transistor T3 and the source region 176f of the sixth transistor T6. The drain region 177c of the third transistor T3 can be connected to the drain region 177d of the fourth transistor T4. The source region 176d of the fourth transistor T4 can be connected to the drain region 177g of the seventh transistor T7. The third transistor T3 can be a double-thin film transistor including two channel regions 131c1 and 131c2, and the region between the channel regions 131c1 and 131c2 can be a region doped with impurities and can partially correspond to the source region of a double-thin film transistor and the drain region of another double-thin film transistor. The fourth transistor T4 can be a double-thin film transistor including two channel regions 131d1 and 131d2, and the region between the channel regions 131d1 and 131d2 can be a region doped with impurities and can partially correspond to the source region of a double-thin film transistor and the drain region of another double-thin film transistor.

[0103] At the boundary between the first pixel region SPA1 and the second pixel region SPA2, the source region 176d of the fourth transistor T4 and the drain region 177g of the seventh transistor T7 in the first pixel PXL can be connected to the source region 176d of the fourth transistor T4 and the drain region 177g of the seventh transistor T7 in the second pixel PXR.

[0104] The first gate insulating layer 111 can be on the semiconductor layer ACT. The first gate insulating layer 111 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof. The first gate insulating layer 111 can have a single-layer or multi-layer structure including the above materials.

[0105] As Figure 6B shown, in the first pixel region SPA1 and the second pixel region SPA2, the gate electrodes 125a of the first transistor T1, 125b of the second transistor T2, 125c1 and 125c2 of the third transistor T3, 125d1 and 125d2 of the fourth transistor T4, 125e of the fifth transistor T5, 125f of the sixth transistor T6, and 125g of the seventh transistor T7 can be on the first gate insulating layer 111. The gate electrode 125a of the first transistor T1 can be used as the lower electrode of the capacitor Cst.

[0106] The first scan line 121, the second scan line 122, and the emission control line 123 (which may be on the same layer and may include the same material as the gate electrodes of the first transistor T1 to the seventh transistor T7) may extend in the first direction D1 on the first gate insulating layer 111 and may span the first pixel region SPA1 and the second pixel region SPA2.

[0107] The first scan line 121 may include a 1-1 scan line 121a in the first pixel region SPA1 and a 1-2 scan line 121b in the second pixel region SPA2. The 1-1 scan line 121a and the 1-2 scan line 121b may be connected to each other. For example, the first scan line 121 may include a 1-1 scan line 121a in the first pixel PXL and a 1-2 scan line 121b in the second pixel PXR that are integrally provided with each other.

[0108] The second scan line 122 may include a 2-1 scan line 122a in the first pixel region SPA1 and a 2-2 scan line 122b in the second pixel region SPA2. The 2-1 scan line 122a and the 2-2 scan line 122b may be connected to each other. For example, the second scan line 122 may include a 2-1 scan line 122a in the first pixel PXL and a 2-2 scan line 122b in the second pixel PXR that are integrally provided with each other.

[0109] The emission control line 123 may include a first emission control line 123a in the first pixel region SPA1 and a second emission control line 123b in the second pixel region SPA2. The first emission control line 123a and the second emission control line 123b may be connected to each other. For example, the emission control line 123 may include a first emission control line 123a in the first pixel PXL and a second emission control line 123b in the second pixel PXR that are integrally provided with each other.

[0110] The gate electrode 125b of the second transistor T2 and the gate electrodes 125c1 and 125c2 of the third transistor T3 may be a part of the first scan line 121 that overlaps with the semiconductor layer ACT or a part that protrudes from the first scan line 121. The gate electrodes 125d1 and 125d2 of the fourth transistor T4 and the gate electrode 125g of the seventh transistor T7 may be a part of the second scan line 122 that overlaps with the semiconductor layer ACT or a part that protrudes from the second scan line 122. The gate electrode 125e of the fifth transistor T5 and the gate electrode 125f of the sixth transistor T6 may be a part of the emission control line 123 that overlaps with the semiconductor layer ACT or a part that protrudes from the emission control line 123. The gate electrode 125a of the first transistor T1 may be an island type that overlaps with the channel regions 131a of the first semiconductor layer ACT1 and the second semiconductor layer ACT2. The third transistor T3 and the fourth transistor T4 may be double thin film transistors each including two gate electrodes.

[0111] The gate electrodes of the first transistor T1 to the seventh transistor T7 may have a single-layer or multi-layer structure including one or more selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0112] The first scan line 121, the second scan line 122, and the emission control line 123 in the pixel region PXA may be separated from the first scan line 121, the second scan line 122, and the emission control line 123 in another pixel region PXA.

[0113] The second gate insulating layer 112 may be on the gate electrodes of the first transistor T1 to the seventh transistor T7. The second gate insulating layer 112 may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof. The second gate insulating layer 112 may have a single-layer or multi-layer structure including the above materials.

[0114] As Figure 6C shown, the electrode voltage layer 127 extends on the second gate insulating layer 112 in the first direction D1 and may extend across the first pixel region SPA1 and the second pixel region SPA2. The electrode voltage layer 127 may include a first portion 127a that may overlap with the gate electrode 125a of the first transistor T1 in the first pixel region SPA1, and a second portion 127b that may overlap with the gate electrode 125a of the first transistor T1 in the second pixel region SPA2. The first portion 127a may serve as the upper electrode of the capacitor Cst in the first pixel PXL, and the second portion 127b may serve as the upper electrode of the capacitor Cst in the second pixel PXR. For example, the capacitor Cst may share the gate electrode 125a of the first transistor T1 as the lower electrode and may overlap with the first transistor T1. Each of the first portion 127a and the second portion 127b in the electrode voltage layer 127 may include an opening 128.

[0115] The electrode voltage layer 127 may have a single-layer or multi-layer structure including one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0116] The electrode voltage layer 127 in the pixel region PXA may be separated from the electrode voltage layer 127 in another pixel region PXA.

[0117] The first shielding electrode 129 may be further on the second gate insulating layer 112. The first shielding electrode 129 may include the same material as that of the electrode voltage layer 127. The first shielding electrode 129 may overlap with the source region 176c / drain region 177c between the two channel regions 131c1 and 131c2 of the third transistor T3 in each of the first pixel PXL and the second pixel PXR. The first shielding electrode 129 may be at the boundary between the first pixel region SPA1 and the second pixel region SPA2 and may be shared by the first pixel PXL and the second pixel PXR. The first shielding electrode 129 may prevent the third transistor T3 in each of the first pixel PXL and the second pixel PXR from being affected by light and / or other electrical signals incident from the outside.

[0118] The first interlayer insulating layer 113 may be on the electrode voltage layer 127 and the first shielding electrode 129. The first interlayer insulating layer 113 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof. The first interlayer insulating layer 113 may have a single-layer or multi-layer structure including the above materials.

[0119] As Figure 6D shown, the node electrode 141, the second shielding electrode 143, the first connection electrode 145, and the second connection electrode 147 may be on the first interlayer insulating layer 113. The node electrode 141, the second shielding electrode 143, the first connection electrode 145, and the second connection electrode 147 may each have a single-layer or multi-layer structure including one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0120] The node electrode 141 may be in each of the first pixel region SPA1 and the second pixel region SPA2. One end of the node electrode 141 may be connected to the gate electrode 125a of the first transistor T1 via the contact hole 12 in the second gate insulating layer 112 and the first interlayer insulating layer 113. The other end of the node electrode 141 may be connected to the drain region 177c of the third transistor T3 and the drain region 177d of the fourth transistor T4 via the contact hole 11 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0121] The second shielding electrode 143 can be in each of the first pixel region SPA1 and the second pixel region SPA2. One end of the second shielding electrode 143 can be connected to the source region 176d of the fourth transistor T4 and the drain region 177g of the seventh transistor T7 via a contact hole 13 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113. The second shielding electrode 143 can overlap with the source region 176d / drain region 177d between the two channel regions 131d1 and 131d2 of the fourth transistor T4. The second shielding electrode 143 can prevent the fourth transistor T4 from being affected by light and / or other electrical signals incident from the outside.

[0122] The first connection electrode 145 can be in each of the first pixel region SPA1 and the second pixel region SPA2. One end of the first connection electrode 145 can be connected to the drain region 177e of the fifth transistor T5 via a contact hole 14 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113, and the other end of the first connection electrode 145 can be connected to an electrode voltage layer 127 that can serve as the upper electrode of the capacitor Cst via a contact hole 15 in the first interlayer insulating layer 113.

[0123] The second connection electrode 147 can be at the boundary between the first pixel region SPA1 and the second pixel region SPA2 and can be shared by the first pixel PXL and the second pixel PXR. One end of the second connection electrode 147 can overlap with the first shielding electrode 129 and can be connected to the first shielding electrode 129 via a contact hole 16 in the first interlayer insulating layer 113. The other end of the second connection electrode 147 overlaps with the electrode voltage layer 127 and can be connected to the electrode voltage layer 127 via a contact hole 17 in the first interlayer insulating layer 113.

[0124] The second interlayer insulating layer 114 can be on the node electrode 141, the second shielding electrode 143, the first connection electrode 145, and the second connection electrode 147. The second interlayer insulating layer 114 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The second interlayer insulating layer 114 can have a single-layer or multi-layer structure including the above materials.

[0125] Figure 6E shown Figures 6A to 6D the stacked structure of the conductive layers shown in. As Figure 6EAs shown, the groove GV surrounding the pixel region PXA may be provided in the buffer layer 110, the first gate insulating layer 111 and the second gate insulating layer 112, and the first interlayer insulating layer 113 and the second interlayer insulating layer 114. Hereinafter, the buffer layer 110, the first gate insulating layer 111 and the second gate insulating layer 112, and the first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be collectively referred to as the inorganic insulating layer IL. The groove GV may represent a trench formed in the inorganic insulating layer IL. In an embodiment, the inorganic insulating layer IL may be divided into island-shaped inorganic patterns by the groove GV in units of the pixel region PXA.

[0126] The groove GV may be provided between adjacent pixel regions PXA and may surround each pixel region PXA. The groove GV may include an opening 111a in the first gate insulating layer 111, an opening 112a in the second gate insulating layer 112, an opening 113a in the first interlayer insulating layer 113, and an opening 114a in the second interlayer insulating layer 114. The groove GV may further include an opening 110a in the buffer layer 110. However, one or more embodiments are not limited thereto, and various modifications may be made to the groove GV. For example, the buffer layer 110 may not include an opening, or the buffer layer 110 may not be partially or entirely removed but may be retained.

[0127] The openings 110a, 111a, 112a, 113a, and 114a in the inorganic insulating layer IL may overlap each other. In Figures 7 to 9 this case, the inner surfaces of the opening 110a in the buffer layer 110, the opening 111a in the first gate insulating layer 111, the opening 112a in the second gate insulating layer 112, the opening 113a in the first interlayer insulating layer 113, and the opening 114a in the second interlayer insulating layer 114 may coincide with each other. In another embodiment, the inner surfaces of the openings 110a, 111a, 112a, 113a, and 114a may not coincide with each other, and the openings 110a, 111a, 112a, 113a, and 114a may have different sizes from each other.

[0128] The width W of the groove GV may be about several μm. For example, the width W of the groove GV in the inorganic insulating layer IL may be about 5 μm to about 10 μm. The substrate 100 may be exposed by the groove GV of the inorganic insulating layer IL.

[0129] The groove GV may be obtained through a mask process. In the mask process, dry etching may be performed.

[0130] Contact holes 21a, 21b, 22a, 22b, 23, 24a, 24b, 25, 26, 27, and 28 for bringing a conductive layer formed on the second interlayer insulating layer 114 into contact with a lower conductive layer (e.g., a semiconductor layer, a gate electrode, an upper electrode of a capacitor, etc.) may be in at least one of the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The contact holes 21a, 21b, 22a, 22b, 23, 24a, 24b, 25, 26, 27, and 28 may be obtained simultaneously with the formation of the trench GV in a masking process for forming the trench GV. For ease of description and disclosure, Figure 6E only the positions corresponding to the contact holes 21a, 21b, 22a, 22b, 23, 24a, 24b, 25, 26, 27, and 28 are shown, and the insulating layers are omitted.

[0131] As Figure 6F shown, the organic material layer 180 may be filled in the trench GV of the inorganic insulating layer IL. The organic material layer 180 may at least partially fill the trench GV of the inorganic insulating layer IL. The organic material layer 180 may not completely fill the trench GV. In addition, the organic material layer 180 may not fill a portion of the trench GV. However, the organic material layer 180 may completely fill the trench GV in order to absorb external shocks. In some embodiments, the organic material layer 180 may extend to the upper surface of the inorganic insulating layer IL. Due to the characteristics of the organic material layer 180, the upper surface of the organic material layer 180 may have a convex shape.

[0132] The angle between the upper surface of the organic material layer 180 and the upper surface of the inorganic insulating layer IL may be about 45 degrees or less. In the case where the inclination of the boundary where the upper surface of the inorganic insulating layer IL and the upper surface of the organic material layer 180 meet is not gradual, the conductive material may not be removed but may remain at the boundary, while the connection lines 151 to 156 may be formed by patterning the conductive layer. In the above case, the remaining conductive material may cause a short circuit with other conductive layers. Therefore, the upper surface of the organic material layer 180 may have a gradual (slow) inclination with respect to the upper surface of the inorganic insulating layer IL.

[0133] The organic material layer 180 may include one or more materials selected from the group consisting of acrylic, metacryl, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0134] The organic material layer 180 surrounds the pixel region PXA together with the trench GV, and thus the pixels PX can be divided in units of the pixel region PXA. Accordingly, stress or cracks due to folding of the display panel 10 can be prevented from spreading to other pixel regions PXA.

[0135] As Figure 6G shown, the connection line 150 may be on the second interlayer insulating layer 114. The third connection electrode 157 may be further on the second interlayer insulating layer 114. The connection line 150 may include a conductive line extending in the first direction D1 or the second direction D2 across the trench GV and the organic material layer 180. The connection line 150 may include flexible cords, each of which includes a material having a high elongation rate. The connection line 150 and the third connection electrode 157 may include a single-layer or multi-layer structure including the following: magnesium (Mg), aluminum (Al), copper (Cu), titanium (Ti), etc., or a combination thereof. In an embodiment, the connection line 150 and the third connection electrode 157 may each have a multi-layer structure including Ti / Al / Ti.

[0136] The connection line 150 may include a first scan connection line 151, a second scan connection line 152, an initialization voltage connection line 153, a power supply voltage connection line 154, an emission control connection line 155, and a semiconductor layer connection line 156.

[0137] The first scan connection line 151 may extend in the first direction D1 while overlapping with the first scan line 121, and may be disposed across the first pixel region SPA1 and the second pixel region SPA2. The first scan connection line 151 may be connected to the first scan line 121 via contact holes 21a and 21b in the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0138] The second scan connection line 152 may extend in the first direction D1 while overlapping with the second scan line 122, and may be disposed across the first pixel region SPA1 and the second pixel region SPA2. The second scan connection line 152 may be connected to the second scan line 122 via contact holes 22a and 22b in the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0139] The initialization voltage connection line 153 may extend in the first direction D1 across the first pixel region SPA1 and the second pixel region SPA2. The initialization voltage connection line 153 may be connected via contact holes 23 in the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 to a portion (e.g., the third semiconductor layer ACT3) where the first semiconductor layer ACT1 of the first pixel PXL and the second semiconductor layer ACT2 of the second pixel PXR may be connected. The initialization voltage connection line 153 may include protrusions 153p protruding in the second direction D2 in each of the first pixel region SPA1 and the second pixel region SPA2.

[0140] The power supply voltage connection line 154 may extend in the first direction D1 while overlapping with the electrode voltage layer 127 and may cross the first pixel region SPA1 and the second pixel region SPA2. The power supply voltage connection line 154 may have a bent shape that partially surrounds the opening 128 without overlapping with the opening 128 in the electrode voltage layer 127. The power supply voltage connection line 154 may be connected to the electrode voltage layer 127 via contact holes 24a and 24b in the first interlayer insulating layer 113 and the second interlayer insulating layer 114.

[0141] The emission control connection line 155 may extend in the first direction D1 while overlapping with the emission control line 123 and may cross the first pixel region SPA1 and the second pixel region SPA2. The emission control connection line 155 may be connected to the emission control line 123 via contact holes 25 in the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 at the boundary between the first pixel region SPA1 and the second pixel region SPA2.

[0142] The semiconductor layer connection line 156 may extend in the second direction D2 (or in a direction between the first direction D1 and the second direction D2) across the upper portion of the organic material layer 180 in the trench GV. One end of the semiconductor layer connection line 156 may be connected via contact holes 26 in the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 to the source region 176g of the seventh transistor T7. The other end of the semiconductor layer connection line 156 may be connected via contact holes 27 in the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 to the drain region 177f of the sixth transistor T6. As Figure 5 and Figure 9 shown, one end and the other end of the semiconductor layer connection line 156 may be at different pixel regions PXA (with the trench GV therebetween) to connect the semiconductor layers of adjacent pixels PX to each other in the second direction D2.

[0143] The third connection electrode 157 may be further on the second interlayer insulating layer 114. The third connection electrode 157 may be connected to the source region 176b of the second transistor T2 via a contact hole 28 in the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The third connection electrode 157 may be in each of the first pixel region SPA1 and the second pixel region SPA2.

[0144] Each of the first scan connection line 151, the second scan connection line 152, the power supply voltage connection line 154, and the emission control connection line 155 may extend across the upper portion of the organic material layer 180 in the trench GV to connect the first scan line 121, the second scan line 122, the electrode voltage layer 127, and the emission control line 123 in the pixel regions PXA adjacent to each other in the first direction D1. For example, each of the first scan connection line 151, the second scan connection line 152, the power supply voltage connection line 154, and the emission control connection line 155 may connect the first scan line 121, the second scan line 122, the electrode voltage layer 127, and the emission control line 123 of the pixels PX in the same row that can be divided in units of pixel regions PXA. The power supply voltage connection line 154 may be connected to the pixels PX in the pixel regions PXA adjacent to each other in the first direction D1 to apply the first power supply voltage ELVDD. The initialization voltage connection line 153 may extend across the upper portion of the organic material layer 180 surrounding the pixel region PXA to be connected to the pixels PX in the pixel regions PXA adjacent to each other in the first direction D1, and may apply the initialization voltage VINT to the pixels PX.

[0145] Before forming Figure 6D the conductive layer shown in Figure 6G or before forming

[0146] the conductive layer shown in, a dehydrogenation annealing process may be performed on the semiconductor layer after forming the contact hole. The driving range of the driving transistor may be increased due to the annealing process.

[0147] In an embodiment, the protective layer 115 may be used as a planarization layer together with an organic insulating layer to be described later. The contact holes in the inorganic layer may have a smaller size than the size of the contact holes in the organic layer. In a foldable display device having an island-type pixel group structure according to an embodiment, the integration rate of the pixel circuit for high-resolution and high radio frequency (e.g., 120 Hz) driving may be increased by providing an inorganic planarization layer.

[0148] The protective layer 115 may not cover the organic material layer 180. For example, due to the trench GV, the protective layer 115 may be provided as an island-shaped insulating pattern in each pixel region PXA. The first insulating layer 116 may be further on the protective layer 115.

[0149] As Figure 6H shown, the data line 161 and the power supply voltage line 163 may be on the first insulating layer 116. The data line 161 and the power supply voltage line 163 extend across the organic material layer 180 in the pixel region PXA in the second direction D2 to be connected to adjacent pixels PX to each other in the second direction D2.

[0150] The data line 161 may include a first data line 161E and a second data line 161O. In each of the first pixel region SPA1 and the second pixel region SPA2, the first data line 161E and the second data line 161O may be separated from each other substantially in parallel. In a plan view, the first data line 161E may be at the left side of the first pixel region SPA1 and at the right side of the second pixel region SPA2. The second data line 161O may be at the right side of the first pixel region SPA1 and at the left side of the second pixel region SPA2.

[0151] Pixels PX in even rows may be connected to the first data line 161E, and pixels PX in odd rows may be connected to the second data line 161O. Figure 5 An example is shown in which the first pixel PXL in the first pixel region SPA1 and the second pixel PXR in the second pixel region SPA2 may be connected to the first data line 161E. For example, Figure 5 as shown, the pixel PX may be a pixel in an even row. The data line 161 may be connected to the third connection electrode 157 via the contact hole 31 in the protective layer 115 and the contact hole 31' in the first insulating layer 116. Since the third connection electrode 157 may be connected to the source region 176b of the second transistor T2, the first data line 161E or the second data line 161O may be connected to the second transistor T2 via the third connection electrode 157.

[0152] The first data line 161E may overlap with the source region 176a of the first transistor T1, and the second data line 161O may overlap with the drain region 177a of the first transistor T1. The first data line 161E and the second data line 161O may overlap with the electrode voltage layer 127 and the power supply voltage connection line 154.

[0153] The power supply voltage line 163 may overlap with the electrode voltage layer 127 and may be substantially parallel to the data line 161. The power supply voltage line 163 may be connected to the power supply voltage connection line 154 via the contact hole 32 in the protective layer 115 and the contact hole 32' in the first insulating layer 116. Since the power supply voltage connection line 154 may be connected to the electrode voltage layer 127, the power supply voltage line 163 may have a mesh structure due to the power supply voltage line 163 extending in the second direction D2 and the electrode voltage layer 127 and the power supply voltage connection line 154 extending in the first direction D1.

[0154] When the potential of the gate electrode 125a in the first transistor T1 is affected by the voltage change in the data line 161, coupling may be caused between the data line 161 and the gate electrode 125a of the first transistor T1. In addition, since the node electrode 141 may be connected to the gate electrode 125a of the first transistor T1, when the node electrode 141 is affected by the voltage change in the first data line 161E or the second data line 161O, the potential of the gate electrode 125a in the first transistor T1 may also be affected.

[0155] According to this embodiment, in the cross-sectional view as shown in Figure 7 , the initialization voltage connection line 153 to which a constant voltage (e.g., the initialization voltage VINT) can be applied may be on the layer between the gate electrode 125a of the first transistor T1 and the data line 161 (a part of the initialization voltage connection line 153 that can be the protrusion 153p of the initialization voltage connection line 153 is shown in Figure 7 . In the plan view as shown in Figure 5 (also refer to Figures 6D to 6H ), the protrusion 153p of the initialization voltage connection line 153 may be located between one end of the node electrode 141 and the first data line 161E. For example, according to this embodiment, the initialization voltage connection line 153 may be on the layer between the data line 161 and the node electrode 141 to reduce the influence on the potential of the gate electrode 125a of the first transistor T1 due to the voltage change in the data line 161, and thus, the display device can display a high-quality image with accurate brightness.

[0156] According to an embodiment, as shown in Figure 8As shown, the electrode voltage layer 127 to which a first power supply voltage ELVDD can be applied and the power supply voltage connection line 154 can be on the layer between the gate electrode 125a of the first transistor T1 and the data line 161, and thus, the potential of the gate electrode 125a of the first transistor T1 can be prevented or reduced from being affected by the voltage change in the data line 161. Therefore, the display device can display a high-quality image with precise brightness. In addition, the electrode voltage layer 127 and the power supply voltage connection line 154 can overlap with the data line 161, and thus, the gate electrode 125a of the first transistor T1 can be shielded.

[0157] Each of the data line 161 and the power supply voltage line 163 can have a single-layer or multi-layer structure including one or more selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In an embodiment, each of the data line 161 and the power supply voltage line 163 can each have a multi-layer structure including Ti / Al / Ti.

[0158] The fourth connection electrode 165 can be further on the first insulating layer 116. The fourth connection electrode 165 can be connected to the semiconductor layer connection line 156 via the contact hole 33 in the protective layer 115 and the contact hole 33' in the first insulating layer 116. The fourth connection electrode 165 can include the same material as the material of the power supply voltage line 163. For example, the fourth connection electrode 165 can have a single-layer or multi-layer structure including one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In an embodiment, the fourth connection electrode 165 can have a multi-layer structure including Ti / Al / Ti.

[0159] The mask process for forming the contact hole in the protective layer 115 and the mask process for forming the contact hole in the first insulating layer 116 can be performed separately. The contact holes 31', 32', and 33' in the first insulating layer 116 can overlap with the contact holes 31, 32, and 33 in the protective layer 115, respectively.

[0160] The second insulating layer 117 and the third insulating layer 118 can be sequentially on the data line 161, the power supply voltage line 163, and the fourth connection electrode 165.

[0161] The first insulating layer 116, the second insulating layer 117, and the third insulating layer 118 may each be a planarization layer and an organic insulating layer. For example, the first to third insulating layers 116, 117, and 118 may each include an organic insulating material such as a general polymer (polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic-based polymer, an imide-based polymer, a siloxane-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluoride-based polymer, a parylene-based polymer, a vinyl alcohol-based polymer, and blends thereof. In an embodiment, the first insulating layer 116 and the third insulating layer 118 may include an organic insulating layer containing polyimide, and the second insulating layer 117 may include an organic insulating layer containing siloxane.

[0162] In the case where the organic light-emitting diode (OLED) has an uneven structure due to a step between conductive layers below the organic light-emitting diode (OLED), a reflected color band due to the reflection of light emitted from the organic light-emitting diode (OLED) can be recognized. According to this embodiment, two or more organic insulating layers can be provided between the organic light-emitting diode (OLED) and the thin-film transistor, and thus, the lower layer of the organic light-emitting diode (OLED) can be planarized to solve the above problem.

[0163] As Figure 3A and Figure 3B shown in, the foldable display device according to an embodiment may include a window 60 made of a thin plastic material and may not include a polarization layer between the display panel 10 and the window 60. In the foldable display device according to an embodiment, the lower layer of the organic light-emitting diode (OLED) can be planarized due to the organic insulating layer, and external light reflection can be reduced without using an additional polarization layer.

[0164] In Figures 7 to 9 , two organic insulating layers, such as the second insulating layer 117 and the third insulating layer 118, may be between the organic light-emitting diode (OLED) and the thin-film transistor. However, in another embodiment, three or more organic insulating layers may be between the organic light-emitting diode (OLED) and the thin-film transistor.

[0165] A display element, such as an organic light-emitting diode (OLED), may be on the third insulating layer 118. The organic light-emitting diode (OLED) may include a first electrode 310 (e.g., a pixel electrode), an intermediate layer 320, and a second electrode 330 (e.g., a counter electrode).

[0166] As Figure 6IAs shown, the first electrode 310 of the organic light-emitting diode OLED can be on the third insulating layer 118. The first electrode 310 in the first pixel area SPA1 and the first electrode 310 in the second pixel area SPA2 can be offset from each other. The center of the first electrode 310 in the first pixel area SPA1 and the center of the first electrode 310 in the second pixel area SPA2 can be offset from each other.

[0167] The first electrode 310 can partially extend to the adjacent pixel area PXA, which can be adjacent to the pixel area PXA of the first electrode 310, with a groove GV therebetween. For example, in Figure 6I the first electrode 310 in the first pixel area SPA1 can be in the first pixel area SPA1 and can partially extend to the upper part of the organic material layer 180 and the second pixel area SPA2 in another pixel area PXA. The first electrode 310 in the second pixel area SPA2 can be in the second pixel area SPA2 and can partially extend to the first pixel area SPA1 and the upper part of the organic material layer 180.

[0168] The first electrode 310 in the first pixel area SPA1 or the first electrode 310 in the second pixel area SPA2 can partially overlap with the first shielding electrode 129. Thus, the first electrode 310 in the first pixel area SPA1 or the first electrode 310 in the second pixel area SPA2 can overlap with the source region 176c / drain region 177c between the two channel regions 131c1 and 131c2 of the third transistor T3 in each of the first pixel PXL and the second pixel PXR. For example, the first electrode 310 in the first pixel area SPA1 or the first electrode 310 in the second pixel area SPA2 can be used as a shielding layer together with the first shielding electrode 129 to prevent the third transistor T3 in each of the first pixel PXL and the second pixel PXR from being affected by light incident from the outside and / or other peripheral electrical signals.

[0169] The first electrode 310 can be connected to the fourth connection electrode 165 via the contact hole 40 in the second insulating layer 117 and the contact hole 40' in the third insulating layer 118, as Figure 9 shown. Thus, the first electrode 310 can be connected to the sixth transistor T6 via the semiconductor connection line 156 on the second interlayer insulating layer 114 and the fourth connection electrode 165 on the first insulating layer 116.

[0170] The mask process for forming the contact hole in the second insulating layer 117 and the mask process for forming the contact hole in the third insulating layer 118 can be performed separately. The contact hole 40' in the third insulating layer 118 can overlap with the contact hole 40 in the second insulating layer 117.

[0171] The first electrode 310 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 )), indium gallium oxide (IGO), or aluminum zinc oxide (AZO), or a combination thereof. In another embodiment, the first electrode 310 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode 310 may further include a layer on and / or under the reflective layer, the layer including ITO, IZO, ZnO, or In 2 O 3 , or a combination thereof.

[0172] The fourth insulating layer 119 may be on the third insulating layer 118. The fourth insulating layer 119 may include openings corresponding to each pixel, e.g., an opening OP for at least exposing a central portion of the first electrode 310. The opening OP in the fourth insulating layer 119 may define an emission region EA of the pixel. For example, the fourth insulating layer 119 may correspond to other regions than the emission region EA, e.g., a non-emission region, and the pixel circuit PC may overlap with the emission region EA and / or the non-emission region.

[0173] The fourth insulating layer 119 may increase the distance between the edge of the first electrode 310 and the second electrode 330 on the first electrode 310 to prevent arcing at the edge of the first electrode 310. The fourth insulating layer 119 may include an organic material such as polyimide (PI), hexamethyldisiloxane (HMDSO), etc., or a combination thereof. The size of the emission region EA may vary according to the color of the light emitted from the pixel.

[0174] The intermediate layer 320 may include an emission layer. The emission layer may include a polymeric organic material or a low molecular weight organic material that emits light (e.g., colored light). In an embodiment, the intermediate layer 320 may further include a first functional layer under the emission layer and / or a second functional layer on the emission layer. The first functional layer and / or the second functional layer may include a layer formed over the entire first electrode 310 or a layer patterned to correspond to each of the first electrodes 310.

[0175] The first functional layer may have a single-layer or multi-layer structure. For example, in the case where the first functional layer includes a polymer organic material, the first functional layer may include a hole transport layer (HTL) having a single-layer structure, and may include poly(3,4-ethylenedioxythiophene) (PEDOT), polyaniline (PANI), or a combination thereof. In the case where the first functional layer includes a low molecular weight organic material, the first functional layer may include a hole injection layer (HIL) and an HTL.

[0176] The second functional layer may be optional. For example, in the case where the first functional layer and the emission layer include polymer organic materials, a second functional layer may be formed to improve the characteristics of the organic light-emitting diode OLED. The second functional layer may have a single-layer or multi-layer structure. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0177] The second electrode 330 may face the first electrode 310, with an intermediate layer 320 therebetween. The second electrode 330 may include a conductive material having a low work function. For example, the second electrode 330 may include a (semi)transparent layer that includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. As another example, the second electrode 330 may further include a layer on the (semi)transparent layer including the above materials, and the layer includes ITO, IZO, ZnO, or In 2 O 3 , or a combination thereof.

[0178] The second electrode 330 may be provided integrally with respect to the organic light-emitting diode OLED to face the first electrode 310, and may be on the intermediate layer 320 and the fourth insulating layer 119.

[0179] The encapsulation layer 400 may be on the second electrode 330 to protect the display panel 10 from external impurities or moisture. The encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figures 7 to 9 It is shown that the encapsulation layer 400 may include a first inorganic encapsulation layer 410 and a second inorganic encapsulation layer 430, and an organic encapsulation layer 420 between the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430. In another embodiment, the stacking order and number of the organic encapsulation layer and the inorganic encapsulation layer may vary.

[0180] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may each include one or more inorganic insulating materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, etc. The organic encapsulation layer 420 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyacrylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.) or combinations thereof. Since the first inorganic encapsulation layer 410 may be formed along the structure thereunder, the first inorganic encapsulation layer 410 may have an uneven upper surface. The organic encapsulation layer 420 may have a sufficient thickness to cover the first inorganic encapsulation layer 410. Throughout the display area DA, the upper surface of the organic encapsulation layer 420 may be substantially flat. The second inorganic encapsulation layer 430 may extend to the outer portion of the organic encapsulation layer 420 to contact the first inorganic encapsulation layer 410, and the organic encapsulation layer 420 may not be exposed to the outside.

[0181] Figure 10 It is a schematic plan view showing the relationship between the pixel region PXA and the connection line 150 according to an embodiment. Figure 10 It shows the pattern of the connection line 150, the trench GV, and the organic material layer 180 and the arrangement of the emission region EA in the display area DA.

[0182] The display area DA of the substrate 100 may include pixel regions PXA, and each of the pixel regions PXA may include a first pixel region SPA1 and a second pixel region SPA2. An inorganic insulating layer IL (see Figure 7 ) including island-shaped inorganic patterns may be on the substrate 100 in the display area DA. The inorganic patterns may be surrounded by trenches GV.

[0183] The organic material layer 180 may be between the inorganic patterns and may include holes (openings). Each of the holes in the organic material layer 180 may correspond to each of the pixel regions PXA. The trenches GV and the organic material layer 180 in the display area DA may have a grid structure.

[0184] The display panel 10 according to an embodiment may include pixels PX in a display area DA. The pixels PX may include a first color pixel PX1 that emits first color light, a second color pixel PX2 that emits second color light, and a third color pixel PX3 that emits third color light. The first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 may be repeatedly arranged in a first direction D1 and a second direction D2 according to a specific pattern. In an embodiment, the first color pixel PX1 may include a red pixel, the second color pixel PX2 may include a green pixel, and the third color pixel PX3 may include a blue pixel. In another embodiment, the first color pixel PX1 may include a red pixel, the second color pixel PX2 may include a blue pixel, and the third color pixel PX3 may include a green pixel.

[0185] Reference Figure 10 , each organic light emitting diode OLED in the first color pixel PX1 may include a first emission area EA1, each organic light emitting diode OLED in the second color pixel PX2 may include a second emission area EA2, and each organic light emitting diode OLED in the third color pixel PX3 may include a third emission area EA3.

[0186] In each row of rows 1R, 2R, 3R..., the first emission area EA1 of the first color pixel PX1, the second emission area EA2 of the second color pixel PX2, the third emission area EA3 of the third color pixel PX3, and the second emission area EA2 of the second color pixel PX2 may be repeatedly arranged in a zigzag manner in the first direction D1.

[0187] In odd numbered columns 1M, 3M..., the first emission area EA1 of the first color pixel PX1 and the third emission area EA3 of the third color pixel PX3 may be alternately arranged in the second direction D2. In even numbered columns 2M, 4M..., the second emission area EA2 of the second color pixel PX2 may be repeatedly arranged in the second direction D2. For example, in the first column 1M, the first emission area EA1 of the first color pixel PX1 and the third emission area EA3 of the third color pixel PX3 may be alternately arranged in the second direction D2. In the second column 2M adjacent to the first column 1M, the second emission area EA2 of the second color pixel PX2 may be repeatedly arranged in the second direction D2. In the third column 3M adjacent to the second column 2M, the third emission area EA3 of the third color pixel PX3 and the first emission area EA1 of the first color pixel PX1 may be alternately arranged in the second direction D2, opposite to the first column 1M.

[0188] The first emission region EA1 of the first color pixel PX1, the second emission region EA2 of the second color pixel PX2, and the third emission region EA3 of the third color pixel PX3 may have different areas from each other. In an embodiment, the third emission region EA3 of the third color pixel PX3 may have an area larger than the area of the first emission region EA1 of the first color pixel PX1. In addition, the third emission region EA3 of the third color pixel PX3 may have an area larger than the area of the second emission region EA2 of the second color pixel PX2. In addition, the first emission region EA1 of the first color pixel PX1 may have an area larger than the area of the second emission region EA2 of the second color pixel PX2. In another embodiment, the third emission region EA3 of the third color pixel PX3 may have an area equal to the area of the first emission region EA1 of the first color pixel PX1. However, one or more embodiments are not limited thereto. For example, the first emission region EA1 of the first color pixel PX1 may be larger than the second emission region EA2 of the second color pixel PX2 and the third emission region EA3 of the third color pixel PX3.

[0189] The first to third emission regions EA1, EA2, and EA3 may each have a polygonal shape (such as a rectangular shape, an octagonal shape, etc.), a circular shape, an elliptical shape, etc., and the polygonal shape may have rounded corners.

[0190] In each of the rows 1R, 2R, 3R..., the pixel region PXA may each include a pair of color pixels arranged therein, the pair of color pixels may be separated by a groove GV, and the pixels PX in the pixel region PXA may be connected to each other by a connection line 150. The pixel regions PXA in the odd rows and the pixel regions PXA in the even rows may be offset from each other by up to a first pixel region SPA1 or a second pixel region SPA2. Thus, in the pixel regions PXA of the odd rows 1R, 3R..., the first color pixel PX1 or the third color pixel PX3 may be in the first pixel region SPA1, and the second color pixel PX2 may be in the second pixel region SPA2. In the pixel regions PXA of the even rows 2R..., the second color pixel PX2 may be in the first pixel region SPA1, and the first color pixel PX1 or the third color pixel PX3 may be in the second pixel region SPA2.

[0191] Figure 11 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to another embodiment. Figure 12A is Figure 11 a partially enlarged schematic diagram of the left capacitor, and Figure 12B is along Figure 12ASchematic cross-sectional view of the left capacitor taken along line IV-IV'. Since the illustrated embodiments are the same as those of Figure 11 except for the shape of the node electrode 141, descriptions of elements identical to those of Figure 5 are omitted. Figure 5 One end of the node electrode 141 in

[0192] Figure 5 may have a size corresponding to the opening 128 in the first portion 127a of the electrode voltage layer 127 or the second portion 127b of the electrode voltage layer 127. Figure 12A and Figure 12B The node electrode 141 shown in

[0193] Figure 13 may include a first protrusion 141p1 and a second protrusion 141p2 that can extend to the outer periphery of the opening 128 in the first portion 127a of the electrode voltage layer 127. The first protrusion 141p1 and the second protrusion 141p2 of the node electrode 141 may overlap with the first portion 127a of the electrode voltage layer 127. The power supply voltage connection line 154 may overlap with the first protrusion 141p1 and the second protrusion 141p2 of the node electrode 141. Accordingly, the capacitor Cst may be formed of a stacked structure (e.g., the gate electrode 125a of the first transistor T1 and the first portion 127a of the electrode voltage layer 127, the first portion 127a of the electrode voltage layer 127 and the first protrusion 141p1 and the second protrusion 141p2 of the node electrode 141, the first protrusion 141p1 and the second protrusion 141p2 of the node electrode 141 and the power supply voltage connection line 154), and thus, the capacitance of the capacitor Cst can be ensured.

[0193] Figure 13 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to another embodiment. Figures 14A to 14H is a schematic plan view showing the elements (such as thin film transistors, capacitors, and pixel electrodes) shown in Figure 13 in layers. Figure 15 is a schematic cross-sectional view of the pixel taken along lines V-V', VI-VI', and VII-VII' of Figure 13 . In Figure 15 , layers disposed after the second insulating layer 117 are omitted for ease of disclosure. Hereinafter, elements different from those of Figure 5 will be described, and descriptions of elements identical to those of Figure 5 will be omitted.

[0194] Referring to Figure 13 and Figure 14A, in units of pixel region PXA, the semiconductor layer ACT can be on the buffer layer 110 of the substrate 100. The semiconductor layer ACT can include a first semiconductor layer ACT1 of the first pixel region SPA1, a second semiconductor layer ACT2 of the second pixel region SPA2, and a third semiconductor layer ACT3 that can connect the first semiconductor layer ACT1 and the second semiconductor layer ACT2 therebetween.

[0195] In Figure 14A the semiconductor layer ACT, the distance D in the first direction D1 between the semiconductor layer ACTg of the first semiconductor layer ACT1 and the semiconductor layer ACTg of the second semiconductor layer ACT2 can be greater than Figure 6A the distance in the first direction D1 between the semiconductor layer ACTg of the first semiconductor layer ACT1 and the semiconductor layer ACTg of the second semiconductor layer ACT2 shown in

[0196] Reference Figure 13 and Figure 14B , the gate electrodes 125a, 125b, 125c, 125d, 125e, 125f, and 125g of the first transistor T1 to the seventh transistor T7, the first scan line 121, the second scan line 122, and the emission control line 123 can be on the first gate insulating layer 111. The second scan line 122 can include a 2-1 scan line 122a in the first pixel region SPA1 and a 2-2 scan line 122b in the second pixel region SPA2. The second scan line 122 can further include a protrusion 122p at the boundary between the first pixel region SPA1 and the second pixel region SPA2. The second gate insulating layer 112 can be on the gate electrodes of the first transistor T1 to the seventh transistor T7.

[0197] Reference Figure 13 and Figure 14C , the electrode voltage layer 127 and the first shielding electrode 129 can be on the second gate insulating layer 112. Each of the first part 127a and the second part 127b in the electrode voltage layer 127 can include an opening 128. The first interlayer insulating layer 113 can be on the electrode voltage layer 127 and the first shielding electrode 129.

[0198] Reference Figure 13 and Figure 14D , the node electrode 141, the first connection electrode 145, and the second connection electrode 147 can be on the first interlayer insulating layer 113. The fifth connection electrode 142, the sixth connection electrode 144, the seventh connection electrode 146, the eighth connection electrode 148, and the ninth connection electrode 149 can be further provided on the first interlayer insulating layer 113.

[0199] The node electrode 141 can be connected to the drain region 177c of the third transistor T3, the drain region 177d of the fourth transistor T4, and the gate electrode 125a of the first transistor T1 via the contact holes 11 and 12. The first connection electrode 145 can be connected to the drain region 177e of the fifth transistor T5 via the contact hole 14. The first connection electrode 145 can overlap with the upper electrode of the capacitor Cst. The second connection electrode 147 can be connected to the first shielding electrode 129 and the electrode voltage layer 127 via the contact holes 16 and 17.

[0200] The fifth connection electrode 142 can be in each of the first pixel region SPA1 and the second pixel region SPA2. The fifth connection electrode 142 can be connected to the source region 176g of the seventh transistor T7 via the contact hole 51 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0201] The sixth connection electrode 144 can be at the boundary between the first pixel region SPA1 and the second pixel region SPA2. The sixth connection electrode 144 can overlap with the protrusion 122p of the second scan line 122, and can be connected to the protrusion 122p of the second scan line 122 via the contact hole 52 in the second gate insulating layer 112 and the first interlayer insulating layer 113.

[0202] The seventh connection electrode 146 can be at the boundary between the first pixel region SPA1 and the second pixel region SPA2, and can extend in the first direction D1. The seventh connection electrode 146 can overlap with the third semiconductor layer ACT3 where the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can be connected. The seventh connection electrode 146 can be connected to the third semiconductor layer ACT3 via the contact hole 53 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113, and thus, can be connected to the source region 176d of the fourth transistor T4 and the drain region 177g of the seventh transistor T7 in each of the first pixel PXL and the second pixel PXR.

[0203] The eighth connection electrode 148 can be in each of the first pixel region SPA1 and the second pixel region SPA2. The eighth connection electrode 148 can be connected to the source region 176b of the second transistor T2 via the contact hole 54 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0204] The ninth connection electrode 149 can be adjacent to the boundary between the first pixel region SPA1 and the second pixel region SPA2. The ninth connection electrode 149 can be connected to the drain region 177f of the sixth transistor T6 via the contact hole 55 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0205] The second interlayer insulating layer 114 may cover the conductive layer on the first interlayer insulating layer 113.

[0206] Before forming the Figure 14D conductive layer shown in and after forming the contact holes in the inorganic insulating layer IL, a dehydrogenation annealing process may be performed on the semiconductor layer. The driving range of the driving transistor may be increased due to the annealing process.

[0207] Figure 14E and Figure 14F also shows the Figures 14A to 14D conductive layer shown in. Referring to Figure 13 and Figure 14E , the contact holes 21a, 21b, 22c, 23a, 23b, 24c, 24d, 24e, 25, 26a, 27a, and 28a may be in at least one of the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 in the pixel region PXA, and the conductive layer on the second interlayer insulating layer 114 may contact the lower conductive layer through these contact holes. For ease of description and disclosure, Figure 14E only the positions corresponding to the contact holes 21a, 21b, 22c, 23a, 23b, 24c, 24d, 24e, 25, 26a, 27a, and 28a are shown, and the insulating layers are omitted.

[0208] Referring to Figure 13 and Figure 14F , after forming the contact holes 21a, 21b, 22c, 23a, 23b, 24c, 24d, 24e, 25, 26a, 27a, and 28a in the pixel region PXA, a groove GV surrounding the pixel region PXA may be formed in the inorganic insulating layer IL. The organic material layer 180 may be filled in the groove GV in the inorganic insulating layer IL. For example, the mask process for forming the groove GV may be performed separately from the mask process for forming the contact holes 21a, 21b, 22c, 23a, 23b, 24c, 24d, 24e, 25, 26a, 27a, and 28a.

[0209] In an embodiment, the process of forming the groove GV may be performed simultaneously with a second masking process for removing the inorganic insulating layer IL on the bent region of the substrate 100. To reduce the area of the peripheral region PA recognized by the user, the substrate 100 may include a bent region in the peripheral region PA. The bent region may be a region separate from the foldable region FA and may be in the peripheral region PA, between the pad region and the display region DA on one side of the substrate 100. The substrate 100 may be bent at the bent region, and the pad region may at least partially overlap the display region DA. The bending direction may be set such that the pad region may not block the display region DA but may be located behind the display region DA. Thus, the user may recognize that the display region DA occupies most of the display device. The pads in the pad region may be electrically connected to a flexible film on which a driver chip may be disposed. The organic material layer 180 may be filled in the region of the bent region, and the inorganic insulating layer IL may be removed from this region.

[0210] Reference Figure 13 and Figure 14G As shown in FIGS. and, the connection line 150 and the third connection electrode 157 may be on the second interlayer insulating layer 114. The connection line 150 may include a first scan connection line 151, a second scan connection line 152, an initialization voltage connection line 153, a power supply voltage connection line 154, an emission control connection line 155, and a semiconductor layer connection line 156.

[0211] The second scan connection line 152 may be connected to the second scan line 122 via a contact hole 22c in the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 at the boundary between the first pixel region SPA1 and the second pixel region SPA2.

[0212] As Figure 15 shown in FIGS., the initialization voltage connection line 153 may overlap the seventh connection electrode 146 and may be connected to the seventh connection electrode 146 via contact holes 23a and 23b in the second interlayer insulating layer 114.

[0213] As Figure 14G shown in FIGS., the power supply voltage connection line 154 may include a first protrusion 154p1 and a second protrusion 154p2 protruding in the second direction D2. The power supply voltage connection line 154 may be connected to the first connection electrode 145 via contact holes 24c and 24d in the second interlayer insulating layer 114 and may be connected to the second connection electrode 147 via a contact hole 24e in the second interlayer insulating layer 114.

[0214] As Figure 14G and Figure 15As shown, one end of the semiconductor layer connection line 156 can be connected to the fifth connection electrode 142 via the contact hole 26a in the second interlayer insulating layer 114, and thus can be connected to the source region 176g of the seventh transistor T7. The other end of the semiconductor layer connection line 156 can be connected to the ninth connection electrode 149 via the contact hole 27a in the second interlayer insulating layer 114, and thus can be connected to the drain region 177f of the sixth transistor T6.

[0215] As Figure 15 shown, the third connection electrode 157 can be connected to the eighth connection electrode 148 via the contact hole 28a in the second interlayer insulating layer 114, and thus can be connected to the source region 176b of the second transistor T2.

[0216] The protective layer 115 can be on the connection line 150 and the third connection electrode 157. The protective layer 115 may not cover the organic material layer 180. The first insulating layer 116 can be further on the protective layer 115. The mask process for forming the contact hole in the protective layer 115 and the mask process for forming the contact hole in the first insulating layer 116 can be performed separately.

[0217] Reference Figure 13 and Figure 14H , the data line 161, the power supply voltage line 163, and the fourth connection electrode 165 can be on the first insulating layer 116. As Figures 7 to 9 shown, the second insulating layer 117 and the third insulating layer 118 can be sequentially on Figure 14H the data line 161, the power supply voltage line 163, and the fourth connection electrode 165. The organic light-emitting diode OLED can be on the third insulating layer 118. The encapsulation layer 400 can be on the organic light-emitting diode OLED.

[0218] Reference Figure 13 explained, the implementation mode is different from Figure 5 the implementation mode in that the mask process for forming the groove GV by removing the inorganic insulating layer IL and the mask process for forming the contact hole by removing the first gate insulating layer 111, the second gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114 in the pixel region PXA can be performed separately, as Figure 14E and Figure 14F shown.

[0219] According to the limitation of the hole depth in the mask process for forming the contact hole, as Figure 15As shown, the seventh connection electrode 146, the eighth connection electrode 148, and the ninth connection electrode 149 may additionally be on the first interlayer insulating layer 113, and each of the initialization voltage connection line 153, the third connection electrode 157, and the semiconductor layer connection line 156 may not be in contact with (e.g., directly contact) the semiconductor layer, but may be connected to the semiconductor layer therebelow via each of the seventh connection electrode 146, the eighth connection electrode 148, and the ninth connection electrode 149.

[0220] Figure 16 is a schematic diagram showing the positions of thin film transistors and capacitors in each of two adjacent pixels according to another embodiment. Figures 17A to 17F is showing according to the layer Figure 16 a schematic plan view of elements (such as thin film transistors, capacitors, and pixel electrodes) shown in Figures 18 to 20 is along Figure 16 a schematic cross-sectional view of a pixel taken along line VIII-VIII', line IX-IX', and line X-X'. In Figure 18 order to facilitate disclosure, the layers arranged after the second insulating layer 117 are omitted. Hereinafter, elements different from those of Figure 5 will be described, and the description of elements the same as those of Figure 5 will be omitted.

[0221] Referring to Figure 16 and Figure 17A , in units of the pixel region PXA, the semiconductor layer ACT may be on the buffer layer 110 of the substrate 100. The semiconductor layer ACT may include a first semiconductor layer ACT1 in the first pixel region SPA1 and a second semiconductor layer ACT2 in the second pixel region SPA2. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be separated from each other. The first gate insulating layer 111 may be on the semiconductor layer ACT. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be symmetric with each other.

[0222] Referring to Figure 16 and Figure 17B , the gate electrodes 125a, 125b, 125c, 125d, 125e, 125f, and 125g of the first transistor T1 to the seventh transistor T7, the first scan line 121, the second scan line 122, and the emission control line 123 may be on the first gate insulating layer 111. The second gate insulating layer 112 may be on the gate electrodes of the first transistor T1 to the seventh transistor T7.

[0223] Referring to Figure 16 and Figure 17C, the electrode voltage layer 127 may be on the second gate insulating layer 112. Each of the first portion 127a and the second portion 127b in the electrode voltage layer 127 may include an opening 128. The electrode voltage layer 127 may further include a protrusion 127p protruding from each of the first portion 127a and the second portion 127b in the second direction D2. The protrusion 127p may overlap with the source region 176c / drain region 177c between the two channel regions 131c1 and 131c2 of the third transistor T3 in each of the first pixel PXL and the second pixel PXR. For example, the protrusion 127p may act as a shielding portion that may prevent the third transistor T3 in each of the first pixel PXL and the second pixel PXR from being affected by light and / or other electrical signals incident from the outside. The first interlayer insulating layer 113 may be on the electrode voltage layer 127.

[0224] Figure 17D shows Figures 17A to 17C the conductive layers shown in total in. Refer to Figure 16 and Figure 17D , contact holes 71, 72, 73a, 73b, 74, 75, 76, 77, 78a, 78b, 79a, and 79b may be formed in at least one of the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113 in the pixel region PXA, and the conductive layer on the first interlayer insulating layer 113 may be in contact with the lower conductive layer through these contact holes. For ease of description and disclosure, Figure 17D only the positions corresponding to the contact holes 71, 72, 73a, 73b, 74, 75, 76, 77, 78a, 78b, 79a, and 79b are shown, and the insulating layers may be omitted.

[0225] A trench GV surrounding the pixel region PXA may be formed in the buffer layer 110, the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113. In an embodiment, the mask process for forming the trench GV may be performed separately from the mask process for forming the contact holes 71, 72, 73a, 73b, 74, 75, 76, 77, 78a, 78b, 79a, and 79b. The trench GV may be obtained through two mask processes (for example, a mask process for removing the inorganic insulating layer after forming the first gate insulating layer 111 and a mask process for removing the inorganic insulating layer after forming the first interlayer insulating layer 113). In another embodiment, the trench GV may be obtained simultaneously with the mask process for forming the contact holes 71, 72, 73a, 73b, 74, 75, 76, 77, 78a, 78b, 79a, and 79b. The organic material layer 180 may be filled in the trench GV in the inorganic insulating layer IL.

[0226] Refer to Figure 16 andFigure 17E The connection line 150 and the connection electrode may be on the first interlayer insulating layer 113.

[0227] The connection line 150 may include a first scan connection line 151', a second scan connection line 152', an initialization voltage connection line 153, an emission control connection line 155, and a semiconductor layer connection line 156.

[0228] The first scan connection line 151' may extend in a first direction D1 across an upper portion of the organic material layer 180 that may surround the pixel region PXA. One end of the first scan connection line 151' may be connected to the 1-1 scan line 121a or the 1-2 scan line 121b in the pixel region PXA via a contact hole 71 in the second gate insulating layer 112 and the first interlayer insulating layer 113. The other end of the first scan connection line 151' may be connected in the first direction D1 to the 1-1 scan line 121a or the 1-2 scan line 121b in an adjacent pixel region PXA via a contact hole 71 in the second gate insulating layer 112 and the first interlayer insulating layer 113. One end and the other end of the first scan connection line 151' may be in different pixel regions PXA (with a trench GV therebetween) so as to connect the first scan lines 121 in adjacent pixels PX in the first direction D1.

[0229] The second scan connection line 152' may extend in a first direction D1 across an upper portion of the organic material layer 180 that may surround the pixel region PXA. One end of the second scan connection line 152' may be connected to the 2-1 scan line 122a or the 2-2 scan line 122b in the pixel region PXA via a contact hole 72 in the second gate insulating layer 112 and the first interlayer insulating layer 113. The other end of the second scan connection line 152' may be connected in the first direction D1 to the 2-1 scan line 122a or the 2-2 scan line 122b in an adjacent pixel region PXA via a contact hole 72 in the second gate insulating layer 112 and the first interlayer insulating layer 113. One end and the other end of the second scan connection line 152' may be in different pixel regions PXA (with a trench GV therebetween) so as to connect the second scan lines 122 in adjacent pixels PX in the first direction D1.

[0230] The initialization voltage connection line 153 may extend in a first direction D1 across the first pixel region SPA1 and the second pixel region SPA2. The initialization voltage connection line 153 may be connected to the source region 176d of the fourth transistor T4 and the drain region 177g of the seventh transistor T7 in each of the first pixel PXL and the second pixel PXR via contact holes 73a and 73b in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0231] The emission control connection line 155 may extend in the first direction D1 while overlapping with the emission control line 123, and may be arranged to straddle the first pixel area SPA1 and the second pixel area SPA2. The emission control connection line 155 may be connected to the emission control line 123 via a contact hole 74 in the second gate insulating layer 112 and the first interlayer insulating layer 113 at the boundary between the first pixel area SPA1 and the second pixel area SPA2.

[0232] The semiconductor layer connection line 156 may extend in the second direction D2 across the upper portion of the organic material layer 180 surrounding the pixel area PXA. One end of the semiconductor layer connection line 156 may be connected to the source region 176g of the seventh transistor T7 via a contact hole 75 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113. The other end of the semiconductor layer connection line 156 may be connected to the drain region 177f of the sixth transistor T6 via a contact hole 76 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113. One end and the other end of the semiconductor layer connection line 156 may be in different pixel areas PXA (with a groove GV therebetween) so as to connect semiconductor layers in adjacent pixels PX in the second direction D2.

[0233] The third connection electrode 157 may be connected to the source region 176b of the second transistor T2 via a contact hole 77 in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0234] The node connection electrode 158 may include a first node connection electrode 158a and a second node connection electrode 158b. The first node connection electrode 158a may be connected to the gate electrode 125a of the first transistor T1 via a contact hole 78a in the second gate insulating layer 112 and the first interlayer insulating layer 113. The second node connection electrode 158b may be connected to the drain regions 177c of the third transistor T3 and 177d of the fourth transistor T4 via a contact hole 78b in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0235] The power supply voltage connection electrode 159 may include a first power supply voltage connection electrode 159a and a second power supply voltage connection electrode 159b. The first power supply voltage connection electrode 159a may be connected to the electrode voltage layer 127 via a contact hole 79a in the first interlayer insulating layer 113. The second power supply voltage connection electrode 159b may be connected to the drain region 177e of the fifth transistor T5 via a contact hole 79b in the first gate insulating layer 111, the second gate insulating layer 112, and the first interlayer insulating layer 113.

[0236] The protective layer 115 may be on the connection line 150 and the connection electrode. The protective layer 115 may not cover the organic material layer 180. The first insulating layer 116 may be further on the protective layer 115. A masking process for forming contact holes in the protective layer 115 and a masking process for forming contact holes in the first insulating layer 116 may be performed separately.

[0237] Reference Figure 16 and Figure 17F , the data line 161, the power supply voltage line 163, the fourth connection electrode 165, and the node electrode 167 may be on the first insulating layer 116.

[0238] The power supply voltage line 163 may be connected to the first power supply voltage connection electrode 159a and the second power supply voltage connection electrode 159b via the contact holes 32a and 32b in the protective layer 115 and the contact holes 32a' and 32b' in the first insulating layer 116.

[0239] The node electrode 167 may be connected to the first node connection electrode 158a and the second node connection electrode 158b via the contact holes 34a and 34b in the protective layer 115 and the contact holes 34a' and 34b' in the first insulating layer 116.

[0240] As Figures 7 to 9 shown, the second insulating layer 117 and the third insulating layer 118 may be sequentially on Figure 17F the data line 161, the power supply voltage line 163, the fourth connection electrode 165, and the node electrode 167. The organic light-emitting diode OLED may be on the third insulating layer 118. The encapsulation layer 400 may be on the organic light-emitting diode OLED.

[0241] According to the embodiment explained in the reference Figure 16 , Figure 17B and Figure 17C the conductive layer shown in may be formed by using a low-resistance metal and connected to Figure 17E the connection line, and thus, compared with the embodiment explained in Figure 5 and Figure 13 , the masking process may be reduced without providing a connection conductive layer as shown in Figure 6D and Figure 14D . Figure 17B and Figure 17CThe conductive layer shown in [the figure] may have a single-layer structure including a low-resistance metal material such as aluminum (Al), aluminum alloy (Al alloy), or copper (Cu), or a combination thereof, or a multi-layer structure including one or more metals selected from platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), and tungsten (W). For example, Figure 17B and Figure 17C the conductive layers shown in [the figure] may each have a single-layer structure including an aluminum alloy, or a multi-layer structure including aluminum alloy / TiN, TiN / aluminum alloy / TiN, etc.

[0242] Figure 21 is a schematic cross-sectional view of a display device according to an embodiment, Figure 22 is a diagram showing Figure 21 the relationship between the black matrix and the emission region in [the figure], and Figure 23 is a diagram showing Figure 21 the relationship between the color filter and the emission region in [the figure].

[0243] Referring to Figure 21 , the black matrix BM and the color filter CF may be on the encapsulation layer 400 as optical functional layers. As Figure 22 shown in [the figure], the black matrix BM may surround the emission region EA and may correspond to other regions except for the opening OP in the fourth insulating layer 119. As Figure 23 shown in [the figure], the color filter CF may at least correspond to the emission region EA. The color filter CF may include a first color filter CF1 that selectively transmits first-color light, a second color filter CF2 that selectively transmits second-color light, and a third color filter CF3 that selectively transmits third-color light. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged adjacent to each other in a specific pattern. The black matrix BM may correspond to the boundaries between the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may partially overlap with the black matrix BM.

[0244] Although not shown in the drawings, an input sensing layer may be further provided between the black matrix BM and the color filter CF and the encapsulation layer 400.

[0245] According to one or more embodiments, a group of pixels may be provided as islands by using slots and an organic material layer, and the island-shaped pixel groups may be connected by using flexible connection lines to provide a high-resolution foldable display device, which may be robust against internal shocks. According to one or more embodiments, some of the connection lines for connecting pixel groups may be used as a shielding layer for preventing coupling (crosstalk) between the gate node of a driving thin film transistor and a data line, and thus, a display device with high image quality may be provided. In addition, according to one or more embodiments, a structure for shielding a floating node between two channel regions of a thin film transistor having a double-gate structure may be provided, and thus, leakage of the thin film transistor may be reduced.

[0246] According to one or more embodiments, an inorganic insulating layer including slots and an organic material layer filling the slots may be provided in a region between pixels, and thus, a high-resolution display device that may be robust against external shocks and may be flexible may be implemented. However, the scope of the present disclosure is not limited to the above effects.

[0247] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims (including any equivalents).

Claims

1. A display device, comprising: a substrate including a display area, the display area including a pixel area, and each of the pixel areas including a first sub-pixel area and a second sub-pixel area adjacent to each other in a first direction; an inorganic insulating layer including an inorganic pattern, each of the inorganic patterns corresponding to each of the pixel areas including the first sub-pixel area and the second sub-pixel area; an organic material layer disposed between the inorganic patterns and surrounding each of the pixel areas including the first sub-pixel area and the second sub-pixel area; and a first conductive line located on the inorganic insulating layer, extending in the first direction, and spanning the pixel area, wherein the first conductive line spans the organic material layer and electrically connects signal lines disposed in each of the pixel areas.

2. The display device according to claim 1, further comprising: a plurality of thin film transistors, each of the plurality of thin film transistors being disposed in each of the first sub-pixel area and the second sub-pixel area.

3. The display device according to claim 2, further comprising: an organic insulating layer located on the inorganic insulating layer, wherein the plurality of thin film transistors are located between the substrate and the organic insulating layer.

4. The display device according to claim 1, further comprising: a first thin film transistor including a first semiconductor layer located in the first sub-pixel area; and a second thin film transistor including a second semiconductor layer located in the second sub-pixel area, wherein at least one of the signal lines is a scan line extending in the first direction and spanning the first sub-pixel area and the second sub-pixel area, and the scan line overlaps with the first semiconductor layer and the second semiconductor layer.

5. The display device according to claim 1, further comprising: a first driving thin film transistor including a first semiconductor layer and a first gate electrode located in the first sub-pixel area; and a second driving thin film transistor including a second semiconductor layer and a second gate electrode located in the second sub-pixel area, wherein at least one of the signal lines includes an electrode layer extending in the first direction and spanning the first sub-pixel area and the second sub-pixel area, and the electrode layer overlaps with the first semiconductor layer and the second semiconductor layer.

6. The display device according to claim 5, further comprising: an organic insulating layer located on the inorganic insulating layer; and a power supply line located on the organic insulating layer, extending in a second direction different from the first direction and spanning the pixel area, wherein the power supply line is electrically connected to the first conductive line.

7. The display device according to claim 5, further comprising: an organic insulating layer located on the inorganic insulating layer; and a data line located on the organic insulating layer, extending in a second direction different from the first direction and spanning the pixel area, wherein the first conductive line is disposed between the electrode layer and the data line and overlaps with the electrode layer.

8. The display device according to claim 7, wherein, A constant voltage is applied to the electrode layer and the first conductive line.

9. The display device according to claim 7, further comprising: A power supply line extending in the second direction and spanning the pixel region, wherein the power supply line and the data line are provided on the same layer, and the power supply line is electrically connected to the first conductive line.

10. The display device according to claim 1, further comprising: A semiconductor layer located in each of the pixel regions; and A second conductive line extending in a second direction different from the first direction and electrically connecting the semiconductor layers in a pair of pixel regions adjacent to each other in the second direction.

11. The display device according to claim 1, further comprising: A display element including a pixel electrode, a counter electrode facing the pixel electrode, and an emission layer provided between the pixel electrode and the counter electrode; and At least two organic insulating layers provided between the inorganic insulating layer and the pixel electrode.

12. The display device according to claim 11, wherein the pixel electrode overlaps with the organic material layer.

13. The display device according to any one of claims 1 to 12, wherein the inorganic pattern in the first row and the inorganic pattern in the second row adjacent to the first row are offset from each other in the first direction.

14. A display device, comprising: A substrate including a first pixel region and a second pixel region adjacent to the first pixel region in a first direction; A first driving thin film transistor located in the first pixel region; A second driving thin film transistor located in the second pixel region; An electrode layer overlapping with the first gate electrode of the first driving thin film transistor and the second gate electrode of the second driving thin film transistor, the electrode layer being provided on the first gate electrode and the second gate electrode; An inorganic pattern corresponding to the first pixel region and the second pixel region; and An organic material layer surrounding the first pixel region and the second pixel region and including holes corresponding to the inorganic pattern.

15. The display device according to claim 14, further comprising: A conductive line located on the electrode layer, overlapping with the electrode layer and electrically connected to the electrode layer, wherein the conductive line extends in the first direction and spans the organic material layer.

16. The display device according to claim 15, further comprising: An organic insulating layer located on the inorganic pattern and the organic material layer; and A power supply line located on the organic insulating layer, extending in a second direction different from the first direction and spanning the organic material layer, wherein the power supply line is electrically connected to the conductive line.

17. The display device according to claim 15, further comprising: An organic insulating layer located on the inorganic pattern and the organic material layer; and A data line located on the organic insulating layer, extending in a second direction different from the first direction and spanning the organic material layer, wherein the conductive line is provided between the electrode layer and the data line.

18. The display device according to claim 17, wherein A constant voltage is applied to the electrode layer and the conductive wire.

19. The display device according to claim 17, further comprising: a power supply line extending in the second direction and crossing the organic material layer, wherein the power supply line and the data line are disposed in the same layer, and the power supply line is electrically connected to the conductive wire.

20. The display device according to claim 14, further comprising: at least two organic insulating layers located on the inorganic pattern and the organic material layer; and a display element located on the at least two organic insulating layers and including a pixel electrode, a counter electrode facing the pixel electrode, and an emission layer disposed between the pixel electrode and the counter electrode.

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