Display substrate, manufacturing method thereof and display device

Abstract

The invention provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a substrate; the first metal layer is located on one side of the substrate, and the first metal layer comprises a data line and a shading part in the display area; the active layer is located on the side, away from the substrate, of the first metal layer and comprises a first part, a second part and a third part in the display area, the third part is connected with the first part and the second part, the orthographic projection of the first part on the substrate falls into the range where the data lines are located, and the orthographic projection of the second part on the substrate falls into the range where the shading part is located; the second metal layer is located on the side, away from the substrate, of the active layer, the second metal layer comprises a first electrode, a second electrode and a grid line in the display area, the first electrode is electrically connected with the data line through a first via hole penetrating through the first part, and the second electrode is electrically connected with the second part; the pixel electrode layer is located on the side, away from the substrate, of the second metal layer, and the pixel electrode layer in the display area comprises a pixel electrode electrically connected with the second electrode.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Existing low-temperature polysilicon (LTPS) technology has a complex film structure, involves numerous steps, uses a large number of masks, and has a long production cycle, significantly impacting production line utilization.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The specific solutions are as follows:

[0005] An embodiment of the present disclosure provides a display substrate, wherein the display substrate is divided into a display area and a peripheral area surrounding the display area; the display substrate includes:

[0006] substrate;

[0007] a first metal layer, located on one side of the substrate, wherein the first metal layer includes a data line and a light shielding portion in the display area;

[0008] an active layer located on a side of the first metal layer facing away from the substrate, the active layer comprising a first portion, a second portion, and a third portion in the display area, the third portion connecting the first portion and the second portion, an orthographic projection of the first portion on the substrate falling within a range where the data line is located, and an orthographic projection of the second portion on the substrate falling within a range where the light shielding portion is located;

[0009] a second metal layer located on a side of the active layer facing away from the substrate, the second metal layer comprising a first electrode, a second electrode, and a gate line in the display area, the first electrode being electrically connected to the data line via a first via hole penetrating the first portion, the second electrode being electrically connected to the second portion, and an overlapping area between an orthographic projection of the gate line on the substrate and the first portion, and an overlapping area between an orthographic projection of the gate line on the substrate and the second portion forming a gate;

[0010] A pixel electrode layer is located on a side of the second metal layer away from the substrate. The pixel electrode layer includes a pixel electrode in the display area. The pixel electrode is electrically connected to the second electrode.

[0011] Optionally, in the embodiment of the present disclosure, the method further includes:

[0012] a first insulating layer, located between the first metal layer and the active layer;

[0013] a second insulating layer, located between the active layer and the second metal layer;

[0014] The first via hole also penetrates the first insulating layer and the second insulating layer at the same time, and the second electrode is electrically connected to the second portion through a second via hole penetrating the second insulating layer;

[0015] The first via hole and the second via hole are located on the same side of the gate line, and the third portion is located on the other side of the gate line.

[0016] Optionally, in an embodiment of the present disclosure, there is a first distance between the first via hole and the gate line, there is a second distance between the second via hole and the gate line, and the first distance is not equal to the second distance.

[0017] Optionally, in the embodiment of the present disclosure, the method further includes:

[0018] a third insulating layer, located between the second metal layer and the pixel electrode layer;

[0019] a common electrode layer, located between the third insulating layer and the pixel electrode layer;

[0020] a fourth insulating layer, located between the common electrode layer and the pixel electrode layer;

[0021] The third insulating layer and the common electrode layer have a third via hole, the fourth insulating layer has a fourth via hole, the fourth via hole is sleeved in the third via hole, and the pixel electrode is connected to the second electrode through the fourth via hole and the third via hole.

[0022] Optionally, in the embodiment of the present disclosure, the orthographic projection of the third via hole on the substrate and the orthographic projection of the second via hole on the substrate are staggered.

[0023] Optionally, in the embodiment of the present disclosure, the method further includes:

[0024] a planar layer, located between the third insulating layer and the common electrode layer;

[0025] The third via hole also penetrates the planar layer.

[0026] Optionally, in the embodiment of the present disclosure, the data line has a widened portion, and an orthographic projection of the widened portion on the substrate covers the first portion.

[0027] Optionally, in the embodiment of the present disclosure, both the first portion and the second portion extend along the data line direction, and have the same width along the gate line direction, and the widened portion and the light shielding portion have the same width along the gate line direction.

[0028] Optionally, in the embodiment of the present disclosure, the orthographic projections of the widening portion and the light-shielding portion on the substrate do not overlap with the third portion.

[0029] Optionally, in an embodiment of the present disclosure, the orthographic projection of the first via hole on the substrate completely falls within the region of the orthographic projection of the widened portion on the substrate.

[0030] Optionally, in an embodiment of the present disclosure, a widening member is provided at an end of the first portion away from the third portion, and the orthographic projection of the first via on the substrate falls within the range of the widening member.

[0031] Optionally, in an embodiment of the present disclosure, a line width center line of the first portion and a line width center line of the data line are staggered.

[0032] Optionally, in an embodiment of the present disclosure, the pixel electrode includes a plurality of strip electrodes extending substantially along the data line direction, the plurality of strip electrodes are connected at one end by a first edge electrode, and the plurality of strip electrodes are connected at the other end by a second edge electrode;

[0033] The pixel electrode further includes a connecting electrode provided at one end of the first edge electrode, the connecting electrode being electrically connected to the second electrode, and the other end of the first edge electrode having a concave structure avoiding the widened portion.

[0034] Optionally, in the embodiment of the present disclosure, an orthographic projection of the second edge electrode on the substrate has an overlapping area with an adjacent gate line.

[0035] Optionally, in the embodiment of the present disclosure, the common electrode layer has a hollow pattern in a portion of the data line except the widened portion.

[0036] Optionally, in an embodiment of the present disclosure, the peripheral area has a GOA area located on one side or both sides of the display area;

[0037] The first metal layer includes a first signal line and a second signal line in the GOA region, and the second metal layer includes a third signal line, a first electrode and a second electrode in the GOA region;

[0038] The first electrode is electrically connected to the first signal line through a via hole penetrating the active layer, and the second electrode is electrically connected to the second signal line through a via hole penetrating the active layer.

[0039] Optionally, in an embodiment of the present disclosure, the peripheral area has a fan-out area located on one side of the display area;

[0040] The data line extends to the fan-out area and is connected to the second metal layer in the fan-out area.

[0041] Accordingly, an embodiment of the present disclosure provides a display device, comprising:

[0042] A display substrate as described in any one of the above items, an opposite substrate arranged opposite to the display substrate, and a liquid crystal layer arranged between the display substrate and the opposite substrate.

[0043] Optionally, in an embodiment of the present disclosure, the opposing substrate includes a plurality of filter portions and a shielding portion surrounding each of the filter portions, and the orthographic projection of the shielding portion on the substrate completely falls within the area of ​​the orthographic projection of the shielding portion on the substrate.

[0044] Accordingly, an embodiment of the present disclosure provides a method for manufacturing a display substrate, wherein the display substrate is divided into a display area and a peripheral area surrounding the display area; the manufacturing method includes:

[0045] forming a first metal layer on one side of the substrate, wherein the first metal layer includes a data line and a light shielding portion in the display area;

[0046] An active layer is formed on a side of the first metal layer facing away from the substrate, wherein the active layer includes a first portion, a second portion, and a third portion in the display area, the third portion connects the first portion and the second portion, an orthographic projection of the first portion on the substrate falls within a range where the data line is located, and an orthographic projection of the second portion on the substrate falls within a range where the light shielding portion is located;

[0047] forming a second metal layer on a side of the active layer facing away from the substrate, the second metal layer including a first electrode, a second electrode, and a gate line in the display area, the first electrode being electrically connected to the data line via a first via hole penetrating the first portion, the second electrode being electrically connected to the second portion, and an overlapping area between an orthographic projection of the gate line on the substrate and the first portion, and an overlapping area between an orthographic projection of the gate line on the substrate and the second portion forming a gate;

[0048] A pixel electrode layer is formed on a side of the second metal layer facing away from the substrate. The pixel electrode layer includes a pixel electrode in the display area. The pixel electrode is electrically connected to the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of a partial top view of a display panel using a 9-pass mask process in the related art;

[0050] FIG2 is a schematic diagram of a cross-sectional structure along the direction indicated by MM in FIG1 ;

[0051] FIG3 is a schematic diagram of a top view of a display substrate provided in an embodiment of the present disclosure;

[0052] FIG4 is a schematic diagram of a cross-sectional structure along the direction NN in FIG3 ;

[0053] FIG5 is an enlarged schematic diagram of a local structure of a display substrate provided by an embodiment of the present disclosure;

[0054] FIG6 is a schematic diagram of another cross-sectional structure along the direction indicated by NN in FIG3 ;

[0055] FIG7 is a schematic diagram of another cross-sectional structure along the direction indicated by NN in FIG3 ;

[0056] FIG8 is an enlarged schematic diagram of one structure along area Q in FIG3 ;

[0057] FIG9 is an enlarged schematic diagram of a local structure of a display substrate provided by an embodiment of the present disclosure;

[0058] FIG10 is an enlarged schematic diagram of one structure of the area P in FIG9 ;

[0059] FIG11 is an enlarged schematic diagram of another structure of the area P in FIG9 ;

[0060] FIG12 is a schematic top view of a portion of a common electrode layer in a display substrate provided by an embodiment of the present disclosure;

[0061] FIG13 is a schematic top view of a local structure between the common electrode layer and the data line shown in FIG12 ;

[0062] FIG14 is a schematic diagram of a top view of a display substrate provided in an embodiment of the present disclosure;

[0063] FIG15 is a schematic diagram of a top view of the area O in FIG14 ;

[0064] FIG16 is a schematic diagram of a cross-sectional structure along the direction indicated by TT in FIG15 ;

[0065] FIG17 is a schematic diagram of a partial top view of the structure of the substrate in FIG1 corresponding to the GOA region;

[0066] FIG18 is a schematic diagram of a cross-sectional structure along the direction indicated by UU in FIG17 ;

[0067] FIG19 is a schematic diagram of a top view of a display substrate provided in an embodiment of the present disclosure;

[0068] FIG20 is a schematic diagram of a top view of the region S in FIG19 ;

[0069] FIG21 is a schematic diagram of a cross-sectional structure along the direction indicated by VV in FIG20 ;

[0070] FIG22 is a schematic diagram of a partial top view of the structure of the substrate in FIG1 corresponding to a position of the fan-out area;

[0071] FIG23 is a schematic diagram of a cross-sectional structure along the direction WW in FIG22;

[0072] FIG24 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0073] FIG25 is a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0075] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0076] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0077] In related technologies, the LTPS process often uses a nine-mask process. As shown in Figures 1 and 2, Figure 1 is a schematic diagram of a partial top view of the display panel structure, and Figure 2 is a schematic diagram of a cross-sectional structure along the direction indicated by MM in Figure 1. 01 represents the substrate; 02 represents the light shielding layer; 03 represents the buffer layer; 04 represents the active layer; 05 represents the gate insulating layer; 06 represents the interlayer insulating layer; 07 represents the source and drain electrode layer; 08 represents the isolation and planarization layer; 09 represents the common electrode layer; 010 represents the passivation layer; and 011 represents the pixel electrode layer. The corresponding layer structures obtained through the nine-mask process are, in order: the first light shielding layer 02; the second active layer 04; the third gate layer 012; the fourth interlayer insulating layer 06; the fifth source / drain lead layer (i.e., the source and drain electrode layer 07); the sixth isolation and planarization layer 08; the seventh common electrode layer 09; the eighth passivation layer 010; and the ninth pixel electrode layer 011. The entire process involves many steps, uses a large number of mask plates, and has a long production cycle, which greatly affects the utilization of the production line.

[0078] In view of this, embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which are used to reduce the number of masks and simplify the process.

[0079] As shown in Figures 3 and 4, Figure 3 is a schematic top view of a display substrate provided in an embodiment of the present disclosure, and Figure 4 is a schematic cross-sectional view along the direction indicated by line NN in Figure 3. Specifically, the display substrate is divided into a display area A and a peripheral area B surrounding the display area A; the display substrate includes:

[0080] Base 10;

[0081] A first metal layer 20 is located on one side of the substrate 10 , and the first metal layer 20 includes a data line 21 and a light shielding portion 22 in the display area A;

[0082] An active layer 30 is located on a side of the first metal layer 20 facing away from the substrate 10. The active layer 30 includes a first portion 31, a second portion 32, and a third portion 33 in the display area A. The third portion 33 connects the first portion 31 and the second portion 32. The orthographic projection of the first portion 31 on the substrate 10 falls within the range of the data line 21. The orthographic projection of the second portion 32 on the substrate 10 falls within the range of the light shielding portion 22.

[0083] a second metal layer 40 located on a side of the active layer 30 facing away from the substrate 10, the second metal layer 40 including a first electrode 41, a second electrode 42, and a gate line 43 in the display area A, the first electrode 41 being electrically connected to the data line 21 via a first via hole H1 penetrating the first portion 31, the second electrode 42 being electrically connected to the second portion 32, and an overlapping region where an orthographic projection of the gate line 43 on the substrate 10 overlaps with the first portion 31, and an overlapping region where an orthographic projection of the gate line 43 on the substrate 10 overlaps with the second portion 32 forming a gate 430;

[0084] The pixel electrode layer 50 is located on a side of the second metal layer 40 facing away from the substrate 10 . The pixel electrode layer 50 includes a pixel electrode 51 in the display area A. The pixel electrode 51 is electrically connected to the second electrode 42 .

[0085] During the specific implementation process, the display area A and the peripheral area B can be set as shown in Figure 3. Of course, in addition to the exemplary embodiment shown in Figure 3, the relative position relationship between the display area A and the peripheral area B can also be set according to actual application needs, which is not limited here. Specifically, the display substrate includes a base 10, a first metal layer 20 located on one side of the base 10, an active layer 30 located on the side of the first metal layer 20 facing away from the base 10, a second metal layer 40 located on the side of the active layer 30 facing away from the base 10, and a pixel electrode layer 50 located on the side of the second metal layer 40 facing away from the base 10. Exemplarily, the base 10 can be a rigid base 10 or a flexible base 10, which is not limited here. The data line 21 is used to transmit the data signal required by the display substrate, and the light shielding portion 22 is used to block the backlight from irradiating the channel, thereby avoiding the generation of leakage current. The active layer 30 includes a first portion 31, a second portion 32 and a third portion 33 in the display area A, and the third portion 33 connects the first portion 31 and the second portion 32. Figure 3 shows one connection relationship between the first portion 31, second portion 32, and third portion 33 of the active layer 30. The orthographic projection of the first portion 31 on the substrate 10 falls within the area where the data line 21 is located, and the orthographic projection of the second portion 32 on the substrate 10 falls within the light shielding portion 22. This effectively shields the channel of the active layer 30 through the first metal layer 20, preventing leakage current and improving electrical anomalies in the product, enabling its application in broadband technologies.

[0086] Furthermore, the second metal layer 40 includes a first electrode 41, a second electrode 42, and a gate line 43 in the display area A. The gate line 43 extends in a direction that intersects with the data line 21. As shown in Figure 3, the direction indicated by arrow X is the extension direction of the gate line 43, and the direction indicated by arrow Y is the extension direction of the data line 21. In a specific implementation, depending on the direction of signal flow, the first electrode 41 serves as the source electrode and the second electrode 42 as the drain electrode; alternatively, the first electrode 41 serves as the drain electrode and the second electrode 42 as the source electrode. Of course, the first and second electrodes 41, 42 can also be arranged according to actual application needs, and this is not limited here. Furthermore, the first electrode 41 is electrically connected to the data line 21 via a first via H1 that penetrates the first portion 31, and the second electrode 42 is electrically connected to the second portion 32. The overlapping areas of the gate line 43's orthographic projection on the substrate 10 and the first portion 31, as well as the overlapping areas of the gate line 43's orthographic projection on the substrate 10 and the second portion 32, constitute the gate 430. In practical applications, the gate 430 can function as a switch for a metal oxide semiconductor field effect transistor (MOS) or a thin film transistor (TFT). By applying a voltage to the gate 430, the conductive channel of the corresponding switch is opened, forming a complete path. This achieves the on / off control function of the channel.

[0087] It should be noted that, for the active layer 30 , the extension direction of the first portion 31 and the second portion 32 may be substantially the same as the extension direction of the data line 21 ; the extension direction of the third portion 33 may be substantially the same as the extension direction of the gate line 43 .

[0088] In addition, the pixel electrode layer 50 includes a pixel electrode 51 in the display area A, and the pixel electrode 51 is electrically connected to the second electrode 42. Exemplarily, the display substrate includes a plurality of pixel electrodes 51 arranged in an array. FIG. 3 schematically illustrates the distribution of some pixel electrodes 51. In actual applications, the number and distribution of pixel electrodes 51 can be set as needed, and this is not limited here. In this way, the driving capability of the display substrate is guaranteed.

[0089] It should be noted that in the embodiment of the present disclosure, the first metal layer 20 includes a data line 21 and a light shielding portion 22. In actual production, the pattern of the data line 21 and the pattern of the light shielding portion 22 can be prepared using the same material as the first metal layer 20, thereby obtaining the desired data line 21 and light shielding portion 22. In this way, the film structure is simplified to a certain extent. Moreover, the transmission of data signals and effective shielding of the channel of the active layer 30 can be achieved simultaneously, thereby improving the performance of the display substrate. In addition, the second metal layer 40, located on the side of the active layer 30 facing away from the substrate 10, includes a first electrode 41, a second electrode 42, and a gate line 43 in the display area A. In actual production, the pattern of the first electrode 41, the second electrode 42, and the gate line 43 can be prepared using the same material as the second metal layer 40, thereby obtaining the desired source and drain electrodes, gate line 43, and even gate 430. In this way, the film structure is further simplified, and the function of driving the source and drain electrodes and gate 430 can be achieved simultaneously, ensuring the performance of the display substrate. In addition, the number of masks used in the actual preparation process can be reduced to a certain extent, simplifying the production process.

[0090] In the disclosed embodiment, the distance between the data line 21 and the common electrode layer 90 is significantly greater than the distance between the data line 21 and the common electrode in the related art, thereby reducing the capacitive coupling between the two and lowering the risk of crosstalk and flicker (FLK).

[0091] In the embodiment of the present disclosure, still referring to FIG4 , the display substrate further includes:

[0092] a first insulating layer 60 , located between the first metal layer 20 and the active layer 30 ;

[0093] a second insulating layer 70 , located between the active layer 30 and the second metal layer 40 ;

[0094] The first via hole H1 also penetrates the first insulating layer 60 and the second insulating layer 70 , and the second electrode 42 is electrically connected to the second portion 32 via a second via hole H2 that penetrates the second insulating layer 70 ;

[0095] The first via hole H1 and the second via hole H2 are located on the same side of the gate line 43 , and the third portion 33 is located on the other side of the gate line 43 .

[0096] In a specific implementation, the display substrate further includes a first insulating layer 60 and a second insulating layer 70, wherein the first insulating layer 60 is located between the first metal layer 20 and the active layer 30, and the second insulating layer 70 is located between the active layer 30 and the second metal layer 40. Exemplarily, the first insulating layer 60 is a buffer layer, and the material used can be at least one of silicon nitride and silicon oxide. In practical applications, silicon nitride has good density and can prevent metal ions in the substrate 10 from diffusing into the active layer 30 during thermal processes. Moreover, silicon oxide has strong step coverage, good electrical insulation, and good thermal insulation properties. During the excimer laser annealing (ELA) crystallization process, it can effectively slow the cooling rate of a-Si, increase the grain size, and ultimately form the pattern of the active layer 30. Exemplarily, the second insulating layer 70 is a gate insulating layer, and the material used can be at least one of silicon nitride and silicon oxide. In practical applications, silicon oxide and polysilicon have an interface that is well-matched (low interface defect density), stress-matched, and has good step coverage. Silicon nitride is a high-k material with high bias stability and breakdown characteristics, effectively blocking the diffusion of metal particles in the second metal layer 40, such as a-Si Cu particles, and exhibits self-hydrogenation repair capabilities. In practical applications, the second insulating layer 70 needs to have holes drilled to the light shielding portion 22 and the active layer 30. This allows for subsequent bridging of the light shielding portion 22 and the active layer 30 through the second metal layer 40, as well as for connections between the active layer 30 and the first electrode 41 and the second electrode 42.

[0097] Furthermore, the first via hole H1 of the first electrode 41 that penetrates the first portion 31 also penetrates the first insulating layer 60 and the second insulating layer 70. When actually creating the first via hole H1, the first insulating layer 60 and the second insulating layer 70 can share a single mask, thereby reducing the number of masks used and simplifying the process. Furthermore, the second electrode 42 is electrically connected to the second portion 32 via a second via hole H2 that penetrates the second insulating layer 70. The second electrode 42 can be directly electrically connected to the second portion 32 via the second via hole H2, thereby simplifying the film structure to a certain extent. Furthermore, the first and second via holes H1, H2 are located on the same side of the gate line 43, while the third portion 33 is located on the other side of the gate line 43. In the exemplary embodiment shown in FIG3 , the first and second via holes H1, H2 are both located above the same gate line 43, while the third portion 33 is located below the gate line 43. This further ensures that the gate line 43 overlaps the active layer 30, forming the desired gate electrode 430 and improving the performance of the display substrate.

[0098] In the embodiment of the present disclosure, a first distance exists between the first via hole H1 and the gate line 43 , and a second distance exists between the second via hole H2 and the gate line 43 . The first distance is not equal to the second distance.

[0099] During the specific implementation process, FIG5 is an enlarged schematic diagram of one of the structures in a local area of ​​the display substrate. Here, d1 represents the first distance between the first via H1 and the gate line 43, and d2 represents the second distance between the second via H2 and the gate line 43; d1>d2. The distance between the corresponding via and the gate line 43 is the minimum distance between the edge of the corresponding via close to the gate line 43 and the gate line 43. In this way, to a certain extent, the aperture ratio of the display substrate is improved and the transmittance is guaranteed. Of course, the specific values ​​of the first distance and the second distance can be set according to the actual application needs and are not limited here.

[0100] In one exemplary embodiment, still referring to FIG4 , the display substrate further includes:

[0101] a third insulating layer 80 , located between the second metal layer 40 and the pixel electrode layer 50 ;

[0102] a common electrode layer 90 , located between the third insulating layer 80 and the pixel electrode layer 50 ;

[0103] a fourth insulating layer 91 , located between the common electrode layer 90 and the pixel electrode layer 50 ;

[0104] The third insulating layer 80 and the common electrode layer 90 have a third via hole H3, the fourth insulating layer 91 has a fourth via hole H4, the fourth via hole H4 is nested in the third via hole H3, and the pixel electrode is connected to the second electrode 42 through the fourth via hole H4 and the third via hole H3.

[0105] During the specific implementation process, the display substrate also includes a third insulating layer 80, a common electrode layer 90, and a fourth insulating layer 91; wherein the third insulating layer 80 is located between the second metal layer 40 and the pixel electrode layer 50. Exemplarily, the third insulating layer 80 is an interlayer insulating layer, and the material used can be at least one of silicon nitride and silicon oxide. The third insulating layer 80 can effectively isolate the common electrode layer 90 from the second metal layer 40, preventing the second metal layer 40 from directly short-circuiting with the common electrode layer 90. At the same time, it can also supplement the hydrogen bonds in the P-Si layer 30, reduce the dangling bonds, reduce the instability of the P-Si layer, and reduce the contact resistance between the first electrode 41, the second electrode 42, and the P-Si layer. In practical applications, the third insulating layer 80 does not need to undergo a separate mask plate and hole opening process. It can share a mask plate with the subsequent fourth insulating layer 91 to open holes and overlap the active layer 30. The fourth insulating layer 91 is located between the common electrode layer 90 and the pixel electrode layer 50. Exemplarily, the fourth insulating layer 91 is a passivation layer, typically made of a material with a high dielectric constant, such as silicon nitride, thereby increasing the pixel capacitance. Thus, the fourth insulating layer 91 effectively prevents short circuits between the common electrode layer 90 and the pixel electrode layer 50. In practical applications, it is necessary to simultaneously open holes in the passivation layer up to the active layer 30 to supply power to the pixel electrode 51 through the active layer 30.

[0106] Furthermore, the third insulating layer 80 and the common electrode layer 90 have a third via hole H3, and the fourth insulating layer 91 has a fourth via hole H4. The fourth via hole H4 is nested within the third via hole H3, and the pixel electrode 51 is connected to the second electrode 42 via the fourth via hole H4 and the third via hole H3. Accordingly, the orthographic projection of the fourth via hole H4 on the substrate 10 completely falls within the area of ​​the orthographic projection of the third via hole H3 on the substrate 10. In practical applications, the fourth insulating layer 91 can extend into the third via hole H3 and terminate at the second electrode 42, thereby effectively isolating the pixel electrode 51 from the common electrode layer 90, thereby ensuring the performance of the display substrate.

[0107] In a specific implementation, the common electrode layer 90 may be made of a transparent electrode material, such as indium tin oxide. The common electrode layer 90 and the pixel electrode 51 may form an electric field to drive the liquid crystal to deflect.

[0108] In one exemplary embodiment, FIG6 is another schematic cross-sectional view of the structure along the direction NN in FIG3. Specifically, the orthographic projection of the third via hole H3 on the substrate 10 is staggered with the orthographic projection of the second via hole H2 on the substrate 10.

[0109] During specific implementation, the center of the third via H3 can be staggered relative to the center of the second via H2. For example, the overlap position of the third via H3 and the second via H2 in a direction parallel to the gate line 43 is less than or equal to 1.5 μm, and the overlap position of the third via H3 and the second via H2 in a direction parallel to the data line 21 is less than or equal to 1.5 μm. Of course, the specific distance between the third via H3 and the second via H2 can also be set according to actual application needs, which is not limited here. By staggering the third via H3 and the second via H2, the occurrence of stains and small black spots can be effectively avoided, thereby improving the performance of the display substrate.

[0110] It should be noted that in the exemplary embodiments shown in Figures 4 and 6, since the materials used for the third insulating layer 80 and the fourth insulating layer 91 are generally inorganic insulating materials, in the actual preparation process, the third insulating layer 80 and the fourth insulating layer 91 can share the same mask plate for opening holes. In this way, the mask plate process required for the entire manufacturing process is as follows: the pattern of the first metal layer 20 requires a mask plate, the pattern of the active layer 30 requires a mask plate, the first insulating layer 60 and the second insulating layer 70 share the same mask plate, the pattern of the second metal layer 40 requires a mask plate, the pattern of the common electrode layer 90 requires a mask plate, the third insulating layer 80 and the fourth insulating layer 91 share a mask plate, and the pattern of the pixel electrode layer 50 requires a mask plate. In this way, the entire manufacturing process requires 7 mask plate processes to obtain a display substrate with the desired film layer structure. In this way, compared with the 9-mask plate process, not only the film layer structure is simplified, but also the process is simplified.

[0111] In one exemplary embodiment, referring to FIG7 and FIG8 , FIG7 is another schematic cross-sectional view along the direction NN in FIG3 , and FIG8 is an enlarged schematic view of one structure along the area Q in FIG3 . Specifically, the display substrate further includes:

[0112] a planar layer 92 , located between the third insulating layer 80 and the common electrode layer 90 ;

[0113] The third via hole H3 also penetrates the planar layer 92 .

[0114] In the exemplary embodiment shown in FIG7 , the display substrate further includes a planar layer 92 located between the third insulating layer 80 and the common electrode layer 90. Exemplarily, the material of the planar layer 92 can be an organic material, such as a resin material, which is not limited here. In this way, the flatness of the film structure is improved. Moreover, in this exemplary embodiment, the third via H3 also penetrates the planar layer 92. In actual applications, since the material used for the planar layer 92 is generally an organic material, and the materials used for the third insulating layer 80 and the fourth insulating layer 91 are generally inorganic insulating materials, accordingly, the planar layer 92 can use a separate mask plate, and the third insulating layer 80 and the fourth insulating layer 91 can share the same mask plate for corresponding openings. In this case, the mask process required for the entire manufacturing process is as follows: the pattern of the first metal layer 20 requires a mask, the pattern of the active layer 30 requires a mask, the first insulating layer 60 and the second insulating layer 70 share the same mask, the pattern of the second metal layer 40 requires a mask, the pattern of the planar layer 92 requires a mask, the pattern of the common electrode layer 90 requires a mask, the third insulating layer 80 and the fourth insulating layer 91 share a mask, and the pattern of the pixel electrode layer 50 requires a mask. In this case, the entire manufacturing process requires eight mask processes to obtain a display substrate with the desired film layer structure. In this way, compared with the nine-mask process, not only the film layer structure is simplified, but also the process is simplified.

[0115] It should be noted that compared with the exemplary embodiment shown in FIG6 , the exemplary embodiment shown in FIG7 further reduces the coupling capacitance between the first electrode 41 and the common electrode layer 90 through the flat layer 92 while taking into account the flatness of the film layer, thereby improving the performance of the display substrate.

[0116] In the embodiment of the present disclosure, the data line 21 has a widened portion 211 , and the orthographic projection of the widened portion 211 on the substrate 10 covers the first portion 31 .

[0117] Still referring to the exemplary embodiments shown in FIG. 3 and FIG. 8 , the data line 21 has a widened portion 211 , the orthographic projection of the widened portion 211 on the substrate 10 covers the first portion 31 , thereby effectively shielding the channel of the active layer 30 , avoiding the generation of leakage current, and improving the performance of the display substrate.

[0118] In the embodiment of the present disclosure, the first portion 31 and the second portion 32 both extend along the data line 21 and have the same width along the gate line 43 . The widened portion 211 and the light shielding portion 22 have the same width along the gate line 43 .

[0119] Still referring to the exemplary embodiments shown in Figures 3 and 8, the first portion 31 and the second portion 32 both extend along the direction of the data line 21 and have the same width along the direction of the gate line 43. For example, the width of the first portion 31 along the direction of the gate line 43 is e1, and the width of the second portion 32 along the direction of the gate line 43 is e2. In actual applications, e1 and e2 are equal. The equality mentioned here can be approximately equal or approximately equal, and is not limited here. Moreover, the width of the widened portion 211 and the light shielding portion 22 along the direction of the gate line 43 are the same. For example, the width of the widened portion 211 along the direction of the gate line 43 is f1, and the width of the light shielding portion 22 along the direction of the gate line 43 is f2. In actual applications, f1 and f2 are equal. The equality mentioned here can be approximately equal or approximately equal, and is not limited here. Of course, the specific values ​​of each width can be set according to actual application needs and are not limited here.

[0120] In the embodiment of the present disclosure, the orthographic projections of the widened portion 211 and the light shielding portion 22 on the substrate 10 do not overlap with the third portion 33 .

[0121] Still referring to the exemplary embodiments shown in Figures 3 and 8, the widened portion 211 and the light shielding portion 22 are both extended along the direction of the data line 21 and terminate at the location of the third portion 33. In this way, the widened portion 211 and the light shielding portion 22 can effectively shield the gate electrode 430 at the intersection of the active layer 30 and the gate line 43, and shield the relevant channels of the active layer 30, thereby effectively preventing the generation of leakage current.

[0122] In the embodiment of the present disclosure, still referring to Figures 3 and 8 , the orthographic projection of the first via H1 on the substrate 10 completely falls within the orthographic projection area of ​​the widened portion 211 on the substrate 10. Thus, the widened portion 211 effectively shields the first electrode 41, thereby improving the performance of the display substrate.

[0123] In the embodiment of the present disclosure, as still shown in FIG3 and FIG8 , a widening member 310 is provided at the end of the first portion 31 away from the third portion 33, and the orthographic projection of the first via H1 on the substrate 10 falls within the range of the widening member 310. This ensures effective electrical connection of the subsequent first electrode 41.

[0124] In the embodiment of the present disclosure, the line width center line of the first portion 31 and the line width center line of the data line 21 are staggered.

[0125] Continuing with the exemplary embodiment shown in FIG8 , dashed line a represents the line width centerline of the first portion 31, dashed line b represents the line width centerline of the data line 21, and d represents the distance between them. For example, as shown in FIG8 , the line width centerline of the first portion 31 is offset to the left of the line width centerline of the data line 21. This ensures the exposure resolution of the first portion 31 and the data line 21. For another example, the line width centerline of the first portion 31 may be offset to the right of the line width centerline of the data line 21, which is not illustrated in the relevant drawings.

[0126] In the embodiment of the present disclosure, the pixel electrode 51 includes a plurality of strip electrodes 510 extending substantially along the direction of the data line 21 . The plurality of strip electrodes 510 are connected at one end by a first edge electrode 511 , and at the other end by a second edge electrode 512 .

[0127] The pixel electrode 51 further includes a connecting electrode 513 disposed at one end of the first edge electrode 511 . The connecting electrode 513 is electrically connected to the second electrode 42 . The other end of the first edge electrode 511 has a concave structure 514 that avoids the widened portion 211 .

[0128] As shown in Figures 9 to 11, Figure 9 is an enlarged schematic diagram of one structure of a local area in the display substrate, Figure 10 is an enlarged schematic diagram of one structure of area P in Figure 9, and Figure 11 is another enlarged schematic diagram of the structure of area P in Figure 9. In a specific implementation, the pixel electrode 51 includes a plurality of strip electrodes 510 extending generally along the direction of the data line 21. The number of the plurality of strip electrodes 510 can be set according to actual application needs and is not limited here. The plurality of strip electrodes 510 are connected at one end by a first edge electrode 511 and at the other end by a second edge electrode 512. For example, the first edge electrode 511 and the second edge electrode 512 extend generally along the direction of the gate line 43. In actual application, a slit structure is provided between two adjacent strip electrodes 510. In this way, when an electrical signal is subsequently applied through the pixel electrode 51 and the common electrode layer 90, light transmittance is maintained while effectively driving the liquid crystal molecules, thereby improving the performance of the display substrate.

[0129] Furthermore, the pixel electrode 51 also includes a connecting electrode 513 disposed at one end of the first edge electrode 511. This connecting electrode 513 is electrically connected to the second electrode 42. This allows the active layer 30 to supply power to the pixel electrode 51 via the second electrode 42 and the connecting electrode 513. Furthermore, the other end of the first edge electrode 511 includes a concave structure 514 that avoids the widened portion 211. In practice, the liquid crystal at the end of the strip electrode 510 is disordered and its local orientation suddenly changes, causing it to deflect in the opposite direction, forming a stable state where the liquid crystal accumulates. In practice, if the end region of the strip electrode 510 is not designed with a corner, the recovered liquid crystals will have difficulty loosening their rotation and freeing up space, allowing other unrecovered liquid crystals to recover, resulting in uneven display. In the disclosed embodiment, by providing a concave structure 514 with a widened portion 211 at the other end of the first edge electrode 511, the electric field torque of the concave structure 514 allows the liquid crystals to recover, resulting in a smaller rotation angle and freeing up space for recovery. This improves display unevenness.

[0130] It should be noted that in actual applications, still referring to Figure 11 , the distance between the first electrode 41 and the second electrode 42 along the direction parallel to the gate line 43 is h1; along the direction parallel to the data line 21, the distance between the second electrode 42 and the adjacent gate line 43 is h2. In actual manufacturing, h1 can be set to be greater than or equal to 3.0 μm, and h2 can also be set to be greater than or equal to 3.0 μm, thereby ensuring the exposure resolution capability of the exposure equipment and improving the performance of the display substrate. Of course, the specific values ​​of h1 and h2 can be set according to actual application needs and are not limited here.

[0131] In the embodiment of the present disclosure, still referring to FIG. 9 to FIG. 11 , the orthographic projection of the second edge electrode 512 on the substrate 10 has an overlapping area with the adjacent gate line 43 .

[0132] In the embodiment of the present disclosure, the common electrode layer 90 has a hollow pattern 93 on a portion of the data line 21 except the widened portion 211 .

[0133] In the specific implementation process, in combination with Figures 12 and 13, Figure 12 is a schematic diagram of a top view of a local structure of the common electrode layer 90, and Figure 13 is a schematic diagram of a top view of a local structure between the common electrode layer 90 and the data line 21 shown in Figure 12; the common electrode layer 90 has a hollow pattern 93 on the portion of the data line 21 except the widened portion 211. In actual applications, the common electrode layer 90 is usually a full-surface layered structure. In addition to the third via H3 provided at the corresponding position electrically connected to the pixel electrode 51, the portion of the data line 21 except the widened portion 211 has a hollow pattern 93. Exemplarily, as shown in Figure 13, the portion of the data line 21 corresponding to each adjacent two pixel electrodes 51 except the widened portion 211 is provided with a groove, thereby having a corresponding hollow pattern 93.

[0134] In the embodiment of the present disclosure, the peripheral area B has a GOA area C located on one side or both sides of the display area A;

[0135] The first metal layer 20 includes a first signal line 201 and a second signal line 202 in the GOA region C, and the second metal layer 40 includes a third signal line 400, a first electrode 401 and a second electrode 402 in the GOA region C;

[0136] The first electrode 401 is electrically connected to the first signal line 201 through a via hole penetrating the active layer 30 , and the second electrode 402 is electrically connected to the second signal line 202 through a via hole penetrating the active layer 30 .

[0137] It should be noted that the GOA area is an area where gate driver on array (GOA) technology is used for related configurations. In practical applications, GOA technology can be used to integrate the drive control circuit on the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the gate driver integrated circuit portion, thereby reducing product costs in terms of both material costs and manufacturing process. The drive control circuit is typically composed of multiple cascaded shift register units. The specific structure of the shift register unit can be implemented with reference to relevant technologies and is not limited here.

[0138] In one exemplary embodiment, FIG14 shows a schematic top view of a display substrate. In this exemplary embodiment, peripheral region B includes GOA regions C located on both sides of display region A. Liquid crystal drive control is achieved through the related circuits and wiring arranged in GOA regions C. FIG15 shows a schematic top view of a portion of the conductive film layer in region O in FIG14 , and FIG16 shows a schematic cross-sectional view along the direction indicated by line TT in FIG15 . Specifically, the first metal layer 20 includes a first signal line 201 and a second signal line 202 in GOA region C, and the second metal layer 40 includes a third signal line 400, a first electrode 401, and a second electrode 402 in GOA region C. Furthermore, the first electrode 401 is electrically connected to the first signal line 201 via a via extending through the active layer 30, and the second electrode 402 is electrically connected to the second signal line 202 via a via extending through the active layer 30.

[0139] The present inventors discovered through actual research that FIG17 shows a partial top view of the substrate at a location corresponding to GOA region C in FIG1 , and FIG18 shows a cross-sectional view of one of the locations along the direction indicated by UU in FIG17 . In the disclosed embodiment, the exemplary embodiment shown in FIG16 simplifies the film structure while maintaining the relevant functions of GOA region C, compared to FIG18 .

[0140] In the embodiment of the present disclosure, the peripheral area B has a fan-out area D located on one side of the display area A;

[0141] The data line 21 extends to the fan-out region D and is connected to the second metal layer 40 in the fan-out region D.

[0142] In one exemplary embodiment, FIG19 shows a schematic top view of a display substrate. In this exemplary embodiment, the fan-out region D is located below the display region A. FIG20 shows a schematic top view of region S in FIG19 , and FIG21 shows a schematic cross-sectional view taken along the direction indicated by VV in FIG20 . Specifically, the data line 21 extends to the fan-out region D and, in this region, connects to the second metal layer 40 via a second via H2 penetrating the second insulating layer 70. This ensures the display substrate's performance in transmitting data signals.

[0143] The inventors discovered through actual research that, as shown in Figure 22, which is a partial top view of the display substrate at a location corresponding to the fan-out region D in Figure 1, and Figure 23, which is a schematic cross-sectional view of one of the structures along the direction indicated by WW in Figure 22, in the disclosed embodiment, the exemplary embodiment shown in Figure 21 reduces the coupling capacitance between the data line 21 and the common electrode layer 90 compared to that shown in Figure 23.

[0144] It should be noted that, in the embodiment of the present disclosure, the display substrate includes other film layer structures in addition to the film layer structure mentioned above, which is not limited here. For example, the material of the first metal layer 20 is titanium aluminum titanium, and the material of the second metal layer 40 includes at least one of molybdenum and molybdenum aluminum molybdenum. In practical applications, the active layer 30 can be bridged with the data line 21 through a high-conductivity second metal layer 40 (for example, molybdenum), thereby reducing the contact resistance of the channel; the pixel electrode 51 and the active layer 30 can also be connected through a high-conductivity second metal layer 40 (for example, molybdenum), thereby reducing the contact resistance of the pixel electrode 51. In this way, the display uniformity of the display substrate is guaranteed.

[0145] Based on the same disclosed concept, as shown in FIG24 , an embodiment of the present disclosure further provides a display device, which includes:

[0146] The display substrate 100 as described in any one of the above items, the opposite substrate 200 disposed opposite to the display substrate 100 , and the liquid crystal layer 300 disposed between the display substrate 100 and the opposite substrate 200 .

[0147] In the specific implementation process, since the principle of solving the problem of the display device is similar to that of the aforementioned display substrate, the implementation of the display device can refer to the implementation of the aforementioned display substrate, and the repeated parts will not be repeated.

[0148] In specific implementations, the display device provided by the embodiments of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not described in detail here, nor should they be construed as limitations of the present invention.

[0149] In the disclosed embodiment, still referring to FIG9 , the opposing substrate 200 includes a plurality of filter sections 210 and a shielding section 220 surrounding each filter section 210. The orthographic projections of the shielding sections on the substrate completely fall within the orthographic projections of the shielding sections 220 on the substrate. The specific number of filter sections 210 can be set based on actual application needs and is not limited here. Of course, in addition to the aforementioned structures, the display device may also include other structures based on actual application needs, which are not limited here.

[0150] Based on the same disclosed concept, as shown in FIG25 , an embodiment of the present disclosure further provides a method for manufacturing a display substrate, wherein the display substrate is divided into a display area and a peripheral area surrounding the display area; the manufacturing method includes:

[0151] S101: forming a first metal layer on one side of a substrate, wherein the first metal layer includes a data line and a light shielding portion in the display area;

[0152] S102: forming an active layer on a side of the first metal layer facing away from the substrate, wherein the active layer includes a first portion, a second portion, and a third portion in the display area, the third portion connecting the first portion and the second portion, an orthographic projection of the first portion on the substrate falling within a range where the data line is located, and an orthographic projection of the second portion on the substrate falling within a range where the light shielding portion is located;

[0153] S103: forming a second metal layer on a side of the active layer facing away from the substrate, wherein the second metal layer includes a first electrode, a second electrode, and a gate line in the display area, wherein the first electrode is electrically connected to the data line via a first via hole penetrating the first portion, the second electrode is electrically connected to the second portion, and an overlapping area between an orthographic projection of the gate line on the substrate and the first portion and an overlapping area between the orthographic projection of the gate line on the substrate and the second portion constitute a gate;

[0154] S104: forming a pixel electrode layer on a side of the second metal layer facing away from the substrate, wherein the pixel electrode layer comprises a pixel electrode in the display area, and the pixel electrode is electrically connected to the second electrode.

[0155] The details and beneficial effects of each step of the manufacturing method provided by the embodiment of the present disclosure have been described in the relevant part of the aforementioned display substrate and will not be described in detail here.

[0156] The embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, wherein the display substrate is divided into a display area and a peripheral area surrounding the display area; the display substrate comprises: a base, a first metal layer located on one side of the base, an active layer located on the side of the first metal layer facing away from the base, a second metal layer located on the side of the active layer facing away from the base, and a pixel electrode layer located on the side of the second metal layer facing away from the base; the first metal layer comprises a data line and a light shielding portion in the display area; wherein the data line is used to transmit the data signal required by the display substrate, and the light shielding portion is used to shield the backlight from the channel, thereby avoiding the generation of leakage current. The active layer comprises a first part, a second part, and a third part in the display area, the third part connects the first part and the second part, the orthographic projection of the first part on the base falls within the range of the data line, and the orthographic projection of the second part on the base falls within the range of the light shielding portion; in this way, the channel of the active layer is effectively shielded by the first metal layer, thereby avoiding the generation of leakage current and improving the electrical anomalies of the product;

[0157] Moreover, the second metal layer includes a first electrode, a second electrode and a gate line in the display area, the first electrode is electrically connected to the data line through a first via hole penetrating the first part, and the second electrode is electrically connected to the second part; the overlapping area of ​​the orthographic projection of the gate line on the substrate and the first part, and the overlapping area of ​​the orthographic projection of the gate line on the substrate and the second part constitute a gate; in practical applications, the gate can be used as a switch of the MOS tube (or TFT tube), and a voltage is applied to the gate to open the conduction channel of the corresponding switch to form a complete path. In this way, the switch control function of the channel is realized. In addition, the pixel electrode layer includes a pixel electrode in the display area, and the pixel electrode is electrically connected to the second electrode, thereby ensuring the driving capability of the display substrate.

[0158] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0159] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display substrate, wherein: The display substrate is divided into a display area and a peripheral area surrounding the display area; the display substrate comprises: substrate; A first metal layer, located on one side of the substrate, wherein the first metal layer comprises a data line and a light shielding portion in the display area; an active layer, located on a side of the first metal layer away from the substrate, the active layer comprising a first portion, a second portion and a third portion in the display area, the third portion connecting the first portion and the second portion, an orthographic projection of the first portion on the substrate falling within a range where the data line is located, and an orthographic projection of the second portion on the substrate falling within a range where the light shielding portion is located; a second metal layer, located at a side of the active layer away from the substrate, the second metal layer comprising a first electrode, a second electrode and a gate line in the display area, the first electrode being electrically connected to the data line through a first via hole penetrating the first portion, the second electrode being electrically connected to the second portion, and an overlapped area of ​​an orthographic projection of the gate line on the substrate and the first portion, and an overlapped area of ​​an orthographic projection of the gate line on the substrate and the second portion forming a gate; The pixel electrode layer is located on a side of the second metal layer away from the substrate. The pixel electrode layer comprises a pixel electrode in the display area. The pixel electrode is electrically connected to the second electrode.

2. The display substrate according to claim 1, wherein: Also includes: a first insulating layer, located between the first metal layer and the active layer; a second insulating layer, located between the active layer and the second metal layer; Wherein, the first via hole also penetrates the first insulating layer and the second insulating layer at the same time, and the second electrode is electrically connected to the second portion through the second via hole penetrating the second insulating layer; The first via hole and the second via hole are located on the same side of the gate line, and the third portion is located on the other side of the gate line.

3. The display substrate according to claim 2, wherein: There is a first distance between the first via hole and the gate line, and there is a second distance between the second via hole and the gate line, and the first distance is not equal to the second distance.

4. The display substrate according to claim 3, wherein: Also includes: a third insulating layer, located between the second metal layer and the pixel electrode layer; A common electrode layer, located between the third insulating layer and the pixel electrode layer; a fourth insulating layer, located between the common electrode layer and the pixel electrode layer; The third insulating layer and the common electrode layer have a third via hole, the fourth insulating layer has a fourth via hole, the fourth via hole is sleeved in the third via hole, and the pixel electrode is connected to the second electrode through the fourth via hole and the third via hole.

5. The display substrate according to claim 4, wherein: The orthographic projection of the third via hole on the substrate is staggered with the orthographic projection of the second via hole on the substrate.

6. The display substrate according to claim 5, wherein: Also includes: a planar layer, located between the third insulating layer and the common electrode layer; The third via hole also penetrates the planar layer.

7. The display substrate according to any one of claims 1 to 6, wherein: The data line has a widened portion, and an orthographic projection of the widened portion on the substrate covers the first portion.

8. The display substrate according to claim 7, wherein: The first portion and the second portion both extend along the data line direction and have the same width along the gate line direction. The widened portion and the light shielding portion have the same width along the gate line direction.

9. The display substrate according to claim 8, wherein: The orthographic projections of the widened portion and the light shielding portion on the substrate do not overlap with the third portion.

10. The display substrate according to claim 9, wherein: The orthographic projection of the first via hole on the substrate completely falls within the region of the orthographic projection of the widened portion on the substrate.

11. The display substrate according to claim 10, wherein: A widening member is disposed at the end of the first portion away from the third portion, and the orthographic projection of the first via on the substrate falls within the range of the widening member.

12. The display substrate according to claim 11, wherein: The line width center line of the first part and the line width center line of the data line are staggered.

13. The display substrate according to any one of claims 1 to 12, wherein: The pixel electrode comprises a plurality of strip electrodes extending substantially along the direction of the data line, the plurality of strip electrodes being connected at one end by a first edge electrode, and the plurality of strip electrodes being connected at the other end by a second edge electrode; The pixel electrode further includes a connecting electrode disposed at one end of the first edge electrode, the connecting electrode being electrically connected to the second electrode, and the other end of the first edge electrode having a concave structure to avoid the widened portion.

14. The display substrate according to claim 13, wherein: The orthographic projection of the second edge electrode on the substrate has an overlapping area with an adjacent gate line.

15. The display substrate according to claim 4, wherein: The common electrode layer has a hollow pattern at a portion of the data line except the widened portion.

16. The display substrate according to any one of claims 1 to 15, wherein: The peripheral area has a GOA area located on one side or both sides of the display area; The first metal layer includes a first signal line and a second signal line in the GOA region, and the second metal layer includes a third signal line, a first electrode and a second electrode in the GOA region; The first electrode is electrically connected to the first signal line through a via hole penetrating the active layer, and the second electrode is electrically connected to the second signal line through a via hole penetrating the active layer.

17. The display substrate according to claim 16, wherein: The peripheral area has a fan-out area located on one side of the display area; The data line extends to the fan-out region and is connected to the second metal layer in the fan-out region.

18. A display device, wherein: include: A display substrate as described in any one of claims 1 to 17, a counter substrate arranged opposite to the display substrate, and a liquid crystal layer arranged between the display substrate and the counter substrate.

19. The display device according to claim 18, wherein: The opposite substrate comprises a plurality of filter portions and a shielding portion surrounding each of the filter portions, and the orthographic projection of the shielding portion on the substrate completely falls within the region of the orthographic projection of the shielding portion on the substrate.

20. A method for manufacturing a display substrate, wherein: The display substrate is divided into a display area and a peripheral area surrounding the display area; the manufacturing method includes: Forming a first metal layer on one side of the substrate, wherein the first metal layer includes a data line and a light shielding portion in the display area; An active layer is formed on a side of the first metal layer away from the substrate, wherein the active layer includes a first portion, a second portion and a third portion in the display area, the third portion connects the first portion and the second portion, an orthographic projection of the first portion on the substrate falls within a range where the data line is located, and an orthographic projection of the second portion on the substrate falls within a range where the light shielding portion is located; A second metal layer is formed on a side of the active layer away from the substrate, the second metal layer comprises a first electrode, a second electrode and a gate line in the display area, the first electrode is electrically connected to the data line through a first via hole penetrating the first portion, the second electrode is electrically connected to the second portion, and an overlapped area of ​​an orthographic projection of the gate line on the substrate and the first portion, and an overlapped area of ​​an orthographic projection of the gate line on the substrate and the second portion constitute a gate; A pixel electrode layer is formed on a side of the second metal layer away from the substrate. The pixel electrode layer includes a pixel electrode in the display area. The pixel electrode is electrically connected to the second electrode.

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