Managing vertical structures in three-dimensional semiconductor devices

Abstract

Systems, devices, and methods for managing vertical structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes two adjacent memory cells (207a, 207b) and a conductive structure (208) between the two adjacent memory cells. Each of the two adjacent memory cells includes a transistor (209a, 209b) having a semiconductor body (201a, 201b), a first terminal (202a, 202b), a second terminal (203a, 203b), and a gate terminal (212a, 212b). The conductive structure is in contact with at least one of the semiconductor bodies of the transistors of the two adjacent memory cells, and the conductive structure is spaced apart from the first terminal and the second terminal of each of the transistors of the two adjacent memory cells.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Art

[0002] Semiconductor devices, such as memory devices, can have various structures to increase the density of memory cells and wires on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuits for facilitating operation of the memory array. The memory cells can include vertical structures, e.g., vertical transistors. Summary of the Invention

[0003] The present disclosure describes methods, apparatuses, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure features a semiconductor device including: two adjacent memory cells, where each of the two adjacent memory cells includes a transistor having a semiconductor body, a first terminal, a second terminal, and a gate terminal; and a conductive structure between the transistors of the two adjacent memory cells, the conductive structure being in contact with at least one of the semiconductor bodies of the transistors of the two adjacent memory cells. The conductive structure is spaced apart from the first terminal and the second terminal of each of the transistors of the two adjacent memory cells.

[0005] In some embodiments, the work function of the conductive structure is higher than the work function of the semiconductor body in contact with the conductive structure.

[0006] In some embodiments, the conductive structure is configured such that a Schottky barrier is formed at an interface between the conductive structure and the semiconductor body in contact with the conductive structure.

[0007] In some embodiments, the conductive structure is coupled to a fixed voltage.

[0008] In some embodiments, the conductive structure is coupled to a fixed voltage such that, in operation, a current path is formed from the semiconductor body to the conductive structure.

[0009] In some embodiments, the fixed voltage is a negative voltage.

[0010] In some embodiments, the fixed voltage is associated with a threshold voltage of at least one of the two adjacent memory cells.

[0011] In some embodiments, the conductive structure includes one or more conductive layers, and the one or more conductive layers include at least one of a metal layer, a polysilicon layer, a germanium-silicon (GeSi) layer, or a barrier layer.

[0012] In some embodiments, the conductive structure contacts each of the semiconductor bodies of the transistors of the two adjacent memory cells.

[0013] In some embodiments, the semiconductor body includes opposite ends along a first direction and opposite sides along a second direction orthogonal to the first direction. The first terminal and the second terminal are respectively at the opposite ends of the semiconductor body along the first direction. The gate terminal and the conductive structure are respectively at two opposite sides of the semiconductor body.

[0014] In some embodiments, the conductive structure contacts at least one of the following: a first portion of the semiconductor body that is closer to the first terminal than to the second terminal; a second portion of the semiconductor body that is closer to the second terminal than to the first terminal; an intermediate portion of the semiconductor body that is between the first portion and the second portion; or the first portion, the second portion, and the intermediate portion of the semiconductor body.

[0015] In some embodiments, the conductive structure has a first portion along the first direction and a second portion that intersects the first portion along the second direction. The second portion of the conductive structure contacts each of the semiconductor bodies of the transistors of the two adjacent memory cells.

[0016] In some embodiments, the first portion of the conductive structure extends along the first direction and is spaced apart from the first terminal and the second terminal of the transistor along the second direction.

[0017] In some embodiments, the conductive structure includes conductive bars spaced apart along the first direction, and each of the conductive bars contacts at least one of the semiconductor bodies along the second direction.

[0018] In some embodiments, the conductive structure includes two conductors spaced apart from each other along the second direction, and each of the two conductors contacts a corresponding one of the semiconductor bodies of the transistors of the two adjacent memory cells.

[0019] In some embodiments, the two conductors are coupled together to the same voltage source.

[0020] In some embodiments, the conductive structure includes an oval shape having an edge that contacts at least one of the semiconductor bodies along the second direction.

[0021] In some embodiments, the semiconductor device further includes: two word lines spaced apart along the second direction, wherein each of the two word lines is coupled to a corresponding one of the two adjacent memory cells, and each word line extends in a third direction orthogonal to the first direction and the second direction; and two rows of memory cells, and each row of memory cells extends along the third direction and is coupled to a corresponding one of the two word lines.

[0022] In some embodiments, the conductive structure extends along the third direction and has opposite sides along the second direction. The two rows of memory cells are respectively coupled to the opposite sides of the conductive structure.

[0023] In some embodiments, the conductive structure includes: a first portion extending along the third direction and coupled to the semiconductor bodies of the two rows of memory cells along the second direction; and one or more second portions extending along the second direction, and each of the one or more second portions is between adjacent semiconductor bodies along the third direction.

[0024] In some embodiments, the conductive structure includes a first conductor and a second conductor spaced apart from each other along the second direction. The first conductor is coupled to the first row of memory cells of the two rows of memory cells, and the second conductor is coupled to the second row of memory cells of the two rows of memory cells.

[0025] In some embodiments, the first conductor includes: a first portion extending along the third direction and coupled to the semiconductor body of the first row of memory cells of the two rows of memory cells along the second direction; and one or more second portions extending along the second direction, and each of the one or more second portions is between adjacent semiconductor bodies along the third direction. The second conductor includes: a third portion extending along the third direction and coupled to the semiconductor body of the second row of memory cells of the two rows of memory cells along the second direction; and one or more fourth portions extending along the second direction, and each of the one or more fourth portions is between adjacent semiconductor bodies along the third direction.

[0026] In some embodiments, the conductive structure includes a plurality of conductors spaced apart from each other along the third direction. Each of the plurality of conductors is coupled to a corresponding adjacent memory cell along the second direction.

[0027] In some embodiments, each of the word lines is coupled to a first connection structure that is positioned along the third direction to be relatively closer to the first storage unit in the corresponding row of storage units than to the last storage unit in the corresponding row of storage units. The conductive structure is coupled to a second connection structure that is positioned to be relatively closer to the last storage unit in the corresponding row of storage units than to the first storage unit in the corresponding row of storage units.

[0028] In some embodiments, the semiconductor structure further includes: a plurality of conductive lines including the two word lines and the conductive structure, each of the plurality of conductive lines extending along the third direction. Adjacent ones of the plurality of conductive lines are spaced apart from each other along the second direction and are coupled to corresponding connection structures located at opposite ends of a row of storage units extending along the third direction.

[0029] In some embodiments, the semiconductor structure further includes a semiconductor substrate having first and second opposite sides. Each of the word lines is coupled to a first connection structure located at the first side of the semiconductor substrate. The conductive structure is coupled to a second connection structure located at the second side of the semiconductor substrate.

[0030] In some embodiments, each of two adjacent storage units includes a corresponding storage cell coupled to the first terminal of the transistor of the storage unit. The semiconductor device further includes a bit line that is coupled to the second terminals of the transistors of the two adjacent storage units and that extends along the second direction.

[0031] In some embodiments, the transistors of the two adjacent storage units are mirror symmetric with respect to the conductive structure.

[0032] Another aspect of the present disclosure features a method of forming a semiconductor device, including: forming two adjacent storage units in a semiconductor substrate, where each of the two adjacent storage units includes a transistor having a semiconductor body, a first terminal, a second terminal, and a gate terminal; and forming a conductive structure between the transistors of the two adjacent storage units, the conductive structure being in contact with at least one of the semiconductor bodies of the transistors of the two adjacent storage units. The conductive structure is spaced apart from the first and second terminals of each of the transistors of the two adjacent storage units.

[0033] In some embodiments, the method further includes: forming a first conductive line coupled to the gate terminal of the transistor of the first storage unit among the two adjacent storage units; forming a second conductive line coupled to the gate terminal of the transistor of the second storage unit among the two adjacent storage units; coupling the first conductive line and the second conductive line to respective first connection structures; and coupling the conductive structure to a second connection structure. The respective first connection structures and the second connection structure are each disposed at opposite ends of the transistor or on opposite sides of the semiconductor substrate.

[0034] In some embodiments, the two adjacent storage units and the conductive structure are formed on the same side of the semiconductor substrate.

[0035] In some embodiments, forming the two adjacent storage units in the semiconductor substrate includes: forming the two adjacent storage units from a first side of the semiconductor substrate. Forming the conductive structure includes: forming the conductive structure from a second side of the semiconductor substrate opposite to the first side.

[0036] Another aspect of the present disclosure features a system including: a storage device and a controller, the controller being coupled to the storage device and configured to control the storage device. In such an embodiment, the storage device includes: two adjacent storage units, wherein each of the two adjacent storage units includes a transistor having a semiconductor body, a first terminal, a second terminal, and a gate terminal; and a conductive structure between the transistors of the two adjacent storage units, the conductive structure being in contact with at least one of the semiconductor bodies of the transistors of the two adjacent storage units. The conductive structure is spaced apart from the first terminal and the second terminal of each of the transistors of the two adjacent storage units.

[0037] In some embodiments, the storage device includes: an array of storage units; a plurality of conductive structures, wherein each of the plurality of conductive structures is between respective adjacent rows of storage units and coupled to the semiconductor bodies of the respective adjacent rows of storage units, and each of the plurality of conductive structures is spaced apart from the first terminal and the second terminal of the transistors of the respective adjacent rows of storage units; and a plurality of word lines, each of the plurality of word lines being coupled to a respective row of storage units and being on an opposite side of the respective row of storage units relative to the conductive structure, and wherein each word line extends in the second direction.

[0038] In some embodiments, each of the plurality of word lines is coupled to a first connection structure that is positioned relatively closer to a first memory cell in a memory cell row than to a last memory cell in the memory cell row. Each of the plurality of conductive structures is coupled to a second connection structure that is positioned relatively closer to the last memory cell in the memory cell row than to the first memory cell of the memory cell row.

[0039] In some embodiments, each of the plurality of word lines is coupled to a first connection structure that is positioned relatively closer to a first surface of a memory cell array than to a second surface different from the first surface of the memory cell row. Each of the plurality of conductive structures is coupled to a second connection structure that is positioned relatively closer to the second surface of the memory cell array than to the first surface of the memory cell array.

[0040] In some embodiments, the system further includes: a plurality of bit lines, wherein each of the plurality of bit lines is coupled to a first terminal of a transistor of a memory cell column. Each memory cell of the memory cell column includes a storage cell coupled to a second terminal of a corresponding transistor of the memory cell.

[0041] Another aspect of the present disclosure features a semiconductor device, including: two adjacent semiconductor bodies; a conductive structure between the two adjacent semiconductor bodies, the conductive structure being in contact with at least one of the two adjacent semiconductor bodies; and two conductive lines on opposite sides of the conductive structure. Each of the two conductive lines is coupled to a corresponding connection structure at an end of the conductive line. The conductive structure is coupled to a corresponding connection structure at an end of the conductive structure. The adjacent ones of the corresponding connection structures coupled to the two conductive lines and the corresponding connection structure coupled to the conductive structure are at at least one of opposite ends on the same side or opposite sides of the semiconductor device.

[0042] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. By using a conductive structure between two adjacent memory cells, charge accumulation in the floating body region of a transistor can be reduced, thereby alleviating the floating body effect in the memory cell. By applying a fixed negative voltage to the conductive structure between the memory cells, the threshold voltage of the memory cell can be conveniently adjusted, reducing the overall manufacturing complexity and cost, and improving the reliability of the memory cell. In addition, by alternately arranging connection structures at different ends of the corresponding word lines and the conductive structure, and / or arranging the connection structures of the word lines and the connection structures of the conductive structure on opposite sides of the semiconductor structure, the overall manufacturing complexity of the semiconductor structure can be reduced.

[0043] This technology can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices), or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) (such as phase-change random-access memory (PCRAM)), spin-transfer torque (STT)-magnetoresistive random-access memory (MRAM), and so on. This technology can also be applied to charge-trapping-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate-based memory devices. These technologies can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices (such as two-level cell devices), three-level cell (TLC) devices, four-level cell (QLC) devices, or five-level cell (PLC) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSD), embedded systems, etc.

[0044] Details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable a person of ordinary skill in the relevant art to make and use the disclosure.

[0046] Figure 1 A cross-sectional view of an exemplary 3D semiconductor device is shown.

[0047] Figures 2A - 2H A cross-sectional view of an exemplary 3D semiconductor structure is shown.

[0048] Figures 3A - 3E Shows a top view of an exemplary 3D semiconductor structure.

[0049] Figures 4A - 4B Shows a top view of an exemplary 3D semiconductor structure.

[0050] Figure 5 Shows a cross-sectional view of an exemplary 3D semiconductor structure.

[0051] Figures 5A - 5M Shows an exemplary process for manufacturing a 3D semiconductor structure.

[0052] Figure 6 Shows a cross-sectional view of another exemplary 3D semiconductor structure.

[0053] Figure 7 Shows a flowchart of an exemplary process for manufacturing a semiconductor structure.

[0054] Figure 8 Shows a block diagram of an exemplary system having one or more semiconductor devices.

[0055] Like reference numerals and labels in the various figures indicate like elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Description

[0056] Figure 1 Shows a side view of a cross-section of an exemplary 3D semiconductor device 100. The 3D semiconductor device 100 can be a 3D dynamic random access memory (DRAM). It should be understood that Figure 1 this is for illustrative purposes only and may not reflect the actual device structure (e.g., interconnects) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 can be joined at a bonding interface 106 therebetween.

[0057] As Figure 1As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single-crystalline silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include peripheral circuits 112 on and / or in the substrate 110. In some embodiments, the peripheral circuits 112 include a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 114) may also be formed on or in the substrate 110. In some examples, the peripheral circuits 112 are formed using complementary metal oxide semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die that may be referred to as a control die or a CMOS die 102.

[0058] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 above the peripheral circuits 112 to transmit electrical signals to and from the peripheral circuits 112. The interconnect layer 116 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and VIA contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers in which the interconnect lines and via contacts may be formed. That is, the interconnect layer 116 may include interconnect lines and via contacts in the plurality of ILD layers. In some embodiments, the peripheral circuits 112 are coupled to each other through the interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include a conductive material, which includes but is not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers may be formed of a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0059] As Figure 1 shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 at the back side at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuits 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material such as Cu. The remaining regions of the bonding layer 118 may be formed of a dielectric material, which is such as silicon oxide. The bonding contacts 119 and the surrounding dielectric in the bonding layer 118 may be used for hybrid bonding. Similarly, as Figure 1As shown, the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining regions of the bonding layer 120 may be formed of a dielectric material, such as silicon oxide. The bonding contacts 121 and the surrounding dielectric in the bonding layer 120 may be used for hybrid bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite a memory cell (e.g., a DRAM cell) 124, where a bit line 123 is positioned between the dielectric layer and the memory cell 124, as Figure 1 shown. The dielectric layer may include the bonding interface 106 having the bonding contacts 121.

[0060] The second semiconductor structure 104 may be bonded on top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), the bonding interface 106 is disposed between the bonding layers 120 and 118, which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and metal-metal bonding and dielectric-dielectric bonding can be obtained simultaneously. In some embodiments, the bonding interface 106 is the location where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 may be a layer having a certain thickness that includes the top surface of the bonding layer 118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0061] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122 (including a bit line 123) above the bonding layer 120 to transmit electrical signals. The interconnect layer 122 may include a plurality of interconnects, such as mid-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 further include local interconnects, such as the bit line 123 and word line contacts (not shown). The interconnect layer 122 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. The interconnects in the interconnect layer 122 may include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0062] In some embodiments, the peripheral circuit 112 includes a word line driver / row decoder that is coupled to word line contacts in the interconnect layer 122 through bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnect layer 116. In some embodiments, the peripheral circuit 112 includes a bit line driver / column decoder that is coupled to bit lines 123 and bit line contacts in the interconnect layer 122 through bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnect layer 116. In some embodiments, contrary to semiconductor bit lines (e.g., doped silicon bit lines), the bit lines 123 are metal bit lines. For example, the bit lines 123 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, contrary to Schottky contacts, the bit line contacts are ohmic contacts.

[0063] In some embodiments, the bit lines 123 are made of a composite conductive material that may be based on a metal material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material may include metal silicides, such as, for example, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0064] In some embodiments, the second semiconductor structure 104 includes DRAM devices, where memory cells are provided in the form of an array of DRAM cells 124 above the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122 including the bit lines 123 may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to the strings of the DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and may be referred to as an array die 104.

[0065] In some embodiments, a semiconductor device may include a plurality of array dies (e.g., array die 104) and a CMOS die (e.g., CMOS die 102). The plurality of array dies and the CMOS die may be stacked and bonded together. The CMOS die may be coupled to each of the plurality of array dies respectively, and may drive each of the plurality of array dies respectively to operate in a manner similar to the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device at least includes a first wafer and a second wafer bonded face to face. The array dies may be disposed on the first wafer together with other array dies, and the CMOS die may be disposed on the second wafer together with other CMOS dies. The first wafer and the second wafer may be bonded together so that the array dies on the first wafer may be bonded to the corresponding CMOS dies on the second wafer. In some examples, the semiconductor device is a chip having at least an array die and a CMOS die bonded together. In an example, the chip is cut from the bonded wafers. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0066] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell composed of one transistor and one capacitor. It should be understood that the DRAM cell 124 may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell. In some embodiments, the vertical transistor 126 includes a semiconductor body 130 (an active region where a channel may be formed) extending vertically (in the z direction), and a gate structure 136 in contact with one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a cuboid shape or a cylindrical shape, and the gate structure 136 may be adjacent to a single side of the semiconductor body 130 in a plan view, e.g., as Figure 1 shown. In some embodiments, the vertical transistor 126 has a structure including two or more gates, e.g., a two-gate structure, a three-gate structure, or a gate-all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132, and the gate dielectric 132 is laterally located between the gate electrode 134 and the semiconductor body 130 in the bit line direction (e.g., in the Y direction). In some embodiments, the gate dielectric 132 is adjacent to one side of the semiconductor body 130, and the gate electrode 134 is adjacent to the gate dielectric 132.

[0067] As Figure 1As shown, in some embodiments, the semiconductor body 130 has two ends in the vertical direction (z-direction), Figure 1 the upper end and the lower end in Figure 1 , and at least one end (e.g., the lower end) extends in the vertical direction (z-direction) beyond the gate dielectric 132 into the ILD layer. In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (the upper end and the lower end) of the semiconductor body 130 extend in the vertical direction (z-direction) beyond the gate electrode 134 into the ILD layer. That is, the semiconductor body 130 may have a larger vertical dimension (e.g., depth) than the gate electrode 134 (e.g., in the z-direction), and neither the upper end nor the lower end of the semiconductor body 130 is flush with the corresponding end of the gate electrode 134. Thus, short circuits between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 may also include a source and a drain (both are referred to as 138 because their positions can be interchanged), and the source and the drain are respectively disposed at both ends (the upper end and the lower end) of the semiconductor body 130 in the vertical direction (z-direction). In some embodiments, one of the source and the drain 138 (e.g., at Figure 1 the upper end in Figure 1 ) is coupled to the capacitor 128, and the other of the source and the drain 138 (e.g., at Figure 1 the lower end in Figure 1 ) is coupled to the bit line 123. That is, the vertical transistor 126 may have a first terminal in the positive z-direction and a second terminal opposite the first terminal in the negative z-direction, as Figure 1 shown.

[0068] In some embodiments, the semiconductor body 130 includes a semiconductor material, such as single-crystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may include single-crystalline silicon. The source and the drain 138 may be doped with an N+-type dopant (e.g., phosphorus (P) or arsenic (As)) or a P-type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (such as a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact portion, or formed between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact portion 142 to reduce the contact resistance. In some embodiments, the gate dielectric 132 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, and the dielectric material includes but is not limited to Al 2 O 3 、HfO 2 、Ta 2 O5 , ZrO 2 , TiO 2 or any combination thereof. In some embodiments, the gate electrode 134 includes a conductive material, which includes but is not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes a plurality of conductive layers, such as a W layer on a TiN layer. In one example, the gate structure 136 can be a "gate oxide / gate polysilicon" gate, where the gate dielectric 132 includes silicon oxide and the gate electrode 134 includes doped polysilicon. In another example, the gate structure 136 can be HKMG, where the gate dielectric 132 includes a high-k dielectric and the gate electrode 134 includes a metal.

[0069] As described above, since the gate electrode 134 can be part of a word line or extend as a word line in the word line direction (e.g., the X direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include a plurality of word lines, each extending in the word line direction. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend in two orthogonal lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a vertical direction orthogonal to the two lateral directions in which the bit lines 123 and the word lines 134 extend. The word line 134 contacts a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material, which includes but is not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 134 includes a plurality of conductive layers, and the conductive layers are, for example, a W layer on a TiN layer, as Figure 1 shown.

[0070] In some embodiments, as Figure 1As shown, the vertical transistor 126 extends vertically through the word line 134 and contacts the word line 134, and the source or drain 138 of the vertical transistor 126 contacts the bit line 123 (or bit line contact, if any) at its lower end. Thus, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be disposed in different planes in the vertical direction, which simplifies the routing of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is vertically disposed between the bonding layer 120 and the word line 134, and the word line 134 is vertically disposed between the bit line 123 and the capacitor 128. The word line 134 can be coupled to the peripheral circuit 112 in the first semiconductor structure 102 through word line contacts (not shown) in the interconnect layer 122, bonding contacts 121 and 119 in the bonding layers 120 and 118, and interconnects in the interconnect layer 116. Similarly, the bit line 123 in the interconnect layer 122 can be coupled to the peripheral circuit 112 in the first semiconductor structure 102 through bonding contacts 121 and 119 in the bonding layers 120 and 118 and interconnects in the interconnect layer 116.

[0071] In some embodiments, the vertical transistors 126 can be arranged in a mirror-symmetric manner to increase the density of the DRAM cells 124 in the bit line direction (Y direction). As Figure 1 shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetric with respect to the trench isolation 160. That is, the second semiconductor structure 104 can include a plurality of trench isolations 160, each trench isolation 160 extending in the word line direction (X direction) parallel to the word line 134 and disposed between the vertical gates 134 of two adjacent rows of vertical transistors. In some embodiments, the rows of vertical transistors 126 separated by the trench isolation 160 are mirror-symmetric with respect to the trench isolation 160. The trench isolation 160 can be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be understood that the trench isolation 160 can include air gaps, each air gap being laterally disposed between adjacent vertical gates 134. Since the pitch of the vertical transistors 126 in the bit line direction (e.g., Y direction) is relatively small, air gaps can be formed. On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, air gaps are also laterally formed between the word line / gate electrodes 134 in the bit line direction according to the pitch of the word line / gate electrodes 134 in the bit line direction.

[0072] In some embodiments, instead of trench isolation 160 having an air gap between adjacent vertical gates 134 of two adjacent rows of vertical transistors 126, a conductive structure 170 (e.g., including a metal such as W) is disposed between adjacent semiconductor bodies 130 of two adjacent rows of vertical transistors 126. As described in further detail below (e.g., Figures 2A - 2H or Figures 3A - 3E ), the conductive structure 170 can contact at least one of the adjacent semiconductor bodies 130 and can be coupled to a low voltage (e.g., a fixed negative voltage), which can reduce charge accumulation in the memory cell 124, thereby alleviating the floating body effect in the memory cell 124. Additionally, by applying a fixed low voltage to the conductive structure 170 between the memory cells 124, the threshold voltage of the memory cells 124 can be conveniently adjusted, which can reduce overall manufacturing complexity and cost and improve the reliability of the memory cells 124. Additionally, as described in further detail below (e.g., Figures 4A - 4B ), the connection structure 170 can be coupled out from the same side as the word line or from a different side than the word line. For example, the conductive structure 170 can be coupled out from the back side of the second semiconductor structure 104.

[0073] As Figure 1 shown, in some embodiments, the capacitor 128 includes a first electrode 144 that is above the source or drain 138 of the vertical transistor 126 (e.g., the upper end of the semiconductor body 130) and is coupled to the source or drain 138 of the vertical transistor 126 via a capacitor contact 142. In some embodiments, contrary to a Schottky contact, the capacitor contact 142 is an ohmic contact, such as a metal silicide contact. For example, the capacitor contact 142 can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. The capacitor 128 can further include a capacitor dielectric above and in contact with the first electrode 144, and a second electrode above and in contact with the capacitor dielectric. That is, the capacitor 128 can be a vertical capacitor where the electrodes and the capacitor dielectric are vertically stacked (in the z - direction), and the capacitor dielectric can be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to the source or drain 138 of the corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146 that is coupled to ground (e.g., a common ground). The capacitor 128 can have a first end in the negative z - direction and a second end opposite the first end in the positive z - direction, as Figure 1As shown. In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (e.g., capacitor contact 142 made of a metal silicide material). As Figure 1 shown, the second semiconductor structure 104 may further include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146 for coupling capacitor 128 to the peripheral circuit 112 or directly to ground. In some embodiments, the capacitor contact 147 (e.g., a conductor) extends in the z - direction from the dielectric layer of the bonding layer 120 to be coupled to the second end of capacitor 128 via the common plate 146, as Figure 1 shown. In some embodiments, the ILD layer in which capacitor 128 is formed has the same dielectric material as the two ILD layers into which the semiconductor body 130 extends, such as silicon oxide.

[0074] It should be understood that the structure and configuration of capacitor 128 are not limited to the Figure 1 examples herein, and may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi - fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate - plate capacitor. In some embodiments, the capacitor dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high - k dielectric, and the dielectric material includes but is not limited to Al 2 O 3 、HfO 2 、Ta 2 O 5 、ZrO 2 、TiO 2 or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor used in a FRAM cell, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material such as PZT or SBT. In some embodiments, the electrodes include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0075] As Figure 1As shown, the vertical transistor 126 extends vertically through the word line 134 and contacts the word line 134. The source or drain 138 of the vertical transistor 126 at its lower end contacts the bit line 123, and the source or drain 138 of the vertical transistor 126 at its upper end is coupled to the capacitor 128. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be disposed in different planes in the vertical direction and are coupled to opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some embodiments, the bit line 123 and the capacitor 128 are disposed on opposite sides of the vertical transistor 126 in the vertical direction, which simplifies the routing of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 as compared to a DRAM cell in which the bit line and the capacitor are disposed on the same side of a planar transistor.

[0076] As Figure 1 shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be arranged to be closer to the peripheral circuit 112 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. As a result, the interconnect layer 122 including the bit line 123 can be arranged close to the bonding interface 106 to reduce the interconnect routing distance and complexity.

[0077] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 can be part of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0078] As Figure 1 shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 150 above the substrate 148 and the DRAM cell 124. The pad-out interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad-out interconnect layer 150 and the interconnect layer 122 can be formed on opposite sides of the DRAM cell 124. The capacitor 128 can be vertically disposed between the vertical transistor 126 and the pad-out interconnect layer 150. In some embodiments, the interconnects in the pad-out interconnect layer 150 can transmit electrical signals between the 3D semiconductor device 100 and an external circuit, e.g., for pad-out purposes.

[0079] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through the substrate 148 and a portion of the pad lead-out interconnect layer 150 to couple the pad lead-out interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. As a result, the peripheral circuit 112 can be coupled to the DRAM cell 124 through the interconnect layers 116 and 122 and the bonding layers 120 and 118, and the peripheral circuit 112 and the DRAM cell 124 can be coupled to an external circuit through the contact 152 and the pad lead-out interconnect layer 150. The contact pad 154 and the contact 152 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In one example, the contact pad 154 may include Al, and the contact 152 may include W. In some embodiments, the contact 152 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically separate the via from the substrate 148. Depending on the thickness of substrate 148 , contact 152 may be an ILV having a depth of sub-micrometer level (eg, between 10 nm and 1 μm) or a TSV having a depth of micrometer level or tens of micrometer level (eg, between 1 μm and 100 μm).

[0080] Although not shown, it should be understood that the pad lead-out of the 3D memory device is not limited to the Figure 1 The second semiconductor structure 104 having the DRAM cell 124 is shown, and can be derived from the first semiconductor structure 102 having the peripheral circuit 112. Although not shown, it is also understood that the air gaps between the word lines 134 and / or between the semiconductor bodies 130 can be partially or completely filled with a dielectric. Although not shown, it is further understood that more than one array of DRAM cells 124 can be stacked on top of each other to vertically scale up the number of DRAM cells.

[0081] In some embodiments, the second semiconductor structure 104 includes a substrate disposed below the DRAM cell 124, rather than Figure 1 1. The substrate 148 is shown with a substrate 148 above the DRAM cell 124. The substrate can be part of a carrier wafer. The DRAM cell 124 can be formed in the front side of the substrate, and the bit line 123 can be formed in the back side of the substrate. The bit line 123 can be conductively coupled to the DRAM cell 124 (e.g., the terminal 138 of the vertical transistor 126) through the substrate.

[0082] Figures 2A - 2H 2 shows a cross-sectional view (eg, in the XZ plane) of example 3D semiconductor structures 200a-h according to some embodiments of the present disclosure. One or more of the 3D semiconductor structures 200a-h may be similar to or identical to Figure 1The 3D semiconductor device 100, or Figure 1 a portion of the 3D semiconductor device 100 (e.g., Figure 1 the second semiconductor structure 104), or a structure in the Figure 1 intermediate manufacturing process of the 3D semiconductor device 100.

[0083] As Figure 2A shown, the semiconductor structure 200a includes two adjacent memory cells 207a and 207b coupled to bit lines 210. Note that, for illustrative purposes only, the semiconductor structure 200a is shown as including two memory cells. In some embodiments, the semiconductor structure 200a includes any suitable number of memory cells.

[0084] In some embodiments, each of the memory cells 207a and 207b includes a vertical transistor and a capacitor coupled to the vertical transistor. In the example shown, the memory cell 207a includes a vertical transistor 209a and a capacitor 204a coupled to the vertical transistor 209a via a contact 205a. The memory cell 207b includes a vertical transistor 209b and a capacitor 204b coupled to the vertical transistor 209b via a contact 205b.

[0085] In some embodiments, each of the vertical transistors 209a and 209b includes a semiconductor body, a first terminal, a second terminal, and a gate terminal. One of the first terminal and the second terminal may be a source terminal, and the other of the first terminal and the second terminal may be a drain terminal. In the example shown, the vertical transistor 209a includes a semiconductor body 201a, a first terminal 202a, a second terminal 203a, and a gate terminal 212a. The vertical transistor 209b includes a semiconductor body 201b, a first terminal 202b, a second terminal 203b, and a gate terminal 212b.

[0086] In some embodiments, each gate terminal of the vertical transistor includes a gate electrode and a gate dielectric. In the example shown, the gate terminal 212a includes a gate electrode 206a and a gate dielectric 211a. The gate terminal 212b includes a gate electrode 206b and a gate dielectric 211b.

[0087] In some embodiments, the semiconductor structure 200a includes a conductive structure between the vertical transistors 209a and 209b. In some examples, the conductive structure may contact at least one of the semiconductor bodies (e.g., semiconductor bodies 201a and 201b) of the vertical transistors 209a and 209b. In the example shown, the conductive structure 208 contacts both of the semiconductor bodies 201a and 201b.

[0088] In some embodiments, the conductive structure 208 includes one or more conductive layers, which include at least one of a metal layer, a polysilicon layer, a germanium-silicon (GeSi) layer, or a barrier layer such as titanium nitride (TiN).

[0089] In some embodiments, each of the semiconductor bodies 201a and 201b includes opposite ends along a first direction (e.g., the Z direction) and opposite sides along a second direction (e.g., the X direction) orthogonal to the first direction. In such embodiments, the first terminals 202a and 202b and the second terminals 203a and 203b are respectively located at the opposite ends of the semiconductor bodies 201a and 201b. In the illustrated example, the first terminal 202a and the second terminal 203a are located at the opposite ends of the semiconductor body 201a, and the first terminal 202b and the second terminal 203b are located at the opposite ends of the semiconductor body 201b.

[0090] In some embodiments, the gate terminals 206a, 206b and the conductive structure 208 are respectively located on two opposite sides of the semiconductor bodies 201a and 201b. In the illustrated example, the gate terminal 212a and the conductive structure 208 are located on opposite sides of the semiconductor body 201a, and the gate terminal 212b and the conductive structure 208 are located on opposite sides of the semiconductor body 201b.

[0091] In some embodiments, the work function of the conductive structure 208 is higher than the work function of the semiconductor body (e.g., semiconductor bodies 201a, 201b) in contact with the conductive structure. In some embodiments, the work function is defined as the minimum amount of energy required to remove an electron from a solid to a point just outside the surface of the solid (e.g., measured in electron volts eV) (or the energy required to move an electron from the Fermi level to a vacuum). In some examples, the work function of a material may depend on the electronic structure of the material and its surface state. Thus, different materials can have different work functions. In some examples, it may be more difficult to remove an electron from a material with a high work function than from a material with a low work function.

[0092] In some examples, when two materials with different work functions are in contact, electrons can move from the material with the lower work function (where it is easier to remove electrons) to the material with the higher work function (where it is more difficult to remove electrons). This can occur until their Fermi levels (the energy levels at which there is a 50% probability of finding an electron) are equal. This electron movement creates an electric field and a barrier called a "Schottky barrier", which prevents further electron flow. However, if an external energy source such as a voltage is applied, it can overcome this barrier, causing current to flow, mainly from the lower work function material to the higher work function material.

[0093] In some embodiments, the conductive structure 208 is configured such that a Schottky barrier is formed at the interface between the conductive structure 208 and a semiconductor body (e.g., semiconductor bodies 201a, 201b) in contact with the conductive structure 208.

[0094] In some embodiments, the conductive structure 208 is coupled to a fixed voltage. In such embodiments, the conductive structure 208 is coupled to a fixed voltage such that, in operation, a current path is formed from the semiconductor body in contact with the conductive structure 208 to the conductive structure 208. In some examples, the fixed voltage is a negative voltage. In some examples, the fixed voltage is associated with the threshold voltage of at least one of the adjacent memory cells (e.g., memory cells 207a or 207b).

[0095] By using a conductive structure (e.g., conductive structure 208) between two adjacent memory cells, the floating body effect can be mitigated. In some examples, the floating body effect may be a phenomenon observed in silicon-on-insulator (SOI) technology, in which the body of a transistor is not connected to a reference voltage but is electrically isolated or "floating". This effect refers to the accumulation of charge in the floating body region, which may cause the threshold voltage of the device to drift and change its characteristics. This sometimes leads to problems such as increased leakage current and device instability, especially in the case of device miniaturization. By coupling the conductive structure to a fixed voltage, the accumulation of charge in the floating body region of the transistor can be reduced, thereby mitigating the floating body effect in the memory cell.

[0096] In some examples, the threshold voltage of a memory cell (e.g., memory cells 207a or 207b) can be adjusted by changing the work function of the gate structure (e.g., gates 206a or 206b) coupled to the memory cell. However, changing the work function of the gate structure may affect other device characteristics, such as leakage current and subthreshold slope. In addition, changing the work function of the gate structure may require different manufacturing processes or conditions, which may affect the overall manufacturing complexity or cost as well as long-term reliability.

[0097] In some examples, the threshold voltage of a memory cell (e.g., memory cells 207a or 207b) can be adjusted by applying a fixed negative voltage to the conductive structure (e.g., conductive structure 208) in contact with the semiconductor body of the memory cell (e.g., semiconductor bodies 201a or 201b). By applying a fixed negative voltage to the conductive structure between the memory cells, the threshold voltage of the memory cell can be conveniently adjusted, reducing the overall manufacturing complexity and cost and improving the reliability of the memory cell.

[0098] In some embodiments, the conductive structure 208 can have different configurations (e.g., shape, part, size, position, etc.). In Figure 2AIn the example shown, the conductive structure 208 contacts an intermediate portion of the semiconductor bodies 201a and 201b.

[0099] Figures 2B - 2H Various other configurations of the conductive structure between adjacent memory cells are shown. For the sake of brevity, the Figures 2B - 2H in which are similar to those in the reference Figure 2A description of the elements and the reference numerals.

[0100] Reference Figure 2B , the conductive structure 220 contacts a portion of the adjacent semiconductor body that is closer to the second terminal of the adjacent vertical transistor than to the first terminal, where the first terminal is positioned closer to the capacitor coupled to the adjacent vertical transistor than the second terminal.

[0101] Reference Figure 2C , the conductive structure 230 contacts a portion of the adjacent semiconductor body that is closer to the first terminal of the adjacent vertical transistor than to the second terminal, where the first terminal is positioned closer to the capacitor coupled to the adjacent vertical transistor than the second terminal.

[0102] Reference Figure 2D , the conductive structure 240 contacts a substantial portion of the adjacent semiconductor body that includes, for example, a first portion closer to the first terminal of the adjacent vertical transistor, a second portion closer to the second terminal of the adjacent vertical transistor, and an intermediate portion between the first and second portions. The conductive structure 240 is spaced apart from the first and second terminals of the adjacent vertical transistor.

[0103] Reference Figure 2E , the conductive structure 250 includes two portions - a first portion along the Z direction and a second portion that crosses the first portion along the X direction. In the example shown, the first portion of the conductive structure 250 extends along the Z direction and is spaced apart from the two terminals of each of the two adjacent transistors. The second portion of the conductive structure 250 contacts each of the semiconductor bodies of the adjacent memory cells. Note that the conductive structure 250 in the semiconductor structure 200e is shown as including two portions for illustrative purposes only. The conductive structure 250 can have any suitable number of portions. In some examples, the conductive structure 250 can have two first portions and one second portion, each first portion extending along the Z direction, and the second portion crossing the two first portions along the X direction. In some examples, the conductive structure 250 can have one first portion and two second portions, the first portion extending along the Z direction, and the two second portions crossing the first portion along the X direction.

[0104] Reference Figure 2F, the conductive structure 260 includes an oval shape having an edge that contacts the semiconductor body of an adjacent transistor. In some embodiments, the conductive structure 260 has any suitable variant of an oval shape, such as circular, elliptical, oblong, stadium, Lame curve, Cassini oval, or Cartesian oval, etc.

[0105] Reference Figure 2G , the conductive structure 270 includes two conductive bars spaced apart along the Z direction. Each of the two conductive bars contacts the semiconductor body of an adjacent transistor. Note that, for illustrative purposes only, the conductive structure 270 is shown as including two conductive bars. In some embodiments, the conductive structure 270 may have any suitable number of conductive bars. The conductive bars in the conductive structure 270 may be coupled to the same voltage source that provides a fixed voltage.

[0106] Reference Figure 2H , the conductive structure 280 includes two conductors spaced apart from each other along the X direction. Each of the two conductors contacts a respective one of the semiconductor bodies of adjacent transistors. Note that, for illustrative purposes only, the conductive structure 280 is shown as including two conductors. In some embodiments, the conductive structure 280 may have any suitable number of conductors. In some examples, the conductive structure 280 may include three conductors - two conductors contact the semiconductor body of a first adjacent transistor, and one conductor contacts the semiconductor body of a second adjacent transistor. In some examples, the conductive structure 280 may include four conductors - two conductors contact the semiconductor body of a first adjacent transistor, and two conductors contact the semiconductor body of a second adjacent transistor. The conductors in the conductive structure 280 may be coupled to the same voltage source that provides a fixed voltage.

[0107] In some embodiments, the conductive structure between two adjacent memory cells may have any suitable combination of the conductive structures as described in reference Figures 2A - 2H . For example, the conductive structures described herein may include an oval portion and one conductive bar. As another example, the conductive structure as described herein may include a conductive bar and a conductor, where the conductive bar contacts the semiconductor bodies of two adjacent transistors, and the conductor contacts the semiconductor body of one of the two adjacent transistors.

[0108] Figures 3A - 3E A top view (e.g., in the XY plane) of example 3D semiconductor structures 300a - e according to some embodiments of the present disclosure is shown. One or more of the 3D semiconductor structures 300a - e may be similar to or the same as Figure 1 the 3D semiconductor device 100, or Figure 1 a portion of the 3D semiconductor device 100 (e.g., Figure 1of the second semiconductor structure 104), or Figure 1 structure at an intermediate manufacturing process of the 3D semiconductor device 100.

[0109] As Figure 3A shown, the semiconductor structure 300a includes two rows of memory cells, where each row of memory cells extends along the Y direction. In some embodiments, each memory cell in the two rows of memory cells includes a semiconductor body. In the illustrated example, the first row of memory cells includes semiconductor bodies 302a, 304a, and 306a. The second row of memory cells includes semiconductor bodies 302b, 304b, and 306b. Note that, for illustrative purposes only, the semiconductor structure 300a is shown as including three memory cells in each row. In some embodiments, the semiconductor structure 300a includes any suitable number of memory cells in each row of memory cells.

[0110] The semiconductor structure 300a further includes two word lines 301a and 301b. The word lines 301a and 301b are spaced apart along the X direction, and each of the word lines 301a and 301b extends along the Y direction. Each of the word lines 301a and 301b is coupled to the memory cells of adjacent rows of memory cells. In some embodiments, the gate terminals of adjacent rows of memory cells are connected together to form a corresponding word line (e.g., word line 301a or 301b).

[0111] The semiconductor structure 300a further includes a conductive structure 308. As shown, the conductive structure 308 extends along the Y direction and has opposite sides along the X direction. The semiconductor bodies of the two rows of memory cells are coupled to the opposite sides of the conductive structure 308. In the illustrated example, the semiconductor bodies 302a, 304a, and 306a are coupled to the first side of the conductive structure 308, and the semiconductor bodies 302b, 304b, and 306b are coupled to the second side of the conductive structure 308.

[0112] Figures 3B - 3E Various other configurations of the conductive structure between two adjacent rows of memory cells are shown. For the sake of brevity, the following may omit Figures 3B - 3E the reference numerals and descriptions of elements similar to those described in reference Figure 3A

[0113] Reference Figure 3B ​, the conductive structure 318 includes a first portion and two second portions. The first portion of the conductive structure 318 extends along the Y direction and is coupled to the semiconductor bodies of two rows of memory cells along the X direction. Each of the two second portions of the conductive structure 318 extends along the X direction and is located between adjacent semiconductor bodies along the Y direction. Note that, for illustrative purposes only, the conductive structure 318 is shown as including two second portions. In some embodiments, the conductive structure 318 includes any suitable number (e.g., 1, 3, or 10) of second portions, depending on the number of memory cells in each row of memory cells. The number of second portions in the conductive structure 318 is the same as the number of memory cells in each row of memory cells minus 1.

[0114] Reference Figure 3C , the conductive structure 328 includes three conductors spaced apart from each other along the Y direction. In the example shown, each of the three conductors of the conductive structure 328 is coupled to the semiconductor bodies of two adjacent memory cells. Note that, for illustrative purposes only, the conductive structure 328 is shown as including three conductors. In some embodiments, the conductive structure 328 includes any suitable number of conductors, depending on the number of memory cells in each row of memory cells. The conductors of the conductive structure 328 can be coupled to the same voltage source to provide the same fixed voltage.

[0115] Reference Figure 3D , the conductive structure 338 includes two conductors spaced apart from each other along the X direction. In the example shown, each of the two conductors of the conductive structure 338 extends along the Y direction. The first conductor of the conductive structure 338 is coupled to the semiconductor body of the first row of memory cells in two rows of memory cells, and the second conductor in the conductive structure 338 is coupled to the semiconductor body of the second row of memory cells in these two rows of memory cells. The two conductive structures 338 can be coupled to the same voltage source to provide the same fixed voltage.

[0116] Reference Figure 3E , the conductive structure 348 includes two conductors. As shown, the first conductor of the conductive structure 348 includes a first portion extending along the Y direction and two second portions extending along the X direction. The first portion of the first conductor is coupled to the semiconductor body of the first row of memory cells in two rows of memory cells. Each of the two second portions is located between adjacent semiconductor bodies along the Y direction.

[0117] The second conductor of the conductive structure 348 is mirror-symmetric with the first conductor of the conductive structure. The second conductor includes a third portion extending along the Y direction and two fourth portions extending along the X direction. The third portion of the second conductor is coupled to the semiconductor body of the second row of memory cells in two rows of memory cells. Each of the two fourth portions is located between adjacent semiconductor bodies along the Y direction. The conductors in the conductive structure 348 can be coupled to the same voltage source to provide the same fixed voltage.

[0118] In some embodiments, the conductive structure between two adjacent rows of memory cells can have any suitable combination of the conductive structures as described in reference Figures 3A - 3E For example, the conductive structure as described herein can include a conductor similar to the conductor described in reference Figure 3C and coupled to the upper two semiconductor bodies and two conductors similar to the conductors described in reference Figure 3D and coupled to the lower four semiconductor bodies. As another example, the conductive structure as described herein can include a conductor similar to the conductor described in reference Figure 3D and coupled to the semiconductor body of the first row of memory cells and a conductor similar to the conductor described in reference Figure 3E and coupled to the semiconductor body of the second row of memory cells.

[0119] In some embodiments, the conductive structure can have any suitable combination of the conductive structure as described in any one of references Figures 3A - 3E and the conductive structure as described in any one of references Figures 2A - 2H For example, Figure 3A or Figure 3B The conductive structure shown can be combined with Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F or Figure 2G The conductive structure shown.

[0120] Figures 4A - 4B FIG. shows a top view (e.g., in the XY plane) of example 3D semiconductor structures 400a and 400b according to some embodiments of the present disclosure. One or more of the 3D semiconductor structures 400a and 400b can be similar to or the same as Figure 1 The 3D semiconductor device 100 of, or Figure 1 A portion of the 3D semiconductor device 100 of (e.g., Figure 1 The second semiconductor structure 104 of), or Figure 1 The structure at an intermediate manufacturing process of the 3D semiconductor device 100 of.

[0121] AsFigure 4A As shown, semiconductor structure 400a includes four rows of semiconductor bodies. The first row of semiconductor bodies includes semiconductor bodies 402a, 404a, and 406a. The second row of semiconductor bodies includes semiconductor bodies 402b, 404b, and 406b. The third row of semiconductor bodies includes semiconductor bodies 402c, 404c, and 406c. The fourth row of semiconductor bodies includes semiconductor bodies 402d, 404d, and 406d. Note that, for illustrative purposes only, semiconductor structure 400a is shown as including three semiconductor bodies in each of the four rows. In some embodiments, semiconductor structure 400a includes any suitable number of rows and any suitable number of semiconductor bodies in each row.

[0122] Semiconductor structure 400a further includes word lines 408a, 408b, 408c, and 408d. Each of the word lines 408a, 408b, 408c, and 408d is coupled to the semiconductor bodies of a corresponding row. Each of the word lines 408a, 408b, 408c, and 408d may be the same as or similar to Figure 3A word lines 301a, 301b. As shown, word line 408a is coupled to the first row of semiconductor bodies including semiconductor bodies 402a, 404a, and 406a. Word line 408b is coupled to the second row of semiconductor bodies including semiconductor bodies 402b, 404b, and 406b. Word line 408c is coupled to the third row of semiconductor bodies including semiconductor bodies 402c, 404c, and 406c. Word line 408d is coupled to the fourth row of semiconductor bodies including semiconductor bodies 402d, 404d, and 406d.

[0123] Semiconductor structure 400a further includes conductive structures 410a and 410b. Each of the conductive structures 410a and 410b is located between two adjacent rows of semiconductor bodies. Each of the conductive structures 410a and 410b may be the same as or similar to Figure 3A conductive structure 308. As shown, conductive structure 410a is located between the first row of semiconductor bodies including semiconductor bodies 402a, 404a, and 406a and the second row of semiconductor bodies including semiconductor bodies 402b, 404b, and 406b. Conductive structure 410b is located between the third row of semiconductor bodies including semiconductor bodies 402c, 404c, and 406c and the fourth row of semiconductor bodies including semiconductor bodies 402d, 404d, and 406d.

[0124] The semiconductor structure 400a further includes connection structures 412a - 412f. Each of the connection structures 412a - 412f is coupled to a respective one of the word lines or the conductive structures. As shown, connection structure 412a is coupled to word line 408a, connection structure 412b is coupled to word line 408b, connection structure 412c is coupled to conductive structure 410b, connection structure 412d is coupled to conductive structure 410a, connection structure 412e is coupled to word line 408c, and connection structure 412f is coupled to word line 408d.

[0125] In some embodiments, the connection structures of the semiconductor structure 400a are located at different ends of adjacent word lines and conductive structures, e.g., on the same side of the semiconductor structure 400a. The connection structures 412a - 412f are arranged such that connection structures 412a, 412b, and 412c are located at one end of the respective word line or conductive structure, and connection structures 412d, 412e, and 412f are located at the other end of the respective word line or conductive structure. In the example shown, connection structure 412a is located at the end of word line 408a closer to semiconductor body 402a than to other semiconductor bodies in the same row, and connection structure 412d is located at the end of conductive structure 410a closer to semiconductor body 406 than to other semiconductor bodies in the same row. By alternately arranging the connection structures at different ends of the respective word lines and conductive structures, the overall manufacturing complexity of the semiconductor structure can be reduced.

[0126] Figure 4B Another example 3D semiconductor structure 400b according to some embodiments of the present disclosure is shown. For the sake of brevity, the following may omit Figure 4B the reference numerals and descriptions of elements similar to those Figure 4A described as

[0127] As shown, the semiconductor structure 400b includes word lines 422a, 422b, 422c, and 422d. Connection structures 424a, 424b, 424c are respectively coupled to word lines 422a, 422b, 422c. The semiconductor structure 400b includes conductive structures 426a and 426b. Connection structures 428a and 428b are respectively coupled to conductive structures 426a and 426b.

[0128] In some embodiments, the semiconductor structure 400b includes a front side and a back side spaced apart along the Z - direction, similar to as referenced Figure 1The described front side and back side. In some embodiments, connection structures (e.g., connection structures 424a - 424d) coupled to word lines in semiconductor structure 400b are located on the front side of semiconductor structure 400b, and connection structures (e.g., connection structures 428a and 428b) coupled to conductive structures in semiconductor structure 400b are located on the back side of semiconductor structure 400b. In some embodiments, connection structures coupled to word lines in semiconductor structure 400b are located on the back side of semiconductor structure 400b, and connection structures coupled to conductive structures in semiconductor structure 400b are located on the front side of semiconductor structure 400b. Adjacent word lines on the same side of semiconductor structure 400b are respectively coupled to connection structures at opposite ends on the same side of semiconductor structure 400b. For example, word line 422b is coupled to connection structure 424b, and word line 322c adjacent to word line 422b is coupled to connection structure 424c, where connection structures 424b, 423c are at opposite ends of semiconductor structure 400b.

[0129] By arranging the connection structures of word lines and the connection structures of conductive structures on opposite sides of the semiconductor structure, the overall manufacturing complexity of the semiconductor structure can be reduced.

[0130] Figure 5 A cross - sectional view (e.g., in the XZ plane) of an exemplary 3D semiconductor structure 500 according to some embodiments of the present disclosure is shown. Semiconductor structure 500 can be similar or identical to Figure 1 the 3D semiconductor device 100, or Figure 1 a part of the 3D semiconductor device 100 (e.g., Figure 1 the second semiconductor structure 104), or a structure at an intermediate manufacturing process of the 3D semiconductor device 100 in Figure 1 the 3D semiconductor device 100.

[0131] As shown, semiconductor structure 500 includes a semiconductor substrate 502, and semiconductor substrate 502 includes trenches 504a, 504b, and 504c. Each of word lines 506a and 506b is located at a corresponding sidewall of trench 504a, and each of word lines 506c and 506d is located at a corresponding sidewall of trench 504c. As described above, the vertical gate terminals of vertical transistors in a row of memory cells (e.g., Figure 2A 206a of Figure 3A ) can be connected together to form corresponding word lines 506a, 506b, 506c, 506d. Each of word lines 506a, 506b, 506c, 506d can be the same or similar to Figures 2A - 2H , Figures 3A - 3E or Figures 4A - 4Bis the same as or similar to any suitable conductive structure described therein or any suitable combination thereof.

[0132] In some embodiments, the semiconductor structure 500 includes a front side and a back side spaced apart along the Z direction, similar to the front side and the back side as described with reference to Figure 1 In the illustrated example, each of the trenches 504a, 504b, and 504c includes an opening on the front side of the semiconductor structure 500. In some embodiments, the word lines 506a - 506d and the conductive structure 508 are fabricated from the same side (e.g., the front side) of the semiconductor structure 500. An example process of fabricating word lines and a conductive structure from the same side of a semiconductor structure will be discussed in more detail below with reference to Figures 5A - 5M

[0133] A semiconductor substrate 512 ( Figure 5A ) is provided. The semiconductor substrate 512 may include silicon (e.g., single - crystal silicon, c - Si), SiGe, GaAs, Ge, SOI, or any other suitable material. In some embodiments, a doping process is performed on the semiconductor substrate 512 to create an n - type region or a p - type region. In some embodiments, an atomic absorption process is performed on the semiconductor substrate 512 to remove impurities in the semiconductor substrate 512.

[0134] The semiconductor substrate 512 includes regions 514. In some embodiments, each of the regions 514 extends along the Y direction. In some embodiments, each of the regions 514 is fabricated by forming a trench from the front side of the semiconductor substrate 512 and filling the trench with an oxide material.

[0135] Then, trenches 516 ( Figure 5B ) are formed in the semiconductor substrate 512. As shown, each of the trenches 516 extends along the X direction. In some embodiments, the trenches 516 are formed by etching the semiconductor substrate 512 along the Y direction using a suitable etching method, such as one or more of wet etching, dry etching, reactive ion etching, deep reactive ion etching, plasma etching, or inductively coupled plasma etching. In some embodiments, the trenches 516 are filled with an oxide material.

[0136] Next, a plurality of trenches 518 ( Figure 5C ) are formed in the semiconductor substrate 512. The trenches 518 may include a plurality of trenches 518, where each of the trenches 518 extends along the X direction. In some embodiments, the trenches 518 may be formed by etching the front side of the semiconductor substrate 512.

[0137] An oxide material is used to fill the trenches 518 to form regions 520 ( Figure 5D)。A subset of region 520 is etched to remove the oxide material filling the subset of the set of regions 520, such that a pattern of alternating trenches 522 and filled trenches 524 is formed. Figure 5E )。Then, a gate dielectric 526 is formed on the sidewalls of trench 522, for example, by depositing an oxide material. Figure 5F )。A gate electrode 528 is formed adjacent to the gate dielectric 526 in trench 522. Figure 5G )。The gate electrodes 528 of the vertical transistors of the rows of the memory cells are connected together to form corresponding word lines (e.g., 506a, 506b, 506c, or 506d). The filled trenches 524 are etched to remove the filled oxide to form trenches 525. Figure 5H )。Subsequently, trench 525 is filled with an oxide material to form a filled trench 530. Figure 5I )。The filled trench 530 is etched to remove a portion of the oxide material filling the trench to form a partially filled trench 532. Figure 5J )。A conductive material is used to fill the partially filled trench 532 to form a filled trench 534. Figure 5K )。The conductive material forms a conductive structure (e.g., Figure 5 the conductive structure 508). Then, the filled trench 532 is etched to remove a portion of the conductive material in the filled trench 534 to form a partially filled trench 535 including the remaining portion of the conductive material. Figure 5L )。Next, the partially filled trench 535 is filled with an oxide material to form a filled trench 536. Figure 5M )。

[0138] In some embodiments, the word lines and the conductive structures are fabricated from opposite sides of the semiconductor structure. Referring to Figure 6 , in some examples, the word lines 606a - 606d and the conductive structure 608 can be fabricated from opposite sides of the semiconductor structure 600. In some examples, the word lines 606a - 606d can be formed from the front side of the semiconductor structure 600, and the conductive structure 608 can be formed from the back side of the semiconductor structure 600. For example, the word lines 604a - 606d can be formed in a semiconductor substrate 602 (e.g., Figure 5In the trenches 604a, 604c formed in the semiconductor substrate 602, the conductive structure 608 can be formed in the intermediate trench 604b between the trenches 604a, 604c. In some embodiments, after fabricating components (e.g., vertical transistors, word lines, and / or capacitors) on the front side of the semiconductor substrate 602, the back side of the semiconductor substrate 602 can be thinned and / or polished (e.g., by CMP). Then, the back side of the semiconductor substrate 602 can be etched until the intermediate trench 604b. The isolation material can be first formed in the intermediate trench 604b from the back side of the semiconductor substrate 602, and then the conductive material can be deposited on the isolation material in the intermediate trench 604 from the back side of the semiconductor substrate 602. Then, the filled conductive material is recessed from the back side semiconductor substrate 602 to form the conductive structure 608. Finally, the isolation material can be further formed on the conductive structure 608 from the back side of the semiconductor substrate 602.

[0139] Figure 7 A flowchart of an exemplary process 700 for fabricating a semiconductor structure is shown. In some embodiments, the process 700 begins (702) when forming two adjacent memory cells (e.g., memory cells 207a and 207b) in a semiconductor substrate (e.g., substrate 502). In some embodiments, each of the two adjacent memory cells includes a transistor (e.g., transistor 209a) having a semiconductor body (e.g., semiconductor body 201a), a first terminal (e.g., terminal 202a), a second terminal (e.g., terminal 203a), and a gate terminal (e.g., gate terminal 212a). In some embodiments, the two adjacent memory cells are formed from a first side of the semiconductor substrate, and the conductive structure is formed from a second side of the semiconductor substrate, where the second side is opposite the first side.

[0140] A conductive structure (e.g., conductive structure 208) is formed between the transistors of the two adjacent memory cells (704). In some embodiments, the conductive structure contacts at least one of the semiconductor bodies of the transistors of the two adjacent memory cells. In some embodiments, the conductive structure is spaced apart from the first terminal and the second terminal of each of the transistors of the two adjacent memory cells.

[0141] A first conductive line (e.g., word line 408a) is formed and coupled to the gate terminal of the transistor of the first memory cell of the two adjacent memory cells (706). A second conductive line (e.g., word line 408b) is formed and coupled to the gate terminal of the transistor of the second memory cell of the two adjacent memory cells (708). The first conductive line and the second conductive line are coupled to respective first connection structures (e.g., connection structures 412a and 412b) (710). The conductive structure is coupled to a second connection structure (e.g., connection structure 412d) (712).

[0142] Figure 8 FIG. 800 shows a block diagram of a system 800 having one or more semiconductor devices (e.g., memory devices) in accordance with one or more embodiments of the present disclosure. The system 800 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 8 shown, the system 800 can include a host device 808 and a storage system 802 having one or more 3D storage devices 804 and a memory controller 806. The host device 808 can include a processor of the electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host device 808 can be configured to send data to or receive data from one or more 3D storage devices 804.

[0143] The 3D storage device 804 can be any 3D storage device disclosed herein, such as the 3D storage device shown in Figure 1 . In some embodiments, the 3D storage device 804 includes NAND flash memory. The memory controller 806 (also referred to as controller circuitry) is coupled to the 3D storage device 804 and the host device 808. Consistent with embodiments of the present disclosure, the 3D storage device 804 can include a plurality of conductive interconnects that contact conductive pads in a conductive pad layer through an overcoat layer, and the memory controller 806 can be coupled to the 3D storage device 804 through at least one of the plurality of conductive interconnects. The memory controller 806 is configured to control the 3D storage device 804. For example, the memory controller 806 can be configured to operate a plurality of channel structures via word lines. The memory controller 806 can manage data stored in the 3D storage device 804 and communicate with the host device 808.

[0144] In some embodiments, the memory controller 806 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an Embedded Multi-Media-Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablets, laptop computers, etc. and enterprise storage arrays. The memory controller 806 may be configured to control the operation of the 3D storage device 804, such as read, erase, and program (or write) operations. The memory controller 806 may also be configured to manage various functions regarding the data stored or to be stored in the 3D storage device 804, which functions include but are not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 806 is further configured to process an Error Correction Code (ECC) regarding the data read from or written to the 3D storage device 804. The memory controller 806 may also perform any other suitable functions, such as formatting the 3D storage device 804.

[0145] The memory controller 806 may communicate with an external device (such as the host device 808) according to a specific communication protocol. For example, the memory controller 806 may communicate with the external device through at least one of various interface protocols, which interface protocols are such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0146] The memory controller 806 and one or more 3D storage devices 804 can be integrated into various types of storage devices, for example, included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the storage system 802 can be implemented and packaged into different types of terminal electronic products. In Figure 8 In one example as shown, the memory controller 806 and a single 3D storage device 804 can be integrated into a memory card 802. The memory card 802 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc.

[0147] The subject matter, as well as the embodiments of the actions and operations described in this disclosure, can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in a combination of one or more of them. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs for execution by, or to control the operation of, a data processing apparatus, e.g., one or more modules of computer program instructions encoded on a computer program carrier. The carrier can be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing apparatus. A computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination of one or more of them, or a portion of a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination of one or more of them. A computer storage medium is not a propagated signal.

[0148] Note that references in this disclosure to "an embodiment", "embodiments", "example embodiments", "some embodiments", "some implementations", etc., mean that the described embodiments may include a particular feature, structure, or characteristic, but each embodiment does not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, influencing such feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the relevant art.

[0149] Generally, terms can be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein can, at least in part, depend on context and can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, and characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood to express a singular or plural usage, at least in part, depending on context. Additionally, the term "based on" can be understood to not necessarily intend to convey a set of exclusive factors and, instead, can allow for the existence of other factors that are not necessarily explicitly described, again, at least in part, depending on context.

[0150] It should be readily understood that the meanings of "on," "above," and "over" in the present disclosure should be interpreted in the broadest manner such that "on" not only means "directly on" something but also includes the meaning of "on" something with intermediate features or layers therebetween. Additionally, "above" or "over" not only means "above" or "over" something but can also include the meaning of "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0151] Furthermore, for ease of description, spatial relative terms such as "under," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (single or multiple) element or feature (single or multiple), as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or in a process step. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be correspondingly interpreted.

[0152] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where a semiconductor device is formed and, thus, unless otherwise stated, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0153] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively closer to the substrate and the top side is relatively farther from the substrate. A layer can extend over the entire underlying or overlying structure or can have a extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region of a uniform or non-uniform continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it, and / or below it. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductive layers and contact layers (wherein contacts, interconnect lines, and / or vertical interconnect paths (VIAs) are formed) and one or more dielectric layers.

[0154] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step that is set during the design phase of a product or process, as well as the range of values above and / or below the expected value. As used herein, the range of values can be due to minor variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity, which can vary based on the particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate a value of a given quantity that varies within, for example, 10 - 30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0155] In the present disclosure, the term "horizontal / horizontally / lateral / laterally" refers to being nominally parallel to the lateral surface of the substrate, and the terms "vertical" or "vertically" refer to being nominally orthogonal to the lateral surface of the substrate.

[0156] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", e.g., a NAND string) on a laterally oriented substrate such that the memory string extends in a vertical direction with respect to the substrate.

[0157] The present disclosure provides many different implementations or examples for implementing different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. Such repetition is for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0158] The foregoing description of specific embodiments can be readily modified and / or changed for various applications. Accordingly, such changes and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein.

[0159] Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope of the claimed subject matter defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claim may be directed to a sub-combination or a variant of the sub-combination.

[0160] Similarly, although operations are depicted in the figures in a particular order and recited in the claims, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order to achieve the desired result, or that all of the illustrated operations be performed. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of the various system modules and components in the above-described embodiments should not be understood as required in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0161] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the acts recited in the claims can be performed in a different order and still achieve the desired result. As one example, in order to achieve the desired result, the processes described in the figures do not necessarily need to be in the particular order or sequential order shown. In some cases, multitasking and parallel processing may be advantageous.

[0162] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: two adjacent memory cells, wherein each of the two adjacent memory cells includes a transistor having a semiconductor body, a first terminal, a second terminal, and a gate terminal; and a conductive structure between the transistors of the two adjacent memory cells, the conductive structure being in contact with at least one of the semiconductor bodies of the transistors of the two adjacent memory cells, wherein the conductive structure is spaced apart from the first terminal and the second terminal of each of the transistors of the two adjacent memory cells.

2. The semiconductor device according to claim 1, wherein, the work function of the conductive structure is higher than the work function of the semiconductor body in contact with the conductive structure.

3. The semiconductor device according to claim 1 or 2, wherein, the conductive structure includes one or more conductive layers, and the one or more conductive layers include at least one of a metal layer, a polysilicon layer, a germanium silicon (GeSi) layer, or a barrier layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein, the conductive structure is in contact with each of the semiconductor bodies of the transistors of the two adjacent memory cells.

5. The semiconductor device according to any one of claims 1 to 4, wherein, the semiconductor body includes opposite ends along a first direction and opposite sides along a second direction orthogonal to the first direction; wherein the first terminal and the second terminal are respectively at the opposite ends of the semiconductor body along the first direction; and wherein the gate terminal and the conductive structure are respectively at two opposite sides of the semiconductor body.

6. The semiconductor device according to claim 5, wherein, the conductive structure is in contact with at least one of the following: a first portion of the semiconductor body, the first portion being closer to the first terminal than to the second terminal; a second portion of the semiconductor body, the second portion being closer to the second terminal than to the first terminal; an intermediate portion of the semiconductor body, the intermediate portion being between the first portion and the second portion; or the first portion, the second portion, and the intermediate portion of the semiconductor body.

7. The semiconductor device according to claim 5 or 6, wherein, the conductive structure has a first portion along the first direction and a second portion intersecting the first portion along the second direction; and wherein the second portion of the conductive structure is in contact with each of the semiconductor bodies of the transistors of the two adjacent memory cells.

8. The semiconductor device according to any one of claims 5 to 7, wherein, the conductive structure includes conductive bars spaced apart along the first direction, and each of the conductive bars is in contact with at least one of the semiconductor bodies along the second direction.

9. The semiconductor device according to any one of claims 5 to 8, wherein, The conductive structure includes two conductors spaced apart from each other along the second direction, and each of the two conductors contacts a corresponding one of the semiconductor bodies of the transistors of the two adjacent memory cells.

10. The semiconductor device according to any one of claims 5 to 9, wherein, the conductive structure includes an oval shape having an edge that contacts at least one of the semiconductor bodies along the second direction.

11. The semiconductor device according to any one of claims 5 to 10, comprising: two word lines spaced apart along the second direction, wherein each of the two word lines is coupled to a corresponding one of the two adjacent memory cells, and each word line extends in a third direction orthogonal to the first direction and the second direction; and two rows of memory cells, wherein each row of memory cells extends along the third direction and is coupled to a corresponding one of the two word lines.

12. The semiconductor device according to claim 11, wherein, the conductive structure extends along the third direction and has opposite sides along the second direction; and wherein the two rows of memory cells are respectively coupled to the opposite sides of the conductive structure.

13. The semiconductor device according to claim 12, wherein, the conductive structure includes: a first portion extending along the third direction and coupled to the semiconductor bodies of the two rows of memory cells along the second direction; and one or more second portions extending along the second direction, and each of the one or more second portions is between adjacent semiconductor bodies along the third direction.

14. The semiconductor device according to claim 12 or 13, wherein, the conductive structure includes a first conductor and a second conductor spaced apart from each other along the second direction; and wherein the first conductor is coupled to the first row of memory cells of the two rows of memory cells, and the second conductor is coupled to the second row of memory cells of the two rows of memory cells.

15. The semiconductor device according to claim 14, wherein: the first conductor includes: a first portion extending along the third direction and coupled to the semiconductor body of the first row of memory cells of the two rows of memory cells along the second direction; and one or more second portions extending along the second direction, and each of the one or more second portions is between adjacent semiconductor bodies along the third direction; and the second conductor includes: a third portion extending along the third direction and coupled to the semiconductor body of the second row of memory cells of the two rows of memory cells along the second direction; and one or more fourth portions extending along the second direction, and each of the one or more fourth portions is between adjacent semiconductor bodies along the third direction.

16. The semiconductor device according to any one of claims 12 to 15, wherein, the conductive structure includes a plurality of conductors spaced apart from each other along the third direction; and Each of the plurality of conductors is coupled to a corresponding adjacent memory cell along the second direction.

17. The semiconductor device according to any one of claims 12 to 16, wherein, each of the word lines is coupled to a first connection structure, and the first connection structure is positioned along the third direction to be relatively closer to the first memory cell in the corresponding row of memory cells than to the last memory cell in the corresponding row of memory cells; and wherein the conductive structure is coupled to a second connection structure, and the second connection structure is positioned to be relatively closer to the last memory cell in the corresponding row of memory cells than to the first memory cell in the corresponding row of memory cells.

18. The semiconductor device according to any one of claims 12 to 17, comprising a semiconductor substrate having first and second opposite sides, wherein, each of the word lines is coupled to a first connection structure located at the first side of the semiconductor substrate; and wherein the conductive structure is coupled to a second connection structure located at the second side of the semiconductor substrate.

19. A method of forming a semiconductor device, comprising: forming two adjacent memory cells in a semiconductor substrate, wherein each of the two adjacent memory cells includes a transistor having a semiconductor body, a first terminal, a second terminal, and a gate terminal; and forming a conductive structure between the transistors of the two adjacent memory cells, the conductive structure being in contact with at least one of the semiconductor bodies of the transistors of the two adjacent memory cells, wherein the conductive structure is spaced apart from the first terminal and the second terminal of each of the transistors of the two adjacent memory cells.

20. A semiconductor device, comprising: two adjacent semiconductor bodies; a conductive structure between the two adjacent semiconductor bodies, the conductive structure being in contact with at least one of the two adjacent semiconductor bodies; and two conductive lines on opposite sides of the conductive structure, wherein each of the two conductive lines is coupled to a corresponding connection structure at an end of the conductive line, wherein the conductive structure is coupled to a corresponding connection structure at an end of the conductive structure, and wherein at least one of the adjacent ones of the corresponding connection structures coupled to the two conductive lines and the corresponding connection structure coupled to the conductive structure is at a relative end on the same side or opposite sides of the semiconductor device.

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