Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device, the display substrate comprises a plurality of pixel island areas (Q1), a plurality of opening areas (Q2) and a plurality of connection bridge areas (Q3), the pixel island areas (Q1) comprise transition areas (Q11) connected with the connection bridge areas (Q3) and pixel areas (Q12); the display substrate comprises a substrate 1, and a first gate insulating layer 2, a second gate insulating layer 3 and an interlayer insulating layer 4 which are sequentially stacked in the direction away from the substrate 1, orthographic projections of the first gate insulating layer 2, the second gate insulating layer 3 and the interlayer insulating layer 4 on the substrate 1 cover the pixel region (Q12) and extend to the transition region (Q11); and the cut-off positions of the first gate insulating layer 2, the second gate insulating layer 3 and the interlayer insulating layer 4 in the transition region (Q11) are different in the direction from the pixel island region (Q1) to the connection bridge region (Q3).

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] With the development of display technology, flexible organic light-emitting diodes (OLEDs) have promoted the diversification of displays and gradually become the mainstream of display technology. In some related technologies, OLED flexible display devices can meet the bending requirements of two-dimensional surfaces, but are not suitable for the flexible display substrates required for more complex display devices (such as wearable devices).

[0003] In order to develop the display function of OLED flexible display devices, some related technologies form islands for preparing pixel areas and bridges for routing by opening holes in the base material of the OLED flexible display device, and the stretching of the display device is achieved through the deformation of the bridges.

[0004] Summary of the Invention

[0005] The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The specific solutions are as follows:

[0006] The present disclosure provides a display substrate comprising a plurality of pixel island regions, a plurality of opening regions and a plurality of connection bridge regions, wherein the pixel island regions comprise transition regions connected to the connection bridge regions and pixel regions;

[0007] The display substrate includes: a base, and a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer stacked in sequence in a direction away from the base; wherein the orthographic projections of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer on the base all cover the pixel area and extend to the transition area; and in a direction from the pixel island area to the connecting bridge area, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer have different cutoff positions in the transition area.

[0008] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the second gate insulation layer is adjacent to the connection bridge region at the cutoff position of the transition region, and the cutoff position of the first gate insulation layer in the transition region and the cutoff position of the interlayer insulation layer in the transition region are both far away from the connection bridge region.

[0009] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the transition region is divided into a first region, a second region, and a third region along a direction from the pixel island region to the connecting bridge region, the orthographic projection of the second gate insulation layer on the substrate covers the orthographic projection of the transition region on the substrate, the orthographic projection of the first gate insulation layer on the substrate covers the orthographic projections of the first region and the second region on the substrate, and the orthographic projection of the interlayer insulation layer on the substrate covers the orthographic projection of the first region on the substrate.

[0010] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the display substrate further includes a first flat layer, a second flat layer, and a passivation layer stacked sequentially on a side of the interlayer insulating layer away from the substrate, wherein the orthographic projections of the first flat layer and the second flat layer on the substrate both cover the pixel island area and the connecting bridge area, and the orthographic projection of the passivation layer on the substrate at least covers the pixel island area; wherein,

[0011] The first flat layer and the second flat layer have a first partition groove penetrating the first flat layer and the second flat layer in the transition area, the passivation layer covers the first partition groove, and the first partition groove above the passivation layer is filled with an organic compensation layer so that the overall thickness of the transition area is consistent with the overall thickness of the pixel area of ​​the pixel island area.

[0012] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the display substrate further includes a pixel defining layer, a spacer, and an organic encapsulation layer stacked in sequence on a side of the passivation layer away from the substrate, and the organic compensation layer is made of the same material as one of the pixel defining layer, the spacer, and the organic encapsulation layer.

[0013] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the display substrate further includes: a barrier layer disposed between the substrate and the first gate insulating layer, a buffer layer disposed between the barrier layer and the first gate insulating layer, a first inorganic encapsulation layer disposed between the spacer and the organic encapsulation layer, and a second inorganic encapsulation layer disposed on a side of the organic encapsulation layer facing away from the substrate;

[0014] A first isolation column is provided on one side of the transition zone close to the opening zone, and the first isolation column is composed of at least part of the film layer of the barrier layer, the buffer layer, the first gate insulation layer, the second gate insulation layer, the passivation layer, the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0015] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the first isolation column is composed of the blocking layer, the buffer layer, the first gate insulation layer, the second gate insulation layer, the passivation layer, the organic compensation layer, the first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer.

[0016] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the first isolation column is composed of the blocking layer, the buffer layer, the first gate insulation layer, the second gate insulation layer, the passivation layer, the first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer.

[0017] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, a side of the first isolation column close to the opening area is disposed closely adjacent to the opening area.

[0018] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, a first preset distance exists between a side of the first isolation column close to the opening area and the opening area.

[0019] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the first preset distance is 1 μm to 5 μm.

[0020] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, a second isolation column is provided on the other side of the transition region close to the opening region, and the second isolation column has the same film layer structure as the first isolation column.

[0021] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the second isolation column and the first isolation column are symmetrically arranged about the center of the transition region.

[0022] In one possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, a third isolation column extending along the extension direction of the connecting bridge area is provided on the side of the connecting bridge area close to the opening area, and the third isolation column is composed of at least part of the film layer of the blocking layer, the buffer layer, the passivation layer, the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0023] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the third isolation column is composed of the barrier layer, the buffer layer, the first flat layer, the second flat layer, the passivation layer, the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0024] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the third isolation column is composed of the barrier layer, the buffer layer, the first planar layer, and the second planar layer.

[0025] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the third isolation column is disposed adjacent to the opening area on a side close to the opening area.

[0026] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, a second preset distance exists between a side of the third isolation column close to the opening area and the opening area.

[0027] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the second preset distance is 1 μm to 3 μm.

[0028] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, a fourth isolation column extending along the extension direction of the connecting bridge area is provided on the other side of the connecting bridge area close to the opening area, and the fourth isolation column and the third isolation column have the same film layer structure.

[0029] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the fourth isolation column and the third isolation column are symmetrically arranged about the center of the connecting bridge area.

[0030] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the third isolation column and the first isolation column are located on the same side, and the third isolation column and the first isolation column are disconnected from each other.

[0031] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the spacer is arranged on a side of the pixel island area close to the connecting bridge area, and / or the spacer is arranged on a side of the connecting bridge area close to the pixel island area.

[0032] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the number of the spacers provided in each pixel island region and the connected connecting bridge region is 1 to 4.

[0033] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the display substrate further includes: an anode disposed between the passivation layer and the pixel defining layer, an organic light-emitting layer disposed between the pixel defining layer and the first inorganic encapsulation layer, and a cathode disposed between the organic light-emitting layer and the first inorganic encapsulation layer;

[0034] A second partition groove is provided at a position of the pixel region close to the transition region, the organic light emitting layer is disconnected at the second partition groove, the cathode is disconnected at the second partition groove, and the first inorganic encapsulation layer covers the second partition groove.

[0035] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the second partition groove penetrates at least a portion of the passivation layer and the second flat layer, a side of the passivation layer close to the second partition groove protrudes out of a side of the second flat layer close to the second partition groove, and the second partition groove is a closed structure arranged around the transition region.

[0036] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the display substrate further includes: a first gate metal layer disposed between the first gate insulating layer and the second gate insulating layer, a second gate metal layer disposed between the second gate insulating layer and the interlayer insulating layer, a first source-drain metal layer disposed between the interlayer insulating layer and the first planarizing layer, and a second source-drain metal layer disposed between the first planarizing layer and the second planarizing layer;

[0037] The pixel island region includes at least one sub-pixel, and the display substrate further includes a plurality of signal lines disposed in the connection bridge region and extending to the pixel island region and electrically connected to the sub-pixel; wherein,

[0038] The multiple signal lines include a first signal line and a second signal line arranged in a stacked manner, wherein a portion of the first signal line located in the pixel island area is arranged in the first gate metal layer, and a portion of the first signal line located in the connecting bridge area is arranged in the first source-drain metal layer; a portion of the second signal line located in the pixel island area is arranged in the second gate metal layer, and a portion of the second signal line located in the connecting bridge area is arranged in the second source-drain metal layer.

[0039] Correspondingly, an embodiment of the present disclosure also provides a display substrate, comprising a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions, wherein the pixel island region comprises a transition region connected to the connecting bridge region and a pixel region; a first isolation column composed of at least a partial inorganic film layer is provided on at least one side of the transition region close to the opening region.

[0040] Correspondingly, an embodiment of the present disclosure also provides a display substrate, comprising a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions, wherein at least one side of the connecting bridge region close to the opening region is provided with a third isolation column extending along the extension direction of the connecting bridge region and composed of at least a partial inorganic film layer.

[0041] Accordingly, an embodiment of the present disclosure further provides a display substrate comprising a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions, wherein the pixel island regions comprise transition regions connected to the connecting bridge regions and pixel regions; wherein,

[0042] A first isolation column composed of at least a partial inorganic film layer is provided on at least one side of the transition zone close to the opening zone, and a third isolation column extending along the extension direction of the connecting bridge zone and composed of at least a partial inorganic film layer is provided on at least one side of the connecting bridge zone close to the opening zone.

[0043] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate provided by an embodiment of the present disclosure.

[0044] Accordingly, the embodiment of the present disclosure further provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate provided by the embodiment of the present disclosure. The manufacturing method includes:

[0045] forming a plurality of pixel island regions, a plurality of opening regions and a plurality of connection bridge regions on a substrate, wherein the pixel island regions include transition regions connected to the connection bridge regions and pixel regions;

[0046] A first gate insulating layer, a second gate insulating layer and an interlayer insulating layer are stacked in sequence along a direction away from the substrate; wherein the orthographic projections of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer on the substrate all cover the pixel area and extend to the transition area; and in a direction from the pixel island area to the connecting bridge area, the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer have different cutoff positions in the transition area. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of a planar structure of a display substrate provided by an embodiment of the present disclosure;

[0048] FIG2A is a schematic diagram of a partially enlarged structure in FIG1 ;

[0049] FIG2B is another partial enlarged structural schematic diagram of FIG1 ;

[0050] FIG3 is a schematic diagram of a cross-sectional structure along the AA′ direction in FIG2A and FIG2B ;

[0051] FIG4 is another schematic cross-sectional view of FIG2A and FIG2B along the AA' direction;

[0052] FIG5 is another schematic cross-sectional view of FIG2A and FIG2B along the AA' direction;

[0053] FIG6 is a schematic diagram of a cross-sectional structure along the DD' direction in FIG2A;

[0054] FIG7 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0055] FIG8 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0056] FIG9 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0057] FIG10 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0058] FIG11 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0059] FIG12 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0060] FIG13 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0061] FIG14 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0062] FIG15 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0063] FIG16 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0064] FIG17 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0065] FIG18 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0066] FIG19 is another schematic cross-sectional view of FIG2A along the DD' direction;

[0067] FIG20 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0068] FIG21 is another schematic cross-sectional view of FIG2B along the DD' direction;

[0069] FIG22 is a schematic diagram of a cross-sectional structure along the CC' direction in FIG2A;

[0070] FIG23 is another schematic cross-sectional view of FIG2B along the CC' direction;

[0071] FIG24 is a schematic diagram of another cross-sectional structure along the CC' direction in FIG2A;

[0072] FIG25 is another schematic cross-sectional view of FIG2B along the CC' direction;

[0073] FIG26 is another schematic cross-sectional view of FIG2A along the CC' direction;

[0074] FIG27 is a schematic diagram of another cross-sectional structure along the CC' direction in FIG2B;

[0075] FIG28 is another schematic cross-sectional view of FIG2A along the CC' direction;

[0076] FIG29 is a schematic diagram of another cross-sectional structure along the CC' direction in FIG2B;

[0077] FIG30 is another schematic cross-sectional view of FIG2B along the CC' direction;

[0078] FIG31 is another partial enlarged structural schematic diagram of FIG1 ;

[0079] FIG32 is another partial enlarged structural schematic diagram of FIG1;

[0080] FIG33 is a schematic diagram of a 2T1C pixel circuit;

[0081] FIG34 is a schematic diagram of a pixel circuit of 3T1C;

[0082] FIG35 is a schematic diagram of a pixel circuit of 7T1C;

[0083] FIG36 is another schematic cross-sectional view of FIG2A and FIG2B along the AA' direction;

[0084] FIG37 is a schematic flow chart of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

[0085] 38A to 38C are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0086] 39A and 39B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0087] 40A and 40B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0088] 41A and 41B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0089] 42A and 42B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0090] FIG43 is a schematic structural diagram of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0091] 44A and 44B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0092] 45A and 45B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0093] 46A and 46B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0094] 47A and 47B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0095] 48A, 48B, and 48C are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0096] FIG49 is a schematic structural diagram of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0097] FIG50 is a schematic structural diagram of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0098] 51A and 51B are schematic structural diagrams of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0099] FIG52 is a schematic structural diagram of a display substrate in a manufacturing process according to an embodiment of the present disclosure;

[0100] Figures 53A, 53B and 53C are schematic structural diagrams corresponding to the manufacturing process of a display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0101] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0102] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0103] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0104] A display substrate (e.g., a stretchable display substrate) generally includes a pixel island region, a connecting bridge region, and an open area surrounded by the pixel island region and the connecting bridge region. The light-emitting structure and the driving circuit are placed in the pixel island region, and adjacent pixel island regions are connected for signal through metal traces on the connecting bridge region. During the stretching process of the display substrate, the pixel island region does not deform, and the connecting bridge region takes on large deformations to achieve a stress / strain isolation design of the pixel island device and achieve the stretching deformation capability of the island-bridge structure during the stretching process. However, during the stretching deformation process, stress concentration usually occurs at the connection position between the pixel island region and the connecting bridge region. Therefore, cracking of the film layer is very likely to occur at the connection position between the pixel island region and the connecting bridge region, especially cracking of the inorganic film layer.

[0105] In order to solve the problem that film layer fractures are very likely to occur at the connection position between pixel island areas and connecting bridge areas, the present disclosure provides a display substrate, as shown in Figures 1, 2A and 2B. Figure 1 is a schematic diagram of the planar structure of the display substrate, Figure 2A is a schematic diagram of a partially enlarged structure in Figure 1, and Figure 2B is a schematic diagram of another partially enlarged structure in Figure 1. The display substrate includes multiple pixel island areas Q1, multiple opening areas Q2 and multiple connecting bridge areas Q3. The pixel island area Q1 includes a transition area Q11 connected to the connecting bridge area Q3 and a pixel area Q12; specifically, the pixel island area Q1 is used to display images, the connecting bridge area Q3 is used for routing (to connect signals between adjacent pixel island areas Q1) and to transmit tensile force, and the opening area Q2 is used to provide deformation space for the display substrate when stretched;

[0106] As shown in Figures 3 to 5, Figures 3 to 5 are schematic diagrams of several cross-sectional structures along the AA' direction in Figure 2A, respectively. The display substrate includes: a substrate 1, and a first gate insulating layer 2, a second gate insulating layer 3, and an interlayer insulating layer 4 stacked in sequence along a direction away from the substrate 1; wherein, the orthographic projections of the first gate insulating layer 2, the second gate insulating layer 3, and the interlayer insulating layer 4 on the substrate 1 all cover the pixel area Q12 and extend to the transition area Q11; along the direction from the pixel island area Q1 to the connecting bridge area Q3, the cutoff positions of the first gate insulating layer 2, the second gate insulating layer 3, and the interlayer insulating layer 4 in the transition area Q11 are different, that is, the orthographic projection boundaries of the first gate insulating layer 2, the second gate insulating layer 3, and the interlayer insulating layer 4 in the transition area Q11 of the substrate 1 do not overlap with each other.

[0107] The above-mentioned display substrate provided by the embodiment of the present disclosure has different cutoff positions of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer in the transition zone, so that a rigid gradient change design of the transition zone from the pixel island area to the connecting bridge area can be achieved, thereby reducing the risk of fracture failure at the island-bridge connection position during the stretching process.

[0108] Specifically, as shown in Figures 1, 2A and 2B, the pixel area Q12 of each pixel island area Q1 includes at least one sub-pixel, and the sub-pixel includes a light-emitting structure and a driving circuit. Figures 1, 2A and 2B provided in the present disclosure are based on the example that each pixel island area Q1 includes three sub-pixels. These three sub-pixels can be a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, respectively, but are of course not limited to this.

[0109] Specifically, as shown in Figures 3-5, substrate 1 can be a flexible substrate, allowing the stretchable region of the display substrate to be stretched. Substrate 1 can include a single flexible layer, or can include a first flexible layer, a barrier layer, and a second flexible layer stacked together. The present disclosure uses the example of substrate 1 including a single flexible layer. Specifically, the material of the flexible layer can be polyimide (PI), polyester, polyamide, or the like.

[0110] Specifically, as shown in Figures 3 to 5, the base 1 and the film layers thereon can be arranged on a glass substrate with a supporting function. After the production of each film layer is completed, the glass substrate is peeled off to obtain a stretchable display substrate, which becomes a stretchable display substrate.

[0111] It should be noted that, as shown in Figures 1, 2A, and 2B, the opening area Q2 in the embodiment of the present disclosure may completely penetrate the display substrate. Of course, the opening area Q2 may also penetrate at least a portion of the film layer on the base 1 of the display substrate and a portion of the base 1. The embodiment of the present disclosure takes the case where the opening area Q2 completely penetrates the display substrate as an example.

[0112] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, the display substrate further includes a first flat layer 5, a second flat layer 6 and a passivation layer 7 stacked in sequence on the side of the interlayer insulating layer 4 away from the substrate 1. The orthographic projections of the first flat layer 5 and the second flat layer 6 on the substrate 1 both cover the pixel island area Q1 and the connecting bridge area Q3, and the orthographic projection of the passivation layer 7 on the substrate 1 at least covers the pixel island area Q1.

[0113] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, the display substrate also includes: a pixel defining layer 8, a spacer (not shown) and an organic encapsulation layer 9 stacked in sequence on the side of the passivation layer 7 away from the substrate 1, a barrier layer 10 arranged between the substrate 1 and the first gate insulating layer 2, a buffer layer 11 arranged between the barrier layer 10 and the first gate insulating layer 2, a first inorganic encapsulation layer 12 arranged between the spacer and the organic encapsulation layer 9, and a second inorganic encapsulation layer 13 arranged on the side of the organic encapsulation layer 9 away from the substrate 1; wherein the orthographic projection of the organic encapsulation layer 9 on the substrate 1 covers the pixel island area Q1 and the orthographic projection boundary ends on the side close to the connecting bridge area Q3. The first inorganic encapsulation layer 12, the organic encapsulation layer 9 and the second inorganic encapsulation layer 13 can reduce the intrusion of water vapor in the external environment into the light-emitting device of the sub-pixel, thereby reducing the probability of failure of the light-emitting device.

[0114] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3-5, the pixel island area Q1 also includes an anode 14 arranged between the passivation layer 7 and the pixel defining layer 8, and the pixel defining layer 8 has a pixel opening to expose the anode 14. The pixel island area Q1 also includes an organic light-emitting layer 15 arranged between the pixel defining layer 8 and the first inorganic encapsulation layer 12 and at least covering the pixel opening, and a cathode 16 arranged between the organic light-emitting layer 15 and the first inorganic encapsulation layer 12. The anode 14, the organic light-emitting layer 15 and the cathode 16 constitute a light-emitting device.

[0115] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, the display substrate further includes: a first gate metal layer G1 arranged between the first gate insulating layer 2 and the second gate insulating layer 3, a second gate metal layer G2 arranged between the second gate insulating layer 3 and the interlayer insulating layer 4, a first source-drain metal layer SD1 arranged between the interlayer insulating layer 4 and the first flat layer 5, and a second source-drain metal layer SD2 arranged between the first flat layer 5 and the second flat layer 6; the pixel island region Q1 further includes a driving circuit arranged between the buffer layer 11 and the anode 14, the driving circuit including a thin film transistor and a storage Storage capacitor; wherein, the thin film transistor includes: an active layer Act arranged between the buffer layer 11 and the first gate insulating layer 2, a gate G arranged on the first gate metal layer G1, a source S and a drain D arranged on the first source-drain metal layer SD1; the storage capacitor includes: a first electrode C1 arranged on the first gate metal layer, and a second electrode C2 arranged on the second gate metal layer; the second source-drain metal layer SD2 includes a lap 17, a data line, etc., the anode 14 is electrically connected to the lap 17 through a via hole that sequentially penetrates the passivation layer 7 and the second flat layer 6, and the lap 12 is electrically connected to the drain D through a via hole that penetrates the first flat layer 5.

[0116] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, the display substrate also includes a plurality of signal lines arranged in the connecting bridge area Q3 and extending to the pixel island area Q1 to be electrically connected to the sub-pixels, and the plurality of signal lines include a first signal line 18 and a second signal line 19 arranged in a stacked manner, a portion of the first signal line 18 located in the pixel island area Q1 is arranged in the first gate metal layer G1, and a portion of the first signal line 19 located in the connecting bridge area Q3 is arranged in the first source and drain metal layer SD1; a portion of the second signal line 19 located in the pixel island area Q1 is arranged in the second gate metal layer G2, and a portion of the second signal line 19 located in the connecting bridge area Q3 is arranged in the second source and drain metal layer SD2.

[0117] In a specific implementation, since the pixel island areas are connected to each other through the metal routing located in the connecting bridge area, the metal routing needs to pass through the transition area to be led to the connecting bridge area after being connected to the sub-pixels in the pixel island area, and the metal routing located in the pixel island area generally goes through the first gate metal layer (for example, the first signal line) and the second gate metal layer (for example, the second signal line), and then in the transition area near the connecting bridge area, the first signal line jumps to the first source and drain metal layer, and the second signal line jumps to the second source and drain metal layer. In order to avoid the short circuit between the first signal line and the second signal line, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, the second gate insulating layer 3 between the first gate metal layer and the second gate metal layer is set at the cut-off position of the transition area Q11 adjacent to the connecting bridge area Q3, and the second gate insulating layer 3 can make the first gate metal layer G1 and The second gate metal layer G2 is insulated, and the cutoff position of the first gate insulating layer 2 in the transition area Q11 and the cutoff position of the interlayer insulating layer 4 in the transition area Q11 are both far away from the connecting bridge area Q3. In this way, the area of ​​the transition area Q11 close to the pixel area Q12 is a three-layer stacked structure of the first gate insulating layer 2, the second gate insulating layer 3 and the interlayer insulating layer 4, with the maximum stiffness; the area of ​​the transition area Q11 close to the connecting bridge area Q3 is a single-layer structure of the second gate insulating layer 3, with the minimum stiffness; between the three-layer stacked structure and the single-layer structure is a two-layer stacked structure of the first gate insulating layer 2 and the second gate insulating layer 3 or a two-layer stacked structure of the second gate insulating layer 3 and the interlayer insulating layer 4, so that the rigidity gradient change design of the transition area Q11 from the pixel island area Q1 to the connecting bridge area Q3 can be realized, thereby reducing the risk of fracture failure at the island-bridge connection position during the stretching process.

[0118] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, the transition area Q11 can be divided into a first area Q111, a second area Q112 and a third area Q113 along the direction from the pixel island area Q1 to the connecting bridge area Q3, and the orthographic projection of the second gate insulation layer 3 on the substrate 1 covers the orthographic projection of the transition area Q11 on the substrate 1, that is, the orthographic projection of the second gate insulation layer 3 on the substrate 1 covers the orthographic projections of the first area Q111, the second area Q112 and the third area Q113 on the substrate 1, the orthographic projection of the first gate insulation layer 2 on the substrate 1 covers the orthographic projections of the first area Q111 and the second area Q112 on the substrate 1, and the orthographic projection of the interlayer insulation layer 4 on the substrate 1 covers the orthographic projection of the first area Q111 on the substrate 1. That is, when the first gate insulating layer 2, the second gate insulating layer 3 and the interlayer insulating layer 4 are manufactured, the first gate insulating layer 2 located in the third region Q113, the connecting bridge region Q3 and the opening region Q2 is removed, the second gate insulating layer 3 located in the connecting bridge region Q3 and the opening region Q2 is removed, and the interlayer insulating layer 4 located in the second region Q112, the third region Q113, the connecting bridge region Q3 and the opening region Q2 is removed. In this way, the first region Q111 of the transition region Q11 close to the pixel region Q12 is the first gate insulating layer 2, the second gate insulating layer 3 and the interlayer insulating layer 4. The inter-insulating layer 4 has a three-layer stacked structure with the greatest rigidity; the third region Q113 of the transition region Q11 close to the connecting bridge region Q3 is a single-layer structure of the second gate insulating layer 3, with the smallest rigidity; the second region Q112 between the first region Q111 and the third region Q113 is a two-layer stacked structure of the first gate insulating layer 2 and the second gate insulating layer 3, so that a rigidity gradient change design can be achieved in the transition region Q11 from the pixel island region Q1 to the connecting bridge region Q3, thereby reducing the risk of fracture failure at the island-bridge connection position during stretching.

[0119] Of course, in a specific implementation, the orthographic projection of the first gate insulating layer 2 on the substrate 1 may cover the orthographic projection of the first region Q111 on the substrate 1, and the orthographic projection of the interlayer insulating layer 4 on the substrate 1 may cover the orthographic projections of the first region Q111 and the second region Q112 on the substrate 1. In this way, the second region Q112 between the first region Q111 and the third region Q113 is a two-layer stacked structure of the second gate insulating layer 3 and the interlayer insulating layer 4. At the same time, a rigid gradient change design of the transition region Q11 from the pixel island region Q1 to the connecting bridge region Q3 can also be realized.

[0120] Optionally, as shown in FIG3-FIG5 , the width of the first region Q111 , the width of the second region Q112 , and the width of the third region Q113 may be distributed at equal distances, or may be unequal, and may be designed according to actual needs.

[0121] Specifically, as shown in Figures 3 to 5, the first signal line 18 located in the first gate metal layer G1 of the pixel island area Q1 jumps to the first source-drain metal layer SD1 in the connecting bridge area Q3, and the second signal line 19 located in the second gate metal layer G2 of the pixel island area Q1 jumps to the second source-drain metal layer SD2 in the third area Q113 near the connecting bridge area Q3 through a via penetrating the first flat layer 5; optionally, the first signal line 18 can be a power line (such as VDD, VSS), a gate line, etc., and the second signal line 19 can be a data line, a sensing signal line, etc.

[0122] Specifically, as shown in Figures 3 to 5, since the orthographic projection boundary of the first gate insulating layer 2 ends at the second area Q112, when the first signal line 18 extends from the pixel area Q12 to the third area Q113, the first signal line 18 will form a first step structure at the junction of the second area Q112 and the third area Q113. Therefore, the subsequently produced film layers, such as the gate insulating layer 3 and the second signal line 19, will also form a step structure at the position of the first step structure; since the second signal line 19 jumps to the second source-drain metal layer SD2 through a via penetrating the first flat layer 5 at a position near the connecting bridge area Q3 in the third area Q113, the second signal line 19 forms a second step structure at the position of the via penetrating the first flat layer 5. Since the thickness of the first flat layer 5 is generally higher than the height of the first gate insulating layer 2, the height of the second step structure formed by the second signal line 19 at the position of the via penetrating the first flat layer 5 is higher than the height of the first step structure.

[0123] It should be noted that the jumper mode of the first signal line 18 and the second signal line 19 is not limited to the jumper from G1 to SD1 and from G2 to SD2, but can also be from G1 to SD1 and then from SD1 to SD2.

[0124] In some embodiments, as shown in Figures 3-5, the orthographic projection of the first signal line 18 on the substrate 1 at least partially overlaps with the orthographic projection of the second signal line 19 on the substrate 1, and the edge of the orthographic projection of the first signal line 18 on the substrate 1 close to the substrate 1 is closer to the connecting bridge area Q3 than the edge of the orthographic projection of the second signal line 19 on the substrate 1. This helps to ensure that the two signal lines 19 are not easily broken during the stretching process.

[0125] In some embodiments, as shown in Figures 3 to 5, the first signal line 18 located in the first gate metal layer SD1 of the pixel island area Q1 jumps to the first source-drain metal layer SD1 in the connecting bridge area Q3, and the second signal line 19 located in the second gate metal layer of the pixel island area Q1 jumps to the second source-drain metal layer SD2 through a via penetrating the first flat layer 5 in the third area Q113 near the connecting bridge area Q3. The jumper position of the first signal line 18 in the connecting bridge area Q3 is staggered with the via jumper position of the second signal line 19, which is beneficial to improving the yield and is also beneficial to stress dispersion according to the jumper position during the stretching process. In some embodiments, as shown in FIG3-FIG5, the first signal line 18 of the pixel island region Q1 located on the first gate metal layer G1 jumps to the first source-drain metal layer SD1 in the connecting bridge region Q3, and the second signal line 19 of the pixel island region Q1 located on the second gate metal layer G2 jumps to the second source-drain metal layer SD2 in the third region Q113 near the connecting bridge region Q3 through a via penetrating the first flat layer 5; wherein the spacing between the first signal line 18 and the second signal line 19 in the connecting bridge region Q3 is greater than the spacing between the first signal line 18 and the second signal line 19 in the pixel island region Q1. 18 and the spacing between the second signal line 19 (for example: the first signal line 18 and the second signal line 19 in the connecting bridge area Q3 include a second gate insulating layer 3, an interlayer insulating layer 4, and a first flat layer 5, and the first signal line 18 and the second signal line 19 in the pixel island area Q1 include a second gate insulating layer 3). Such a design is conducive to ensuring that the first signal line 18 and the second signal line 19 do not interfere with each other in signal transmission in the connecting bridge area Q3, and at the same time ensure that the first signal line 18 and the second signal line 19 will not break due to more frequent stretching in the connecting bridge area Q3.

[0126] In a specific implementation, in the above-mentioned display substrate provided by the embodiment of the present disclosure, as shown in Figures 3 to 5, the first planar layer 5 and the second planar layer 6 have a first partition groove U1 that penetrates the first planar layer 5 and the second planar layer 6 in the transition area Q11. The first partition groove U1 can prevent water vapor in the first planar layer 5 and the second planar layer 6 on the connecting bridge area Q3 from penetrating from the transition area Q11 to the pixel island area Q1; the passivation layer 7 covers the first partition groove U1, that is, the passivation layer 7 covers the pixel island area Q1, the transition area Q11 and the connecting bridge area Q3, and the passivation layer 7 covers the side walls of the first partition groove U1 on both sides in the transition area Q11 and is connected to the second signal line 19 is in direct contact with the portion located in the transition area Q11, and the passivation layer 7 forms a step structure at the position of the step structure formed by the second signal line 19 in the third area Q113; in order to reduce the problem of large differences in stiffness matching of the three film layer stacks in the transition area Q11, the pixel area Q12 and the connecting bridge area Q3, the organic compensation layer 20 is filled in the first partition groove U1 above the passivation layer 7 to make the overall thickness of the transition area Q11 consistent with the overall thickness of the pixel area Q12 of the pixel island area Q1, thereby avoiding a large mutation in the stiffness of the transition area Q11 and further reducing the risk of fracture failure at the island-bridge connection position during stretching.

[0127] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as shown in Figure 3, the orthographic projection of the organic compensation layer 20 on the substrate 1 overlaps with the orthographic projections of the first gate insulating layer 2, the second gate insulating layer 3, and the interlayer insulating layer 4 on the substrate 1; and the orthographic projection of the organic compensation layer 20 on the substrate 1 is located within the orthographic projection of the second gate insulating layer 3 on the substrate 1.

[0128] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, as shown in Figure 3, the overlapping area of ​​the orthographic projection of the organic compensation layer 20 on the substrate 1 and the orthographic projection of the second gate insulating layer 3 on the substrate 1 is greater than the overlapping area of ​​the orthographic projection of the organic compensation layer 20 on the substrate 1 and the orthographic projection of the first gate insulating layer 2 on the substrate 1, and the center of gravity of the organic compensation layer 20 is close to the edge of the second gate insulating layer 3 (the center of gravity of the organic compensation layer 20 is roughly located at the portion where the second gate insulating layer 3 exceeds the edge of the first gate insulating layer 2), that is, most of the weight of the organic compensation layer 20 is located at the edge portion of the second gate insulating layer 3 that exceeds the first gate insulating layer 2, which is conducive to fixing the organic compensation layer 20 and the subsequent encapsulation layer.

[0129] In specific implementations, in the display substrate provided in the embodiments of the present disclosure, as shown in FIG3 , the organic compensation layer 20 can be made of the same material as the pixel defining layer 8. This allows the organic compensation layer 20 and the pixel defining layer 8 to be patterned together in a single process, eliminating the need for a separate process for preparing the organic compensation layer 20. This simplifies the manufacturing process, reduces production costs, and improves production efficiency.

[0130] In specific implementations, in the display substrate provided in the embodiments of the present disclosure, as shown in FIG4 , the organic compensation layer 20 can be made of the same material as the spacers. This allows the organic compensation layer 20 and the spacers to be patterned in a single process, eliminating the need for a separate process for preparing the organic compensation layer 20. This simplifies the manufacturing process, reduces production costs, and improves production efficiency.

[0131] 3 and 4 , the surface of the organic compensation layer 20 facing away from the substrate 1 may be arranged substantially flush with the surface of the pixel defining layer 8 facing away from the substrate 1 , so that the overall thickness of the transition region Q11 is substantially the same as the overall thickness of the pixel region Q12 of the pixel island region Q1 .

[0132] In a specific implementation, in the display substrate provided in the embodiment of the present disclosure, as shown in FIG5 , the organic compensation layer 20 can be made of the same material as the organic encapsulation layer 9. Thus, when forming the organic encapsulation layer 9, the first partition groove U1 is filled with an organic material. Therefore, there is no need to add a separate process for preparing the organic compensation layer 20, which can simplify the preparation process, save production costs, and improve production efficiency.

[0133] In some embodiments, as shown in Figure 5, the organic compensation layer 20 can be made of the same material as the organic encapsulation layer 9, that is, the thickness of the organic encapsulation layer 9 near the connecting bridge area Q3 is greater than the thickness of the organic encapsulation layer 9 in the pixel island area Q1. For example, the thickness of the organic encapsulation layer 9 near the connecting bridge area Q3 is greater than the height from the second source-drain metal layer SD2 (for example, the second source-drain metal layer includes the overlapping portion 17 and the data line) to the second inorganic encapsulation layer 13.

[0134] In a specific implementation, as shown in Figures 2A and 2B, during the stretching process of the display substrate, the two sides of the transition region Q11 close to the opening region Q2 are often the starting positions for forming Cracks. Therefore, in order to improve the tensile deformation ability of the display substrate, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, and 6-9, Figures 6 and 7 are schematic diagrams of two cross-sectional structures along the DD' direction in Figure 2A, respectively, and Figures 8 and 9 are partial schematic diagrams of two cross-sectional structures along the DD' direction in Figure 2B, respectively. A first isolation column E1 is provided on one side of the transition region Q11 close to the opening region Q2 (for example, point D), and the first isolation column E1 is composed of at least part of the film layer of the barrier layer 10, the buffer layer 11, the first gate insulation layer 2, the second gate insulation layer 3, the passivation layer 7, the first inorganic encapsulation layer 12, and the second inorganic encapsulation layer 13. By designing a first isolation column E1 composed of at least a partial inorganic film layer at the boundary position (for example, point D) of the transition area Q11 close to the opening area Q2, the inorganic film layer in the first isolation column E1 is physically separated from the inorganic film layer in the transition area Q11 away from the opening area Q2 and the pixel area Q12 along the DD' direction through processes such as photolithography / etching, so as to avoid the formation of cracks in the inorganic film layer close to the side of the opening area Q2 (for example, point D) during the stretching process and extending along the direction from D to D'. The first isolation column E1 has the effect of blocking the extension of cracks in the inorganic film layer at the junction of the pixel island area Q1 and the connecting bridge area Q3, reducing the risk of disconnection of the metal signal line at the connection position and the risk of rupture of the inorganic film layer in the pixel island area Q1, thereby improving the tensile deformation capacity of the display substrate.

[0135] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, 3, 6 and 8, when the organic compensation layer 20 and the pixel defining layer 8 are made of the same material, the first isolation column E1 can be composed of a barrier layer 10, a buffer layer 11, a first gate insulating layer 2, a second gate insulating layer 3, a passivation layer 7, an organic compensation layer 20 (pixel defining layer 8), a first inorganic encapsulation layer 12, an organic encapsulation layer 9 and a second inorganic encapsulation layer 13. In this way, the first isolation column E1 physically separates all inorganic and organic film layers on the side of the transition region Q11 close to the opening region Q2 from the inorganic and organic film layers far from the opening region Q2, which can completely block the effect of crack extension in the inorganic film layer, thereby further improving the tensile deformation capacity of the display substrate.

[0136] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, 4, 6 and 8, when the material of the organic compensation layer 20 is the same as that of the spacer, the first isolation column E1 can be composed of a blocking layer 10, a buffer layer 11, a first gate insulation layer 2, a second gate insulation layer 3, a passivation layer 7, an organic compensation layer 20 (spacer), a first inorganic encapsulation layer 12, an organic encapsulation layer 9 and a second inorganic encapsulation layer 13.

[0137] Specifically, as shown in FIG2A and FIG6 , the orthographic projections of the first side edges of the film layers in the first isolation column E1 on the side of the transition region Q11 close to the opening region Q2 (for example, point D) on the substrate 1 can overlap. Of course, this only means overlapping, and there may be a certain deviation. The orthographic projections of the second side edges of the barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 in the first isolation column E1 on the side of the transition region Q11 away from the opening region Q2 (for example, point D) on the substrate 1 can overlap. The organic compensation layer 20 (spacer) in the first isolation column E1 can cover the side away from the opening region Q2. The cover barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 are arranged in contact with the substrate 1. The first inorganic encapsulation layer 12 in the first isolation column E1 can cover the organic compensation layer 20 on the side away from the hole area Q2 and is arranged in contact with the substrate 1. The organic encapsulation layer 9 in the first isolation column E1 can cover a part of the side of the first inorganic encapsulation layer 12 on the side away from the hole area Q2. The second inorganic encapsulation layer 13 in the first isolation column E1 can cover a part of the side of the organic encapsulation layer 9 on the side away from the hole area Q2.

[0138] Specifically, as shown in Figures 2B and 8, the orthographic projections of the barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 in the first isolation column E1 on the substrate 1 can roughly overlap, the organic compensation layer 20 in the first isolation column E1 can wrap the barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 and be arranged in contact with the substrate 1, the first inorganic encapsulation layer 12 in the first isolation column E1 can wrap the organic compensation layer 20 and be arranged in contact with the substrate 1, the organic encapsulation layer 9 in the first isolation column E1 can cover a portion of the side of the first inorganic encapsulation layer 12 on the side away from the hole area Q2, and the orthographic projection of the second inorganic encapsulation layer 13 in the first isolation column E1 on the substrate 1 can cover the orthographic projection of the organic encapsulation layer 9 on the substrate 1.

[0139] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, 5, 7 and 9, when the material of the organic compensation layer 20 is the same as that of the organic encapsulation layer 9, the first isolation column E1 can be composed of a barrier layer 10, a buffer layer 11, a first gate insulation layer 2, a second gate insulation layer 3, a passivation layer 7, a first inorganic encapsulation layer 12, an organic encapsulation layer 9 and a second inorganic encapsulation layer 13.

[0140] Specifically, as shown in FIG2A and FIG7, the orthographic projections of the first side edges of the film layers in the first isolation column E1 on the side of the transition region Q11 close to the opening region Q2 (for example, point D) on the substrate 1 can overlap, of course, it means only overlapping, and there may be a certain deviation; the orthographic projections of the second side edges of the barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 in the first isolation column E1 on the side of the transition region Q11 away from the opening region Q2 (for example, point D) on the substrate 1 can overlap, and the first inorganic encapsulation layer 12 in the first isolation column E1 on the side away from the opening region Q2 can overlap. One side of the opening area Q2 can cover the blocking layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 away from the side of the opening area Q2 and be in contact with the substrate 1. The organic encapsulation layer 9 in the first isolation column E1 can cover a portion of the side of the first inorganic encapsulation layer 12 away from the side of the opening area Q2 on the side away from the opening area Q2. The second inorganic encapsulation layer 13 in the first isolation column E1 can cover a portion of the side of the organic encapsulation layer 9 away from the side of the opening area Q2 on the side away from the opening area Q2 and be in contact with the first inorganic encapsulation layer 12.

[0141] Specifically, as shown in Figures 2B and 9, the orthographic projections of the barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, and the passivation layer 7 in the first isolation column E1 on the substrate 1 can roughly overlap, the first inorganic encapsulation layer 12 in the first isolation column E1 can wrap the barrier layer 10, the buffer layer 11, the first gate insulating layer 2, the second gate insulating layer 3, the passivation layer 7 and be arranged in contact with the substrate 1, the organic encapsulation layer 9 in the first isolation column E1 can cover part of the side of the first inorganic encapsulation layer 12, and the second inorganic encapsulation layer 13 in the first isolation column E1 can wrap the organic encapsulation layer 9 and be arranged in contact with the first inorganic encapsulation layer 12.

[0142] In specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 6 and 7, the side of the first isolation column E1 close to the opening area Q2 (point D) can be set adjacent to the opening area Q2, that is, the first isolation column E1 is adjacent to the boundary position of the opening area Q2 (point D).

[0143] In a specific implementation, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 2B, 8, and 9, a first predetermined distance W1 is provided between the side of the first spacer E1 proximate to the opening region Q2 and the opening region Q2. By designing the first spacer E1 so that it is not immediately adjacent to the boundary position (point D) of the opening region Q2, i.e., the first spacer E1 is designed to have the inorganic and organic film layers recessed at the boundary position (point D) of the opening region Q2, completely removing the inorganic and organic film layers above the substrate 1 immediately adjacent to the boundary position (point D) of the opening Q2. For example, the inorganic and organic film layers are recessed by 1 μm to 5 μm along the DD' direction, i.e., the first predetermined distance W1 is 1 μm to 5 μm. Compared to the non-retracted design of Figures 6 and 7, the recessed inorganic and organic film layers of the first spacer E1 can further enhance the tensile deformation capability of the transition region Q11.

[0144] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, 10 to 13, Figures 10 and 11 are respectively two more schematic cross-sectional structural diagrams along the DD' direction in Figure 2A, and Figures 12 and 13 are respectively two more schematic cross-sectional structural diagrams along the DD' direction in Figure 2B. A second isolation column E2 is provided on the other side of the transition region Q11 close to the opening region Q2 (for example, point D'), and the second isolation column E2 has the same film layer structure as the first isolation column E1. By designing a second isolation column E2 at another boundary position (for example, point D') of the transition region Q11 close to the opening region Q2, the inorganic film layer and the organic film layer in the second isolation column E2 are physically separated from the inorganic film layer and the organic film layer in the transition region Q11 along the DD' direction away from the opening region Q2 and the pixel region Q12 by processes such as photolithography / etching, so as to prevent the inorganic film layer on the other side of the opening region Q2 (for example, point D') from forming a crack during the stretching process and extending along the direction from D' to D. The second isolation column E2 has the effect of blocking the extension of cracks in the inorganic film layer, thereby improving the tensile deformation capacity of the display substrate.

[0145] In specific implementations, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 2A, 2B, and 10-13, the second isolation pillars E2 and the first isolation pillars E1 can be symmetrically arranged about the center of the transition region Q11. Of course, this arrangement is not limited to the symmetrical arrangement shown in Figures 10-13. For example, the first isolation pillars E1 can be positioned adjacent to the opening region Q2, while the second isolation pillars E2 can be recessed. Alternatively, the first isolation pillars E1 can be recessed, while the second isolation pillars E2 can be positioned adjacent to the opening region Q2.

[0146] It should be noted that the signal lines connecting the adjacent pixel island areas Q1 on the display substrate shown in Figures 6 to 13 adopt a double-layer routing design. In this way, the signal line layer at the middle position from point D to point D' can be a double-layer routing design of the first gate metal layer and the second gate metal layer. The first gate metal layer and the second gate metal layer are separated by the second gate insulation layer 3, which can reduce the width of the transition area Q11 along the DD' direction, thereby saving the space area requirement of the transition area Q11.

[0147] Of course, in a specific implementation, the signal line connecting the adjacent pixel island area Q1 in the display substrate can also adopt a single-layer routing design (for example, only the first gate metal layer or only the second gate metal layer routing). The embodiment of the present disclosure adopts the first gate metal layer single-layer routing, as shown in Figures 14 to 21. The difference between Figure 14 and Figure 6 is only that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same; the difference between Figure 15 and Figure 7 is only that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same; the difference between Figure 16 and Figure 8 is only that the first gate metal layer is adopted. Single-layer routing design, the rest of the structure is the same; the only difference between Figure 17 and Figure 9 is that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same; the only difference between Figure 18 and Figure 10 is that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same; the only difference between Figure 19 and Figure 11 is that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same; the only difference between Figure 20 and Figure 12 is that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same; the only difference between Figure 21 and Figure 13 is that the first gate metal layer single-layer routing design is adopted, and the rest of the structure is the same.

[0148] In a specific implementation, in the display substrate provided by the embodiment of the present disclosure, as shown in FIG. 6 to FIG. 21 , the width of the first isolation column E1 and the second isolation column E2 along the DD′ direction may be 3 μm to 10 μm.

[0149] It should be noted that the patterns of the film layers in the first isolation columns E1 at the same position in Figures 6 to 21 may be different due to reasons such as the manufacturing process, and the patterns of the film layers in the second isolation columns E2 at the same position may be different due to reasons such as the manufacturing process. As long as the film layers in the first isolation columns E1 and the second isolation columns E2 are disconnected from the film layers corresponding to the transition zone, the effect of preventing crack extension can be achieved. First isolation columns E1 and second isolation columns E2 with various patterns all fall within the scope of protection of the present disclosure, and the present disclosure does not limit the specific shapes of the first isolation columns E1 and the second isolation columns E2.

[0150] In a specific implementation, as shown in FIG2A and FIG2B, during the stretching process of the display substrate, in addition to the inorganic film layer cracking easily occurring at the island-bridge connection position, the inorganic film layer on the connecting bridge area Q3 is also prone to cracking. During the stretching process of the connecting bridge area Q3, the inorganic film layer cracking extends along the boundary of the connecting bridge area Q3 close to the opening area Q2 into the connecting bridge area Q3, that is, the crack extends along point C to point C' (or point C' to point C), thereby breaking the metal traces on the connecting bridge area and causing tensile failure of the display substrate. In order to solve the problem of the inorganic film layer cracking on the connecting bridge area Q3, a method is proposed. k. In the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, 22 to 25, Figures 22 and 24 are respectively schematic diagrams of two cross-sectional structures along the CC' direction in Figure 2A, and Figures 23 and 25 are respectively schematic diagrams of two cross-sectional structures along the CC' direction in Figure 2B. A third isolation column E3 extending along the extension direction of the connecting bridge area Q3 is provided on one side of the connecting bridge area Q3 close to the opening area Q2 (for example, point C). The third isolation column E3 is composed of at least part of the film layer of the barrier layer 10, the buffer layer 11, the passivation layer 7, the first inorganic encapsulation layer 12 and the second inorganic encapsulation layer 13. By designing a third isolation column E3 composed of at least a partial inorganic film layer on the side of the connecting bridge area Q3 close to the opening area Q2 (for example, point C), the inorganic film layer in the third isolation column E3 is physically separated from the inorganic film layer in the connecting bridge area Q3 along the CC' direction away from the opening area Q2 and the pixel area Q12 by processes such as photolithography / etching, so as to avoid the formation of a crack in the inorganic film layer on the side close to the opening area Q2 (for example, point C) during the stretching process and extending along the direction from C to C'. The third isolation column E3 can prevent the crack on the side of the connecting bridge area Q3 from extending toward the connecting bridge area Q3, reducing the risk of disconnection of the metal signal line at the connecting bridge area Q3, thereby further improving the tensile deformation capacity of the display substrate.

[0151] In a specific implementation, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 2A, 2B, 22, and 23, the third spacer E3 is composed of a barrier layer 10, a buffer layer 11, a first planarization layer 5, a second planarization layer 6, a passivation layer 7, a first inorganic encapsulation layer 12, and a second inorganic encapsulation layer 13. Thus, the third spacer E3 physically separates all inorganic and organic film layers on the side of the bridge region Q3 close to the opening region Q2 from those farther from the opening region Q2, completely blocking the extension of cracks in the inorganic film layers and thereby further enhancing the tensile deformation capability of the display substrate.

[0152] In practice, due to the low elongation at break of the inorganic film layer, cracking is likely to occur first, which in turn triggers cracking of the signal line, reducing the overall tensile performance. Therefore, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 2A, 2B, 24, and 25, the third isolation column E3 can be composed of a barrier layer 10, a buffer layer 11, a first planarization layer 5, and a second planarization layer 6. By removing the passivation layer 7, the first inorganic encapsulation layer 12, and the second inorganic encapsulation layer 13 on the connecting bridge region Q3, signal line breakage can be avoided, further improving the tensile performance of the display substrate.

[0153] In some embodiments, referring to Figures 25 and 16, as shown in Figure 21, the height of the third isolation column E3 can be smaller than the height of the second isolation column E2 and / or the first isolation column E1. In this way, removing the passivation layer 7, the first inorganic encapsulation layer 12 and the second inorganic encapsulation layer 13 on the connecting bridge area Q3 can avoid breakage of the signal line and further improve the tensile performance of the display substrate.

[0154] In some embodiments, referring to FIG. 16 , FIG. 21 and FIG. 25 , the second preset distance W2 may be smaller than the first preset distance W1 . Such a design is beneficial for improving the stretchability of the pixel island region Q1 .

[0155] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 22 and 24, the third isolation column E3 is arranged close to the opening area Q2 on one side thereof, that is, the third isolation column E3 is close to the boundary position (point C) of the opening area Q2. In this way, the third isolation column E3 alone can be used to block the cracks caused by the biaxial stretching process.

[0156] In a specific implementation, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 2B, 23, and 25, a second predetermined distance W2 is provided between the side of the third spacer E3 proximate to the opening region Q2 and the opening region Q2. By designing the third spacer E3 so that it is not proximate to the boundary position (point C) of the opening region Q2, i.e., the third spacer E3 is designed to have the inorganic and organic film layers recessed at the boundary position (point C) of the opening region Q2, completely removing the inorganic and organic film layers above the substrate 1 proximate to the boundary position (point C) of the opening Q2. For example, the inorganic and organic film layers are recessed by 1 μm to 3 μm along the CC' direction, i.e., the second predetermined distance W2 is 1 μm to 3 μm. Compared to the non-retracted design of Figures 22 and 24, the recessed inorganic and organic film layers of the third spacer E3 can further enhance the tensile deformation capability of the connecting bridge region Q3.

[0157] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 26 to 29, Figures 26 and 28 are two more schematic diagrams of cross-sectional structures along the CC' direction in Figure 2A, and Figures 27 and 29 are two more schematic diagrams of cross-sectional structures along the CC' direction in Figure 2B. A fourth isolation column E4 extending along the extension direction of the connecting bridge area Q3 is provided on the other side of the connecting bridge area Q3 close to the opening area Q2 (for example, point C'), and the fourth isolation column E4 and the third isolation column E3 have the same film layer structure. By designing a fourth isolation column E4 at another boundary position (for example, point C') of the connecting bridge area Q3 close to the opening area Q2, the inorganic film layer and the organic film layer in the fourth isolation column E4 are physically separated from the inorganic film layer and the organic film layer in the connecting bridge area Q3 along the CC' direction away from the opening area Q2 and the pixel area Q12 by processes such as photolithography / etching, so as to prevent the inorganic film layer from forming a crack on the other side of the opening area Q2 (for example, point C') close to the opening area Q2 during the stretching process and extending along the direction from C' to C. The fourth isolation column E4 has the effect of blocking the extension of cracks in the inorganic film layer, thereby improving the tensile deformation capacity of the display substrate.

[0158] In specific implementations, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 26-29 , the fourth spacer E4 and the third spacer E3 are symmetrically arranged about the center of the connecting bridge region Q3. Of course, this arrangement is not limited to the symmetrical arrangement shown in Figures 26-29 . For example, as shown in Figure 30 , the third spacer E3 can be recessed, with the fourth spacer E4 positioned adjacent to the opening region Q2. Alternatively, the third spacer E3 can be positioned adjacent to the opening region Q2, with the fourth spacer E4 recessed.

[0159] It should be noted that the signal lines connecting adjacent pixel islands Q1 on the display substrate shown in Figures 26-30 employ a dual-layer routing design. Thus, the signal line layer between points C and C' can be a dual-layer routing design consisting of a first source / drain metal layer and a second source / drain metal layer. The first and second source / drain metal layers are separated by a second planarization layer 5. This reduces the width of the connecting bridge region Q3 along the CC' direction and improves the deformation capability of the connecting bridge region Q3. Of course, the metal routing on the connecting bridge region Q3 can also employ a three-layer or higher routing design.

[0160] It should be noted that the shape of the third isolation column E3 in Figures 22-30 can be that the latter film layer covers the previous film layer, the orthographic projections of two adjacent layers can be roughly flush, or a combination of the above. In addition, the patterns of the film layers in the third isolation column E3 at the same position in Figures 22-30 may vary due to factors such as the manufacturing process, and the patterns of the film layers in the fourth isolation column E4 at the same position may vary due to factors such as the manufacturing process. As long as the film layers in the third isolation column E3 and the fourth isolation column E4 are disconnected from the film layers corresponding to the connecting bridge area, the effect of preventing crack extension can be achieved. Third isolation columns E3 and fourth isolation columns E4 with various patterns all fall within the scope of protection of this disclosure, and this disclosure does not limit the specific shapes of the third isolation column E3 and the fourth isolation column E4.

[0161] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 2A, 2B, and 6-30, the third isolation column E3 and the first isolation column E1 are located on the same side, and the third isolation column E3 and the first isolation column E1 are disconnected; the fourth isolation column E4 and the second isolation column E2 are located on the same side, and the fourth isolation column E4 and the second isolation column E2 are disconnected.

[0162] In a specific implementation, in the display substrate provided in the embodiment of the present disclosure, as shown in FIG. 22 to FIG. 30 , the width of the third spacer E3 and the fourth spacer E4 along the CC′ direction may be 3 μm to 10 μm.

[0163] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in FIG31 , the spacer 21 can be arranged on the side of the pixel island region Q1 close to the connecting bridge region Q3; as shown in FIG32 , the spacer 20 can be arranged on the side of the connecting bridge region Q3 close to the pixel island region Q1. Of course, it is also possible that a portion of the spacer 21 is arranged on the side of the pixel island region Q1 close to the connecting bridge region Q3, and another portion of the spacer 20 is arranged on the side of the connecting bridge region Q3 close to the pixel island region Q1. Of course, the spacer 21 can also be arranged at any position in the pixel island region Q1 or the connecting bridge region Q3, and this disclosure does not impose any particular restrictions on this.

[0164] In a specific implementation, in the display substrate provided in the embodiment of the present disclosure, as shown in FIG. 31 and FIG. 32 , the number of spacers 21 provided in each pixel island region Q1 and the connected bridge region Q3 is 1 to 4.

[0165] In a specific implementation, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 3-5 , a second partitioning trench U2 is provided near the transition region Q11 in the pixel region Q12. The organic light-emitting layer 15 and the cathode 16 are disconnected at the second partitioning trench U2. The first inorganic encapsulation layer 12 covers the second partitioning trench U2. Because the organic light-emitting layer 15 and cathode 16 near the opening region Q2 are susceptible to water and oxygen intrusion, the second partitioning trench U2 can be provided to surround all sub-pixels within the pixel island region Q1. Alternatively, a second partitioning trench U2 can be provided around each sub-pixel. In this way, the second partitioning trench U2 can disconnect the organic light-emitting layer 15 and cathode 16 near the opening region Q2 from the organic light-emitting layer 15 and cathode 16 within the sub-pixel. This prevents water and oxygen from invading the organic light-emitting layer 15 and cathode 16 within the sub-pixel from the opening region Q2, thereby ensuring normal display of the display product.

[0166] In a specific implementation, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 3-5 , the second partitioning trench U2 can penetrate at least a portion of the passivation layer 7 and the second planar layer 6. The side of the passivation layer 7 near the second partitioning trench U2 protrudes beyond the side of the second planar layer 6 near the second partitioning trench U2, and the second partitioning trench U2 is a closed structure disposed around the transition region Q11. In this way, the portion of the passivation layer 7 protruding relative to the second planar layer 6 forms a recessed structure with the side surfaces of the second planar layer 6 and the bottom near the substrate 1. Specifically, the passivation layer 7 is made of an inorganic material, and the second planar layer 6 is made of an organic material. Thus, during the formation of the second partitioning trench U2, an etchant with a lower lateral etching rate for inorganic materials can be used to etch the passivation layer 7, while an etchant with a higher lateral etching rate for organic materials can be used to etch the second planar layer 6, thereby forming a recessed structure on the sidewalls of the second partitioning trench U2.

[0167] In some embodiments, as shown in Figures 3-5, the second partition groove U2 can penetrate at least a portion of the passivation layer 7 and the second planar layer 6, and the second partition groove U2 is located between the anode 14 and the first partition groove U1; wherein, the width of the second partition groove U2 is smaller than the width of the first partition groove U1; and the depth of the second partition groove U2 is smaller than the depth of the first partition groove U1.

[0168] In some embodiments, as shown in Figures 3-5 , the interlayer insulating layer 4 is located at the orthographic projection boundary of the substrate 1, between the orthographic projection of the second partition trench U2 on the substrate 1 and the orthographic projection of the first partition trench U1 on the substrate 1. This design helps avoid excessive film step difference between the second partition trench U2 and the first partition trench U1. In some embodiments, as shown in Figures 3-5 , at least a portion of the cathode 16 and / or the light-emitting functional layer 15 is retained on the passivation layer 7 between the second partition trench U2 and the first partition trench U1; and at least a portion or all of the passivation layer 7 of the first partition trench U1 is free of the cathode 16 or the light-emitting functional layer 15, thereby forming a transition zone of the partitioned cathode 16 or the light-emitting functional layer 15, avoiding excessive light differences between adjacent areas.

[0169] In some embodiments, as shown in Figures 3-5, at least a portion of the cathode 16 and / or the light-emitting functional layer 15 is retained on the passivation layer 7 between the second partition groove U2 and the first partition groove U1; the orthographic projection of the portion of the cathode 16 and / or the light-emitting functional layer 15 on the substrate 1 overlaps with the orthographic projection of the first signal line 18 and the second signal line 19 on the substrate 1.

[0170] It should be noted that the embodiment of the present disclosure takes the setting of one second partition groove U2 as an example. Of course, in a specific implementation, the number of second partition grooves U2 can be 2, 3 or more, and multiple second partition grooves U2 are set at intervals.

[0171] Specifically, the anode may include a three-layer stacked structure of transparent conductive film / metal film / transparent conductive film, wherein the material of the transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO, and the metal film may be a metal film such as Al, Ag, or Cu.

[0172] Specifically, the material of the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0173] Specifically, the light-emitting device can be an inorganic light-emitting diode, an organic light-emitting diode (OLED) made of organic materials, a micro light-emitting diode (Micro LED), or a mini light-emitting diode (Mini LED). The embodiments of the present disclosure take the light-emitting device as an organic light-emitting diode as an example.

[0174] Specifically, the driving circuit can adopt a variety of structures. For example, the driving circuit can be a structure including 2 transistors and 1 capacitor (2T1C), as shown in Figure 33; or the driving circuit can be a structure including 3 transistors and 1 capacitor (3T1C), as shown in Figure 34; or the driving circuit can be a structure including 7 transistors and 1 capacitor (7T1C), as shown in Figure 35.

[0175] The present disclosure also provides a display substrate, as shown in Figures 1, 2A, 2B, and 36. Figure 36 is a schematic cross-sectional view taken along the AA' direction in Figures 2A and 2B. The display substrate comprises a plurality of pixel island regions Q1, a plurality of opening regions Q2, and a plurality of connecting bridge regions Q3. The pixel island region Q1 includes a transition region Q11 connected to the connecting bridge region Q3 and a pixel region Q12. As shown in Figures 6-21, a first isolation pillar E1 composed of at least a partial inorganic film layer is disposed on at least one side of the transition region Q11 adjacent to the opening region Q2. The display substrate provided in this embodiment can adopt any of the schemes shown in Figures 6-21. For a detailed structural description, see the relevant descriptions of Figures 6-21.

[0176] The present disclosure also provides a display substrate, as shown in Figures 1, 2A, 2B, and 36. Figure 36 is a schematic cross-sectional view taken along the AA' direction in Figures 2A and 2B. The display substrate includes a plurality of pixel island regions Q1, a plurality of opening regions Q2, and a plurality of connecting bridge regions Q3. As shown in Figures 22-30, a third isolation column E3 extending along the extension direction of the connecting bridge region Q3 and composed of at least a partial inorganic film layer is provided on at least one side of the connecting bridge region Q3 adjacent to the opening region Q2. The display substrate provided in this embodiment can adopt any of the schemes shown in Figures 22-30. For a detailed structural description, see the relevant description of Figures 22-30.

[0177] The present disclosure also provides a display substrate, as shown in FIG1 , FIG2A , FIG2B and FIG36 . FIG36 is a schematic cross-sectional view along the AA′ direction in FIG2A and FIG2B , comprising a plurality of pixel island regions Q1 , a plurality of opening regions Q2 and a plurality of connecting bridge regions Q3 . The pixel island region Q1 comprises a transition region Q11 connected to the connecting bridge region Q3 and a pixel region Q12 .

[0178] As shown in Figures 6-30, a first isolation pillar E1 composed of at least a partially inorganic film layer is provided on at least one side of the transition region Q11 near the opening region Q2. A third isolation pillar E3 composed of at least a partially inorganic film layer is provided on at least one side of the connecting bridge region Q3 near the opening region Q2, extending along the extension direction of the connecting bridge region Q3. The display substrate provided in this embodiment can adopt any of the schemes shown in Figures 6-21 and any of the schemes shown in Figures 22-30. For a detailed structural description, see the relevant descriptions of Figures 6-30.

[0179] Optionally, in the display substrate shown in FIG. 36 provided by the present disclosure, three second partition grooves U2 are provided as an example, and the structure of each second partition groove U2 can refer to the description shown in the aforementioned FIG. 3 to FIG. 5 .

[0180] Optionally, FIG36 provided in the present disclosure only shows the first signal line 18. The first signal line 18 is taken as an example of jumping from G1 to SD1 and then jumping from SD1 to SD2. Of course, the signal line routing methods in the aforementioned FIG3-FIG5 can also be referred to.

[0181] It should be noted that the other membrane layer structures in FIG36 can be referred to the description in the aforementioned FIG3 to FIG5 , which will not be described in detail here.

[0182] Optionally, the display substrate provided in the embodiment of the present disclosure is a stretchable display substrate.

[0183] Optionally, the display substrate provided by the embodiment of the present disclosure can be used in display devices such as VR (virtual reality), but is certainly not limited thereto.

[0184] In specific implementation, the display substrate provided by the present disclosure may further include other functional film layers well known to those skilled in the art, which will not be described in detail here.

[0185] Based on the same inventive concept, the present disclosure further provides a method for manufacturing the display substrate described above, which is used to manufacture the display substrate provided in the embodiment of the present disclosure, as shown in FIG37 , comprising:

[0186] S3701, forming a plurality of pixel island regions, a plurality of opening regions, and a plurality of connecting bridge regions on a substrate, wherein the pixel island region includes a transition region connected to the connecting bridge region and a pixel region;

[0187] S3702. A first gate insulating layer, a second gate insulating layer and an interlayer insulating layer are sequentially formed in a stacked manner along a direction away from the substrate; wherein the orthographic projections of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer on the substrate all cover the pixel area and extend to the transition area; in a direction from the pixel island area to the connecting bridge area, the cutoff positions of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer in the transition area are different.

[0188] The manufacturing method of the above-mentioned display substrate provided in the embodiment of the present disclosure realizes a rigid gradient change design of the transition zone from the pixel island area to the connecting bridge area by making the cutoff positions of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer different in the transition zone, thereby reducing the risk of fracture failure at the island-bridge connection position during the stretching process.

[0189] The process of forming each film layer in the present disclosure may include a composition process and a photolithography process, among which the composition process may include depositing a film layer, coating a photoresist, mask exposure, development, etching, stripping the photoresist and other processes, while the photolithography process may include coating a film layer, mask exposure, development and other processes. The evaporation, deposition, coating, and coating used are all mature preparation processes in the relevant technology.

[0190] Taking the display substrates shown in FIG. 3 , FIG. 6 and FIG. 22 as an example, the manufacturing process of the display substrates shown in FIG. 3 , FIG. 6 and FIG. 22 is described in detail below. The manufacturing process may include the following steps:

[0191] (1) Taking the substrate 1 including a flexible layer structure as an example, the substrate 1 is divided into a pixel island region Q1, an opening region Q2 and a connecting bridge region Q2, the substrate 1 is formed on a glass substrate 100, a barrier material film layer is deposited on the substrate 1, a buffer material film layer is formed on the barrier material film layer, and the barrier material film layer and the buffer material film layer are patterned by a single patterning process to form a barrier layer 10 and a buffer layer 11, and the barrier layer 10 and the buffer layer 11 part of the first isolation column E1 are formed on the side of the transition region Q11 close to the opening region Q2 (for example, point D), and a connection bridge region Q3 is formed on the side of the connecting bridge region Q3 close to the opening region Q2 (for example, point C). The barrier layer 10 and the buffer layer 11 of the third isolation column E3 extending in the extension direction of the region Q3, the orthographic projections of the barrier layer 10 and the buffer layer 11 on the substrate 1 cover the pixel island region Q1 and the connecting bridge region Q3, and the barrier layer 10 and the buffer layer 11 of the opening region Q2 are removed; then, an active layer thin film (such as an amorphous silicon layer) is deposited on the buffer layer 11, and after the amorphous silicon layer is dehydrogenated at high temperature, excimer laser annealing (ELA) is used to convert the amorphous silicon into polycrystalline silicon, and then the polycrystalline silicon layer is patterned through a patterning process to form an active layer Act, and the active layer Act may include partial ion doping, as shown in Figures 38A, 38B, and 38C.

[0192] (2) A first gate insulating layer 2 is formed on the active layer Act by deposition and patterning processes. The orthographic projection of the first gate insulating layer 2 on the substrate 1 covers the first region Q111 and the second region Q112 in the pixel region Q12 and the transition region Q11. The first gate insulating layer 2 in the third region Q113, the connecting bridge region Q3 and the opening region Q2 is removed, and a portion of the first gate insulating layer 2 of the first isolation column E1 is formed on one side of the transition region Q11 close to the opening region Q2 (for example, point D), as shown in Figures 39A and 39B.

[0193] (3) A metal film (first gate metal layer) is deposited on the first gate insulating layer 2, and the metal film is patterned through a patterning process to form a gate G, a gate line (not shown), a first electrode C1, and a portion of the first signal line 18 located in the pixel island area Q1 on the first insulating layer 2, as shown in Figures 40A and 40B.

[0194] (4) A second gate insulating layer 3 is formed on the gate G by deposition and patterning processes. The orthographic projection of the second gate insulating layer 3 on the substrate 1 covers the pixel island area Q1. The second gate insulating layer 3 connecting the bridge area Q3 and the opening area Q2 is removed, and a portion of the second gate insulating layer 3 of the first isolation column E1 is formed on one side of the transition area Q11 close to the opening area Q2 (for example, point D), as shown in Figures 41A and 41B.

[0195] (5) A metal film (second gate metal layer) is deposited on the second gate insulating layer 3, and the metal film is patterned through a patterning process to form a second electrode C2 and a portion of the second signal line 19 located in the pixel island area Q1 on the second insulating layer 3. The position of the second electrode C2 corresponds to the position of the first electrode C1, as shown in Figures 42A and 42B.

[0196] (6) An interlayer insulating layer 4 is formed on the second gate metal layer by deposition and patterning processes. The orthographic projection of the interlayer insulating layer 4 on the substrate 1 covers the first area Q111, the second area Q112, and the third area Q113 in the pixel area Q12 and the transition area Q11, and the interlayer insulating layer 4 in the connecting bridge area Q3 and the opening area Q2 is removed. Vias are provided above both ends of the active layer Act, penetrating the interlayer insulating layer 4, the second gate insulating layer 3, and the first gate insulating layer 2, as shown in FIG. 43 .

[0197] (7) A metal film (first source-drain metal layer) is deposited on the interlayer insulating layer 4, and the metal film is patterned through a patterning process to form a source S, a drain D located in the pixel island area Q1, and a portion of the first signal line 18 located in the connecting bridge area Q3 on the interlayer insulating layer 4. This portion is electrically connected to the portion of the first signal line 18 located in the pixel island area Q1 in the connecting bridge area Q3, as shown in Figures 44A and 44B.

[0198] (8) A flat film of organic material is coated on the first source / drain metal layer, and a first flat layer 5 is formed in the pixel island area Q1 through masking, exposure, and development processes. The first flat layer 5 has a via hole corresponding to the drain electrode D position, the first flat layer 5 has a first partition groove U1 corresponding to the transition area Q11, and the first flat layer 5 has a via hole corresponding to the second signal line 19 position in the third area Q113. The first flat layer 5 in the opening area Q2 is removed, and a portion of the first flat layer 5 of the third isolation column E3 extending along the extension direction of the connecting bridge area Q3 is formed on the side of the connecting bridge area Q3 close to the opening area Q2 (for example, point C), as shown in Figures 45A and 45B.

[0199] (9) A metal film (second source-drain metal layer) is deposited on the first flat layer 5, and the metal film is patterned through a patterning process to form a lap joint 17 located on the first flat layer 5 in the pixel island area Q1 and a portion of the second signal line 19 located in the connecting bridge area Q3. This portion is electrically connected to the portion of the second signal line 19 located in the pixel island area Q1 in the third area Q113, as shown in Figures 46A and 46B.

[0200] (10) A flat thin film coated with an organic material is formed on the film layer where the overlapping portion 17 is located, and a second flat layer 6 is formed through masking, exposure, and development processes. The second flat layer 6 has a via hole corresponding to the overlapping portion 17. The second flat layer 6 has a first partition groove U1 corresponding to the transition area Q11, which is a sub-partition groove located in the second flat layer 6. The first flat layer 5 in the opening area Q2 is removed, and a second flat layer 6 portion of the third isolation column E3 extending along the extension direction of the connecting bridge area Q3 is formed on the side of the connecting bridge area Q3 close to the opening area Q2 (for example, point C), as shown in Figures 47A and 47B.

[0201] (11) An inorganic insulating material film layer is deposited on the second flat layer 6, and the inorganic insulating material film layer is patterned to form a passivation layer 7. The passivation layer 7 has a via hole at the position corresponding to the overlap portion 17, and a sub-partitioning groove penetrating the inorganic insulating material film layer is formed around all sub-pixels in the pixel island region Q1. In addition, a passivation layer 7 portion of the first isolation column E1 is formed on a side of the transition region Q11 close to the opening region Q2 (for example, point D), and a passivation layer 7 portion of the third isolation column E3 is formed on a side of the connecting bridge region Q3 close to the opening region Q2 (for example, point C) extending along the extension direction of the connecting bridge region Q3. The passivation layer 7 covers both side walls of the first partitioning groove U1 and is in direct contact with the portion of the second signal line 19 located in the transition region Q11, as shown in Figures 48A, 48B, and 48C.

[0202] (12) Using the passivation layer 7 as a mask, the second planar layer 6 is exposed and developed to form a sub-partition groove located in the second planar layer 6 below the sub-partition groove of the passivation layer 7, as shown in FIG49.

[0203] (13) A conductive film is deposited on the passivation layer 7 and patterned by a patterning process to form an anode 14. The anode 14 is electrically connected to the overlapping portion 17 through a via hole penetrating the passivation layer 7 and the second flat layer 6, as shown in FIG50.

[0204] (14) A pixel defining film is coated on the anode 14, and a pixel defining layer 8 is formed on the pixel island Q1 through masking, exposure, and development processes. A pixel opening is provided on the pixel defining layer 8 of the pixel island Q1, and the pixel defining film in the pixel opening is developed away to expose the surface of the anode 14; and the pixel defining film corresponding to the position of the opening area Q2, the position of the connecting bridge area Q3, and the position of the second partition groove U2 are all developed away, and a pixel defining material is filled in the first partition groove U1 to form an organic compensation layer 20, and a portion of the pixel defining layer 8 of the first isolation column E1 is formed on the side of the transition area Q11 close to the opening area Q2 (for example, point D), as shown in Figures 51A and 51B.

[0205] (15) An organic light-emitting layer 15 and a cathode 16 are sequentially formed on the pixel defining layer 9. The organic light-emitting layer 15 at least covers the pixel opening. The organic light-emitting layer 15 and the cathode 16 are respectively disconnected at the position of the second partition groove U2, as shown in FIG52.

[0206] (16) A first inorganic encapsulation film 12' is formed on the cathode 16, and an organic encapsulation film is formed on the first inorganic encapsulation film 12'. The organic encapsulation film is exposed and developed to form an organic encapsulation layer 9 in the pixel island area Q1, and all organic encapsulation films connecting the bridge area Q3 and the opening area Q2 are removed. A portion of the organic encapsulation layer 9 of the first isolation column E1 is formed on one side of the transition area Q11 close to the opening area Q2 (for example, point D), and then a second inorganic encapsulation film 13' is formed on the organic encapsulation layer 9, as shown in Figures 53A, 53B, and 53C.

[0207] (17) The first inorganic encapsulation film 12' and the second inorganic encapsulation film 13' are patterned, and the first inorganic encapsulation film 12' and the second inorganic encapsulation film 13' corresponding to the opening area Q2 are removed, and the first inorganic encapsulation layer 12 and the second inorganic encapsulation layer 13 are formed in the pixel island area Q1, and the first inorganic encapsulation layer 12 and the second inorganic encapsulation layer 13 portions of the first isolation column E1 are formed on the side of the transition area Q11 close to the opening area Q2 (for example, point D), and the first inorganic encapsulation layer 12 and the second inorganic encapsulation layer 13 portions of the third isolation column E3 extending along the extension direction of the connecting bridge area Q3 are formed on the side of the connecting bridge area Q3 close to the opening area Q2 (for example, point C). The first inorganic encapsulation layer 12 and the second inorganic encapsulation layer 13 are used as masks to pattern the substrate 1 and remove the substrate 1 in the opening area Q2, as shown in Figures 3, 6 and 22.

[0208] Finally, a protective film is attached to the second inorganic encapsulation layer 13 , and then the glass substrate 100 is peeled off through a laser lift-off process. After that, the protective film is removed to form a stretchable display substrate.

[0209] It should be noted that the present embodiment is described using the method for manufacturing the display substrate shown in FIG3 as an example. The method for manufacturing the display substrate shown in FIG4 is similar to the method shown in FIG3, except that in the above step (14), a spacer material is filled in the first partition groove U1 to form the organic compensation layer 20. The method for manufacturing the display substrate shown in FIG5 is similar to the method shown in FIG3, except that the organic compensation layer 20 is filled when the organic encapsulation layer 9 is formed in the above step (16).

[0210] Based on the same inventive concept, the present disclosure further provides a display device comprising any of the aforementioned display substrates. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The implementation of the display device can be referenced to the aforementioned embodiments of the display substrate, and any repetitive details will not be repeated here.

[0211] The above-mentioned display device can be an organic light emitting diode (Organic Light Emitting Diode; abbreviated as: OELD) display device, an active matrix organic light emitting diode (Active Matrix-Organic Light Emitting Diode; abbreviated as: AM-OLED) display device, or a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes; abbreviated as: QELD) display device.

[0212] The embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device. By arranging the cutoff positions of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer in the transition region to be different, a rigid gradient change design of the transition region from the pixel island region to the connecting bridge region can be achieved, thereby reducing the risk of fracture failure at the island-bridge connection position during the stretching process.

[0213] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0214] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display substrate, wherein: It includes a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions, wherein the pixel island region includes a transition region connected to the connecting bridge region and a pixel region; The display substrate comprises: a base, and a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer which are stacked in sequence in a direction away from the base; wherein the orthographic projections of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer on the base all cover the pixel area and extend to the transition area; and in a direction from the pixel island area to the connecting bridge area, the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer have different cutoff positions in the transition area.

2. The display substrate according to claim 1, wherein: The second gate insulating layer is adjacent to the connection bridge region at a cut-off position in the transition region, and the first gate insulating layer and the interlayer insulating layer at cut-off positions in the transition region are both far away from the connection bridge region.

3. The display substrate according to claim 2, wherein: The transition region is divided into a first region, a second region and a third region along a direction from the pixel island region to the connecting bridge region, the orthographic projection of the second gate insulating layer on the substrate covers the orthographic projection of the transition region on the substrate, the orthographic projection of the first gate insulating layer on the substrate covers the orthographic projection of the first region and the second region on the substrate, and the orthographic projection of the interlayer insulating layer on the substrate covers the orthographic projection of the first region on the substrate.

4. The display substrate according to any one of claims 1 to 3, wherein: The display substrate further comprises a first flat layer, a second flat layer and a passivation layer which are sequentially stacked on a side of the interlayer insulating layer away from the substrate, wherein the orthographic projections of the first flat layer and the second flat layer on the substrate both cover the pixel island area and the connecting bridge area, and the orthographic projection of the passivation layer on the substrate at least covers the pixel island area; wherein The first planar layer and the second planar layer have a first partition groove penetrating the first planar layer and the second planar layer in the transition region, the passivation layer covers the first partition groove, and the first partition groove above the passivation layer is filled with an organic compensation layer, so that the overall thickness of the transition region is equal to The pixel island region has a uniform overall thickness of the pixel region.

5. The display substrate according to claim 4, wherein: The display substrate further comprises a pixel defining layer, a spacer and an organic encapsulation layer stacked in sequence on the side of the passivation layer away from the substrate, and the organic compensation layer is made of the same material as one of the pixel defining layer, the spacer and the organic encapsulation layer.

6. The display substrate according to claim 5, wherein: The display substrate further includes: a barrier layer disposed between the substrate and the first gate insulating layer, a buffer layer disposed between the barrier layer and the first gate insulating layer, a first inorganic encapsulation layer disposed between the spacer and the organic encapsulation layer, and a second inorganic encapsulation layer disposed on a side of the organic encapsulation layer away from the substrate; A first isolation column is arranged on one side of the transition zone close to the opening zone, and the first isolation column is composed of at least part of the film layers of the barrier layer, the buffer layer, the first gate insulation layer, the second gate insulation layer, the passivation layer, the first inorganic encapsulation layer and the second inorganic encapsulation layer.

7. The display substrate according to claim 6, wherein: The first isolation column is composed of the barrier layer, the buffer layer, the first gate insulating layer, the second gate insulating layer, the passivation layer, the organic compensation layer, the first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer.

8. The display substrate according to claim 6, wherein: The first spacer is composed of the barrier layer, the buffer layer, the first gate insulating layer, the second gate insulating layer, the passivation layer, the first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer.

9. The display substrate according to claim 7 or 8, wherein: A side of the first isolation column close to the opening area is arranged closely adjacent to the opening area.

10. The display substrate according to claim 7 or 8, wherein: A first preset distance exists between a side of the first isolation column close to the opening area and the opening area.

11. The display substrate according to claim 10, wherein: The first preset distance is 1 μm to 5 μm.

12. The display substrate according to any one of claims 6 to 11, wherein: A second isolation column is disposed on the other side of the transition zone close to the opening zone, and the second isolation column has the same film layer structure as the first isolation column.

13. The display substrate according to claim 12, wherein: The second isolation column and the first isolation column are symmetrically arranged about the center of the transition region.

14. The display substrate according to any one of claims 6 to 13, wherein: A third isolation column extending along the extension direction of the connecting bridge area is arranged on one side of the connecting bridge area close to the opening area, and the third isolation column is composed of at least part of the film layer of the blocking layer, the buffer layer, the passivation layer, the first inorganic encapsulation layer and the second inorganic encapsulation layer.

15. The display substrate according to claim 14, wherein: The third spacer is composed of the barrier layer, the buffer layer, the first planar layer, the second planar layer, the passivation layer, the first inorganic encapsulation layer, and the second inorganic encapsulation layer.

16. The display substrate according to claim 14, wherein: The third isolation column is composed of the barrier layer, the buffer layer, the first planar layer and the second planar layer.

17. The display substrate according to claim 15 or 16, wherein: The third isolation column is disposed adjacent to the opening area on one side thereof close to the opening area.

18. The display substrate according to claim 15 or 16, wherein: A second preset distance exists between a side of the third isolation column close to the opening area and the opening area.

19. The display substrate according to claim 18, wherein: The second preset distance is 1 μm to 3 μm.

20. The display substrate according to any one of claims 14 to 19, wherein: A fourth isolation column extending along the extending direction of the connecting bridge area is arranged on the other side of the connecting bridge area close to the opening area, and the fourth isolation column has the same film layer structure as the third isolation column.

21. The display substrate according to claim 20, wherein: The fourth isolation column and the third isolation column are symmetrically arranged about the center of the connecting bridge region.

22. The display substrate according to any one of claims 14 to 21, wherein: The third isolation column and the first isolation column are located on the same side, and the third isolation column and the first isolation column are disconnected from each other.

23. The display substrate according to any one of claims 5 to 22, wherein: The spacer is arranged on a side of the pixel island region close to the connection bridge region, and / or the spacer is arranged on a side of the connection bridge region close to the pixel island region.

24. The display substrate according to claim 23, wherein: The number of the spacers disposed in each pixel island region and the connected bridge region is 1 to 4.

25. The display substrate according to any one of claims 6 to 24, wherein: The display substrate further includes: an anode disposed between the passivation layer and the pixel defining layer, an organic light emitting layer disposed between the pixel defining layer and the first inorganic encapsulation layer, and a cathode disposed between the organic light emitting layer and the first inorganic encapsulation layer; A second partition groove is provided at a position of the pixel region close to the transition region, the organic light emitting layer is disconnected at the second partition groove, the cathode is disconnected at the second partition groove, and the first inorganic encapsulation layer covers the second partition groove.

26. The display substrate according to claim 25, wherein: The second partition groove penetrates at least part of the passivation layer and the second flat layer, a side of the passivation layer close to the second partition groove protrudes out of a side of the second flat layer close to the second partition groove, and the second partition groove is a closed structure arranged around the transition zone.

27. The display substrate according to any one of claims 4 to 26, wherein: The display substrate further includes: a first gate metal layer disposed between the first gate insulating layer and the second gate insulating layer, a second gate metal layer disposed between the second gate insulating layer and the interlayer insulating layer, a first source-drain metal layer disposed between the interlayer insulating layer and the first planarizing layer, and a second source-drain metal layer disposed between the first planarizing layer and the second planarizing layer; The pixel island region includes at least one sub-pixel, and the display substrate further includes a plurality of signal lines disposed in the connection bridge region and extending to the pixel island region and electrically connected to the sub-pixel; wherein, The multiple signal lines include a first signal line and a second signal line that are stacked, wherein a portion of the first signal line located in the pixel island area is arranged in the first gate metal layer, and a portion of the first signal line located in the connecting bridge area is arranged in the first source-drain metal layer; a portion of the second signal line located in the pixel island area is arranged in the second gate metal layer, and a portion of the second signal line located in the connecting bridge area is arranged in the second source-drain metal layer.

28. A display substrate, wherein: It includes multiple pixel island areas, multiple opening areas and multiple connecting bridge areas, wherein the pixel island area includes a transition area connected to the connecting bridge area and a pixel area; at least one side of the transition area close to the opening area is provided with a first isolation column composed of at least a part of an inorganic film layer.

29. A display substrate, wherein: It comprises a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions, wherein at least one side of the connecting bridge region close to the opening region is provided with a third isolation column extending along the extending direction of the connecting bridge region and composed of at least a part of an inorganic film layer.

30. A display substrate, wherein: It includes a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions, wherein the pixel island region includes a transition region connected to the connecting bridge region and a pixel region; wherein, A first isolation column composed of at least a portion of an inorganic film layer is disposed on at least one side of the transition zone close to the opening zone, and a third isolation column composed of at least a portion of an inorganic film layer is disposed on at least one side of the connecting bridge zone close to the opening zone, extending along the extending direction of the connecting bridge zone.

31. A display device, wherein: Comprising the display substrate according to any one of claims 1-30.

32. A method for manufacturing a display substrate, used for manufacturing the display substrate according to any one of claims 1 to 27, wherein: The production method comprises: Forming a plurality of pixel island regions, a plurality of opening regions and a plurality of connecting bridge regions on a substrate, wherein the pixel island region includes a transition region connected to the connecting bridge region and a pixel region; A first gate insulating layer, a second gate insulating layer and an interlayer insulating layer are stacked in sequence in a direction away from the substrate; wherein the orthographic projections of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer on the substrate all cover the pixel area and extend to the transition area; and in a direction from the pixel island area to the connecting bridge area, the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer have different cutoff positions in the transition area.

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