ADC performance test method and platform

Abstract

The invention discloses an ADC performance test method and platform, and the method comprises the steps: obtaining a differential serial digital signal outputted by a to-be-tested chip, the serial digital signal comprising a slow clock signal and serial data; converting the serial digital signal into a parallel digital signal, wherein the parallel digital signal comprises a slow clock signal and parallel data; the parallel digital signals are registered and spliced, parallel output data are recovered, and when serial data lags behind a slow clock signal, the highest bit of the parallel data in the current clock period is replaced with the lowest bit of the parallel data in the previous clock period, and then the serial data are output in the next clock period. When the serial data is ahead of the slow clock signal, the highest bit to the second low bit of the parallel data in the previous clock period and the lowest bit of the parallel data in the current clock period are spliced and then output in the next clock period; outputting the parallel output data to a computer for analysis to obtain dynamic parameter indexes; according to the invention, the ADC parallel data can be correctly recovered, the cost is low, and the transferability is high.

Description

Technical Field

[0001] The present invention relates to the technical field of ADC testing, and particularly relates to an ADC performance testing method and platform. Background Art

[0002] In application fields such as radar and communication, receiver chips usually adopt a multi-channel architecture. In a low-IF system within a single channel, after the radio frequency signal received by the antenna passes through a low-noise amplifier, it passes through I and Q mixers and a complex filter to filter out image noise and interference. Subsequently, the VGA adjusts the gain of the receiving channel, and the generated intermediate-frequency signal is sampled by an internally integrated ADC to convert the intermediate-frequency analog signal into a digital signal. The multi-channel receiver architecture will cause the number of pins of the chip to increase exponentially with the number of channels. Therefore, a serial-to-parallel conversion circuit needs to be added inside the chip, and the digital signal output by the ADC is output outside the chip via the serial-to-parallel conversion circuit. The serial output data of the ADC brings the following challenges to chip testing: (1) The test needs to adapt to the high-speed characteristics of serial data transmission. (2) The test needs to meet the timing requirements of serial-to-parallel conversion and correctly recover the ADC parallel data.

[0003] Due to the high rate of the ADC serial output data, in ADC testing, a logic analyzer is usually used to build a testing platform, and the sampling rate data mode and sampling depth are set to test the ADC. A logic analyzer is an important testing instrument in the data domain, mainly composed of two parts: data capture and display. The input of each channel of the logic analyzer generally searches for specified data words according to the data capture method, and then converts them into corresponding data stream forms through the data input part, and can display and store the data to be observed, so as to realize the capture and analysis of ADC data and complete the testing of ADC performance indicators. The logic analyzer has many advantages such as a large number of channels, a high timing analysis rate, and a rich variety of triggers. Therefore, a high-performance logic analyzer can be used to test ADCs with different rates, serial or parallel outputs. However, the cost of the logic analyzer is high, and the logic analyzer can only be used as an output signal acquisition tool and cannot provide test input signals for the chip, and cannot be applied to scenarios that require both chip input and chip output acquisition.

[0004] The FPGA has rich IO expansion port resources, providing various user-defined solutions for chip testing, with flexibility and reconfigurability. Therefore, building a test platform based on the FPGA to replace the logic analyzer is another ADC test solution with feasibility and flexibility. When the FPGA is applied to the test scenario of the serial ADC output, the FPGA needs to complete tasks such as collecting serial data, differential-to-single-ended conversion, serial-to-parallel conversion, observing data waveforms, and storing and saving data. The above tasks pose high requirements on the performance of the FPGA. The FPGA needs to support functions such as high-speed communication and IO expansion. During the process of building the test platform, factors such as Dupont wires, PCB trace errors, and inconsistencies in the internal traces of the FPGA, especially the high speed of transmitting serial data, will cause time errors in high-speed differential serial signals, resulting in timing offsets or even errors in serial-to-parallel conversion, thus causing problems in the process of restoring parallel data and even leading to test failures.

[0005] For example, the patent application document with the publication number CN116774022A proposes an ADC performance test system based on the FPGA and its test method. This solution needs to rely on the host computer to send function configuration instructions to the FPGA processing chip. The FPGA processing chip sends configuration information to the ADC chip under test, the ADC current sampling chip, and the DDR3 memory respectively and configures the function mode. The host computer sends a test start instruction to the FPGA processing chip, generates a test analog signal through the signal source, and the FPGA processing chip enables the ADC chip under test and the current sampling chip. In addition, it is necessary to set the current sampling chip to collect the serial output signal of the ADC chip under test, and convert the voltage analog signal into a digital signal and transmit it to the FPGA processing chip.

[0006] In the patent application document with the publication number CN110798211A, it is proposed that after the FPGA configures the AD to send a test sequence, the calibration instruction and the state machine are started, the delay parameter calibration algorithm is run, the delay parameters are dynamically placed into the FPGA input delay control primitive, and all data lines within and between channels are aligned. The AD exits the test sequence and outputs the actual signal to complete the system input delay calibration; however, the calibration object of this solution is the time error between channels of the parallel alternating sampling technology (TIADC), and time delays of parallel multi-channel sampled data may be inconsistent in multiple stages of the solution, manifested as non-uniform sampling, that is, data alignment problems when the FPGA performs data splicing processing. When the AD sampling rate is high, this problem is particularly obvious, seriously affecting the performance of the sampling system.

[0007] Therefore, due to the reasons of its own performance of low-cost FPGA, the internal routing in the FPGA will cause timing deviation in the acquisition of ADC serial data. Especially when the serial data rate is very high, the timing deviation will be more obvious, which will bring errors or even failures to the restoration of parallel data. Therefore, the traditional test tools for acquiring ADC serial output data are logic analyzers or high-performance FPGAs, which have disadvantages such as high cost and poor portability. Summary of the Invention

[0008] The technical problem to be solved by the present invention is how to design a low-cost FPGA-based test platform to implement the performance test of ADC chips and correctly restore the ADC parallel data.

[0009] The present invention solves the above technical problems by the following technical means:

[0010] A method for testing ADC performance is proposed. The method is applied to an FPGA and includes:

[0011] Obtain the differential serial digital signal output by the ADC chip to be tested. The serial digital signal includes a slow clock signal and serial data;

[0012] Convert the serial digital signal into a parallel digital signal. The parallel digital signal includes a slow clock signal and parallel data;

[0013] Perform a register splicing operation on the parallel digital signal to restore the ADC parallel output data. Among them, when the serial data lags behind the slow clock signal, the highest bit of the parallel data in the current clock cycle is replaced with the lowest bit of the parallel data in the previous clock cycle and then output in the next clock cycle. When the serial data is ahead of the slow clock signal, the highest bit to the second lowest bit of the parallel data in the previous clock cycle is spliced with the lowest bit of the parallel data in the current clock cycle and then output in the next clock cycle;

[0014] Output the ADC parallel output data to a computer so that the computer analyzes the ADC parallel output data to obtain the dynamic parameter indexes of the ADC.

[0015] Further, the converting the serial digital signal into a parallel digital signal includes:

[0016] Use Select IP to splice the input slow clock signal and the serial data to obtain a parallel digital signal. Among them, Select IP is a Verilog encapsulation file deployed in the FPGA chip. The bit width of the data input port of Select IP is 2, and the serialization factor of the IP core is N.

[0017] Further, the serial digital signal further includes a fast clock signal, and the method further includes:

[0018] Use Select IP to convert the input fast clock signal into a control clock signal, where the control clock signal is 2*N times the fast clock signal;

[0019] Among them, the control clock signal is synchronously output with the parallel digital signal, and the parallel digital signal is updated at the rising edge of each cycle of the control clock signal.

[0020] Further, the operation of registering and splicing the parallel digital signal to restore the ADC parallel output data includes:

[0021] Perform a splicing operation on the parallel digital signal to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N;

[0022] Respectively register and splice the slow clock signal with a bit width of N and the parallel data with a bit width of N to obtain a slow clock signal with a bit width of 2*N and parallel data with a bit width of 2*N.

[0023] Further, when the serial data lags behind the slow clock signal, perform a splicing operation on the parallel digital signal with a bit width of 2*N to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N, including:

[0024] Register the parallel data data[N-1:0] in the previous clock cycle clk M-1 to the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M;

[0025] Replace the highest bit of the newly entered parallel data data[N-1:0] in the previous clock cycle clk M with the lowest bit of the parallel data data_reg[N-1:0] in the previous clock cycle and output it in the next clock cycle clkM+1.

[0026] Further, when the serial data is ahead of the slow clock signal, perform a splicing operation on the parallel digital signal with a bit width of 2*N to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N, including:

[0027] Register the parallel data data[N-1:0] in the previous clock cycle clk M-1 to the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M;

[0028] Discard the newly entered parallel data data[N-1:1] in the current clock cycle clk M and retain data[0];

[0029] The parallel data data_reg[N-1:1] is concatenated with data[0] and output in the next clock cycle clkM+1.

[0030] Further, the slow clock signal with a bit width of N and the parallel data with a bit width of N are respectively registered and concatenated to obtain a slow clock signal with a bit width of 2*N and parallel data with a bit width of 2*N, including:

[0031] The parallel data in the previous clock cycle and the parallel data in the current clock cycle are positively concatenated and reversely concatenated to obtain a slow clock signal with a bit width of 2*N and parallel data with a bit width of 2*N.

[0032] Further, the bit width of the ADC parallel data is twice the serialization factor of the IP core.

[0033] In addition, the present invention also proposes an ADC performance test platform, including an FPGA and a computer. The output of the FPGA is connected to the computer. The FPGA is used to execute the steps of the above ADC performance test method. The FPGA includes:

[0034] A signal acquisition module, used to acquire the differential serial digital signal output by the ADC chip to be tested, and the serial digital signal includes a slow clock signal and serial data;

[0035] A deserialization module, used to convert the serial digital signal into a parallel digital signal, and the parallel digital signal includes a slow clock signal and parallel data;

[0036] A parallel digital signal recovery module, used to perform a register concatenation operation on the parallel digital signal to recover the ADC parallel output data. Among them, when the serial data lags behind the slow clock signal, the highest bit of the parallel data in the current clock cycle is replaced with the lowest bit of the parallel data in the previous clock cycle and output in the next clock cycle. When the parallel data is ahead of the slow clock signal, the highest bit to the second lowest bit of the parallel data in the previous clock cycle is concatenated with the lowest bit of the parallel data in the current clock cycle and output in the next clock cycle;

[0037] A signal output module, used to output the ADC parallel output data to the computer so that the computer can analyze the ADC parallel output data to obtain the dynamic parameter indexes of the ADC.

[0038] Further, the platform further includes a clock generator, a signal generator and a power supply connected to the ADC chip to be tested;

[0039] The clock generator is used to generate the clock signal for the ADC chip to be tested to work;

[0040] The signal generator is used to generate an input signal for the ADC chip under test, and the frequency of the input signal satisfies the coherent sampling theorem;

[0041] The power supply is used to generate the operating voltage for the ADC chip under test.

[0042] The advantages of the present invention are as follows:

[0043] (1) Aiming at the problems of errors in Dupont wires, PCB traces, and inconsistent internal traces of FPGA during the construction of the test platform, especially the high speed of transmitting serial data, these factors will cause time errors in high-speed differential serial signals, resulting in incorrect recovered parallel data. The present invention designs a timing error correction logic. On the basis of realizing the function of converting serial data into parallel data, for the timing error between the slow clock signal and the serial data, it can correct the parallel data converted by a low-cost FPGA and recover the correct parallel data; this test platform does not need to use a high-performance FPGA, and compared with a logic analyzer, it reduces the equipment volume, has the advantages of miniaturization and low cost, and the designed error correction logic algorithm and test platform have scalability and universality, can be applied to more ADC serial output tests with different parameters, and are also applicable to FPGAs of different brands and models, having practical engineering reference value.

[0044] Additional aspects and advantages of the present invention will be given in part in the following description, will become apparent in part from the following description, or will be understood through the practice of the present invention. Description of the Drawings

[0045] Figure 1 is a schematic flowchart of an ADC performance test method proposed in an embodiment of the present invention;

[0046] Figure 2 is a schematic diagram of the ADC test principle in an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of the serial-to-parallel principle using Select IP in an embodiment of the present invention;

[0048] Figure 4 is a schematic diagram of the basic principle of recovering parallel data from serial data in an embodiment of the present invention;

[0049] Figure 5 is a timing diagram of error analysis in an embodiment of the present invention, where (a) is the timing diagram of the ideal situation, (b) is the timing diagram of the serial data lag, and (c) is the timing diagram of the serial data lead;

[0050] Figure 6 is a schematic diagram of the error correction principle in the case of serial data lag in an embodiment of the present invention;

[0051] Figure 7 It is a schematic diagram of the error correction principle in the case of serial data leading in an embodiment of the present invention;

[0052] Figure 8 It is a schematic diagram of the principle of restoring parallel data in an embodiment of the present invention;

[0053] Figure 9 It is a schematic diagram of the structure of an ADC performance test platform proposed in an embodiment of the present invention. Specific embodiments

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0055] As Figure 1 shown, a first embodiment of the present invention proposes an ADC performance test method, which is applied to an FPGA and includes the following steps:

[0056] S10. Obtain the differential serial digital signal output by the ADC chip to be tested, where the serial digital signal includes a slow clock signal and serial data;

[0057] It should be noted that the ADC chip to be tested converts the input analog signal into a digital signal under certain trigger conditions and outputs it to the FPGA in a serial differential manner.

[0058] S20. Convert the serial digital signal into a parallel digital signal, where the parallel digital signal includes a slow clock signal and parallel data;

[0059] It should be noted that the parallel digital signal is the alternating appearance of parallel slow clock signals and parallel data.

[0060] S30. Perform a register splicing operation on the parallel digital signal to restore the ADC parallel output data. Among them, when the serial data lags behind the slow clock signal, the highest bit of the parallel data in the current clock cycle is replaced with the lowest bit of the parallel data in the previous clock cycle and then output in the next clock cycle. When the serial data is ahead of the slow clock signal, the highest bit to the second lowest bit of the parallel data in the previous clock cycle is spliced with the lowest bit of the parallel data in the current clock cycle and then output in the next clock cycle;

[0061] It should be noted that when the FPGA receives the differential serial digital signal output by the ADC chip and converts it into a single-ended parallel digital signal, the timing error between the serial data and the slow clock signal will bring errors to the parallel data recovery. Therefore, in this embodiment, a timing error correction logic is designed. Through operations such as registering and splicing the parallel digital signal, on the basis of realizing the function of converting serial data into parallel data, aiming at the timing error between the slow clock signal and the serial data, it can correct the error and recover the correct ADC parallel output data.

[0062] S40. Output the ADC parallel output data to a computer so that the computer analyzes the ADC parallel output data to obtain the dynamic parameter indexes of the ADC.

[0063] Finally, the recovered correct ADC parallel output data is output to the computer, and the computer performs Fourier transform FFT analysis on the parallel ADC parallel output data to obtain the ADC dynamic parameter indexes. The entire test process does not require the assistance of hardware devices such as a host computer, a current sampling chip, and a logic analyzer, and has the advantages of miniaturization and low cost.

[0064] It should be noted that the test object of the present invention is an ADC with serial output. The performance indexes of the ADC are usually divided into two parts: static indexes and dynamic indexes. Among them: (1) The static indexes represent the internal characteristics of the ADC itself and are related to the internal errors and noises of the ADC. Comparing the static indexes with the relationship between a specific analog input level and the corresponding output code can be obtained through the code density histogram method. The code density histogram method is to continuously test and analyze the output digital codes in a large number of collected sample data based on a statistical method to accurately test the static parameters of the ADC. (2) The dynamic indexes focus on the ability of the ADC to sample and reproduce time-varying signals. During the test, the dynamic performance parameters such as the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SINAD), total harmonic distortion (THD), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are mainly concerned. The dynamic parameter indexes can be obtained by using the test method of performing a fast Fourier transform on the data sampled by the ADC. This test technology analyzes the signal components such as the fundamental frequency, noise, and harmonics within the entire sampling bandwidth. This embodiment is mainly aimed at the test method of the ADC dynamic parameter indexes.

[0065] During the test process, as Figure 2 shown, the parallel-to-serial conversion circuit converts the parallel data output by the ADC chip to be tested into serial data, and then outputs it through a low-voltage differential signal (LVDS) interface circuit. Since high-speed serial data transmission has high efficiency, the number of channels required for serial transmission is greatly reduced, and the number of pins can be reduced; and the two transmission lines of the differential signal adopt a parallel wiring method, which can cancel the external common-mode noise and has the characteristics of low power consumption, low radiation, and high anti-noise.

[0066] Therefore, based on the above Figure 2 The ADC dynamic performance index and the principle of the parallel-to-serial conversion circuit shown in the figure, the basic idea of ​​the ADC serial output test in this embodiment is: the FPGA accurately obtains the serial data differential signal output by the ADC, and performs differential conversion to single-ended in the FPGA, and according to the timing requirements, correctly restores the ADC single-ended parallel data output to the computer, and then the computer performs FFT analysis to obtain the ADC dynamic parameter index.

[0067] As a further preferred technical solution, the step S20: converting the serial digital signal into a parallel digital signal specifically includes:

[0068] Select IP is used to splice the input slow clock signal and the serial data to obtain a parallel digital signal with a bit width of 2*N, wherein Select IP is a Verilog encapsulation file deployed in the FPGA chip, the bit width of the data input port of Select IP is 2, and the serialization factor of the IP core is N.

[0069] Specifically, this embodiment completes the serial-to-parallel conversion based on the FPGA Select IP. The principle of completing the serial-to-parallel conversion based on the FPGA Select IP is as follows: Figure 3 Select IP is a Verilog package file that generates instantiated I / O logic according to user configuration. In this embodiment, Select IP is used to generate an interface program that supports the LVDS level standard, and the deserializer provided by SelectIP is used to complete the serial-to-parallel conversion in data transmission, with the first bit arriving as the high bit, and the differential-to-single-ended conversion is completed at the same time.

[0070] As a further preferred technical solution, the serial digital signal further includes a fast clock signal, and the method further includes:

[0071] Using Select IP to convert the input fast clock signal into a control clock signal, where the control clock signal is 2*N times the fast clock signal;

[0072] The control clock signal is output synchronously with the parallel digital signal, and the parallel digital signal is updated at the rising edge of each cycle of the control clock signal.

[0073] Specifically, the serial digital signal output by the ADC chip under certain trigger conditions includes a fast clock signal clk, a slow clock signal refclk, and serial data serial_data. The serial digital signal is used as the input of the FPGA. The SelectIP is utilized to splice the slow clock signal refclk and the serial data serial_data and send them to the data input port data_in of the Select IP. Therefore, the bit width of the data input port data_in is 2. By setting the serialization factor of the IP core to N, the bit width of the parallel digital signal parallel_data output by the Select IP is 2*N. There is also a control clock signal slow_clk output synchronously with the parallel digital signal parallel_data, and the clock period of slow_clk is 2*N times that of the input clock clk. In this way, parallel_data and slow_clk are synchronized, that is, parallel_data is updated at the rising edge of each cycle of slow_clk.

[0074] Furthermore, the bit width of the parallel digital signal is twice the serialization factor of the IP core.

[0075] Specifically, in this embodiment, the serialization factor N of the IP core is not limited to the case where it is equal to 6. For example, when the ADC parallel data bit widths are 8, 10, and 14 respectively, N becomes 4, 5, and 7 respectively. The principle of restoring the parallel data is the same, only the data bit widths change. Therefore, the error correction logic and test method designed in this embodiment have scalability and universality, can be applied to more ADC serial output tests with different parameters, and are also applicable to FPGAs of different brands and models, having practical engineering reference value.

[0076] As a further preferred technical solution, in step S30: performing a register splicing operation on the parallel digital signal to restore the ADC parallel output data, specifically includes the following steps:

[0077] S31. Perform a splicing operation on the parallel digital signal with a bit width of 2*N to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N;

[0078] S32. Perform register and splicing operations on the slow clock signal with a bit width of N and the parallel data with a bit width of N respectively to obtain a slow clock signal with a bit width of 2N and parallel data with a bit width of 2N.

[0079] Specifically, the parallel digital signal parallel_data output by Select IP is not the true parallel output data of the ADC. Parallel_data contains data from refclk and serial_data. Therefore, it is necessary to separate refclk and serial_data to restore the ADC parallel output data. As Figure 4 shown, in the parallel digital signal parallel_data output by Select IP, the data from refclk and serial_data appear alternately. The total bit width of parallel_data is 2*N. By performing a concatenation operation on it, data with a bit width of N is obtained. This data only comes from the original refclk or only from the original serial_data. Then, the N-bit data is registered and concatenated to obtain data with a bit width of 2N, that is, the ADC parallel output data is restored.

[0080] Furthermore, when building an ADC chip test platform based on FPGA, DuPont wires are used to connect the PCB board and the FPGA. Time errors will be introduced by the transmission signals in the DuPont wires, the PCB board, and the FPGA internal. Taking the serial output of a 50MHz, 12-bit ADC as an example, the serial data rate is as high as 600MHz. The time errors caused by non-ideal factors such as DuPont wires, PCB boards, and FPGA internal traces will be more obvious, resulting in a timing offset of the signal high-speed serial output data, thus bringing difficulties or even errors to the restoration of parallel data. The timing diagram of error analysis is as Figure 5 shown, clk, refclk, and serial_data are all outputs of the ADC. As Figure 5 shown in (a) of, ideally, one slow clock cycle refclk is required to transmit 12 serial data serial_data. The high level of refclk corresponds to the first 6 serial data serial_data, that is, the high 6 bits [d6, d11] of the original parallel data. The low level of refclk corresponds to the last 6 serial data serial_data, that is, the low 6 bits [d0, d5] of the original parallel data. Refclk is used to indicate the start and end bits of serial_data and provides a reference for converting parallel data. However, when the high-speed serial data is transmitted through the PCB board, DuPont wires, and FPGA internal traces, an error occurs in the timing relationship between refclk and serial_data. As Figure 5 shown in (b) of, when the rising edge of refclk arrives, the serial_data of the current cycle has not arrived yet, corresponding to the last two bits of the serial data of the previous cycle. At this time, serial_data lags behind refclk. As Figure 5As shown in (c), when the rising edge of refclk arrives, the first few bits of the current cycle's serial_data have been transmitted. At this time, serial_data is ahead of refclk.

[0081] After the above analysis, when the FPGA chip receives the differential serial digital signal output by the ADC chip and converts it into a single-ended parallel digital signal, the timing error between the serial data and the slow clock signal will cause errors in parallel data recovery. Therefore, it is necessary to Figure 4 add an error correction logic algorithm to the process of recovering parallel data from the serial data shown in. Specifically, when the serial data lags behind the slow clock signal, in step S31: perform a splicing operation on the parallel digital signal with a bit width of 2*N to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N, which specifically includes:

[0082] Latch the parallel data data[N-1:0] in the previous clock cycle clk M-1 to the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M;

[0083] Replace the highest bit of the newly entered parallel data data[N-1:0] in the previous clock cycle clk M with the lowest bit of the parallel data data_reg[N-1:0] in the previous clock cycle and output it in the next clock cycle clkM+1.

[0084] Specifically, the principle is as Figure 6 shown. When the serial data lags behind the slow clock signal, the highest bit of the parallel data data with a bit width of N bits, that is, data[N-1], actually comes from the lowest bit of the data in the previous clock cycle. If the data[N-1:0] is directly latched and spliced into data with a bit width of 2N, errors will occur. Therefore, latch the data data[N-1:0] in the previous clock cycle clk M-1 to the current clock cycle clk M, that is, it becomes data_reg[N-1:0]. At the same time, in the current clock cycle clk M, a new data[N-1:0] will enter. The highest bit of this data[N-1:0] comes from the lowest bit of the data in the previous clock cycle clk M-1. Since the data data in the previous clock cycle clk M-1 is the data_reg in the current clock cycle clkM, replace the highest bit of data with the lowest bit of data_reg and output it in the next clock cycle clk M+1 to obtain the correct intermediate signal temp[N-1:0] with a bit width of N.

[0085] Specifically, when the serial data is ahead of the slow clock signal, step S31: performing a splicing operation on the parallel data with a bit width of 2*N to obtain a slow clock signal with a bit width of N and serial data with a bit width of N, specifically including:

[0086] Storing the parallel data data[N-1:0] in the previous clock cycle clk M-1 into the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M;

[0087] Discarding the newly entered parallel data data[N-1:1] in the current clock cycle clk M and retaining data[0];

[0088] Splicing the parallel data data_reg[N-1:1] and data[0] and outputting them in the next clock cycle clk M+1.

[0089] Specifically, as Figure 7 shown, when the serial data is ahead of the slow clock signal, for the parallel data data with a bit width of N bits, from the highest bit to the second highest bit, i.e., data[N-1:1], it actually comes from the highest bit to the second highest bit of the data in the next clock cycle, that is, the data in the next clock cycle is advanced to the current clock cycle and is incorrect data. Therefore, storing the data data[N-1:0] in the previous clock cycle clk M-1 into the current clock cycle clk M, which becomes data_reg[N-1:0]. At the same time, in the current clock cycle clk M, a new data[N-1:0] will enter. The data[N-1:1] comes from the next clock cycle clk M+1 and is incorrect data caused by errors. Therefore, discarding the data[N-1:1] in the current clock cycle clk M and retaining data[0]. Since the data data in the previous clock cycle clk M-1 is the data_reg in this clock cycle clk M, the data_reg[N-1:1] is retained. In the current clock cycle clk M, splicing data_reg[N-1:1] and data[0] and outputting them in the next clock cycle clk M+1, the correct intermediate signal temp[N-1:0] with a bit width of N can be obtained.

[0090] Furthermore, as Figure 6 and Figure 7 shown, the intermediate signal temp[N-1:0] with a bit width of N and without timing error is obtained. When using the intermediate temp[N-1:0] to restore the parallel data with a bit width of 2N, storage and splicing operations are required. As Figure 8 shown, the operation process is as follows:

[0091] The serial data temp[N - 1:0] in the previous clock cycle clk M - 1 is registered into the current clock cycle clk M, becoming temp_reg[N - 1:0]. Meanwhile, within the current clock cycle clk M, a new temp[N - 1:0] will enter. Since temp[N - 1:0] may originate from either the lower N bits or the higher N bits of the original data, during the process of concatenating and restoring to a data with a bit width of 2N, it should be concatenated both in the normal order and in the reverse order once, so as to avoid online error delay in actual testing and ensure the correct data is restored.

[0092] Specifically, as Figure 8 shown, the normal concatenation is to use temp_reg[N - 1:0] as the higher N bits and temp[N - 1:0] as the lower N bits to obtain a data with a bit width of 2N, that is, data_2Nbit[2N - 1:0]; the reverse concatenation is to use temp[N - 1:0] as the higher N bits and temp_reg[N - 1:0] as the lower N bits to obtain a data with a bit width of 2N, that is, data_2Nbit_n[2N - 1:0].

[0093] In addition, as Figure 9 shown, the second embodiment of the present invention also proposes an ADC performance test platform, including FPGA100 and computer 200. The output of FPGA100 is connected to computer 200. The FPGA chip is used to execute the functional steps of the ADC performance test method described in the first embodiment above. The FPGA100 includes:

[0094] A signal acquisition module, which is used to acquire the differential serial digital signal output by the ADC chip to be tested. The serial digital signal includes a slow clock signal and serial data;

[0095] A deserialization module, which is used to convert the serial digital signal into a parallel digital signal. The parallel digital signal includes a slow clock signal and parallel data;

[0096] A parallel digital signal restoration module, which is used to perform register concatenation operations on the parallel digital signal to restore the ADC parallel output data. Among them, when the serial data lags behind the slow clock signal, the highest bit of the parallel data in the current clock cycle is replaced with the lowest bit of the parallel data in the previous clock cycle and then output in the next clock cycle. When the serial data is ahead of the slow clock signal, the highest bit to the second - highest bit of the parallel data in the previous clock cycle is concatenated with the lowest bit of the parallel data in the current clock cycle and then output in the next clock cycle;

[0097] A signal output module, which is used to output the ADC parallel output data to the computer so that the computer can analyze the ADC parallel output data to obtain the dynamic parameter indicators of the ADC.

[0098] As a further preferred technical solution, the platform further includes a clock generator 300, a signal generator 400, and a power supply 500 connected to the ADC chip to be tested;

[0099] The clock generator 300 is used to generate a clock signal for the operation of the ADC chip to be tested;

[0100] The signal generator 400 is used to generate an input signal for the ADC chip to be tested, and the frequency of the input signal satisfies the coherent sampling theorem;

[0101] The power supply 500 is used to generate the operating voltage of the ADC chip to be tested.

[0102] It should be noted that the ADC sample test platform is the main tool for testing the performance of the ADC. The FPGA-based ADC performance test platform designed in this embodiment is as Figure 9 shown. The ADC test platform mainly consists of a clock generator, a signal generator, a power supply, an FPGA, and a computer. The clock generator generates a clock signal for the operation of the ADC to be tested. The signal generator generates an input signal for the ADC, which is a sine wave signal, and the frequency of the input signal should satisfy the coherent sampling theorem. The power supply generates the operating voltage of the ADC. The ADC to be tested converts the input analog signal into a digital signal, and uses serial differential output. The FPGA receives the differential serial digital signal and converts it into a single-ended parallel digital signal, and saves the output data to the computer through the FPGA debugging tool. The computer performs FFT analysis on the data to obtain the ADC dynamic parameter indicators.

[0103] As a further technical solution, the deserialization module 20 is used to splice the input slow clock signal and the serial data by using Select IP to obtain a parallel digital signal with a bit width of 2*N, where Select IP is a Verilog encapsulation file deployed in the FPGA chip, the bit width of the data input port of Select IP is 2, and the serialization factor of the IP core is N.

[0104] As a further technical solution, the deserialization module 20 is further used to convert the input fast clock signal into a control clock signal by using Select IP, and the control clock signal is 2*N times the fast clock signal;

[0105] Wherein, the control clock signal is synchronously output with the parallel digital signal, and the parallel digital signal is updated at the rising edge of each cycle of the control clock signal.

[0106] As a further technical solution, the parallel digital signal recovery module 30 specifically includes:

[0107] The splicing unit is used to splice the parallel digital signals to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N;

[0108] The parallel data calculation unit is used to register and splice the slow clock signal with a bit width of N and the parallel data with a bit width of N respectively to obtain a slow clock signal with a bit width of 2N and parallel data with a bit width of 2N.

[0109] As a further preferred technical solution, the splicing unit is used to register the parallel data data[N-1:0] in the previous clock cycle clk M-1 to the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M; replace the highest bit of the newly entered parallel data data[N-1:0] in the previous clock cycle clk M with the lowest bit of the parallel data data_reg[N-1:0] in the previous clock cycle and output it in the next clock cycle clkM+1.

[0110] As a further preferred technical solution, the splicing unit is further used for:

[0111] Register the parallel data data[N-1:0] in the previous clock cycle clk M-1 to the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M;

[0112] Discard the newly entered parallel data data[N-1:1] in the current clock cycle clk M and retain data[0];

[0113] Splice the parallel data data_reg[N-1:1] and data[1] and output it in the next clock cycle clkM+1.

[0114] As a further preferred technical solution, the parallel data calculation unit is specifically used to perform forward splicing and reverse splicing on the parallel data in the previous clock cycle and the serial data in the current clock cycle to obtain a slow clock signal with a bit width of 2N and parallel data with a bit width of 2N.

[0115] It should be noted that other embodiments or specific implementation methods of the ADC performance test platform of the present invention can refer to the above method embodiments and will not be elaborated here.

[0116] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0117] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0118] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for testing ADC performance, characterized in that: include: Acquire a differential serial digital signal output by the ADC chip to be tested, wherein the serial digital signal includes a slow clock signal and serial data; Converting the serial digital signal into a parallel digital signal, wherein the parallel digital signal includes a slow clock signal and parallel data; Performing a register splicing operation on the parallel digital signal to restore ADC parallel output data, wherein when the serial data lags behind the slow clock signal, the highest bit of the parallel data in the current clock cycle is replaced by the lowest bit of the parallel data in the previous clock cycle and then output in the next clock cycle; when the serial data leads the slow clock signal, the highest bit to the second lowest bit of the parallel data in the previous clock cycle are spliced ​​with the lowest bit of the parallel data in the current clock cycle and then output in the next clock cycle; The ADC parallel output data is output to a computer so that the computer analyzes the ADC parallel output data to obtain dynamic parameter indicators of the ADC.

2. The ADC performance testing method according to claim 1, wherein: The converting the serial digital signal into a parallel digital signal comprises: The input slow clock signal and the serial data are spliced ​​using Select IP to obtain a parallel digital signal, wherein Select IP is a Verilog encapsulation file deployed in the FPGA chip, the bit width of the data input port of Select IP is 2, and the serialization factor of the IP core is N.

3. The ADC performance testing method according to claim 2, wherein: The serial digital signal further includes a fast clock signal, and the method further includes: Using Select IP to convert the input fast clock signal into a control clock signal, where the control clock signal is 2*N times the fast clock signal; The control clock signal is output synchronously with the parallel digital signal, and the parallel digital signal is updated at the rising edge of each cycle of the control clock signal.

4. The ADC performance testing method according to claim 1, wherein: The performing a register splicing operation on the parallel digital signal to restore ADC parallel output data includes: Performing a splicing operation on the parallel digital signal with a bit width of 2*N to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N; The slow clock signal with a bit width of N and the parallel data with a bit width of N are respectively registered and spliced ​​to obtain a slow clock signal with a bit width of 2*N and parallel data with a bit width of 2*N, and the ADC parallel output data is restored.

5. The ADC performance testing method according to claim 4, characterized in that: When the serial data lags behind the slow clock signal, the parallel digital signal with a bit width of 2*N is spliced ​​to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N, including: The parallel data data[N-1:0] in the previous clock cycle clk M-1 is stored in the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M; The highest bit of the newly entered parallel data data[N-1:0] in the previous clock cycle clk M is replaced by the lowest bit of the parallel data data_reg[N-1:0] in the previous clock cycle and then output in the next clock cycle clkM+1.

6. The ADC performance testing method according to claim 4, wherein: When the serial data is ahead of the slow clock signal, the parallel digital signal with a bit width of 2*N is spliced ​​to obtain a slow clock signal with a bit width of N and parallel data with a bit width of N, including: The parallel data data[N-1:0] in the previous clock cycle clk M-1 is stored in the current clock cycle clk M to obtain the parallel data data_reg[N-1:0] in the current clock cycle clk M; The parallel data data[N-1:1] newly entered in the current clock cycle clk M is discarded, and data[0] is retained; The parallel data data_reg[N-1:1] is concatenated with data[0] and outputted in the next clock cycle clkM+1.

7. The ADC performance testing method according to claim 4, characterized in that: The method of registering and splicing a slow clock signal with a bit width of N and parallel data with a bit width of N respectively to obtain a slow clock signal with a bit width of 2*N and parallel data with a bit width of 2*N includes: The parallel data in the previous clock cycle is forward-joined and reverse-joined with the parallel data in the current clock cycle to obtain a slow clock signal with a bit width of 2*N and parallel data with a bit width of 2*N.

8. The ADC performance testing method according to claim 2, wherein: The bit width of the parallel digital signal is twice the serialization factor of the IP core.

9. An ADC performance test platform, characterized in that: The method comprises an FPGA and a computer, wherein the output of the FPGA is connected to the computer, and the FPGA is used to execute the ADC performance test method according to any one of claims 1 to 8, and the FPGA comprises: A signal acquisition module, used to acquire a differential serial digital signal output by the ADC chip to be tested, wherein the serial digital signal includes a slow clock signal and serial data; A deserialization module, used for converting the serial digital signal into a parallel digital signal, wherein the parallel digital signal includes a slow clock signal and parallel data; A parallel digital signal recovery module is used to perform a register splicing operation on the parallel digital signal to recover the ADC parallel output data, wherein when the serial data lags behind the slow clock signal, the highest bit of the parallel data in the current clock cycle is replaced by the lowest bit of the parallel data in the previous clock cycle and then output in the next clock cycle; when the serial data leads the slow clock signal, the highest bit to the second lowest bit of the parallel data in the previous clock cycle are spliced ​​with the lowest bit of the parallel data in the current clock cycle and then output in the next clock cycle; The signal output module is used to output the ADC parallel output data to a computer so that the computer can analyze the ADC parallel output data to obtain the dynamic parameter index of the ADC.

10. The ADC performance test platform according to claim 9, characterized in that: The platform also includes a clock generator, a signal generator and a power supply connected to the ADC chip to be tested; The clock generator is used to generate a clock signal for the ADC chip to be tested; The signal generator is used to generate an input signal for the ADC chip to be tested, and the frequency of the input signal satisfies the coherent sampling theorem; The power supply is used to generate the operating voltage of the ADC chip to be tested.

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