DShot digital communication method and system based on I2S peripheral, medium, program and terminal

Abstract

The invention provides a DShot digital communication method and system based on an I2S peripheral, a medium, a program and a terminal, the I2S peripheral is adopted to transmit a DShot signal, the burden and development complexity of an MCU are effectively reduced, and a higher audio data signal transmission rate and better signal synchronism can be supported.

Description

Technical Field

[0001] The present application relates to the field of UAV communication, and particularly to a DShot digital communication method, system, medium, program, and terminal based on an I2S peripheral. Background Art

[0002] The electronic speed controller (ESC), controller, and DShot signal of an unmanned aerial vehicle (UAV) are key components in the UAV power system, and they work together to achieve precise flight control. The ESC, as an electronic speed controller, is responsible for converting the instructions of the flight controller into the rotational speed signal of the motor to ensure the stable flight of the UAV. DShot (DigitalShot) is a digital communication protocol used to control the ESC (Electronic Speed Controller) of the UAV flight controller (FlightController). It aims to replace the old analog protocols (such as PWM) and early digital protocols (such as OneShot and MultiShot), and has higher precision, higher reliability, and stronger anti-interference ability.

[0003] The conventional output method of the DShot signal is to use the PWM peripheral of the MCU or directly operate the GPIO, and combine with DMA to automatically send the DShot signal. These two methods have the following disadvantages:

[0004] (1) The software implementation logic is relatively complex, and the overhead of the MCU is also large. Using the PWM peripheral requires a complex initialization and configuration process, including setting the clock source, adjusting the duty cycle and frequency, etc. These steps require detailed code writing and debugging, increasing the difficulty of software development. Directly operating the GPIO pins requires manual control of the rising and falling edges of the signal, which has high requirements for the real-time performance and accuracy of the software, further increasing the implementation complexity. Moreover, combining with DMA to automatically send the DShot signal, although it improves the efficiency, requires correct configuration of the DMA controller, setting the transfer descriptor, and ensuring that the data can be accurately transmitted to the PWM or GPIO peripheral. This process requires in-depth understanding of the working principle and interface of DMA, increasing the complexity of software design.

[0005] (2) The DShot communication rate is limited by the MCU hardware, and currently the highest rate usually only supports up to DShot1200. Since the generation of the DShot signal depends on the clock frequency of the MCU. To support a higher signal frequency, the MCU needs to have a higher clock frequency, which may lead to increased power consumption and heat dissipation problems. Moreover, as the DShot signal frequency increases, the MCU needs to complete the tasks of signal generation and transmission in a shorter time, which poses higher requirements for the processing ability of the MCU. And a higher frequency means a shorter pulse width, requiring faster response and more precise timing control.

[0006] (3) When multiple channels of DShot work simultaneously, the data synchronization between channels is poor. In an unmanned aerial vehicle (UAV), it is usually necessary to control multiple motors simultaneously, and each motor corresponds to a DShot signal channel. When using the PWM+DMA or GPIO+DMA method, the signal generation of each channel may be independent, lacking a unified synchronization mechanism, resulting in a phase deviation between signals. Since the signal generation of each channel depends on its respective PWM or GPIO configuration, it is difficult to ensure the strict synchronization of all channel signals. This difference in timing may affect the attitude control and flight stability of the UAV. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of this application is to provide a DShot digital communication method, system, medium, program, and terminal based on the I2S peripheral to solve the above problems.

[0008] To achieve the above purpose and other related purposes, the first aspect of this application provides a DShot digital communication method based on the I2S peripheral, which is applied to an MCU integrated with multiple I2S data channels, including: setting the working mode, audio data unit width, width, depth, and data slot width of the transmission FIFO corresponding to each data channel of the I2S peripheral according to preset parameters, where the data slot width should be greater than or equal to the audio data unit width, and the total number of data slots that each transmission FIFO can accommodate should be greater than or equal to 16; adjusting the BCLK clock frequency in the I2S peripheral to 16 times the DShot signal frequency according to the preset DShot signal frequency; using 16 audio data units to implement 1 frame of DShot signal according to the bit pulse width modulation coding method of the DShot signal, where the logic 0 or 1 of each bit of the DShot signal is implemented by 1 audio data unit; in response to the user's operation instruction, encoding the corresponding DShot signal with an audio data signal and simultaneously outputting the encoded multiple channels of DShot signals from their corresponding SDOUT ports, where an interval is set between adjacent frames of the DShot signal during encoding, and the audio data signal corresponding to the interval is set to a low level.

[0009] In an embodiment of the first aspect of this application, the audio data width in the preset parameters is 16 bit, the width of the transmission FIFO is 32 bit and the depth is greater than or equal to 8, and the data slot width is 16 bit.

[0010] In an embodiment of the first aspect of the present application, before the audio data fills all the data slots in each transmission FIFO, the output of the I2S peripheral is paused. After all the data slots in each transmission FIFO are filled with audio data, the output of the I2S peripheral is then enabled.

[0011] In an embodiment of the first aspect of the present application, when the working mode of the I2S peripheral is the master mode, while MCLK, BCLK, and LRCLK provide the clock reference for this I2S peripheral, they output clock signals to other I2S peripherals operating in the slave mode to provide the clock reference for the I2S peripherals operating in the slave mode.

[0012] In an embodiment of the first aspect of the present application, when the working mode of the I2S peripheral is the slave mode, MCLK, BCLK, and LRCLK receive the clock signals sent by the I2S peripheral operating in the master mode as the clock reference for this I2S peripheral.

[0013] To achieve the above object and other related objects, the second aspect of the present application provides a DShot digital communication system based on an I2S peripheral. The I2S peripheral supports multi-channel data transmission and includes: an I2S peripheral and a CPU, which cooperate to perform the following method: set the working mode, audio data unit width, width, depth, and data slot width of the transmission FIFO corresponding to each data channel of the I2S peripheral according to preset parameters, where the data slot width should be greater than or equal to the audio data unit width, and the total number of data slots that each transmission FIFO can accommodate should be greater than or equal to 16; adjust the BCLK clock frequency in the I2S peripheral to the product of the DShot signal frequency and the audio data unit width according to the preset DShot signal frequency; use 16 audio data units to implement 1 frame of DShot signal according to the bit pulse width modulation coding method of the DShot signal, where the logic 0 or 1 of each bit of the DShot signal is implemented by 1 audio data unit; in response to the user's operation instruction, encode the corresponding DShot signal using the audio data signal and simultaneously output the encoded multi-channel DShot signals from their corresponding SDOUT ports. During encoding, an interval is set between adjacent frames of the DShot signal, and the audio data signal corresponding to the interval is set to a low level.

[0014] In an embodiment of the second aspect of the present application, it includes a plurality of cascaded I2S peripherals. The BCLK, LRCLK, and MCLK of each I2S peripheral in the master mode are respectively connected to the corresponding clocks of other I2S peripherals in the slave mode. Before the audio data fills all the data slots in each transmission FIFO of all I2S peripherals, the output of the I2S peripherals is paused. After all the data slots in each transmission FIFO of all I2S peripherals are filled with audio data, the output of the I2S peripherals is then enabled.

[0015] To achieve the above object and other related objects, a third aspect of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method described in any one of the foregoing is implemented.

[0016] To achieve the above object and other related objects, a fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code runs on a computer, the computer is enabled to implement the method described in any one of the foregoing.

[0017] To achieve the above object and other related objects, a fifth aspect of the present application provides an electronic terminal, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the method described in any one of the foregoing.

[0018] As described above, the present application has the following beneficial effects:

[0019] (4) Since the I2S peripheral itself has built-in synchronization and timing control functions, the present application can reduce the direct control requirements for signal rising edges and falling edges in software. Moreover, the I2S protocol has built-in hardware clock synchronization, so the generation and timing control of signals no longer depend on the processing power and clock frequency of the MCU, thereby effectively reducing the burden on the MCU and at the same time reducing the power consumption problem. In addition, the configuration of the I2S peripheral is simpler. Compared with the PWM and GPIO methods, I2S does not require developers to finely control the clock, duty cycle, and signal regulation, greatly reducing the development complexity.

[0020] (5) The high-precision timing control of I2S can achieve more precise pulse width adjustment without depending on the clock frequency of the MCU, thus avoiding the bottleneck of response speed and real-time performance at high frequencies. Therefore, it can support a higher audio data signal transmission rate. When the present application uses 16 audio data units to implement 1 frame of DShot signal, it can also maintain a relatively high DShot signal frequency, making the implementation of DShot2400 and DShot4800 no longer a pipe dream.

[0021] (6) The multiple channels within the I2S peripheral and the shared clock signals between multiple I2S peripherals can ensure that the data transmission of each channel is strictly synchronized, so that the output of each DShot signal can be completed within the same clock cycle, which greatly improves the reliability and consistency of data transmission, thereby improving the stability of multi-motor control and flight accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a partial structural diagram of a Codec integrating multiple I2S data channels in one embodiment of the present application.

[0023] Figure 2 It is a schematic diagram showing the corresponding relationship between the Dshot signal and the audio data signal in one embodiment of the present application.

[0024] Figure 3 Shown is a schematic diagram of the DShot signal bit encoding rules in one embodiment of the present application.

[0025] Figure 4 It is a schematic diagram showing the use of an audio data unit with a bit width of 16 to implement one bit of a DShot signal in one embodiment of the present application.

[0026] Figure 5 Shown is a schematic diagram of a process of using a four-way data channel I2S peripheral to output a DShot signal in one embodiment of the present application.

[0027] Figure 6 Shown is a schematic diagram of the structure of multiple I2S peripheral cascades in one embodiment of the present application.

[0028] Figure 7 Shown is a flow chart of using multiple cascaded I2S peripheral data channels to output DShot signals in one embodiment of the present application.

[0029] Figure 8 Shown is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0031] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0032] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the front and back associated objects. "At least one (item)" or similar expressions thereof refer to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c may represent: a, b, c, a - b, a - c, b - c or a - b - c, where a, b, c may be single or multiple.

[0033] As Figure 1 shown, a first aspect of the present application provides a DShot digital communication method based on an I2S peripheral, which is applied to an MCU integrating multiple I2S data channels, and its steps include:

[0034] S1: Set the working mode, audio data unit width, width, depth and data slot width of the transmission FIFO corresponding to each data channel of the I2S peripheral according to preset parameters, where the data slot width should be greater than or equal to the audio data unit width, and the total number of data slots that each transmission FIFO can accommodate should be greater than or equal to 16.

[0035] In I2S audio transmission, the "audio data unit width" generally refers to the bit width of mono data in each sample or audio frame. The bit widths of existing audio data units are 16 bits, 24 bits or 32 bits.

[0036] It should be understood that the transmission FIFO mentioned in this application refers to the transmission FIFO buffer. The FIFO buffer (hereinafter referred to as FIFO) includes a transmission FIFO and a reception FIFO. FIFO is a first-in-first-out queue storage structure. Each data channel corresponds to an independent transmission FIFO and reception FIFO to ensure parallel processing of multiple-channel data without mutual conflict. The width of the FIFO refers to the number of bits of the audio data unit that each FIFO cell can accommodate. For example, when the bit width of the audio data unit is 16 bits, the width of the FIFO will be set to be greater than or equal to 16 bits to ensure that a single read / write operation exactly corresponds to a complete sample or "pulse data unit".

[0037] The data slot is used to allocate a fixed-width transmission time slot to a sound channel or channel in the time domain. It is a time division concept at the protocol layer / interface layer and can be regarded as a container for carrying audio data units. The FIFO is responsible for queuing and storing data, while the data slot tells the hardware at what time point to fetch which data (or put it where). Only by the cooperation of the two can the multi-channel and orderly audio data transmission be successfully achieved. If we want to ensure that a complete audio data unit can be placed within the corresponding time window, the bit width of the data slot must be greater than or equal to the bit width of the audio data unit. If the data slot is too small, it will cause the data unit to not be sent completely at one time, or be truncated and distorted. Therefore, it is necessary to ensure that the data slot is large enough to accommodate a whole "sample" or whole "pulse unit". Currently, the data slot width supports 16 bits and 32 bits. Since the bit width of the audio data unit can be 16 bits, 24 bits or 32 bits, the following four data format combinations can be generated: (1) encapsulating 16-bit audio data into a 16-bit data slot; (2) encapsulating 16-bit audio data into a 32-bit data slot; (3) encapsulating 24-bit audio data into a 32-bit data slot; (4) encapsulating 32-bit audio data into a 32-bit data slot.

[0038] The DShot signal is a digital pulse signal output based on the DShot protocol format, which supports a variety of different transmission rates, such as DShot150, DShot300, DShot600, DShot1200 (the number represents the bit rate, and the unit is kbps). The DShot signal adopts a fixed-length frame format, and one frame has a total of 16 bits. Since this application uses one audio data unit to encode one bit of the DShot signal, the 16 bits of one frame of the DShot signal need to be encoded by 16 audio data units. If we want the transmission FIFO to be able to store the 16 bits of one frame of the DShot signal, at least 16 data slots can be stored in the transmission FIFO. Since the bit width of the FIFO is usually 16 and 32, to meet this condition, the possible bit width and depth of the transmission FIFO are as follows:

[0039] (1) Enclose 16-bit audio data into 16-bit data slots. When the transmission FIFO bit width is 16, the depth is 16.

[0040] (2) Enclose 16-bit audio data into 16-bit data slots. When the transmission FIFO bit width is 32, the depth is 8.

[0041] (3) Enclose 16-bit audio data into 32-bit data slots. When the transmission FIFO bit width is 32, the depth is 16.

[0042] (4) Enclose 24-bit audio data into 32-bit data slots. When the transmission FIFO bit width is 32, the depth is 16.

[0043] (5) Enclose 32-bit audio data into 32-bit data slots. When the transmission FIFO bit width is 32, the depth is 16.

[0044] Preferably, the width of the audio data in the preset parameters is 16 bit, the width of the transmission FIFO is 32 bit and the depth is greater than or equal to 8, and the width of the data slot is 16 bit. In the case of this preferred embodiment, the 32-bit wide buffer FIFO with a depth of 8 can exactly hold all 16 uint16_t audio data, that is, the transmission FIFO with a depth of 1 can accommodate the audio data corresponding to 2 data slots with a width of 16 Bit. If 32-bit data slots are used, a 32-bit wide transmission FIFO with a depth of 16 is required. Therefore, this embodiment can reduce the requirement for the depth of the I2S transmission FIFO.

[0045] In the I2S protocol, each channel will be assigned a data slot. When multiple channels are set, CLK (clock) will transmit these data slots in a time-sharing manner. For example, one slot for the left channel, one slot for the right channel, or more channels arranged in sequence. The embodiments of the present application introduce the related technologies by taking the dual-channel as an example, but single-channel or other multi-channel I2S peripherals that can implement the encoding and transmission of DShot signals according to the method described in the present application fall within the protection scope of the present application. The dual-channel here does not constitute a limitation on the protection scope of the present application.

[0046] S2: According to the preset DShot signal frequency, adjust the BCLK clock frequency in the I2S peripheral to the product of the DShot signal frequency and the width of the audio data unit.

[0047] The signal frequency of DShot is how many bits are transmitted per second. For example, the transmission rate of DShot300 is 300 kbps, and its signal frequency is 300 kHz, that is, 300,000 bits are transmitted per second. In I2S, the frequency of the audio data signal is how many audio bits are transmitted per second, and BCLK (bit clock) is the clock that controls each bit of the transmitted audio data signal. Therefore, when the bit width of the audio data signal is 16 and 16 audio data units are used to implement one frame of DShot signal, the BCLK frequency is 16 times that of the DShot signal; when the bit width of the audio data signal is 24 and 16 audio data units are used to implement one frame of DShot signal, the BCLK frequency is 24 times that of the DShot signal; when the bit width of the audio data signal is 32 and 16 audio data units are used to implement one frame of DShot signal, the BCLK frequency is 32 times that of the DShot signal. In summary, the BCLK frequency is the product of the DShot signal frequency and the bit width of the audio data signal.

[0048] In an embodiment of the present application, when the bit width of the audio data signal unit is 16, since one frame of DShot signal has 16 bits, 16 16-bit audio data can be used to drive it, that is, convert a uint16_t data into a one-dimensional uint16_t array with a length of 16. As Figure 2 shown, the DShot protocol uses the MSB-first method during data transmission, that is, the most significant bit (MSB) of the data frame is sent first, and the least significant bit (LSB) is sent last. Therefore, it should be noted to convert the bit order of the 16-bit DShot data into 16 16-bit audio data. Bit15 of the DShot data corresponds to Index: 0 of the audio array, Bit14 of the DShot data corresponds to Index: 1 of the audio array; and so on, Bit0 of the DShot data corresponds to Index: 15 of the audio array. It should be understood that the bit width of the audio data unit being 16 is only an embodiment of the present application and does not limit the protection scope of the present invention. Audio data signals with a bit width of 24, 32, or other bit widths can also implement one bit of the Dshot signal according to the above corresponding rules.

[0049] S3: According to the pulse width modulation coding method of the bits of the DShot signal, use 16 audio data units to implement 1 frame of DShot signal, where the logic 0 or 1 of each bit of the DShot signal is implemented by 1 audio data unit.

[0050] As Figure 3As shown, each bit of the DShot signal adopts a pulse-width modulation coding rule, that is, the logical 0 and logical 1 of the bit are represented by the duration of the high and low levels. The high-level duration of logical 0 is shorter (short pulse), and the high-level duration of logical 1 is longer (long pulse). The time of T0H + T0L or T1H + T1L is the time of one bit period. For example, DSHOT600, that is, 600 kbps, the time of 1 bit is 1.67 us, that is, the time of T0H + T0L or T1H + T1L is 1.67 us.

[0051] As Figure 4 As shown, in an embodiment of the present application, when the bit width of the audio data unit is 16, 16-bit audio data signals are required to implement one bit of the DShot signal. It can be set that when the upper 10 bits of the 16-bit audio data are 1 and the lower 6 bits are 0, that is, the hexadecimal number is 0xFFC0, which represents the logical 1 of one bit of the DShot; when the upper 6 bits of the 16-bit audio data are 1 and the lower 10 bits are 0, that is, the hexadecimal number is 0xFC00, which represents the logical 0 of one bit of the DShot.

[0052] It should be understood that the bit width of the audio data unit being 16 is an embodiment of the present application and does not constitute a limitation on the protection scope of the present invention. It is also possible to use 24-bit, 32-bit or other bit-width audio data signals to implement one bit of the DShot signal according to the pulse-width modulation coding rule.

[0053] S4: In response to the user's operation instruction, use the audio data signal to encode the corresponding DShot signal, and simultaneously output the encoded multiple DShot signals from their corresponding SDOUT ports. Among them, an interval is set between adjacent frames of the DShot signal during encoding, and the audio data signal corresponding to the interval is set to a low level.

[0054] In an embodiment of the first aspect of the present application, before the audio data fills all the data slots in each transmit FIFO, the output of the I2S peripheral is paused. After all the data slots in each transmit FIFO are filled with audio data, the output of the I2S peripheral is then enabled.

[0055] As Figure 5As shown in the figure, in an embodiment of the present application, I2S has a total of four data channels, including four transmit FIFOs, four receive FIFOs, as well as four SDOUTs and SDINs. First, the application prepares four channels of DShot data to be output, that is, 4 uint16_t data; then, these four channels of DShot data are converted into 4 uint16_t audio arrays with a length of 16. Next, the clock of the I2S peripheral is turned off to prohibit the I2S peripheral from outputting DShot signals from the SDOUT port. After all four transmit FIFOs are filled (that is, a frame of DShot signals is stored inside the transmit FIFOs), the clock is turned on to start the output of I2S.

[0056] It should be understood that the reason for turning on the output of the I2S peripheral only after all transmit FIFOs are filled is that when the interface control module of the I2S peripheral receives audio data sent by the CPU from the bus, it will not write all the data to fill the four transmit FIFOs at one time; it will forward the data to each transmit FIFO in sequence according to the internal timing. There are mainly two modes in this forwarding process:

[0057] One is polling filling, that is, each time only one audio data unit is filled into a certain transmit FIFO. The example process is as follows: first, fill one audio data unit into the SOUT0 transmit FIFO, then fill the next audio data unit into the SOUT1 transmit FIFO, and then fill the transmit FIFOs of SOUT2 and SOUT3 in sequence. Then, loop back to the SOUT0 transmit FIFO and fill the next batch of data units.

[0058] The other is sequential filling, that is, first continuously write to the SOUT0 transmit FIFO until it is filled; then switch to the SOUT1 transmit FIFO and fill it; then fill the transmit FIFOs of SOUT2 and SOUT3 in sequence.

[0059] Since the filling is carried out in batches or by channels, if the I2S output is turned on before all four transmit FIFOs are fully filled, some transmit FIFOs may not have obtained enough data, resulting in the risk of interruption or incomplete output during subsequent transmission. By waiting for all transmit FIFOs to be filled before starting the output, it can be ensured that the data of each channel is ready, thus ensuring that the subsequent DShot signals can be output in frames.

[0060] In an embodiment of the first aspect of the present application, when the working mode of the I2S peripheral is the master mode, while MCLK, BCLK, and LRCLK provide a clock reference for this I2S peripheral, they output clock signals to other I2S peripherals operating in the slave mode to provide a clock reference for the I2S peripherals operating in the slave mode.

[0061] In an embodiment of the first aspect of the present application, when the working mode of the I2S peripheral is the slave mode, MCLK, BCLK, and LRCLK receive the clock signals sent by the I2S peripheral operating in the master mode as the clock reference for this I2S peripheral.

[0062] The second aspect of the present application provides a DShot digital communication system based on an I2S peripheral. The I2S peripheral supports multi-channel data transmission, including: setting the working mode of the I2S peripheral, the width of the audio data unit, the width, depth, and data slot width of the transmit FIFO corresponding to each data channel according to preset parameters, where the data slot width should be greater than or equal to the audio data unit width, and the total number of data slots that each transmit FIFO can accommodate should be greater than or equal to 16; adjusting the BCLK clock frequency in the I2S peripheral to the product of the DShot signal frequency and the audio data unit width according to the preset DShot signal frequency; using 16 audio data units to implement 1 frame of DShot signal according to the bit pulse width modulation coding method of the DShot signal, where the logic 0 or 1 of each bit of the DShot signal is implemented by 1 audio data unit; in response to the user's operation instruction, encoding the corresponding DShot signal with an audio data signal and simultaneously outputting the encoded multi-channel DShot signals from their corresponding SDOUT ports respectively, where an interval is set between adjacent frames of the DShot signal during encoding, and the audio data signal corresponding to the interval is set to a low level; a bus for data transmission between the I2S peripheral and the CPU.

[0063] It should be understood that the specific processes for each module to execute the above corresponding steps have been described in detail in the above method embodiments. For the sake of brevity, they will not be repeated here.

[0064] It should also be understood that the division of modules in the embodiments of the present application is illustrative, merely a logical function division. In actual implementation, there may be other division methods. Additionally, in each embodiment of the present application, the various functional modules may be integrated in one processor, or may exist separately physically, or two or more modules may be integrated in one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0065] In an embodiment of the second aspect of the present application, it includes a plurality of cascaded I2S peripherals. The BCLK, LRCLK, and MCLK of each I2S peripheral in the master mode are respectively connected to the corresponding clocks of other I2S peripherals in the slave mode; before the audio data fills all the data slots in each transmission FIFO of all I2S peripherals, the output of the I2S peripherals is paused. After all the data slots in each transmission FIFO of all I2S peripherals are filled with audio data, the output of the I2S peripherals is then turned on. The I2S of this patent can also be cascaded. Using multiple I2S peripherals can achieve fully synchronous output of more channels of DShot signals.

[0066] As Figure 6 shown, after cascading N I2S peripherals, only one of the I2S peripherals works in the master mode, and the remaining (N - 1) I2S peripherals work in the slave mode. When the I2S in the master mode is working, it outputs MCLK, FCLK, and BCLK to drive the I2S in the slave mode to work, so that the I2S in the master mode and the I2S in the slave mode synchronously output the data in their respective SDOUT transmission FIFOs. In this way, the I2S in the master mode and the I2S in the slave mode can achieve fully synchronous output, and more channels of SDOUT signal synchronous output can be extended, that is, DShot signal synchronous output.

[0067] After cascading N I2S peripherals, assuming there are M data channels in total, the I2S in the master mode closes and starts transmission according to service requirements. The working process of fully synchronous output of M channels of DShot signals is as Figure 7 shown. When the master and slave I2S are cascaded, the I2S in the slave mode starts transmission after initialization, but whether data transmission can actually be performed depends on whether the master mode starts transmission. If the I2S in the master mode does not start transmission, it will not output MCLK, FCLK, and BCLK. Therefore, the I2S in the slave mode has no clock signal to drive and will not transmit data either; if the I2S in the master mode starts transmission, it will output MCLK, FCLK, and BCLK. The I2S in the slave mode gets the clock signal to drive and it has already started transmission, so the slave mode also starts to transmit data, which realizes synchronous data transmission between the master and slave I2S.

[0068] To achieve the above object and other related objects, the third aspect of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the method described in any one of the foregoing.

[0069] To achieve the above object and other related objects, the fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code runs on a computer, it causes the computer to implement the method described in any one of the foregoing.

[0070] To achieve the above and other related objectives, a fifth aspect of the present application provides an electronic terminal, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the method described in any one of the foregoing. As shown in the figure, the electronic terminal includes: at least one processor 801, a memory 802, at least one network interface 803, and a user interface 805. Each component in the device is coupled together through a bus system 804. It can be understood that the bus system 804 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus.

[0071] Among them, the user interface 805 may include a display, a keyboard, a mouse, a trackball, a click gun, a button, a touchpad, or a touch screen, etc.

[0072] It can be understood that the memory 802 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory). The memory described in the embodiments of the present invention is intended to include but not limited to these and any other suitable categories of memories.

[0073] The memory 802 in the embodiments of the present invention is used to store various categories of data to support the operation of the electronic terminal 800. Examples of these data include: any executable program for operating on the electronic terminal 800, such as an operating system 8021 and an application program 8022; the operating system 8021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 8022 may include various application programs, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. Implementing the method provided by the embodiments of the present invention may be included in the application program 8022.

[0074] The method disclosed in the embodiments of the present invention described above can be applied to or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above method can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 801. The above-mentioned processor 801 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 801 may be a microprocessor or any conventional processor, etc. Combining the steps of the accessory optimization method provided in the embodiments of the present invention can be directly embodied as being completed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory. The processor reads the information in the memory and combines its hardware to complete the steps of the foregoing method.

[0075] In an exemplary embodiment, the electronic terminal 800 may be an application specific integrated circuit (ASIC), a DSP, a programmable logic device (PLD), or a complex programmable logic device (CPLD) for executing the foregoing method.

[0076] The terms "component", "module", "system", etc. used in this specification are used to denote computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, an application running on a computing device and the computing device can both be components. One or more components may reside in a process and / or execution thread, and a component may be located on one computer and / or distributed between two or more computers. In addition, these components may execute from various computer-readable media on which various data structures are stored. A component may communicate, for example, according to a signal having one or more data packets (such as data from two components interacting with each other from a local system, a distributed system, and / or a network, such as data interacting with other systems via a signal on the Internet) via local and / or remote processes.

[0077] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0078] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0079] In several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0080] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0082] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a high-definition digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD), etc.).

[0083] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application. The foregoing storage medium includes: USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disc, etc., which can store program codes of various kinds.

[0084] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all of them should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0085] In summary, the present application effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0086] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present application should still be covered by the claims of the present application.

Claims

1. A DShot digital communication method based on I2S peripherals, applied to an MCU integrating multiple I2S data channels, characterized in that: include: The working mode of the I2S peripheral, the audio data unit width, the width, depth and data slot width of the transmit FIFO corresponding to each data channel are set according to preset parameters, wherein the data slot width should be greater than or equal to the audio data unit width, and the total number of data slots that each transmit FIFO can accommodate should be greater than or equal to 16; According to a preset DShot signal frequency, adjusting the BCLK clock frequency in the I2S peripheral to the product of the DShot signal frequency and the audio data unit width; According to the bit pulse width modulation encoding method of the DShot signal, 16 audio data units are used to realize one frame of the DShot signal, wherein the logic 0 or 1 of each bit of the DShot signal is realized by one audio data unit; In response to the user's operation instructions, the corresponding DShot signal is encoded using the audio data signal, and the encoded multiple DShot signals are output simultaneously from their corresponding SDOUT ports, wherein an interval is set between adjacent frames of the DShot signal during encoding, and the audio data signal corresponding to the interval is set to a low level.

2. A DShot digital communication method based on I2S peripherals according to claim 1, characterized in that: The audio data width in the preset parameters is 16 bits, the width of the sending FIFO is 32 bits and the depth is greater than or equal to 8, and the data slot width is 16 bits.

3. A DShot digital communication method based on I2S peripherals according to claim 1, characterized in that: Before the audio data fills up all the data slots in each transmit FIFO, the output of the I2S peripheral is suspended, and after all the data slots in each transmit FIFO are filled up with the audio data, the output of the I2S peripheral is enabled.

4. A DShot digital communication method based on I2S peripherals according to claim 1, characterized in that: When the working mode of the I2S peripheral is the master mode, MCLK, BCLK and LRCLK provide clock references for the I2S peripheral and output clock signals to other I2S peripherals working in the slave mode to provide clock references for the I2S peripherals working in the slave mode.

5. A DShot digital communication method based on I2S peripherals according to claim 1, characterized in that: When the working mode of the I2S peripheral is the slave mode, MCLK, BCLK and LRCLK receive the clock signal sent by the I2S peripheral working in the master mode as the clock reference of the I2S peripheral.

6. A DShot digital communication system based on an I2S peripheral, wherein the I2S peripheral supports multi-channel data transmission, characterized in that: include: The I2S peripheral and the CPU are used to work together to perform the following method: setting the working mode of the I2S peripheral, the audio data unit width, the width, depth and data slot width of the sending FIFO corresponding to each data channel according to preset parameters, wherein the data slot width should be greater than or equal to the audio data unit width, and the total number of data slots that each sending FIFO can accommodate should be greater than or equal to 16; according to the preset DShot signal frequency, adjusting the BCLK clock frequency in the I2S peripheral to the product of the DShot signal frequency and the audio data unit width; according to the bit pulse width modulation encoding method of the DShot signal, using 16 audio data units to realize 1 frame of DShot signal, wherein the logic 0 or 1 of each bit of the DShot signal is realized by 1 audio data unit; in response to the user's operation instruction, using the audio data signal to encode the corresponding DShot signal, and outputting the encoded multiple DShot signals from their corresponding SDOUT ports simultaneously, wherein, when encoding, setting an interval between adjacent frames of the DShot signal, and setting the audio data signal corresponding to the interval to a low level; A bus is used for data transmission between the I2S peripheral and the CPU.

7. A DShot digital communication system based on I2S peripherals according to claim 6, characterized in that: The method comprises a plurality of cascaded I2S peripherals, wherein the BCLK, LRCLK and MCLK of each master mode I2S peripheral are respectively connected to the corresponding clocks of other slave mode I2S peripherals; before the audio data fills up all the data slots in each transmit FIFO of all the I2S peripherals, the output of the I2S peripherals is suspended, and after all the data slots in each transmit FIFO of all the I2S peripherals are filled up with the audio data, the output of the I2S peripherals is enabled.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

9. A computer program product, characterized in that The computer program product includes a computer program code, and when the computer program code is executed on a computer, the computer is enabled to implement the method as described in any one of claims 1 to 5.

10. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 1 to 5.

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