Voltage selection circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a voltage selection circuit, a chip and electronic equipment, and the voltage selection circuit comprises a bias current generation module which is used for generating bias current; the voltage comparison module is used for comparing the first voltage and the second voltage according to the bias current and outputting a level control signal; the maximum voltage output module is used for selecting the highest one of the first voltage and the second voltage to output according to the level control signal; the bias current generating module generates bias current according to the first voltage and the second voltage. No extra reference voltage or power supply needs to be provided for the bias current generation module, so that the circuit complexity and the circuit power consumption of the voltage selection circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a voltage selection circuit, a chip, and an electronic device. Background Art

[0002] Currently, when a circuit involves multiple voltage sources for power supply, it is often necessary to select the input voltage signal with a higher voltage as the power supply voltage signal to improve the driving ability of the circuit.

[0003] In the related art, in order to improve the current driving ability, the maximum voltage selection circuit usually includes a bias current source, a voltage comparison circuit, and a Schmitt trigger. The bias current source provides the bias current required for the operation of the voltage comparison circuit, enabling the voltage comparison circuit to compare the magnitudes of two voltages, and finally selecting the higher one of the two voltage signals as the maximum voltage output through the level signal output by the Schmitt trigger. However, generating the bias current by the bias current source usually requires providing an additional reference voltage or power supply, which results in additional circuit overhead. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application provide a voltage selection circuit, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a voltage selection circuit, including:

[0006] A bias current generation module for generating a bias current;

[0007] A voltage comparison module for comparing the magnitudes of a first voltage and a second voltage according to the bias current and outputting a level control signal;

[0008] A maximum voltage output module for selecting and outputting the higher one of the first voltage and the second voltage according to the level control signal;

[0009] Wherein, the bias current generation module generates the bias current according to the first voltage and the second voltage.

[0010] In a second aspect, an embodiment of the present application further provides a chip including the above voltage selection circuit.

[0011] In a third aspect, an embodiment of the present application further provides an electronic device including the above chip or voltage selection circuit.

[0012] In this application, a bias current generation module generates a bias current, enabling the voltage comparison module to compare the magnitudes of a first voltage and a second voltage based on the bias current and output a level control signal. Consequently, the maximum voltage output module can select the higher of the first voltage and the second voltage according to the level control signal for output, thereby achieving the purpose of outputting the maximum voltage. Meanwhile, since the bias current generation module generates the bias current based on the first voltage and the second voltage, this means that no additional reference voltage or power supply needs to be provided to the bias current generation module. Therefore, it is beneficial to reduce the circuit complexity and circuit power consumption of the voltage selection circuit.

[0013] These aspects or other aspects of this application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 FIG. shows a schematic diagram of a maximum voltage selection circuit in the related art.

[0016] Figure 2 FIG. shows a schematic diagram of a voltage selection circuit in an embodiment of this application.

[0017] Figure 3 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0018] Figure 4 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0019] Figure 5 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0020] Figure 6 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0021] Figure 7 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0022] Figure 8 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0023] Figure 9 FIG. shows another schematic diagram of a voltage selection circuit in an embodiment of this application.

[0024] Figure 10 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0025] Figure 11 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0026] Figure 12 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0027] Figure 13 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0028] Figure 14 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0029] Figure 15 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0030] Figure 16 Shows another schematic diagram of the voltage selection circuit in the embodiment of the present application.

[0031] Among them, 10 is the bias current generation module, 11 is the voltage comparison unit, 12 is the bias current generation unit, 121 is the resistance adjustment sub-unit, 20 is the voltage comparison module, 21 is the current mirror unit, 22 is the clamping unit, 30 is the maximum voltage output module, 31 is the Schmitt trigger unit, 32 is the output driving unit, and 40 is the error correction module;

[0032] The first voltage VDD1, the second voltage VDD2, the maximum voltage VMAX, the bias current I0, the level control signal V0, the bias voltage Vdd, the first level signal VL1, and the second level signal VL2;

[0033] The first resistor R1, the second resistor R2, the adjustable resistor Rt, the voltage dividing resistor R0, the first node m1, the second node m2, the third node m3, the fourth node m4, the fifth node m5, and the sixth node m6;

[0034] The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, and the twelfth PMOS transistor MP12;

[0035] The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14. Detailed implementation manners

[0036] The following describes in detail the implementation manners of the present application. Examples of the implementation manners are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The implementation manners described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0037] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0038] In the embodiments of the present application, it should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0039] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0040] In the description of the embodiments of the present application, words such as "example" or "for example" are used to represent examples, explanations or descriptions. Any embodiment or design solution described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0041] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, it can be understood as one, two or more. For example, including at least one means including one, two or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A, B, and C.

[0042] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the associated objects before and after.

[0043] It should be pointed out that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0044] In the embodiments of the present application, the control terminal of each transistor is the gate of the transistor, the first pole / first end of each transistor is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be symmetric in structure, there may be no difference in their structures. That is to say, there may be no difference in the structures of the first pole / first end and the second pole / second end of the transistors in the embodiments of the present application. Exemplarily, when the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; Exemplarily, when the transistor is an N-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the source-drain.

[0045] In the circuit structure provided by the embodiments of the present application, nodes such as the first node and the second node do not represent actually existing components, but represent the convergence points of relevant couplings in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0046] Currently, when a circuit involves power supply by multiple voltage sources, it is often necessary to select the input voltage signal with a higher voltage as the power supply voltage signal. Refer to Figure 1 , Figure 1Shows a schematic diagram of a maximum voltage selection circuit in the related art. Among them, the maximum voltage selection circuit includes a bias current source, PMOS transistors M1 and M2 connected in common gate, a current mirror circuit, and an output circuit.

[0047] Among them, the current mirror circuit makes the drain currents of PMOS transistor M1 and PMOS transistor M2 equal by mirroring the current of the bias current source. The drain currents of PMOS transistor M1 and PMOS transistor M2 satisfy the following formula:

[0048]

[0049] Among them, μ n is the electron mobility of the MOS transistor, C ox is the gate oxide capacitance per unit area of the MOS transistor, W / L is the channel width-to-length ratio of the MOS transistor, V GS is the voltage difference between the gate and source of the MOS transistor, V th is the threshold voltage of the MOS transistor, λ is the channel modulation coefficient of the MOS transistor, V DS is the voltage difference between the source and drain of the MOS transistor.

[0050] If the voltage VDD1 > VDD2, it can be known that:

[0051] V GS1 > V GS2

[0052] Among them, V GS1 is the voltage difference between the gate and source of PMOS transistor M1, V GS2 is the voltage difference between the gate and source of PMOS transistor M2.

[0053] Therefore, according to the above drain current calculation formula of the MOS transistor, to ensure that the drain currents of PMOS transistor M1 and PMOS transistor M2 are equal, it is necessary to satisfy:

[0054] V DS1 < V DS2

[0055] Among them, V DS1 is the voltage difference between the source and drain of PMOS transistor M1, V DS is the voltage difference between the source and drain of PMOS transistor M2.

[0056] Therefore, when the voltage VDD1 > VDD2, the drain of PMOS transistor M2 outputs a low-level signal, so that the output circuit can recognize the low-level signal and select the voltage VDD1 as the maximum voltage VMAX for output.

[0057] If the voltage VDD1 < VDD2, it can be known that:

[0058] VGS1 <V GS2

[0059] Therefore, according to the above drain current calculation formula of the MOS transistor, it can be known that to ensure that the drain currents of PMOS transistor M1 and PMOS transistor M2 are equal, the following conditions need to be met:

[0060] V DS1 >V DS2

[0061] Therefore, when the voltage VDD1 < VDD2, the drain of PMOS transistor M2 will output a high-level signal, so that the output circuit can recognize the high-level signal and select the voltage VDD2 as the maximum voltage VMAX for output.

[0062] It can be seen that the bias current source provides the bias current required for the operation of the voltage comparison circuit composed of PMOS transistors M1 and M2, enabling the voltage comparison circuit to compare the magnitudes of the two voltages, so that the output unit can select the higher of the two voltage signals as the maximum voltage output according to the level signal output by the voltage comparison.

[0063] However, generally, the bias current source needs to provide an additional reference voltage Vref or power supply VDD to generate the bias current, which leads to the problem of additional circuit overhead in the current maximum voltage selection circuit.

[0064] For this reason, the present application provides a voltage selection circuit, a chip and an electronic device. Refer to Figure 2 , Figure 2 FIG. shows a schematic diagram of the voltage selection circuit in an embodiment of the present application. Among them, the voltage selection circuit includes a bias current generation module 10, a voltage comparison module 20, and a maximum voltage output module 30.

[0065] Specifically, the bias current generation module 10 is used to generate a bias current I0, so that the voltage comparison module 20 can compare the magnitudes of the first voltage VDD1 and the second voltage VDD2 according to the bias current I0. In some embodiments of the present application, the bias current generation module 10 can generate the bias current I0 based on a fixed resistor biasing method, that is, a resistor voltage division network provides a stable base or gate voltage for a transistor (such as a triode or a MOS transistor), so as to output the bias current I0 (such as a collector current or a drain current).

[0066] Those skilled in the art can understand that the bias current generation module 10 can also generate the bias current I0 based on other methods. For example, the current mirror biasing method, the self-biasing method, the constant current source biasing, etc.

[0067] The voltage comparison module 20 is used to compare the magnitudes of the first voltage VDD1 and the second voltage VDD2 according to the bias current I0 and output a level control signal V0, so that the maximum voltage output module 30 can select the higher one of the first voltage VDD1 and the second voltage VDD2 as the maximum voltage VMAX for output according to the level control signal V0. For example, when the first voltage VDD1 is greater than the second voltage VDD2, the voltage comparison module 20 can output a voltage control signal with a low level, so that the maximum voltage output module 30 selects the first voltage VDD1 as the maximum voltage VMAX for output; for another example, when the first voltage VDD1 is less than the second voltage VDD2, the voltage comparison module 20 can output a voltage control signal with a high level, so that the maximum voltage output module 30 selects the second voltage VDD2 as the maximum voltage VMAX for output.

[0068] The maximum voltage output module 30 can select the higher one of the first voltage VDD1 and the second voltage VDD2 as the maximum voltage VMAX for output according to the level control signal V0 to improve the driving ability of the circuit. In some embodiments of the present application, the maximum voltage output module 30 can generate a first level signal and a second level signal according to the level control signal V0, so as to control the transistors for outputting the first voltage VDD1 and the second voltage VDD2 respectively through the first level signal and the second level signal.

[0069] For example, when the level control signal V0 is at a low level, the first level signal generated by the maximum voltage output module 30 is at a low level, the second level signal is at a high level, the first level signal controls the transistor for outputting the first voltage VDD1 to conduct, and the second level signal controls the transistor for outputting the second voltage VDD2 to cut off. Therefore, the maximum voltage output module 30 can select the first voltage VDD1 as the maximum voltage VMAX for output.

[0070] For another example, when the level control signal V0 is at a high level, the first level signal generated by the maximum voltage output module 30 is at a high level, the second level signal is at a low level, the first level signal controls the transistor for outputting the first voltage VDD1 to cut off, and the second level signal controls the transistor for outputting the second voltage VDD2 to conduct. Therefore, the maximum voltage output module 30 can select the second voltage VDD2 as the maximum voltage VMAX for output.

[0071] In the embodiments of the present application, the bias current generation module 10 can generate a bias current I0 according to the first voltage VDD1 and the second voltage VDD2. For example, in the embodiments where the bias current generation module 10 generates the bias current I0 in a self-bias manner, the bias current generation module 10 uses the first voltage VDD1 or the second voltage VDD2 as a power source to generate the bias current I0. For another example, in the embodiments where the bias current generation module 10 generates the bias current I0 in a constant current source bias manner, the bias current generation module 10 can use the first voltage VDD1 or the second voltage VDD2 as a reference voltage to generate the bias current I0. Therefore, this means that the present application does not need to provide an additional reference voltage and / or power source for the bias current generation module 10, which is beneficial to reducing the circuit complexity and circuit power consumption of the voltage selection circuit.

[0072] In some embodiments of the present application, when the first voltage VDD1 is greater than the second voltage VDD2, the bias current generation module 10 generates the bias current I0 based on the first voltage VDD1; when the first voltage VDD1 is less than the second voltage VDD2, the bias current generation module 10 generates the bias current I0 based on the second voltage VDD2.

[0073] It should be noted that the first voltage VDD1 and the second voltage VDD2 may experience a power-off phenomenon during operation. If the bias current generation module 10 generates the bias current I0 only based on one of the first voltage VDD1 or the second voltage VDD2, it is possible that the bias current generation module 10 cannot provide the bias current I0 due to the power-off of one of the first voltage VDD1 or the second voltage VDD2, ultimately resulting in the voltage selection circuit being unable to output the maximum voltage VMAX or outputting an incorrect voltage.

[0074] In the above embodiments, the bias current generation module 10 generates the bias current I0 according to the higher voltage of the first voltage VDD1 or the second voltage VDD2. If the first voltage VDD1 loses power, the bias voltage module can generate the bias current I0 according to the second voltage VDD2; if the second voltage VDD2 loses power, the bias voltage module can generate the bias current I0 according to the first voltage VDD1, thereby avoiding the phenomenon that the voltage selection circuit cannot output the maximum voltage VMAX or outputs an incorrect voltage due to the power-off of one of the first voltage VDD1 or the second voltage VDD2.

[0075] In some embodiments of the present application, refer to Figure 3 , Figure 3 shows another schematic diagram of the voltage selection circuit in the embodiments of the present application, where the bias current generation module 10 includes a voltage comparison unit 11 and a bias current generation unit 12.

[0076] It should be noted that the voltage comparison unit 11 can compare the magnitudes of the first voltage VDD1 and the second voltage VDD2, and generate a bias voltage Vdd according to the higher one of the first voltage VDD1 and the second voltage VDD2. For example, when the first voltage VDD1 is higher than the second voltage VDD2, the voltage comparison unit 11 generates the bias voltage Vdd according to the first voltage VDD1; conversely, when the second voltage VDD2 is higher than the first voltage VDD1, the voltage comparison unit 11 generates the bias voltage Vdd according to the second voltage VDD2. Therefore, when one of the first voltage VDD1 or the second voltage VDD2 loses power, the voltage comparison unit 11 can only provide the bias voltage Vdd to the bias current generation unit 12, so that the bias current generation unit 12 generates a bias current I0 according to the bias voltage Vdd.

[0077] As an exemplary embodiment of the voltage comparison unit 11, refer to Figure 4 , Figure 4 , which shows another schematic diagram of the voltage selection circuit in the embodiment of the present application. Among them, the voltage comparison unit 11 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, and a second resistor R2; the second end of the first PMOS transistor MP1 is used to connect to the first voltage VDD1, the first end of the first PMOS transistor MP1 is connected to the first end of the second PMOS transistor MP2, and the second end of the second PMOS transistor MP2 is used to connect to the second voltage VDD2; the first end of the first resistor R1 is connected to the second end of the first PMOS transistor MP1, and the second end of the first resistor R1 is connected to the control end of the second PMOS transistor MP2; the first end of the second resistor R2 is connected to the second end of the second PMOS transistor MP2, and the second end of the second resistor R2 is connected to the control end of the first PMOS transistor MP1.

[0078] It should be noted that the first resistor R1 and the second resistor R2 are used for delay. When the magnitudes of the first voltage VDD1 and the second voltage VDD2 are similar and they are powered on at the same time, the first resistor R1 and the second resistor R2 can make the voltage change at the gate terminals of the first PMOS transistor MP1 and the second PMOS transistor MP2 lag behind the changes of the first voltage VDD1 and the second voltage VDD2, so as to turn on the first PMOS transistor MP1 and the second PMOS transistor MP2 and charge the first node m1 during the delay period.

[0079] Specifically, when the first voltage VDD1 is greater than the second voltage VDD2, the first PMOS transistor MP1 is turned on and the second PMOS transistor MP2 is turned off. At this time, the bias voltage Vdd generated at the first node m1 is:

[0080] Vdd = VDD1 - VDS1

[0081] Wherein, VDS1 is the voltage difference between the first end and the second end of the first PMOS transistor MP1.

[0082] When the first voltage VDD1 is less than the second voltage VDD2, the first PMOS transistor MP1 is turned off and the second PMOS transistor MP2 is turned on. At this time, the bias voltage Vdd generated at the first node m1 is:

[0083] Vdd = VDD2 - VDS2

[0084] Wherein, VDS2 is the voltage difference between the first end and the second end of the second PMOS transistor MP2.

[0085] It can be seen that when the first voltage VDD1 is greater than the second voltage VDD2, the voltage comparison unit 11 outputs the bias voltage Vdd according to the first voltage VDD1; when the first voltage VDD1 is less than the second voltage VDD2, the voltage comparison unit 11 outputs the bias voltage Vdd according to the second voltage VDD2.

[0086] Therefore, the above voltage comparison unit 11 can generate the bias voltage Vdd according to the higher voltage of the first voltage VDD1 and the second voltage VDD2, avoiding the phenomenon that the bias current I0 cannot be provided due to the power failure of one of the first voltage VDD1 or the second voltage VDD2.

[0087] It can be understood that the above voltage comparison unit 11 is only an exemplary embodiment of the present application. In some possible embodiments, the voltage comparison unit 11 may also include a comparator, which compares the magnitudes of the first voltage VDD1 and the second voltage VDD2, and selects the higher voltage of the first voltage VDD1 and the second voltage VDD2 according to the level signal output by the comparator to generate the bias voltage Vdd.

[0088] As an exemplary embodiment of the bias current generating unit 12, refer to Figure 5 , Figure 5Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. Among them, the bias current generation unit 12 includes a resistance adjustment sub-unit 121, a voltage dividing resistor R0, a first NMOS transistor MN1, and a second NMOS transistor MN2. The first end of the resistance adjustment sub-unit 121 is connected to the first node m1 between the first PMOS transistor MP1 and the second PMOS transistor MP2. The second end of the resistance adjustment sub-unit 121 is connected to the first end of the voltage dividing resistor R0. The second end of the first NMOS transistor MN1 is connected to the second end of the voltage dividing resistor R0. The control end of the first NMOS transistor MN1 is connected to the first end of the voltage dividing resistor R0. The first end of the first NMOS transistor MN1 is connected to the second end of the second NMOS transistor MN2. The control end of the second NMOS transistor MN2 is connected to the second end of the voltage dividing resistor R0. The first end of the second NMOS transistor MN2 is connected to the ground terminal.

[0089] It should be noted that the resistance adjustment sub-unit 121 Figure 5 employs an adjustable resistor Rt formed by a resistor array, but is not limited thereto. The resistance adjustment sub-unit 121 can also employ a MOS array connected in diode form, or the resistance adjustment sub-unit 121 can be a combination of the above two forms. Specifically, after providing the bias voltage Vdd at the first node m1, a bias current I0 is generated in the branch where the voltage dividing resistor R0, the first NMOS transistor MN1, and the second NMOS transistor MN2 are located. By changing the size of the resistance adjustment sub-unit 121, the size of the bias current I0 can be changed to ensure that the transistors in the voltage comparison module 20 operate normally in the amplification region or the linear region.

[0090] It can be understood that the above embodiments are only exemplary embodiments of the bias current generation unit 12 of the present application, and the embodiments of the bias current generation unit 12 are not limited thereto. For example, referring to Figure 6 , Figure 6 Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. The bias current generation unit 12 can also only include the resistance adjustment sub-unit 121 and the first NMOS transistor MN1.

[0091] In some embodiments of the present application, referring to Figure 7 , Figure 7Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. Among them, the voltage comparison module 20 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a current mirror unit 21; the first end of the third PMOS transistor MP3 is used to access the first voltage VDD1, the control end of the third PMOS transistor MP3 is connected to the control end of the fourth PMOS transistor MP4, the first end of the fourth PMOS transistor MP4 is used to access the second voltage VDD2, the control end of the three PMOS transistors is connected to the second end, and the current mirror unit 21 can control the second end currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 to be equal according to the bias current I0.

[0092] It should be noted that when the first voltage VDD1 is greater than the second voltage VDD2, since the control end of the third PMOS transistor MP3 is connected to the control end of the fourth PMOS transistor MP4, it can be known that the gate-source voltage differences of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 satisfy the following relational expression:

[0093] V GS3 >V GS4

[0094] Among them, V GS3 is the gate-source voltage difference of the third PMOS transistor MP3, and V GS4 is the gate-source voltage difference of the fourth PMOS transistor MP4.

[0095] According to the drain current calculation formula of the MOS transistor, it can be known that to ensure that the drain currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are equal, the source-drain voltage differences of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 need to satisfy the following relational expression:

[0096] V DS3 <V DS4

[0097] Among them, V DS3 is the source-drain voltage difference of the third PMOS transistor MP3, and V DS4 is the source-drain voltage difference of the fourth PMOS transistor MP4.

[0098] Combined with the fact that the second voltage VDD2 is less than the first voltage VDD1 and the above formula, it can be known that at this time, the drain of the fourth PMOS transistor MP4 will output a low-level signal.

[0099] On the contrary, when the first voltage VDD1 is less than the second voltage VDD2, since the control end of the third PMOS transistor MP3 is connected to the control end of the fourth PMOS transistor MP4, it can be known that the gate-source voltage differences of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 satisfy the following relational expression:

[0100] V GS3 <V GS4

[0101] According to the drain current calculation formula of the MOS transistor, it can be known that to ensure that the drain currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are equal, the source-drain voltage differences of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 need to satisfy the following relational expression:

[0102] V DS3 >V DS4

[0103] Combined with the fact that the second voltage VDD2 is greater than the first voltage VDD1 and the above formula, it can be known that at this time, the drain of the fourth PMOS transistor MP4 will output a high-level signal.

[0104] It can be seen that the above voltage comparison module 20 can output a level control signal V0 with a low level when the first voltage VDD1 is greater than the second voltage VDD2, and output a level control signal V0 with a high level when the first voltage VDD1 is less than the second voltage VDD2, so that the maximum voltage output module 30 can select the highest voltage of the first voltage VDD1 and the second voltage VDD2 as the maximum voltage VMAX output according to the level control signal V0.

[0105] In some embodiments of the present application, refer to Figure 8 , Figure 8 shows another schematic diagram of the voltage selection circuit in the embodiment of the present application. Among them, the voltage comparison module 20 further includes a clamping unit 22; when the first voltage VDD1 is greater than the second voltage VDD2, the clamping unit 22 clamps the second terminal voltage of the fourth PMOS transistor MP4 to be less than the second terminal voltage of the third PMOS transistor MP3; when the first voltage VDD1 is less than the second voltage VDD2, the clamping unit 22 clamps the second terminal voltage of the fourth PMOS transistor MP4 to be greater than the second terminal voltage of the third PMOS transistor MP3.

[0106] It should be noted that when the first voltage VDD1 is slightly less than the second voltage VDD2, the establishment speed of the bias current I0 is slow, which in turn causes the current in the branch where the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are located to be small or even zero for a long time. At this time, the body diode of the third PMOS transistor MP3 is considered to be in the conducting state. Therefore, the voltage of the second node m2 (i.e., the voltage at the second terminal of the third PMOS transistor MP3) may rise to VDD1 + Vdiode3 (Vdiode3 is the conduction voltage of the body diode of the third PMOS transistor MP3). That is, at this time, the gate voltage of the fourth PMOS transistor MP4 may be greater than its source voltage, which in turn causes the fourth PMOS transistor MP4 to turn off and the voltage of the third node m3 (i.e., the voltage at the second terminal of the fourth PMOS transistor MP4) to change to a low level, ultimately resulting in the phenomenon that the maximum voltage output module 30 selects the lower first voltage VDD1 as the maximum voltage VMAX output.

[0107] In the above embodiment, when the first voltage VDD1 is greater than the second voltage VDD2, the clamping unit 22 can clamp the voltage at the second terminal of the fourth PMOS transistor MP4 to be less than the voltage at the second terminal of the third PMOS transistor MP3, so that the level control signal V0 with a low level is output at the third node m3, thereby ensuring that the maximum voltage output module 30 selects the highest first voltage VDD1 as the maximum voltage VMAX output; when the first voltage VDD1 is slightly less than the second voltage VDD2, the clamping unit 22 can clamp the voltage at the second terminal of the fourth PMOS transistor MP4 to be greater than the voltage at the second terminal of the third PMOS transistor MP3, so that the level control signal V0 with a high level is output at the third node m3, thereby ensuring that the maximum voltage output module 30 selects the highest second voltage VDD2 as the maximum voltage VMAX output.

[0108] It can be seen that in this application, the clamping unit 22 clamps the voltage of the third node m3 according to the voltage of the second node m2, ensuring the reliability of the voltage of the third node m3 and avoiding the phenomenon that when the first voltage VDD1 is slightly less than or slightly greater than the second voltage VDD2, the voltage selection circuit outputs an incorrect maximum voltage VMAX due to the slow establishment speed of the bias current I0.

[0109] In some embodiments of this application, refer to Figure 9 , Figure 9Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. Among them, the clamping unit 22 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4; the second end of the third NMOS transistor MN3 is connected to the second end of the third PMOS transistor MP3, the control end of the third NMOS transistor MN3 is connected to the second end of the third PMOS transistor MP3, and the first end of the third NMOS transistor MN3 is connected to the second end of the fourth PMOS transistor MP4; the second end of the fourth NMOS transistor MN4 is connected to the second end of the fourth PMOS transistor MP4, the control end of the fourth NMOS transistor MN4 is connected to the second end of the fourth PMOS transistor MP4, and the first end of the fourth NMOS transistor MN4 is connected to the second end of the third PMOS transistor MP3.

[0110] Specifically, when the first voltage VDD1 is greater than the second voltage VDD2, the voltage of the second node m2 is greater than the voltage of the third node m3, the third NMOS transistor MN3 is turned on and the fourth NMOS transistor MN4 is turned off. Therefore, the voltage of the third node m3 satisfies the following relationship:

[0111] Vm3 = Vm2 - Vgs3

[0112] Where, Vm3 is the voltage of the third node m3, Vm2 is the voltage of the second node m2, and Vgs1 is the voltage difference between the gate and the source of the third NMOS transistor MN3.

[0113] When the first voltage VDD1 is less than the second voltage VDD2, the voltage of the second node m2 is less than the voltage of the third node m3, the third NMOS transistor MN3 is turned off and the fourth NMOS transistor MN4 is turned on. Therefore, the voltage of the third node m3 satisfies the following relationship:

[0114] Vm3 = Vm2 + Vgs4

[0115] Where, Vgs4 is the voltage difference between the gate and the source of the fourth NMOS transistor MN4.

[0116] It can be seen that when the first voltage VDD1 is greater than the second voltage VDD2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 can make the voltage of the third node m3 less than the voltage of the second node m2, so that the third node m3 outputs a low-level level control signal V0; when the first voltage VDD1 is less than the second voltage VDD2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 can make the voltage of the third node m3 greater than the voltage of the second node m2, so that the third node m3 outputs a high-level level control signal V0. Therefore, the clamping unit 22 can preferably clamp the voltage of the third node m3, avoiding the generation of a small bias current I0 due to the proximity of the first voltage VDD1 and the second voltage VDD2, and further avoiding the phenomenon of unstable voltage of the third node m3.

[0117] In some embodiments of the present application, referring to Figure 10 , Figure 10 , another schematic diagram of the voltage selection circuit in the embodiments of the present application is shown. Among them, the current mirror unit 21 includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8; the second end of the fifth NMOS transistor MN5 is connected to the second end of the third PMOS transistor MP3, the first end of the fifth NMOS transistor MN5 is connected to the second end of the sixth NMOS transistor MN6, and the first end of the sixth NMOS transistor MN6 is connected to the ground terminal; the second end of the seventh NMOS transistor MN7 is connected to the second end of the fourth PMOS transistor MP4, the first end of the seventh NMOS transistor MN7 is connected to the second end of the eighth NMOS transistor MN8, and the first end of the eighth NMOS transistor MN8 is connected to the ground terminal.

[0118] It should be noted that the control terminals of the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 are connected to the control terminal of the first NMOS transistor MN1, and the control terminals of the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8 are connected to the control terminal of the second NMOS transistor MN2. The first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 form a current mirror. The mirror ratio between the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 is 1:1, and the mirror ratio between the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8 is 1:1. Therefore, it can be ensured that the drain currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are equal.

[0119] It can be understood that the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 in the above embodiments are actually a cascode current mirror. In fact, the current mirror circuit that ensures the drain currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are equal is not limited to this. For example, in some possible embodiments, the present application can also use a basic current mirror, a Wilson current mirror, or a wide-swing current mirror and other current mirror circuits to make the drain currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 equal.

[0120] In some embodiments of the present application, referring to Figure 11 , Figure 11Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. The maximum voltage output module 30 includes a Schmitt trigger unit 31 and an output driving unit 32. The Schmitt trigger unit 31 is configured to output a first level signal VL1 and a second level signal VL2 according to the level control signal V0. The output driving unit 32 is configured to select and output the one with the highest voltage among the first voltage VDD1 and the second voltage VDD2 according to the first level signal VL1 and the second level signal VL2.

[0121] It should be noted that one of the first level signal VL1 and the second level signal VL2 is a high level signal, and the other is a low level signal. Therefore, the output driving unit 32 can select and output the one with the highest voltage among the first voltage VDD1 and the second voltage VDD2 according to the first level signal VL1 and the second level signal VL2 with opposite levels. For example, when the first voltage VDD1 is greater than the second voltage VDD2, and the first level signal VL1 output by the Schmitt trigger unit 31 is a low level signal and the second level signal VL2 is a high level signal, the output driving unit 32 can select the first voltage VDD1 as the maximum voltage VMAX when the first level signal VL1 is at a low level. On the contrary, when the first voltage VDD1 is less than the second voltage VDD2, and the first level signal VL1 output by the Schmitt trigger unit 31 is a high level signal and the second level signal VL2 is a low level signal, the output driving unit 32 can select the second voltage VDD2 as the maximum voltage VMAX when the second level signal VL2 is at a low level.

[0122] As an exemplary embodiment of the Schmitt trigger unit 31, refer to Figure 12 , Figure 12Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. The Schmitt trigger unit 31 includes a fifth PMOS transistor MP5, an eleventh PMOS transistor MP11, a ninth NMOS transistor MN9, a fourteenth NMOS transistor MN14, a sixth PMOS transistor MP6, a tenth NMOS transistor MN10, a seventh PMOS transistor MP7, and an eleventh NMOS transistor MN11. The first end of the eleventh PMOS transistor MP11 is connected to the output end of the output driving unit 32 to access the maximum voltage VMAX. The second end of the eleventh PMOS transistor MP11 is connected to the first end of the fifth PMOS transistor MP5. The second end of the fifth PMOS transistor MP5 is connected to the second end of the ninth NMOS transistor MN9. The control ends of the eleventh PMOS transistor MP11 and the fifth PMOS transistor MP5 are connected to the level control signal V0. The first end of the ninth NMOS transistor MN9 is connected to the second end of the fourteenth NMOS transistor MN14. The first end of the fourteenth NMOS transistor MN14 is connected to the ground terminal. The control ends of the ninth NMOS transistor MN9 and the fourteenth NMOS transistor MN14 are connected to the level control signal V0. The first end of the sixth PMOS transistor MP6 is connected to the output end of the output driving unit 32 to access the maximum voltage VMAX. The second end of the sixth PMOS transistor MP6 is connected to the second end of the tenth NMOS transistor MN10. The first end of the tenth NMOS transistor MN10 is connected to the ground terminal. The control ends of the sixth PMOS transistor MP6 and the tenth NMOS transistor MN10 are connected to the second end of the fifth PMOS transistor MP5. The first end of the seventh PMOS transistor MP7 is connected to the output end of the output driving unit 32 to access the maximum voltage VMAX. The second end of the seventh PMOS transistor MP7 is connected to the second end of the eleventh NMOS transistor MN11. The first end of the eleventh NMOS transistor MN11 is connected to the ground terminal. The control ends of the seventh PMOS transistor MP7 and the eleventh NMOS transistor MN11 are connected to the second end of the sixth PMOS transistor MP6. Wherein, the second end of the sixth PMOS transistor MP6 is used to output the first level signal VL1, and the second end of the seventh PMOS transistor MP7 is used to output the second level signal VL2.

[0123] Specifically, when the first voltage VDD1 is greater than the second voltage VDD2, the third node m3 is at a low level, the fifth PMOS transistor MP5 and the eleventh PMOS transistor MP11 are turned on, the fourth node m4 is at a high level, the tenth NMOS transistor MN10 is turned on, the fifth node m5 is at a low level, the seventh PMOS transistor MP7 is turned on, and the sixth node m6 is at a high level. Therefore, the fifth node m5 can output the first level signal VL1 at a low level, and the sixth node m6 can output the second level signal VL2 at a high level, so that the output driving unit 32 can select the first voltage VDD1 as the maximum voltage VMAX to output when the first level signal VL1 is at a low level.

[0124] When the first voltage VDD1 is greater than the second voltage VDD2, the third node m3 is at a high level, the ninth NMOS transistor MN9 and the fourteenth NMOS transistor MN14 are turned on, the fourth node m4 is at a low level, the sixth PMOS transistor MP6 is turned on, the fifth node m5 is at a high level, the eleventh NMOS transistor MN11 is turned on, and the sixth node m6 is at a low level. Therefore, the fifth node m5 can output a first level signal VL1 at a high level, and the sixth node m6 can output a second level signal VL2 at a low level, so that the output driving unit 32 can select the second voltage VDD2 as the maximum voltage VMAX to output when the second level signal VL2 is at a low level.

[0125] As an exemplary embodiment of the output driving unit 32, refer to Figure 13 , Figure 13 which shows another schematic diagram of the voltage selection circuit in the embodiment of the present application. The output driving unit 32 includes an eighth PMOS transistor MP8 and a ninth PMOS transistor MP9; the second end of the eighth PMOS transistor MP8 is used to connect to the second voltage VDD2, the first end of the eighth PMOS transistor MP8 is connected to the first end of the ninth PMOS transistor MP9, and the second end of the ninth PMOS transistor MP9 is used to connect to the first voltage VDD1; wherein, the control end of the eighth PMOS transistor MP8 is connected to the second level signal VL2, the control end of the ninth PMOS transistor MP9 is connected to the first level signal VL1, and the first end of the eighth PMOS transistor MP8 is used to output the maximum voltage VMAX.

[0126] Specifically, when the first voltage VDD1 is greater than the second voltage VDD2, the first level signal VL1 is at a low level, and the second level signal VL2 is at a high level. Therefore, the eighth PMOS transistor MP8 is turned off, and the ninth PMOS transistor MP9 is turned on. At this time, the seventh node m7 outputs the first voltage VDD1 as the maximum voltage VMAX; conversely, when the first voltage VDD1 is less than the second voltage VDD2, the first level signal VL1 is at a high level, and the second level signal VL2 is at a low level. Therefore, the eighth PMOS transistor MP8 is turned on, and the ninth PMOS transistor MP9 is turned off. At this time, the seventh node m7 outputs the second voltage VDD2 as the maximum voltage VMAX.

[0127] In some embodiments of the present application, refer to Figure 14 , Figure 14Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. The voltage selection circuit further includes an error correction module 40, which is used to correct the level control signal V0 to prevent the maximum voltage output module 30 from selecting and outputting the one with the lowest voltage among the first voltage VDD1 and the second voltage VDD2. For example, when the first voltage VDD1 is greater than the second voltage VDD2, if the level control signal V0 output by the third node m3 is a high level, the error correction module 40 can change the voltage of the third node m3 to make the level control signal V0 change to a low level, thereby avoiding the phenomenon that the maximum voltage output module 30 selects the second voltage VDD2 as the maximum voltage VMAX for output.

[0128] As an exemplary embodiment of the error correction module 40, refer to Figure 15 , Figure 15 Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown, where the error correction module 40 includes a tenth PMOS transistor MP10, a twelfth NMOS transistor MN12, and a thirteenth NMOS transistor MN13; the first end of the tenth PMOS transistor MP10 is used to connect to the first voltage VDD1, the control end of the tenth PMOS transistor MP10 is connected to the output end of the maximum voltage output module 30 to connect to the maximum voltage VMAX, and the second end of the tenth PMOS transistor MP10 is connected to the second end of the twelfth NMOS transistor MN12; the control end of the twelfth NMOS transistor MN12 is connected to its second end, the first end of the twelfth NMOS transistor MN12 is connected to the ground terminal; the second end of the thirteenth NMOS transistor MN13 is connected to the output end of the voltage comparison module 20, the control end of the thirteenth NMOS transistor MN13 is connected to the control end of the twelfth NMOS transistor MN12, and the first end of the thirteenth NMOS transistor MN13 is connected to the ground terminal.

[0129] Specifically, when the first voltage VDD1 is greater than the second voltage VDD2, if the level control signal V0 output by the third node m3 is a high level, causing the maximum voltage VMAX selection module to select the second voltage VDD2 as the maximum voltage VMAX for output, at this time, the gate voltage of the tenth PMOS transistor MP10 is the second voltage VDD2, so the tenth PMOS transistor MP10 is turned on, and the third node m3 is grounded, so the level control signal V0 changes to a low level, thereby avoiding the phenomenon that the maximum voltage output module 30 selects the second voltage VDD2 as the maximum voltage VMAX for output.

[0130] It should be noted that the above content about the voltage selection circuit is intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can also make equivalent modified designs under the guidance of the present application. For example, refer to Figure 16 , Figure 16Another schematic diagram of the voltage selection circuit in the embodiment of the present application is shown. Among them, the error correction module can also adopt a tenth PMOS transistor with its source connected to the second voltage VDD and its gate connected to the maximum voltage VMAX. When the first voltage VDD1 is less than the second voltage VDD2, but the maximum voltage VMAX is the first voltage VDD1, the tenth PMOS transistor is turned on, and the voltage of the third node m3 is pulled up to near the second voltage VDD2. Therefore, the level control signal V0 changes to a high level, thus avoiding the phenomenon that the maximum voltage output module 30 selects the first voltage VDD1 as the maximum voltage VMAX for output; for another example, continue to refer to Figure 16 , the Schmitt trigger unit 31 can also include a twelfth PMOS transistor MP12, so as to discharge the second end of the eleventh PMOS transistor MP11 through the twelfth PMOS transistor MP12, avoiding the phenomenon that the drain voltage of the eleventh PMOS transistor MP11 floats.

[0131] The embodiment of the present application also provides a chip, which includes the above-mentioned voltage selection circuit. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be but is not limited to being a SOC (System on Chip, chip-level system) chip, a SIP (system in package, system-level package) chip. Since the chip of the present application has the voltage selection circuit described in the above embodiment, it has all the beneficial effects of the voltage selection circuit in the above embodiment, which will not be elaborated here.

[0132] The embodiment of the present application also provides an electronic device, which includes a device main body and a chip as described above provided inside the device main body. The electronic device can be but is not limited to a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus, universal serial bus) expansion dock, a stylus pen, a true wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes but is not limited to a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes but is not limited to a smart phone, a laptop computer, a tablet computer, and a POS (point of sales terminal, sales point terminal) machine. The smart home device includes but is not limited to a smart socket, a smart rice cooker, a smart floor sweeper, and a smart light.

[0133] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A voltage selection circuit, characterized in that: include: A bias current generating module, wherein the bias current generating module is used to generate a bias current; A voltage comparison module, the voltage comparison module is used to compare the first voltage and the second voltage according to the bias current and output a level control signal; a maximum voltage output module, the maximum voltage output module being used to select the highest voltage between the first voltage and the second voltage for output according to the level control signal; The bias current generating module generates the bias current according to the first voltage and the second voltage.

2. The voltage selection circuit according to claim 1, characterized in that: When the first voltage is greater than the second voltage, the bias current generating module generates the bias current based on the first voltage; When the first voltage is less than the second voltage, the bias current generating module generates the bias current based on the second voltage.

3. The voltage selection circuit according to claim 2, characterized in that: The bias current generating module comprises a voltage comparing unit and a bias current generating unit; The voltage comparison unit is used to generate a bias voltage according to the highest voltage between the first voltage and the second voltage; The bias current generating unit is used to generate the bias current according to the bias voltage.

4. The voltage selection circuit according to claim 3, characterized in that: The voltage comparison unit includes a first PMOS tube, a second PMOS tube, a first resistor and a second resistor; The second end of the first PMOS tube is used to access a first voltage, the first end of the first PMOS tube is connected to the first end of the second PMOS tube, and the second end of the second PMOS tube is used to access a second voltage; The first end of the first resistor is connected to the second end of the first PMOS transistor, and the second end of the first resistor is connected to the control end of the second PMOS transistor; The first end of the second resistor is connected to the second end of the second PMOS tube, and the second end of the second resistor is connected to the control end of the first PMOS tube.

5. The voltage selection circuit according to claim 4, characterized in that: The bias current generating unit includes a resistance adjusting subunit, a voltage dividing resistor, a first NMOS tube and a second NMOS tube; The first end of the resistance adjustment subunit is connected to a first node between the first PMOS tube and the second PMOS tube, and the second end of the resistance adjustment subunit is connected to the first end of the voltage dividing resistor; The second end of the first NMOS tube is connected to the second end of the voltage-dividing resistor, the control end of the first NMOS tube is connected to the first end of the voltage-dividing resistor, and the first end of the first NMOS tube is connected to the second end of the second NMOS tube; The control end of the second NMOS tube is connected to the second end of the voltage-dividing resistor, and the first end of the second NMOS tube is connected to the ground end.

6. The voltage selection circuit according to claim 1, characterized in that: The voltage comparison module includes a third PMOS tube, a fourth PMOS tube and a current mirror unit; The first end of the third PMOS tube is used to access the first voltage, the control end of the third PMOS tube is connected to the control end of the fourth PMOS tube, the first end of the fourth PMOS tube is used to access the second voltage, and the control end of the third PMOS tube is connected to the second end; The current mirror unit is used to control the currents at the second ends of the third PMOS tube and the fourth PMOS tube to be equal according to the bias current, and the second end of the fourth PMOS tube is used to output the level control signal.

7. The voltage selection circuit according to claim 6, characterized in that: The voltage comparison module also includes a clamping unit; When the first voltage is greater than the second voltage, the clamping unit clamps the second terminal voltage of the fourth PMOS tube to be smaller than the second terminal voltage of the third PMOS tube; When the first voltage is lower than the second voltage, the clamping unit clamps the second terminal voltage of the fourth PMOS tube to be higher than the second terminal voltage of the third PMOS tube.

8. The voltage selection circuit according to claim 7, characterized in that: The clamping unit includes a third NMOS tube and a fourth NMOS tube; The second end of the third NMOS tube is connected to the second end of the third PMOS tube, the control end of the third NMOS tube is connected to the second end of the third PMOS tube, and the first end of the third NMOS tube is connected to the second end of the fourth PMOS tube; The second end of the fourth NMOS tube is connected to the second end of the fourth PMOS tube, the control end of the fourth NMOS tube is connected to the second end of the fourth PMOS tube, and the first end of the fourth NMOS tube is connected to the second end of the third PMOS tube.

9. The voltage selection circuit according to claim 1, characterized in that: The maximum voltage output module includes a Schmitt trigger unit and an output drive unit; The Schmitt trigger unit is used to output a first level signal and a second level signal according to the level control signal; The output driving unit is used for selecting and outputting the highest voltage between the first voltage and the second voltage according to the first level signal and the second level signal.

10. The voltage selection circuit according to claim 9, characterized in that: The Schmitt trigger unit includes a fifth PMOS tube, an eleventh PMOS tube, a ninth NMOS tube, a fourteenth NMOS tube, a sixth PMOS tube, a tenth NMOS tube, a seventh PMOS tube and an eleventh NMOS tube; The first end of the eleventh PMOS tube is connected to the output end of the output driving unit, the second end of the eleventh PMOS tube is connected to the first end of the fifth PMOS tube, the second end of the fifth PMOS tube is connected to the second end of the ninth NMOS tube, and the control ends of the eleventh PMOS tube and the fifth PMOS tube are connected to the level control signal; The first end of the ninth NMOS tube is connected to the second end of the fourteenth NMOS tube, the first end of the fourteenth NMOS tube is connected to the ground end, and the control ends of the ninth NMOS tube and the fourteenth NMOS tube are connected to the level control signal; The first end of the sixth PMOS tube is connected to the output end of the output driving unit, the second end of the sixth PMOS tube is connected to the second end of the tenth NMOS tube, the first end of the tenth NMOS tube is connected to the ground end, and the control ends of the sixth PMOS tube and the tenth NMOS tube are connected to the second end of the fifth PMOS tube; The first end of the seventh PMOS tube is connected to the output end of the output driving unit, the second end of the seventh PMOS tube is connected to the second end of the eleventh NMOS tube, the first end of the eleventh NMOS tube is connected to the ground end, and the control ends of the seventh PMOS tube and the eleventh NMOS tube are connected to the second end of the sixth PMOS tube; The second end of the sixth PMOS tube is used to output the first level signal, and the second end of the seventh PMOS tube is used to output the second level signal.

11. The voltage selection circuit according to claim 9, characterized in that: The output driving unit includes an eighth PMOS tube and a ninth PMOS tube; The second end of the eighth PMOS tube is used to access the second voltage, the first end of the eighth PMOS tube is connected to the first end of the ninth PMOS tube, and the second end of the ninth PMOS tube is used to access the first voltage; The control end of the eighth PMOS tube is connected to the second level signal, the control end of the ninth PMOS tube is connected to the first level signal, and the first end of the eighth PMOS tube is used to output the maximum voltage.

12. The voltage selection circuit according to claim 1, wherein: The voltage selection circuit also includes an error correction module; The error correction module is used for correcting the error of the level control signal to prevent the maximum voltage output module from selecting the lowest voltage between the first voltage and the second voltage for output.

13. The voltage selection circuit according to claim 12, characterized in that: The error correction module includes a tenth PMOS tube, a twelfth NMOS tube and a thirteenth NMOS tube; The first end of the tenth PMOS tube is used to access the first voltage, the control end of the tenth PMOS tube is connected to the output end of the maximum voltage output module, and the second end of the tenth PMOS tube is connected to the second end of the twelfth NMOS tube; The control end of the twelfth NMOS tube is connected to the second end, and the first end of the twelfth NMOS tube is connected to the ground end; The second end of the thirteenth NMOS tube is connected to the output end of the voltage comparison module, the control end of the thirteenth NMOS tube is connected to the control end of the twelfth NMOS tube, and the first end of the thirteenth NMOS tube is connected to the ground end.

14. A chip, characterized in that: The invention comprises the voltage selection circuit as claimed in any one of claims 1 to 13.

15. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 14 arranged in the device body.

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