Power stage controller

Abstract

The invention relates to a power stage controller. A controller for controlling a power stage having a plurality of phases is presented. The controller generates a control signal; transmitting a control signal to the plurality of phases via the first link; receiving a feedback signal from each phase via a second link; the plurality of feedback signals are summed and an average current per phase is derived.

Description

Technical Field

[0001] The present disclosure relates to a controller for controlling a power stage having multiple phases. The present disclosure also relates to a power supply including such a controller, the controller being coupled to a power stage having multiple phases. Background Art

[0002] Controlling an external power module via a single remote controller allows for improved power planning of an application circuit board. When the control circuit can be integrated as part of a larger power management integrated circuit (PMIC), the power conversion module can be placed close to the load. This configuration increases the power handling capacity of the PMIC while not increasing the power consumption of the circuit. Most of the power consumed by the power converter is consumed in the remote power module. This also reduces the constraints on the power envelope of the PMIC.

[0003] A driver plus MOSFET (DrMos) power stage introduces a standard interface for a power module that provides power into large digital systems. Example embodiments of DrMos are shown in Figure 1 as Figure 1As shown, the ISL69127 controller and the ISL99227 intelligent power module can be used in a similar manner, allowing for high-performance current power conversion systems (see the data sheet ISL69127, "Digital Dual Output 6+1-Phase VR13 PWM Controller", January 2018, Renesas Electronics, and the data sheet ISL99227, "Smart Power Stage (SPS) Module with Integrated High Accuracy Current and Temperature Monitors", November 2023, Renesas Electronics). This type of power stage was initially targeted at high-power systems but can also be adapted for lower-power systems, freeing up the large PMIC from the power consumption of some power conversion rails. Lower-power modules (such as the UCD74106) and the related controller UCD9244 provide a scalable power management platform when using an interface similar to the DrMos interface (see the data sheet, "Synchronous-Buck PowerStage", December 2012, Texas Instruments; and the data sheet, ""Digital PWM System Controller with 4-bit, 6-bit, or 8-bit VID Support", February 2011, Texas Instruments).

[0004] For a system such as Figure 1 shown, the large number of pins used to control the power module interface increases the complexity of the board layout design and also increases the pin cost of the power module. The proposed dual single-wire interface can be used, as Figure 2 shown in. The P91E0A PMIC can be connected to the P9148A power stage by using a simplified interface that switches the control interface DIF and the general control interface DIO, as can be seen in Figure 2 However, the current DIF interface and the current DIO interface are limited by the limited bandwidth and the general communication delay, which reduces the performance of the power supply. Therefore, it is necessary to revolutionize the control of the power stage interface by using a simplified protocol, thereby reducing the bus delay and increasing the transient performance of the power supply while still having a simple design.

[0005] The subject of the present disclosure is to address one or more of the above limitations. Summary of the Invention

[0006] According to a first aspect of the present disclosure, a controller is provided to control a power stage having multiple phases, the controller being configured to: generate a control signal; transmit the control signal to the multiple phases via a first link; receive feedback signals from each phase via a second link; sum the multiple feedback signals and derive an average current per phase.

[0007] Optionally, the controller has a first port connected to the first link and a second port connected to the second link, and a resistance circuit coupled to the second port, the resistance circuit having multiple resistors coupled in parallel, each resistor being connected to ground via a respective switch. For example, the number of resistors can be greater than or equal to the number of phases.

[0008] Optionally, the resistance circuit includes an additional switch for performing a phase address reading function.

[0009] Optionally, the control signal includes one or more of a first pulse width for activating a first phase; a second pulse having a second pulse width for incrementally activating additional phases; a third pulse having a third pulse width for deactivating all phases; a fourth pulse having a fourth pulse width for starting each phase to read its own address.

[0010] Optionally, the first link and the second link are unidirectional links.

[0011] Optionally, the sum of the feedback signals is proportional to the output current generated by the multiple phases.

[0012] Optionally, the controller is further configured to generate a configuration signal for configuring one or more phases, the configuration signal being transmissible via a third link. For example, the configuration signal can be configured to activate a turn-off during zero-crossing detection of an inductor, or set a current limit for a phase.

[0013] According to a second aspect of the present disclosure, a power supply including the controller according to the first aspect is provided, the controller being coupled to a power stage having multiple phases.

[0014] Optionally, the controller is coupled to the power stage via a single-wire interface.

[0015] Optionally, each phase includes a decoder for decoding the control signal.

[0016] Optionally, the decoder includes a finite state machine coupled to a phase counter and logic circuitry; wherein the finite state machine is configured to execute a decoding protocol.

[0017] Optionally, the logic circuitry includes an arbiter coupled to one or more wait units.

[0018] Optionally, each phase includes an address reader configured to read the phase address by sending a current through an address resistor.

[0019] Optionally, the address reader includes logic circuitry configured to initiate a read sequence.

[0020] Optionally, the address reader includes a compensator circuit configured to compensate for errors generated by the address resistor. For example, the compensator circuit may include an electronically controlled voltage shifter using an operational amplifier.

[0021] Optionally, the decoder is configured to measure the pulse width of each pulse in the control signal; and perform a related protocol based on the measurement.

[0022] According to a third aspect of the present disclosure, a method of controlling a power stage according to the second aspect of the present disclosure having multiple phases is provided, the method including: generating a control signal including a series of pulses; sending the control signal to the multiple phases via a first link; decoding the control signal for each phase and activating or deactivating the phase based on the control signal; receiving feedback signals from each phase via a second link; summing the multiple feedback signals and obtaining the average current per phase.

[0023] Optionally, the control signal includes one or more of a first pulse having a first pulse width for activating a first phase; a second pulse having a second pulse width for incrementally activating additional phases; a third pulse having a third pulse width for deactivating all phases; a fourth pulse having a fourth pulse width for initiating each phase to read its own address. Description of the Drawings

[0024] The present disclosure is described in more detail hereinafter by way of example and with reference to the accompanying drawings, in which:

[0025] Figure 1 is a schematic diagram of a power supply circuit using a conventional power stage and a controller;

[0026] Figure 2 is a schematic diagram of a known dual-single wire interface that can be used with Figure 1 the power management circuit of;

[0027] Figure 3 is a method for controlling a power stage according to the present disclosure;

[0028] Figure 4 is a schematic diagram of a power supply according to the present disclosure;

[0029] Figure 5 is a waveform diagram illustrating an exemplary control signal that can be used to operate Figure 4 the power supply of;

[0030] Figure 6 is a circuit schematic of the controller and the phase of the system from Figure 4 .

[0031] Figure 7A is an example embodiment of a circuit that can be used to perform address reading of the phase;

[0032] Figure 7B illustrates the address read control signal waveform that can be used to read the address of the phase of Figure 4 ;

[0033] Figure 8A is Figure 6 an example embodiment of a decoder of; and

[0034] Figure 8B is Figure 7A an example of the protocol of the decoder used;

[0035] Figure 9A illustrates the operation of the first wait unit in the circuit for Figure 8A ;

[0036] Figure 9B illustrates the operation of the second wait unit in the circuit for Figure 8A ; and

[0037] Figure 9C illustrates the operation of the arbiter in the circuit for Figure 8A . Detailed Description

[0038] Figure 1 is a schematic diagram of a power supply circuit using a traditional power stage with multiple intelligent power phases (see data sheet ISL992277, ""Smart Power Stage (SPS) Module with Integrated High Accuracy Current and Temperature Monitors"", November 2023, Renesas Electronics) and a controller (see data sheet ISL69127, ""Digital Dual Output 6+1-Phase VR13 PWM Controller"", January 2018, Renesas Electronics). The shown circuit is a power stage solution that can be configured for DC / DC power conversion. The circuit includes a standard interface for power phases in large digital systems.

[0039] Figure 2 is a schematic diagram of a known dual-single wire interface that can be used with a Figure 1 power supply. This interface allows a controller to connect to a phase using standard control interfaces (such as a digital interface (DIF)) and general control interfaces (such as digital input / output (DIO)). At the same time, implementing Figure 1 the interface settings as shown in Figure 2 the circuit can help reduce the complexity of circuit design. Figure 2 The DIF and DIO interfaces implemented in

[0040] Figure 3 is a flowchart of a method for controlling a power stage with multiple phases according to the present disclosure. The method includes steps 310 to 350.

[0041] At step 310, the controller generates a control signal. The control signal includes a series of pulses. At step 320, the controller sends the control signal to the multiple phases via a first link. The first link can be, for example, a unidirectional link.

[0042] At step 330, for each phase, the control signal is decoded and each phase is activated or deactivated based on the control signal. For example, each control signal can activate or deactivate a phase according to the configuration of the phase in the control signal.

[0043] At step 340, the controller receives feedback signals from each phase via a second link. The second link can also be, for example, a unidirectional link. Finally, at step 350, the controller sums the multiple feedback signals and calculates the average current per phase. The average current per phase can be used to balance the current between the multiple phases in the power stage.

[0044] Figure 4 is a schematic diagram of a power supply 400 according to the present disclosure. The power supply includes a controller 410 and a power stage 420, where the power stage 420 has multiple (N) phases, labeled 430, 431... 43N-1. The controller 410 controls the power stage 420 using the method outlined in Figure 3 The controller 410 includes a first port connected to a first link 440 and a second port connected to a second link 450. Each of the multiple phases is connected to the controller via both the first link 440 and the second link 450. Both the first link and the second link can be, for example, unidirectional links. The controller 410 and the power stage 420 can also be coupled via a single wire interface.

[0045] The controller 410 is configured to control a power stage 420 having multiple phases. The controller 410 generates a control signal that is transmitted via a first link 440 to the multiple phases. Each phase receives the control signal and decodes the signal. Based on the decoded control signal, each phase is either activated or deactivated. Each phase has its unique address. In this example, the first phase 430 has address 0, the second phase 431 has address 1, and the Nth phase 43N-1 has address N-1. This address is assigned during startup of the power supply 400 and is described in more detail hereinafter.

[0046] Each phase generates a feedback signal and an output current. For example, phase 430 generates output current I out,0 , and phase 431 generates output I out,1 . The total output current I out received at the load is the sum of each of the independent output currents from each of the multiple phases. The controller 410 is configured to receive the feedback signal from each phase via a second link 450. The controller 410 then sums the multiple feedback signals to derive the average current per phase. The average current per phase is proportional to the output current of each phase. Thus, the controller 410 uses the signals received via the second link 450 to monitor the output currents of the multiple phases 430. The output current of each phase needs to be monitored to balance the current between all phases, otherwise this may result in excessive power consumption and power loss between the power stages 420.

[0047] In a specific embodiment, the first link 440 can be a digital interface (DIF), and the second link 450 can be an analog feedback link (IFB). In other embodiments, the controller 410 can be a power distribution unit (DPU) controller, and the multiple phases 430 can be multiple DPUs.

[0048] The controller 410 may further include an optional third port connected to a third link 460. In this case, each phase is also connected to the controller 410 via the third link. The third link can be, for example, a unidirectional link. In such an embodiment, the controller 410 is configured to further generate a configuration signal that can be transmitted via the third link 460 to the multiple phases. The third link 460 transmits operating configuration conditions to the phases, such as activating turn-off during zero-crossing detection of the inductor, or setting a current limit for the phase. In a specific embodiment, the third link can be a digital input / output (DIO). DIO allows the transmission of more complex control signals. A standard bi-directional, multi-device bus can be used for this purpose.

[0049] The first link 440 transmits a single unidirectional control signal. The control signal is unidirectional, driven by the controller 410 and received by all of the multiple phases 430. The control signal can be a single-ended signal (1-wire) or a differential signal (2-wire).

[0050] Figure 5 is a waveform diagram showing an example control signal 510 that can be generated by the controller 410 in Figure 4 for controlling a power stage 420 including multiple (N) phases 430... 43N-1.

[0051] The reset state of the control signal 510 is 0. The control signal 510 includes a series of commands for the multiple phases using pulse-width encoding. The control signal includes a pulse sequence. The pulse width of each pulse can be used to perform specific phase activation or deactivation functions. In Figure 5 the control signal 510 includes a pulse sequence labeled 511 to 515.

[0052] The first pulse 511 has a first pulse width T1 that activates the first phase 430. The first pulse T1 triggers the activation of the phase with address 0 and resets the phase counter, phcount, to 0. The pulse width of T1 can be selected as the smallest possible duration. The corresponding phcount for the example control signal 510 is shown in Figure 5 using the phase counter 520.

[0053] The second pulse 512 has a second pulse width T2 that incrementally activates additional phases. The second pulse 512 triggers the activation of the phase with address phcount + 1. For example, if the current phcount is 0, the T2 pulse will activate the phase with address 0 + 1 = 1; if the current phcount is 2, the T2 pulse will activate the phase with address 2 + 1 = 3. The pulse width T2 of 512 is selected to be greater than the pulse width T1 of 511, but should still be small enough to reduce the delay in the response of the multiple phases 430.

[0054] In the general phase of operation, as the load applied to the power supply 400 increases, the number of phases that need to be activated will increase to cope with the increase in the load. Therefore, the control signal can have any configuration of T1 pulses and T2 pulses. The falling edge of the phase detection control signal is detected and a response is made based on the detected pulse width. By setting the most critical controls T1 and T2 to the minimum pulse duration, the critical delay is thus reduced. Once triggered, the phase generates a conduction time conduction pulse.

[0055] In Figure 5Among them, the duty cycle waveforms of three phases are shown. The first phase 430 with address 0 is shown by 530, the second phase 431 with address 1 is shown by 531, and the third phase 432 with address 2 is shown by 532. The example control signal 510 includes pulse sequences 511, 512, 513, and 514. The pulse 511 of the pulse with T1 activates the phase 430 with address 0. The pulse 512 (the first T2 pulse width) activates the phase 431 with address 1, as shown by the conduction pulse of the on-time in the duty cycle 531. The pulse 513 (the second T2 pulse width) corresponds to the pulse counter 520 of 2 and thus the phase 432 with address 2 is activated by the third pulse 513.

[0056] Additional pulses (not shown) can be used to perform different functions.

[0057] For example, a deactivation pulse having a third pulse width T3 can be used to deactivate all phases. The deactivation pulse sets all power stages to the high impedance mode. For example, when the load applied to the power supply 400 suddenly drops and multiple phases 430 need to be quickly deactivated, this deactivation pulse can be used. When a large load drop transient requires using a freewheeling diode instead of a switch to obtain a higher dI / dt, this deactivation pulse can also be used.

[0058] Another pulse is called an address pulse, which has a fourth pulse width T4 that can be used to start each phase to read its own address. The pulse width T4 can be selected to be relatively long compared to T1, T2, and T3. The address pulse triggers an address reading sequence for all pulses among the multiple pulses. In the general mode of operation of the power supply 400, when the power supply 400 is first initialized, the address pulse will be sent out in the control signal generated by the controller 410. The address pulse is transmitted to the multiple phases via the first link 440, where the first link 440 triggers an event sequence using the second link 450. The resistor connected via the first link for each phase can be used to read the phase address. Alternatively, the address resistor can be connected via the second input or the third input for each phase. This will be further discussed later.

[0059] In Figure 5 the control signal 510 in is just an example of the way different pulses can be configured. Generally speaking, the control signal can include one or more of the above pulses. In an alternative embodiment, more pulses with different pulse widths can be incorporated into the control signal to encode other instructions for the power stage 420.

[0060] Use a unidirectional link, for example, as the first link 440 to transmit the generated control signal, which allows for a simplified input / output design with reduced parasitic capacitance, lower power consumption, and generally faster speed.

[0061] Figure 6 is a circuit diagram showing an example of the coupling between one of the multiple phases of the controller 410 and Figure 4 one of the multiple phases.

[0062] The controller 410 includes a resistance circuit 412 coupled to a second port carrying the second link 450. The resistance circuit 412 has a plurality of resistors coupled in parallel, each resistor being connected to ground via a corresponding switch, and the corresponding switch is referred to as a sense switch (Ss1 - Ssn). The resistance circuit 412 also includes an additional address read switch Sr, which is used to perform the address read function in Figure 6 . The number of resistors in the resistance circuit 412 can be greater than or equal to the number of N phases. The sense switches Ss1 - Ssn are used to pull the corresponding resistor R s to ground to change the equivalent sense resistance R s / n as a function of the number of active phases n. The address read switch Sr is used to abbreviate for address reading, as explained in more detail with reference to Figure 7A and Figure 7B .

[0063] Each of the multiple (N) phases includes a decoder 432 coupled to the controller via the first link 440. Each phase also includes an address reader 434 coupled to the decoder 432. The address reader 434 is also coupled to the address resistor R addr (also referred to as R a ) via the second link 450. Each phase also includes a current monitoring module 438 and a current balancing module 436, where the current monitoring module 438 receives an input from the demodulator 432, and the current balancing module 436 receives an input from the address reader 434. A driver 433 is also provided to drive the high side and low side of the power switch of the phase.

[0064] Each phase generates a feedback signal I fb proportional to the output current of that phase. All the feedback signals are summed at the second link port of the controller 410. The resistance circuit 412 performs this summation. By adjusting the number of active resistors in the resistance circuit 412 to match the number of active phases, the feedback signal voltage represents the average current per phase. The number of active resistors can be selected by a signal nb_phases generated by the controller 410 through the resistance circuit 412 to turn on or off some switches in the circuit. For example, if the power supply 400 uses a single phase and an output current I oFor the operation, only one resistor is connected to the ground. In this case, the feedback voltage is I o / R, where R is the resistance value in the resistor circuit 412. If the power supply 400 operates with four phases, the total load current is 4I o and four resistors are connected to the ground, thus keeping the feedback voltage at I o / R. This can be used by the phase for current balancing purposes. When triggered, the driver 433 drives the high-side switch for a duration, which is called the on-time T on , which is a function of the input voltage and pre-programmed parameters. The balance circuit 436 is used to tune the T on duration. If the feedback current from a single phase is greater than the average output current I o of all phases, then the current balance module 436 sends a signal to the driver 433 to reduce the on-time T on of the high-side power switch. Conversely, if the feedback current from a single phase is lower than the average output current of all phases, the current balance module 436 sends a signal to the driver 433 to increase the on-time T on .

[0065] Each phase among multiple phases is assigned an independent address. Generally speaking, the assigned addresses start from 0 and are assigned continuously. When the power supply 400 is first connected to the power, the phase address reading is completed, and when the decoder 432 receives and decodes the address pulse of the pulse width T4, the phase address reading is started. This starts the address reading sequence. The address reading switch Sr is turned on and the current passes through R addr to measure the voltage at this phase, and the phase that will tell its own address. Each phase has its own R addr , and this R addr is placed between the controller 410 and the phase along the second link. Each resistor for address reading is placed in front of the common node between multiple phases and the controller, so that each phase reads its own resistor.

[0066] Figure 7A is a circuit diagram showing an exemplary embodiment of the address reader 434. The same components in the previous picture have been given the same labels and have the same meanings. The address reader 434 includes a logic circuit 434a, where the logic circuit 434a receives the decoded control signal from the decoder 432 that starts the reading sequence of the starting phase 430. The logic circuit 434a is coupled to the address resistor R a via the ADC. The address reader 434 also includes a current source for providing the reading current I read . The logic circuit 434a is configured to provide an enable signal I sns_enaTo turn on the current source.

[0067] By pushing the read current I read through the address resistor R a and measuring the voltage across the address resistor: V Ra = V sns-dpu – V sns Perform an address read. When I sns-ena = 1, I read is pushed through R a , otherwise I read = 0. The address reader 434 can only measure the phase voltage V sns_dpu related to the ground, so the resistor circuit 412 of the controller 410 turns on Sr to short-circuit the current sensing resistor R s / n and thus pulls the control voltage V sns to the ground. The read current I read with a preset and known value is forced through the address resistor R a by the address reader 434, while V sns is pulled to the ground. The phase voltage is then given by V sns_dpu = R a I read . To determine R a and thus determine the phase address, the analog-to-digital converter ADC in the address reader 434 measures V sns_dpu , and since I read is known, the address can be determined as R a = V sns_dpu / I read .

[0068] During the address read operation, the phase does not transfer power. The current i* is the measured value of the output current of the phase, so i* = 0 during the address read operation. Outside the address read, the current I read is deactivated and the current i* is proportional to the output current of the phase. The voltage at the control circuit 412 is given by V sns = R s i*. For a power stage with multiple phases connected in parallel, the voltage is then given by V sns = R s / nx(i* 1 + i* 2 + … + i* n ) = (R s / n)i* total , where n is the number of phases included in the power stage. By measuring V sns_dpu = R a i* + (R s / n)i* total, each phase can compare its own output current with the average load current. During the operation mode other than address reading operation, the current through the resistor R can be compensated by the compensator 434b. a The error generated. In this example, the compensator 434 uses an operational amplifier to form a current controller voltage shifter, where the operational amplifier output V sns_dpu -(R b Ki*), where R b is any resistor value, and K is the address read resistor R a The output of compensator 434b is therefore: R a i*+(R s / n)i* total -Ki*R b Therefore, the address resistor R a The introduced error can be reduced by setting K = R a / R b Removed.

[0069] Figure 7B is shown during the address read sequence Figure 7A 7 is a waveform diagram of signals received and sent in the address reader circuit 434 of FIG. 7. The control signal 710 is received by the decoder 432 including the pulse T4. The address read switch Sr is turned on at the beginning of the pulse T4, as shown in the waveform 720. The decoder 432 provides a signal 730 to the logic circuit 434a to start address reading and assert the enable signal I sns_ena 740. Read current I read Through the address resistor and maintain a constant value, and the voltage 750 can be measured. The measurement can be performed by an analog-to-digital converter, or even by a comparator that compares the voltage to some fixed reference voltage. The voltage measured on the address resistor gives the phase address in question. Waveform 760 indicates that the phase has an unidentified ID until the address reader 434 ends measuring the voltage. Waveform 770 indicates this point. At this point, the reader logic 434a generates different pulses indicating the phase address, where the phase address is read at the point where the address reading switch Sr is turned off. If the sense switches are turned off, they can be turned on again. The phase is now ready to receive further commands through the control signal 710. In an alternative embodiment, pulse 770 is not needed because the regional read sequence can be set to end after a predetermined time, at the end of which the address will be read.

[0070] Connecting a resistor with a readable value to the first link through the address reader may result in increased latency and degradation of the pulse width decoding performance of the decoder 432. Instead, the second link is used. This link is designed to be slow, and the second link input of the control circuit can be pulled low with a large transistor without degrading the interface.

[0071] Using R addr address reads introduce additional errors into the phase balance system, which is required to balance the different power module loads of the system. Therefore, the current balance module 436 is configured to take into account the additional voltage error introduced by R addr when balancing the feedback signals on the multiple phases 430.

[0072] The decoder 432 is configured to decode the control signal. It measures the pulse width of each pulse in the control signal and executes the relevant protocol based on this measurement.

[0073] Figure 8A is an example implementation method of a decoder 800 for which the high-side power switch and the low-side power switch for driving the phase are coupled to the driver 433. The decoder 800 includes a decoding asynchronous finite state machine (AFSM) 810 coupled to a counter or phase counter 820 and coupled to a logic circuit 830. The logic circuit 830 includes an arbiter labeled WAITX and two wait units labeled WAIT1 and WAIT0. The logic circuit 830 is implemented as part of the decoder to mitigate the undesired effects due to faults or non-persistent signals. The circuits of the arbiter and the wait units are shown in Figure 9A , Figure 9B and Figure 9C and. An example implementation method of the arbiter is described in Khomenko, D. Sokolov, A. Mokhov and A. Yakovlev, “WAITX: An Arbiter for Non-persistent Signals,” 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), San Diego, CA, USA, 2017. A brief description is provided herein. For the unit WAIT1, the output is asserted when the input to the unit is 1. Even if the input value becomes greater than 1, the output will have the value 1 and the output will remain at that value. Once WAIT1 is disabled, no output is produced. Similarly, the unit WAIT0 waits for the output to become 1 after being enabled. WAITX receives two inputs and waits for each input to become 1 after being enabled. However, the arbiter WAITX only allows input 1 to pass. After being enabled, the first input that becomes 1 is held and passed through WAITX until WAITX is disabled.

[0074] In operation, decoder 800 receives a control signal from controller 410 at the input of logic circuit 830, which is transmitted to decoding AFSM 810. AFSM 810 is configured to decode the control signal via a decoding protocol. The decoded AFSM 810 then updates switch drive circuit 433 and counter 820. Decoder 800 represents Figure 6 and Figure 7A an example implementation method of decoder 432, and thus they operate in the same manner.

[0075] Figure 8B is a flowchart of the decoding protocol executed by decoded AFSM 810, also known as a signal transition graph (STG). The flowchart provides instructions for a method of performing any pulse among pulses having pulse widths T1, T2, T3, or T4 of a control signal.

[0076] The controller of the present disclosure allows for better control of multiple (N) phases 430 - 43N-1 using a first link in combination with a simple yet effective current balancing and monitoring system with a shared feedback signal transmitted via a second link. Optionally, the controller may also include a compensation configuration for the entire power system 400 via a third link. The combination of the first and second links can be used for reading of power modules / phases without increasing the number of pins. The reduced number of pins reduces the cost associated with the pins of the power module and reduces the pin congestion of the PMIC embedding the control circuit.

[0077] Figure 9A is a schematic diagram illustrating the operation of a first waiting unit in a Figure 8A circuit.

[0078] Figure 9B is a schematic diagram illustrating the operation of a second waiting unit in a Figure 8A circuit.

[0079] Figure 9C is a schematic diagram illustrating the operation of an arbiter in a Figure 8A circuit.

[0080] Those skilled in the art will realize that variations of the present disclosure are possible without exceeding the scope of the present disclosure. Accordingly, the description of the above specific embodiments is provided by way of example only and not for purposes of limitation. It will be clear to those skilled in the art that minor adjustments can be made without significant changes to the operations described.

Claims

1. A controller for controlling a power stage having multiple phases, the controller being configured to: generating a control signal; sending the control signal to the plurality of phases via a first link; receiving a feedback signal from each phase via a second link; summing a plurality of the feedback signals; as well as Find the average current per phase.

2. The controller according to claim 1, having a first port connected to the first link and a second port connected to the second link, and a resistance circuit coupled to the second port, the resistance circuit having a plurality of resistors coupled in parallel, each resistor being connected to ground via a corresponding switch.

3. The controller of claim 2, wherein the resistor circuit includes an additional switch for performing a phase address reading function.

4. The controller according to claim 1, wherein the control signal comprises one or more of the following: a first pulse having a first pulse width, for activating a first phase; a second pulse having a second pulse width for incrementally activating additional phases; a third pulse having a third pulse width for deactivating all phases; as well as The fourth pulse with a fourth pulse width is used to start each phase to read the address of each phase itself. The controller of claim 1 , wherein the first link and the second link are unidirectional links. 6 . The controller of claim 1 , wherein a sum of the feedback signals is proportional to output currents generated by the plurality of phases. 7 . The controller according to claim 1 , wherein the controller is further configured to generate a configuration signal for configuring one or more phases, wherein the configuration signal can be transmitted via a third link.

8. A power supply comprising the controller of claim 1 coupled to a power stage having a plurality of phases.

9. The power supply of claim 8, wherein the controller is coupled to the power stage via a single-wire interface.

10. The power supply of claim 8, wherein each phase includes a decoder for decoding the control signal.

11. The power supply of claim 10, wherein the decoder comprises a finite state machine coupled to a phase counter and a logic circuit; wherein the finite state machine is configured to execute a decoding protocol.

12. The power supply of claim 11, wherein the logic circuit comprises an arbiter coupled to one or more wait cells.

13. The power supply of claim 8, wherein each phase includes an address reader configured to read the phase address by sending a current through an address resistor.

14. The power supply of claim 13, wherein the address reader comprises logic circuitry configured to initiate a read sequence.

15. The power supply of claim 14, wherein the address reader includes a compensator circuit configured to compensate for errors generated by the address resistors.

16. The power supply of claim 10, wherein the decoder is configured to measure the pulse width of each pulse in the control signal; and execute a related protocol based on the measurement.

17. A method of controlling a power stage having a plurality of phases, the method comprising: generating a control signal comprising a series of pulses; sending the control signal to the plurality of phases via a first link; for each phase, decoding the control signal and activating or deactivating the phase based on the control signal; receiving a feedback signal from each phase via a second link; summing a plurality of the feedback signals; as well as Find the average current per phase.

18. The method of claim 17, wherein the control signal comprises one or more of the following: a first pulse having a first pulse width, for activating a first phase; a second pulse having a second pulse width for incrementally activating additional phases; a third pulse having a third pulse width for deactivating all phases; as well as The fourth pulse having a fourth pulse width is used to start each phase to read its own address.

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