A page storage method, virtual machine system, device, medium and product

Abstract

The present invention discloses a page storage method, a virtual machine system, a device, a medium and a product, and relates to the field of computer data storage. Based on a hardware mechanism, the page information stored in the virtual machine memory is obtained, and the access and modification information of the page is directly recorded to reduce software overhead. Based on the page information in the page tracking process, the virtual machine page hit rate and page access frequency are determined, and the subsequent page migration process is participated in. According to the page migration strategy and the page access frequency, the target page of the target virtual machine is migrated and processed, and the page is flexibly adjusted according to the real-time running status of the virtual machine to improve the adaptability of the system. According to the page migration strategy corresponding to the upgrade or downgrade under different circumstances of the current state machine level of the virtual machine and the target state machine level, the virtual machine upgrade and downgrade status is controlled, and the memory level corresponding to the page is adjusted in time and dynamically.

Description

Technical Field

[0001] The present invention relates to the field of computer data storage, and in particular to a page storage method, a virtual machine system, a device, a medium and a product. Background Art

[0002] The memory tiering system primarily consists of three components: page tracking, page classification, and page migration. Page tracking regularly checks and clears memory accesses through page table scanning. This method, which scans and searches through multiple levels of page tables, consumes significant processor resources and results in high overhead. Page classification typically identifies hot and cold pages based on page characteristics, such as access time or frequency. Once classified, hot and cold pages can change over time, and maintaining the same allocation across different memory tiers consumes more memory space at the corresponding tier, resulting in high storage resource overhead.

[0003] Therefore, how to reduce the overhead of computing resources and storage resources is a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0004] The purpose of the present invention is to provide a page storage method, virtual machine system, device, medium and product to solve the problem of high overhead of computing resources for page tracking and storage resources for page classification.

[0005] To solve the above technical problems, the present invention provides a page storage method, comprising:

[0006] Obtaining page information corresponding to read and write operations of the virtual machine memory based on a hardware mechanism; and determining the virtual machine page hit rate and page access frequency based on the page information;

[0007] Determining a target state machine level based on a relationship between the memory capacity of the target virtual machine allocated to the first memory, the page hit rate of the virtual machine, and a state level condition of the state machine; and determining a page migration strategy for the target virtual machine based on the current state machine level and the target state machine level;

[0008] In the memory hierarchy, the target page of the target virtual machine is migrated according to the page migration strategy and the page access frequency to complete page storage; wherein, the memory hierarchy includes a first memory and a second memory; the storage rate of the first memory is greater than the storage rate of the second memory.

[0009] On the one hand, the page information corresponding to the read and write operations of the virtual machine memory is obtained based on the hardware mechanism, including:

[0010] Obtaining first page information corresponding to a virtual machine memory write operation based on a page modification log mechanism;

[0011] Acquire second page information corresponding to the virtual machine memory read operation based on an event precise sampling mechanism;

[0012] The first page information and the second page information are used as the page information.

[0013] On the other hand, determining the target state machine level based on the relationship between the memory capacity of the target virtual machine allocated to the first memory, the page hit rate of the virtual machine, and the state level condition of the state machine includes:

[0014] Determining the stability of the current state machine level based on the rate of change of the virtual machine page hit rate;

[0015] The target state machine level is determined according to a relationship between the current state machine level, the memory capacity, the stability level, and a state machine state level condition.

[0016] On the other hand, the state level conditions include an upgraded state level condition, a stable state level condition, and a downgraded state level condition;

[0017] Among them, the upgrade status level condition includes a first upgrade status level condition and a second upgrade status level condition; the first upgrade status level condition is that the memory capacity is less than the upgrade waterline of the virtual machine memory; the second upgrade status level condition is that the memory capacity is greater than or equal to the upgrade waterline, and less than the demotion waterline of the virtual machine memory, and the stability level is unstable; the stable status level condition is that the memory capacity is greater than or equal to the upgrade waterline, and less than the demotion waterline, and the stability level is stable; the demotion status level condition is that the memory capacity is greater than or equal to the demotion waterline.

[0018] On the other hand, determining the target state machine level according to the relationship between the current state machine level, the memory capacity, the stability level, and the state machine state level condition includes:

[0019] When the current state machine level is in the upgrade state, if the memory capacity meets the first upgrade state level condition, determining that the target state machine level is in the upgrade state; if the memory capacity does not meet the first upgrade state level condition, determining whether a second upgrade state level condition is met based on the memory capacity and the stability;

[0020] If the second upgrade state level condition is met, determining the target state machine level to be the upgrade state; if the second upgrade state level condition is not met, determining whether the stable state level condition is met based on the memory capacity and the stability;

[0021] If the stable state level condition is met, the target state machine level is determined to be stable; if the stable state level condition is not met, whether the degraded state level condition is met is determined based on the memory capacity;

[0022] If the degraded state level condition is met, the target state machine level is determined to be in a degraded state.

[0023] On the other hand, determining the target state machine level according to the relationship between the current state machine level, the memory capacity, the stability level, and the state machine state level condition includes:

[0024] When the current state machine level is in a stable state, if the memory capacity satisfies the degraded state level condition, determining that the target state machine level is in a degraded state; if the memory capacity does not satisfy the degraded state level condition, determining whether the first upgraded state level condition is satisfied based on the memory capacity;

[0025] If the first upgrade state level condition is met, determining the target state machine level to be the upgrade state; if the first upgrade state level condition is not met, determining whether the second upgrade state level condition is met based on the memory capacity and the stability;

[0026] If the second upgrade state level condition is met, the target state machine level is determined to be the upgrade state; if the second upgrade state level condition is not met, the target state machine level is determined to be the stable state.

[0027] On the other hand, migrating the target page of the target virtual machine according to the page migration policy and the page access frequency in the memory hierarchy to complete page storage includes:

[0028] Get the threshold page access frequency;

[0029] When migrating from the second memory to the first memory, obtaining access frequencies of multiple pages of the second memory based on array information corresponding to the Bloom filter;

[0030] Screening a target page access frequency greater than the threshold page access frequency from a plurality of page access frequencies;

[0031] A page corresponding to the target page access frequency is used as a target page to be migrated to the first memory.

[0032] On the other hand, obtaining multiple page access frequencies of the second memory based on array information corresponding to the Bloom filter includes:

[0033] Performing mapping processing on the current page using a first hash function to determine a tag value of the index data block;

[0034] Determine the address information of the corresponding index data block according to the tag value;

[0035] Obtain K second hash functions;

[0036] Processing the data blocks of the address information using K second hash functions to determine their corresponding values;

[0037] If multiple values and the current page are stored in the index data block, it is convenient to obtain the page access frequency.

[0038] On the other hand, migrating the target page of the target virtual machine according to the page migration policy and the page access frequency in the memory hierarchy to complete page storage includes:

[0039] Get the threshold page access frequency;

[0040] When migrating from the first memory to the second memory, scanning the physical address information of the first memory by a linear scanning mechanism;

[0041] Comparing the page access frequency corresponding to the physical address information of the first memory with the threshold page access frequency;

[0042] If the page access frequency is less than the threshold page access frequency, a page corresponding to a target page access frequency less than the threshold page access frequency is used as a target page to be migrated to the second memory.

[0043] On the other hand, the process of determining the virtual machine page hit rate includes:

[0044] Converting the virtual address information of the page information into physical address information;

[0045] Obtaining a physical address range corresponding to the first memory;

[0046] Determining a current hit count corresponding to the page information in the first memory according to the physical address information and a physical address range of the first memory;

[0047] Get the last virtual machine page hit rate and total hit count;

[0048] Determining an initial virtual machine page hit rate according to the current hit count and the total hit count;

[0049] The virtual machine page hit rate is determined based on the initial virtual machine page hit rate, the last virtual machine page hit rate, and respective corresponding hit rate weight parameters.

[0050] On the other hand, the process of determining the page access frequency includes:

[0051] Obtain the page read operation count, page write operation count, and total access count of the page information;

[0052] Determine a weight parameter according to the read and write bandwidths corresponding to the first memory and the second memory;

[0053] Determine a read operation access frequency and a write operation access frequency according to the number of page read operations, the number of page write operations, and the total number of accesses;

[0054] The page access frequency is determined based on the weight parameter, the read operation access frequency, and the write operation access frequency.

[0055] On the other hand, determining a page migration strategy of the target virtual machine according to the current state machine level and the target state machine level includes:

[0056] Obtaining a current state machine level of the target virtual machine, wherein the state machine level is set to an upgraded state when the state machine level is determined for the first time;

[0057] If the current state machine level is in the upgraded state and the target state machine level is in the upgraded state, the upgraded state is maintained without page migration; if the target state machine level is in the stable state, the state is changed to the stable state without page migration; if the target state machine level is in the degraded state, the target page of the target virtual machine is migrated from the first memory to the second memory;

[0058] If the current state machine level is in a degraded state and the target state machine level is in an upgraded state, the target page of the target virtual machine is migrated from the second memory to the first memory; if the target state machine level is in a stable state, the state is changed to a stable state without performing page migration; if the target state machine level is in a degraded state, the degraded state is maintained without performing page migration;

[0059] If the current state machine level is in a stable state and the target state machine level is in a degraded state, the target page of the target virtual machine is migrated from the first memory to the second memory; if the target state machine level is in a degraded state, the target page of the target virtual machine is migrated from the second memory to the first memory; if the target state machine is in a level state, the stable state is maintained and no page migration is performed.

[0060] On the other hand, obtaining the first page information corresponding to the virtual machine memory write operation based on the page modification log mechanism includes:

[0061] Call the first process;

[0062] Obtaining a virtual machine file descriptor by calling a first function through the first process;

[0063] Sending a call instruction through a virtual machine file descriptor to set a dirty page tracking flag for the virtual machine memory to enable a dirty page tracking function for the memory of the virtual machine;

[0064] Dirty page log information is acquired according to a first preset period, and the dirty page log information is used as the first page information.

[0065] On the other hand, obtaining the second page information corresponding to the virtual machine memory read operation based on the event precise sampling mechanism includes:

[0066] Call the second process;

[0067] Configuring and starting memory read event tracing corresponding to the second process;

[0068] Create a shared ring buffer to store event data;

[0069] A second function is called to start a tracing function, so as to obtain event data of the shared ring buffer according to a second preset period as the second page information.

[0070] On the other hand, the aging process of the read access frequency and the write access frequency includes:

[0071] Traversing pages corresponding to the read operation access frequency and the write operation access frequency, and performing a union process to obtain a third page;

[0072] Acquire a read operation count and a write operation count according to the third page;

[0073] Performing aging operations on the read operation count and the write operation count to obtain updated read operation count and write operation count respectively; and using the updated read operation count and write operation count as the updated fourth page;

[0074] The read operation access frequency and the write operation access frequency are determined based on the fourth page to complete an aging process.

[0075] On the other hand, before migrating the target page from the second memory to the first memory, the method further includes:

[0076] Determining a current space utilization of the first memory;

[0077] If the current space utilization is greater than the first preset space utilization, the threshold page access frequency is increased, and the process returns to the step of screening a target page access frequency greater than the threshold page access frequency from multiple page access frequencies to redetermine a new target page for migration processing.

[0078] To solve the above technical problems, the present invention also provides a virtual machine system, including at least one virtual machine, at least one virtual machine memory including at least one page; the hierarchical storage of at least one page is completed by the steps of the page storage method described above.

[0079] To solve the above technical problems, the present invention further provides a page storage device, comprising:

[0080] memory for storing computer programs;

[0081] A processor is used to implement the steps of the page storage method when executing the computer program.

[0082] To solve the above technical problem, the present invention further provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the page storage method as described above are implemented.

[0083] To solve the above technical problem, the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the page storage method when executed by a processor.

[0084] The beneficial effects of the present invention are as follows: first, based on a hardware mechanism, page information stored in the virtual machine memory is obtained, and page access and modification information is directly recorded. Compared to conventional software mechanisms that scan page tables, this mechanism periodically triggers scans of the entire page, reducing software overhead and eliminating the need for frequent page table scans, thus reducing processor time and memory bandwidth, and conserving processor computing resources. The hardware mechanism can provide accurate page access and modification information to avoid delays that may be introduced by software sampling. Second, based on the page information during the page tracking process, the present invention determines the virtual machine page hit rate and page access frequency, and participates in the subsequent page migration process. First, at the virtual machine level, the memory capacity allocated to the fast memory, such as the first memory, is determined. The target state machine level is determined based on the memory capacity, the virtual machine page hit rate, and the state level conditions of the state machine. The actual target state machine level is determined based on the overall state of the virtual machine, so that a page migration strategy can be determined based on the current state machine level and the target state machine level. By focusing on the overall virtual machine's storage capacity corresponding to the allocated fast memory, the page migration strategy is more comprehensive. Compared with conventional technical solutions that only store page data at the page level, it can achieve global optimization of resource allocation and reduce memory fragmentation. Thirdly, the target pages of the target virtual machine are migrated in the memory hierarchy according to the page migration strategy and the page access frequency. The pages are flexibly adjusted according to the real-time running status of the virtual machine to improve the adaptability of the system. The page migration strategy corresponding to the upgrade or downgrade under different circumstances of the current state machine level and the target state machine level of the virtual machine is used to control the upgrade and downgrade status of the virtual machine, and the memory hierarchy corresponding to the page is adjusted dynamically in time so that the memory of different memory levels only stores the corresponding pages, so as to avoid the situation where cold pages are stored in the fast memory and hot pages are stored in the slow memory, resulting in a large storage resource overhead of the memory occupied by each, thereby reducing the storage resource overhead.

[0085] In addition, the present invention also provides a virtual machine system, a page storage device, a non-volatile storage medium, and a computer program product, which have the same beneficial effects as the above-mentioned page storage method. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0087] Figure 1 A schematic diagram of the delay properties of various memory storage types provided by an embodiment of the present invention;

[0088] Figure 2A flow chart of a page storage method provided by an embodiment of the present invention;

[0089] Figure 3 A schematic diagram of a state machine transition for virtual machine upgrade and downgrade provided by an embodiment of the present invention;

[0090] Figure 4 A schematic diagram of a virtualization layered system framework provided by an embodiment of the present invention;

[0091] Figure 5 A structural diagram of a page storage device provided by an embodiment of the present invention;

[0092] Figure 6 A structural diagram of a page storage device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0093] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0094] The core of the present invention is to provide a page storage method, virtual machine system, device, medium and product to solve the problem of high overhead of computing resources for page tracking and storage resources for page classification.

[0095] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0096] Virtualization technology is a key enabler of cloud computing. Virtual machines, with their hardware compatibility, security, reliability, and high performance, support the vast majority of cloud-based businesses. As modern cloud-based AI applications increasingly demand more memory, the capacity and bandwidth required are increasing. Due to slowing density growth and persistently high costs of dynamic random access memory (DRAM), the supply-demand gap continues to widen. Memory tiering based on the Compute Express Link (CXL) interconnect is one of the most promising solutions to this challenge. Memory connected via the CXL interface supports byte addressing, can be directly accessed by the host central processing unit (CPU), and supports standard memory allocation interfaces. Compared to local DRAM, CXL-connected memory offers greater capacity and lower cost per GB, but also higher latency and lower bandwidth. Different CXL memory devices may have different latency and bandwidth. Current (directly connected) CXL memory devices introduce an additional 50 to 100 nanoseconds of access latency compared to local DRAM. These differences lead to increased heterogeneity in CXL-based computer memory systems. Therefore, a corresponding page scheduling method is designed based on the heterogeneity of memory, which keeps the hot data in the virtual machine memory in the fast memory (local DRAM) and stores the remaining data in the slow memory (CXL memory). This does not affect the performance of the virtual machine and can also increase the system's available memory capacity at a lower cost.

[0097] Figure 1 A schematic diagram of the delay properties of various memory storages provided by an embodiment of the present invention, such as Figure 1 As shown, most memory accesses are concentrated on a small portion of data, and the memory access heat distribution follows a highly skewed Zipf's distribution, where a small portion of memory accounts for the majority of accesses. A typical memory hierarchy system includes three components: page tracking, page classification, and page migration. Page migration is generally implemented by the kernel or hypervisor, focusing primarily on page tracking and page classification. Page tracking is used to capture the memory access information required for memory management. Page table (PT) scanning tracks memory accesses by periodically checking and clearing the access / dirty bits. For virtualized systems, scanning of two-dimensional page tables is required. Without proper optimization, page table scanning can cause unacceptable overhead due to additional pressure on the Memory Management Unit (MMU), primarily consuming CPU computing resources.

[0098] Page classification is used to distinguish between hot and cold pages. Currently, mainstream page classification methods fall into two categories. One classifies pages based on recent access time, using the distance of access time to approximate data popularity. This approach is characterized by low overhead and low recognition accuracy. The other classifies hot data based on access frequency, which is characterized by high recognition accuracy but high overhead. However, conventional page classification only operates at the page level and fails to consider the current state of the memory hierarchy or the virtual machine state machine. Consequently, once classified, hot and cold pages can change over time. Classifying them to different memory hierarchies requires maintaining the same hierarchical allocation, resulting in a significant increase in memory space occupied by the corresponding hierarchical level. For example, in fast memory, a previously hot page may become a cold page due to time fluctuations, still occupying fast memory storage resources. In slow memory, a previously cold page may become a hot page due to time fluctuations, occupying slow memory storage resources. Hot pages may also be left out of the slow memory. Over time, after becoming cold, they may continue to be misleadingly considered cold pages. Overall, this leads to high storage resource usage and overhead, while untimely dynamic adjustments can lead to poor system performance. The page storage method provided by the present invention can solve the above technical problems.

[0099] Figure 2 A flow chart of a page storage method provided by an embodiment of the present invention is as follows: Figure 2 As shown, the method includes:

[0100] S11: Obtaining page information corresponding to read and write operations of the virtual machine memory based on the hardware mechanism; and determining the virtual machine page hit rate and page access frequency based on the page information;

[0101] S12: determining a target state machine level based on a relationship between the memory capacity of the target virtual machine allocated to the first memory, the page hit rate of the virtual machine, and a state level condition of the state machine; and determining a page migration strategy for the target virtual machine based on the current state machine level and the target state machine level;

[0102] S13: Migrating the target page of the target virtual machine in the memory hierarchy according to the page migration policy and the page access frequency to complete the page storage;

[0103] The memory hierarchy includes a first memory and a second memory; the storage rate of the first memory is greater than the storage rate of the second memory.

[0104] Specifically, conventional technical solutions employ a software mechanism, such as page table scanning, to acquire page information. Page table scanning is a common memory management operation used to search or update the mapping between virtual addresses and physical addresses. Modern operating systems typically use multi-level page tables (such as two-, three-, or four-level page tables) to manage virtual address space. While this structure saves memory space, it requires accessing page table entries level by level during lookups, increasing access latency. In a multi-level page table, each address translation may require multiple memory read operations. For example, in a four-level page table, searching for a virtual address may require accessing four different page table entries, each of which consumes computing resources and results in significant computational overhead. The hardware mechanism employed in step S11 directly records page access and modification information, eliminating the need for frequent page scans by software and reducing software overhead. This allows for direct acquisition of relevant data when performance events occur, avoiding delays introduced by software sampling. Furthermore, while conventional page table scanning is an active scan, the hardware mechanism in this embodiment utilizes a passive acquisition mechanism. This mechanism can immediately record relevant information when an event occurs, without requiring software scanning, thereby providing more real-time page access information. This reduces reliance on software, lowering software complexity and the likelihood of errors. In the aforementioned hardware mechanism, the same hardware mechanism can be used to obtain page information corresponding to both read and write operations of the virtual machine's memory, or different hardware mechanisms can be used to obtain page information corresponding to both read and write operations of the virtual machine's memory. This is not limited in this embodiment and can be set according to actual circumstances.

[0105] After determining the page information, the virtual machine page hit rate and page access frequency are determined based on the page information. The virtual machine page hit rate here refers to the proportion of virtual machine pages accessed during the statistical period that are located in the first memory. The first and second memories here are distinguished as fast and slow memories. Fast memory can be local DRAM, which has smaller capacity, higher bandwidth, and lower latency than CXL memory. Slow memory, such as CXL memory, can be obtained by direct output from the system, calculated using page information, or a combination of the two previous technical solutions. If the two are the same, the virtual machine page hit rate corresponding to either technical solution is used as the final virtual machine page hit rate. If they are different, the final virtual machine page hit rate is averaged. In this embodiment, the calculation process based on page information can be performed using a conventional method, dividing the number of hits by the total number of accesses, or using a new method that takes into account the impact of historical hit rates on the current number of hits and incorporates the previous virtual machine page hit rate into the calculation of the number of hits and the total number of accesses. This relationship can be determined using a weighted approach.

[0106] The typical calculation method for page access frequency is (page read operations + page write operations) / total access times. You can also set read / write weights based on the specific business and slow memory characteristics, and determine page access frequency based on the ratio of read / write weights. There are no specific restrictions here; you can set it based on your actual situation.

[0107] It should be noted that, in the page tracking process of this embodiment, the virtual machine page hit rate and page access frequency are mainly determined for use in subsequent page classification.

[0108] The target virtual machine in step S12 allocates memory capacity to the first memory. The target virtual machine can correspond to one or more of the following: A virtual machine system includes multiple virtual machines, each of which contains multiple virtual machine memories. The virtual machine memory pages are classified into the first memory and the second memory of the memory hierarchy. Statistics here refer to the memory capacity allocated to the first memory by the target virtual machine. The target state machine level is determined based on the memory capacity, the virtual machine page hit rate, and the state level conditions of the state machine. It should be noted that the virtual machine state machine is a mechanism for managing the virtual machine lifecycle and state transitions. It defines the different states a virtual machine may be in and the transition rules between states. In this embodiment, the state machine is used for virtual machine memory tier adjustment and has three states: "upgrade," "downgrade," and "stable." The upgrade state performs an operation to migrate the virtual machine memory from the second memory (slow memory) to the first memory (fast memory), the downgrade state performs the opposite operation, and the stable state performs no operation.

[0109] The change in the virtual machine page hit rate can determine the stability of the proportion of its accessed virtual machine pages located in the fast memory. Therefore, this embodiment determines its stability through the virtual machine page hit rate. The target state machine level is determined based on the relationship between the memory capacity and stability and the state level conditions of the corresponding state machine. It should be noted that the target state machine level is the actual state machine level calculated based on the current data. The current state machine level is the currently defined state machine level. There may be changes between the current state machine level and the target state machine level. Therefore, the page migration strategy is determined based on the changes between the current state machine level and the target state machine level, whether it is an upgrade, downgrade or stable state.

[0110] The page migration strategy in step S12 can be used to determine the virtual machine state machine level to be changed. In step S13, based on the change in the virtual machine state machine level, the corresponding virtual machine memory storage pages also need to be adjusted. The adjustment here is based on the page level, and the migration process between the first memory and the second memory can be performed based on the page access frequency.

[0111] The beneficial effects of the embodiments of the present invention are as follows: first, a hardware-based mechanism obtains page information stored in the virtual machine's memory and directly records page access and modification information. Compared to conventional software mechanisms that scan page tables, this mechanism periodically triggers scans of the entire page, reducing software overhead and eliminating the need for frequent page table scans. This reduces processor time and memory bandwidth, thus conserving processor computing resources. The hardware mechanism can provide accurate page access and modification information, avoiding delays that may be introduced by software sampling. Second, the present invention determines the virtual machine's page hit rate and page access frequency based on page information during the page tracking process, and participates in the subsequent page migration process. First, at the virtual machine level, the memory capacity allocated to a fast memory such as the first memory is determined. The target state machine level is determined based on the memory capacity, the virtual machine's page hit rate, and the state level of the state machine. The actual target state machine level is determined based on the overall state of the virtual machine, so that a page migration strategy can be determined based on the current state machine level and the target state machine level. By focusing on the overall virtual machine's storage capacity corresponding to the allocated fast memory, the page migration strategy is more comprehensive. Compared to conventional solutions that only store page data at the page level, this strategy achieves global optimization of resource allocation and reduces memory fragmentation. Thirdly, the target pages of the target virtual machine are migrated in the memory hierarchy according to the page migration strategy and the page access frequency. The pages are flexibly adjusted according to the real-time running status of the virtual machine to improve the adaptability of the system. The page migration strategy corresponding to the upgrade or downgrade under different circumstances of the current state machine level and the target state machine level of the virtual machine is used to control the upgrade and downgrade status of the virtual machine, and the memory hierarchy corresponding to the page is adjusted dynamically in time so that the memory of different memory levels only stores the corresponding pages, so as to avoid the situation where cold pages are stored in the fast memory and hot pages are stored in the slow memory, resulting in a large storage resource overhead of the memory occupied by each, thereby reducing the storage resource overhead.

[0112] In some embodiments, obtaining page information corresponding to read and write operations of a virtual machine memory based on a hardware mechanism includes:

[0113] Obtaining first page information corresponding to a virtual machine memory write operation based on a page modification log mechanism;

[0114] Acquire the second page information corresponding to the virtual machine memory read operation based on the event precise sampling mechanism;

[0115] The first page information and the second page information are regarded as page information.

[0116] Specifically, in this embodiment, different hardware mechanisms are used to obtain the page information corresponding to read and write operations. The first page information corresponding to virtual machine memory write operations is obtained based on the Page Modification Logging (PML) mechanism. This mechanism relies on hardware characteristics and is used to efficiently track virtual machine write operations to memory pages in a virtualized environment. The second page information corresponding to virtual machine memory read operations is obtained based on the Precise Event-Based Sampling (PEBS) mechanism, accurately sampling performance events on the processor. With hardware support, relevant data is directly saved to memory when a performance event occurs, rather than relying on interrupt processing, thereby reducing sampling latency and improving sampling accuracy.

[0117] This embodiment provides two different hardware mechanisms for obtaining page information, thereby achieving more comprehensive monitoring, improving the performance of the virtualization system, and optimizing memory management and reducing power consumption.

[0118] In some embodiments, obtaining first page information corresponding to a virtual machine memory write operation based on a page modification log mechanism includes:

[0119] Call the first process;

[0120] Obtain a virtual machine file descriptor by calling a first function through a first process;

[0121] Sending a call instruction through the virtual machine file descriptor to set a dirty page tracking flag for the virtual machine memory to enable a dirty page tracking function for the virtual machine memory;

[0122] Dirty page log information is acquired according to a first preset period, and the dirty page log information is used as the first page information.

[0123] Specifically, KVM enables the global PML function by default, and the process of tracking memory write events of a specific virtual machine is as follows:

[0124] FUN: TraceMemoryWrite;

[0125] INPUT: vmpid / / virtual machine process ID;

[0126] vmfd=pid2fd(vmpid);

[0127] / / Add flag KVM_MEM_LOG_DIRTY_PAGES to virtual machine memory;

[0128] foreach mem_slot in memory(fd){

[0129] mem_slot->flags |=KVM_MEM_LOG_DIRTY_PAGES;

[0130] ioctl(vmfd, KVM_SET_USER_MEMORY_REGION, &mem_slot);

[0131] }

[0132] / / Periodically read and save records;

[0133] loop every second{

[0134] ioctl(vmfd, KVM_GET_DIRTY_LOG, &dlog);

[0135] backlog.save(vmpid, WRITE, HPA(dlog.vaddr), timestamp);

[0136] }.

[0137] In the above code, the virtual machine process identity (ID) is input (the first process), and the first function (pid2fd) is called by the first process to obtain the file descriptor associated with the virtual machine. Setting the dirty page tracking flag for the virtual machine's memory area requires identifying all the virtual machine's memory areas (mem_slots). For each memory area, a bitwise operation is performed to add the dirty page tracking flag to enable dirty page tracking for the virtual machine's memory.

[0138] Obtain dirty page log information according to a first preset period, execute the operation cyclically, and use the obtained log information as the first page information.

[0139] The processor's virtualization hardware enhancements allow the Virtual Machine Monitor (VMM) to use Extended Page Tables (EPT) to monitor physical page modifications during virtual machine execution. When PML is enabled, every write operation to the EPT with the dirty flag set generates a log recording the virtual machine's physical address. When the log is full, a VM exit is triggered, allowing the VMM to monitor modified pages. This feature allows monitoring of only page modification events.

[0140] This embodiment provides a specific process for obtaining the first page information corresponding to a virtual machine memory write operation using a page modification log mechanism, implementing a virtual machine memory management scenario to optimize memory synchronization by tracking dirty pages. The page modification log mechanism efficiently tracks virtual machine memory write operations, significantly reducing software page table scanning overhead and improving the performance of operations such as virtual machine migration.

[0141] In some embodiments, obtaining second page information corresponding to a virtual machine memory read operation based on an event precise sampling mechanism includes:

[0142] Call the second process;

[0143] Configure and start memory read event tracing corresponding to the second process;

[0144] Create a shared ring buffer to store event data;

[0145] The second function is called to start the tracing function, so as to obtain the event data of the shared ring buffer according to the second preset period as the second page information.

[0146] Specifically, the reading process is as follows:

[0147] FUN: TraceMemoryRead;

[0148] INPUT: vmpid / / virtual machine process ID;

[0149] / / Start memory ALL_LOADS event tracking for the virtual machine process pid through the system call perf_event_open;

[0150] attr.type=PERF_TYPE_RAW;

[0151] attr.config=0x81D0;

[0152] fd=syscall(__NR_perf_event_open, attr, vmpid, -1 / on any CPU / ,-1,0);

[0153] / / Create a shared ring buffer to store PEBS memory read events, so that user mode can access the trace data;

[0154] buffer=mmap(NULL, MMAP_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);

[0155] / / Enable tracing via ioctl(fd, PERF_EVENT_IOC_ENABLE, 0);

[0156] ioctl(fd, PERF_EVENT_IOC_ENABLE, 0);

[0157] / / Periodically read and save records;

[0158] loop every second{

[0159] for rec in buffer{

[0160] if(rec.vaddr is vm memory)

[0161] backlog.save(vmpid,READ,HPA(rec.vaddr),timestamp);

[0162] }

[0163] }.

[0164] In the above code, the VM process ID (the second process) is input. Performance event tracing is configured and started in the second process. A shared ring buffer is created using the mmap system call to store PEBS event data. The second function (ioctl) is called to start tracing. Records are read and saved according to the second preset period, and the saved data is used as the second page information.

[0165] Event-based precise sampling technology is an extension of standard performance event counters. The processor writes the instruction pointer into a software-specified PEBS memory buffer. When the buffer is full, it triggers a hardware performance monitoring interrupt to notify the system software. This technology mitigates instruction slip (defined as the distance between the instruction that triggers the performance event and the instruction at the time the sample is recorded) and reduces overhead.

[0166] This embodiment provides an event-based precise sampling mechanism for obtaining second page information corresponding to a virtual machine memory read operation. The event-based precise sampling mechanism is supported by hardware and triggers an interrupt only when the sampling buffer reaches a certain threshold, thereby reducing the operating system's overhead in processing interrupts and improving the overall performance of the system.

[0167] In some embodiments, the process of determining the page hit rate of the virtual machine includes:

[0168] Convert the virtual address information of the page information into physical address information;

[0169] Obtaining a physical address range corresponding to the first memory;

[0170] Determine the current hit count corresponding to the page information in the first memory according to the physical address information and the physical address range of the first memory;

[0171] Get the last virtual machine page hit rate and total hit count;

[0172] Determine the initial virtual machine page hit rate based on the current hit count and the total hit count;

[0173] The virtual machine page hit rate is determined based on the initial virtual machine page hit rate, the last virtual machine page hit rate, and the respective corresponding hit rate weight parameters.

[0174] Specifically, the virtual address information of the page information needs to be converted into physical address information. The hit count of the page information in the first memory is determined based on this physical address information and the physical address range of the first memory. In this embodiment, the VMM converts the guest physical address (GPA) of the virtual machine page address obtained by the PML or PBES into the host physical address (HPA). By comparing the HPA of the page with the physical address ranges of the fast and slow memories, the page's location is quickly determined. This determines that the physical address information is within the address range of the first memory (fast memory), which is considered a hit. Conventional hit count determination fails to account for the impact of historical hit rates on the current hit rate. In this embodiment, the conventional hit count is calculated as the sum of the total hit rate and the current hit rate divided by the total hit count. This requires summing all past hit rates, i.e., calculating all hit rates. Using an average value would average out historically high hit rates, thereby misleading the current hit count of the corresponding virtual machine page. Therefore, this embodiment will give weight to the current hit rate with a higher weight through exponential weighted average. After that, the last hit rate is calculated by (1- ) corresponding weight parameters, so that the current virtual machine page hit rate is obtained by summing the processing. The specific value of is not limited here, as long as it exceeds the weight parameter corresponding to the previous hit rate.

[0175] About the code implementation of hit:

[0176] / / Traverse backlog record rec<vm,op,page,ts> ;

[0177] foreach rec in backlog[vmpid]{

[0178] if(rec.op==READ)rCBF.inc(rec.page);

[0179] else wCBF.inc(rec.page);

[0180] total++;

[0181] / / If the HPA is in the fast memory address range, it is considered a hit;

[0182] if(HPA(rec.page) is FMEM)hits++;

[0183] backlog.del(rec);

[0184] }.

[0185] The formula is as follows:

[0186] hitratio= (hits / total)+(1- ) lastHitratio;

[0187] in, is the hit rate weight parameter, hits is the current number of hits, total is the total number of hits, is (hits / total) the initial virtual machine page hit rate, lastHitratio is the last virtual machine page hit rate, and hitratio is the virtual machine page hit rate.

[0188] The process for determining the virtual machine page hit rate provided in this embodiment adopts an exponentially weighted average statistical method, so that the data point of the most recent current hit rate has a higher weight, so as to pay more attention to the current hit rate. While taking into account the higher current hit rate, it also takes into account the impact of historical hit rates on the current one, thereby improving the accuracy of determining the virtual machine page hit rate.

[0189] In some embodiments, the process of determining page access frequency includes:

[0190] Get the page information of page read operation count, page write operation count and total access count;

[0191] Determine a weight parameter according to the read and write bandwidth corresponding to the first memory and the second memory;

[0192] Determine the read operation access frequency and the write operation access frequency according to the number of page read operations, the number of page write operations and the total number of accesses;

[0193] The page access frequency is determined based on the weight parameter, the read operation access frequency, and the write operation access frequency.

[0194] Specifically, read operation monitoring increments the page's read operation count each time a page is read. Write operation monitoring increments the page's write operation count each time a page is written. Counting access counts the number of read and write operations on each page within a specified period of time. Total access counts are the sum of the read and write operations for all pages.

[0195] The conventional page access frequency is the sum of the page read access frequency obtained by dividing the number of page read operations by the total number of accesses, and the page write access frequency obtained by dividing the number of page write operations by the total number of accesses. In the conventional access frequency process, taking into account the characteristics of the specific memory hierarchy, the read and write bandwidth of the fast memory device is defaulted to 2:3. Table 1 is a delay / bandwidth data table corresponding to the memory hierarchy. As shown in Table 1, the comparative values of the read and write delays and bandwidths corresponding to the fast memory and the slow memory, if the conventional page access frequency is followed, will result in fewer pages corresponding to the write operation occurring in the fast memory due to the distinction between the read and write bandwidths. Therefore, this embodiment performs difference correction in the read and write access of the page access frequency to achieve a balance between the read and write impacts of the fast memory and the slow memory.

[0196] Table 1 Latency / bandwidth data corresponding to memory hierarchy

[0197]

[0198] In the process of determining the page access frequency provided by this embodiment, the proportional weight parameters of the read and write bandwidths corresponding to different memory levels are taken into consideration to correct the read and write differences and achieve a balanced impact of different memory levels on read and write.

[0199] In some embodiments, determining corresponding weight parameters of the first memory and the second memory according to their corresponding read and write bandwidths includes:

[0200] Determine a first weight ratio according to the read bandwidth and the write bandwidth corresponding to the first memory;

[0201] Determine a second weight ratio according to the read bandwidth and write bandwidth corresponding to the second memory;

[0202] A weight parameter is determined based on the first weight ratio and the second weight ratio.

[0203] In combination with the above embodiment, the specific formula is as follows:

[0204] freq(Page)=R r_weight+W w_weight;

[0205] Wherein, freq(Page) is the page access frequency, R is the read operation access frequency, r_weight is the weight parameter corresponding to the read operation access frequency, W is the write operation access frequency, and w_weight is the weight parameter corresponding to the write operation access frequency.

[0206] As shown in Table 1, the read and write bandwidths of different memories determine their corresponding weight ratios. Specifically, the read and write bandwidths of the first memory determine the first weight ratio, while the read and write bandwidths of the second memory determine the second weight ratio. The weight ratios here may be decimals in actual calculations. For ease of calculation, they are rounded to integers, either by rounding or retaining the integer portion. This is not specified here.

[0207] Based on the first weight ratio and the second weight ratio, an addition and an average process are performed here to obtain a final weight ratio.

[0208] The weight ratios of different memory levels provided in this embodiment are different. Therefore, an addition and averaging method is adopted here to obtain the final weight ratio to improve the authority and fairness of determining the weight parameters.

[0209] In some embodiments, the aging process of the read access frequency and the write access frequency includes:

[0210] Traverse the pages corresponding to the read operation access frequency and the write operation access frequency, and take the union process to obtain the third page;

[0211] Obtain read operation count and write operation count according to the third page;

[0212] Performing aging operations on the read operation count and the write operation count to obtain updated read operation count and write operation count respectively; and using the updated read operation count and write operation count as the updated fourth page;

[0213] A read operation access frequency and a write operation access frequency are determined based on the fourth page to complete the aging process.

[0214] Specifically, aging the page read and write frequency counter is a technique used to simulate the least recently used page replacement algorithm. By periodically aging the page access frequency counter to reduce the counter value, the recent access of the page is more accurately reflected.

[0215] Traverse the pages corresponding to the read and write access frequencies and take the union to obtain the third page. This is to obtain all pages that may be read or written. The code is foreach page in rCBF∪wCBF. Obtain the read and write operation counts based on the third page. Perform an aging operation on the read and write operation counts to obtain the updated read and write operation counts. The specific operations are as follows:

[0216] Perform an aging operation on the read operation counter R: if R is not zero, reduce its value by half (R / 2) and reset the updated value into rCBF.

[0217] Perform an aging operation on the write operation counter W: if W is not zero, reduce its value by half (W / 2) and set the updated value back into wCBF.

[0218] The updated read operation count and write operation count are used as the updated fourth page; the read operation access frequency and the write operation access frequency are determined according to the fourth page, and the corresponding aging process is completed.

[0219] The specific code is as follows:

[0220] / / Use Bloom filter to store virtual machine page read and write frequencies. First, obtain VM-related rCBF and wCBF.

[0221] rCBF = getCBF(vmpid, READ);

[0222] wCBF=getCBF(vmpid,WRITE);

[0223] / / Age and halve all Page access record data in rCBF and wCBF;

[0224] foreach page in rCBF∪wCBF{

[0225] R=rCBF.get(Page), W=wCBF.get(Page);

[0226] / / Count aging is halved. If the count is zero, delete the page related count.

[0227] if(R)rCBF.set(page, R / 2);

[0228] if(W)wCBF.set(page,W / 2);

[0229] }.

[0230] This embodiment provides an aging process for read access frequency and write access frequency to ensure rapid identification of subsequent recent hot pages, better adapt to dynamically changing workloads, eliminate data that is no longer frequently accessed, free up storage space, and improve storage resource utilization.

[0231] In some embodiments, determining the target state machine level based on a relationship between the memory capacity of the target virtual machine allocated to the first memory, the virtual machine page hit rate, and the state level condition of the state machine includes:

[0232] Determining the stability of the current state machine level based on the rate of change of the virtual machine page hit rate;

[0233] The target state machine level is determined based on the relationship between the current state machine level, memory capacity, stability and the state machine's state level conditions.

[0234] Specifically, the virtual machine page hit rate is the proportion of virtual machine pages accessed during the statistical period that are located in the fast memory. Taking into account the change process of the page hit rate corresponding to the virtual machine level, the stability of the data parameter is determined based on the change rate of the data parameter, so that the operating status of the virtual machine can be monitored in real time. If the hit rate change rate is large, it may indicate that there are frequent page replacements in the system. Based on the analysis of the hit rate change rate, resources can be allocated more accurately. For example, for virtual machines with a low and stable hit rate change rate, their allocated resources can be appropriately reduced to release resources for other virtual machines in need. In this embodiment, the target state machine level is determined based on the relationship between the current state machine level, the memory capacity currently allocated to the fast memory by the virtual machine, the degree of stability, and the state level condition of the state machine.

[0235] It should be noted that the current state machine level in this embodiment is based on the state machine level currently in use during the virtual machine memory tiering adjustment process. The target state machine level is determined by determining the theoretical corresponding state machine level based on the memory capacity and stability of the fast memory already allocated to the virtual machine.

[0236] This embodiment provides a method for determining the target state machine level based on the relationship between the current state machine level, memory capacity, stability, and the state machine's state level conditions, facilitating subsequent changes to the state machine level at the virtual machine state machine level to improve the accuracy of subsequent page classification. In this embodiment, the target state machine level is determined based on two parameters: memory capacity and stability, improving the accuracy of the target state machine level determination, rationally allocating memory, and maintaining subsequent stable operation.

[0237] In some embodiments, the status level condition includes an upgraded status level condition, a stable status level condition, and a downgraded status level condition;

[0238] Among them, the upgrade status level conditions include a first upgrade status level condition and a second upgrade status level condition; the first upgrade status level condition is that the memory capacity is less than the upgrade waterline of the virtual machine memory; the second upgrade status level condition is that the memory capacity is greater than or equal to the upgrade waterline and less than the downgrade waterline of the virtual machine memory, and the stability is unstable; the stable status level condition is that the memory capacity is greater than or equal to the upgrade waterline and less than the downgrade waterline, and the stability is stable; the downgrade status level condition is that the memory capacity is greater than or equal to the downgrade waterline.

[0239] Specifically, the status level conditions include three level conditions, namely, an upgraded status level condition, a stable status level condition, and a downgraded status level condition.

[0240] Considering the two parameters of memory capacity and stability in the above embodiment, the upgrade state level condition includes two upgrade state level conditions: a first upgrade state level condition and a second upgrade state level condition. The first upgrade state level condition does not involve the corresponding stability level. That is, the first upgrade state level condition is that the memory capacity is less than the upgrade watermark of the virtual machine memory, while the second upgrade state level condition is that the memory capacity is greater than or equal to the upgrade watermark and less than the demotion watermark of the virtual machine memory, and the stability level is unstable. If any upgrade state level condition is met, the target state machine level is determined to be in the upgrade state.

[0241] The stable state level condition is that the memory capacity is greater than or equal to the upgrade waterline and less than the downgrade waterline, and the stability is stable; the degraded state level condition is that the memory capacity is greater than or equal to the downgrade waterline.

[0242] The promotion watermark (P) and demotion watermark (D) are two important concepts used in dynamic memory management in virtualized environments. They control the allocation and deallocation of virtual machine memory to optimize resource utilization and system performance. The memory degradation watermark refers to the system automatically reducing the memory allocated to a virtual machine when its memory usage falls below a preset threshold.

[0243] In this embodiment, the upgrade watermark and the downgrade watermark are used as part of the measurement of the target state machine level. The corresponding state level conditions are set at the level of the virtual machine state level to improve the accuracy of the state level determination.

[0244] In some embodiments, determining the target state machine level based on the relationship between the current state machine level, memory capacity, stability, and the state machine level condition includes:

[0245] When the current state machine level is in the upgrade state, if the memory capacity meets the first upgrade state level condition, the target state machine level is determined to be in the upgrade state; if the memory capacity does not meet the first upgrade state level condition, whether the second upgrade state level condition is met is determined based on the memory capacity and stability;

[0246] If the second upgrade state level condition is met, the target state machine level is determined to be the upgrade state; if the second upgrade state level condition is not met, whether the stable state level condition is met is determined based on the memory capacity and stability;

[0247] If the stable state level condition is met, the target state machine level is determined to be stable; if the stable state level condition is not met, whether the degraded state level condition is met is determined based on the memory capacity;

[0248] If the degraded state level condition is met, the target state machine level is determined to be a degraded state.

[0249] Specifically, when the current state machine level is in the upgraded state, it is necessary to determine whether to maintain the upgraded state or to reduce the level to a stable state by one level. The determination is made based on the various level conditions in the above-mentioned embodiment. Priority is given to determining whether the first upgraded state level condition is met. If so, the subsequent judgment process will not be performed. If not, the judgment is continued to determine whether the second upgraded state level condition is met. The judgment process here is based on the memory capacity and stability. If the second upgraded state level condition is met, it is determined to be an upgraded state. If the second upgraded state level condition is not met, the judgment is continued to determine whether the stable state level condition is met. If so, it is determined to be a stable state. If not, the judgment is continued to determine whether the downgraded state level condition is met. This process is repeated until the target state machine level is determined.

[0250] In this embodiment, when the current state machine level is in the upgrade state, the target state machine level is determined step by step, ensuring the gradual development of the judgment process to improve the accuracy of determining the target state machine level. At the same time, when judging the upgrade state level conditions, the flexibility of the judgment is improved by judging the two upgrade state level conditions.

[0251] In other embodiments, determining the target state machine level based on the relationship between the current state machine level, memory capacity, stability, and the state machine level condition includes:

[0252] When the current state machine level is in a degraded state, if the memory capacity meets the first upgrade state level condition, the target state machine level is determined to be in an upgraded state; if the memory capacity does not meet the first upgrade state level condition, then based on the memory capacity and stability, it is determined whether the second upgrade state level condition is met; if the second upgrade state level condition is met, then the target state machine level is determined to be in an upgraded state; if the second upgrade state level condition is not met, then based on the memory capacity and stability, it is determined whether the stable state level condition is met;

[0253] If the stable state level condition is met, the target state machine level is determined to be a stable state; if the stable state level condition is not met, the target state machine level is determined to be a degraded state.

[0254] Specifically, similar to the step-by-step determination method in the above embodiment, when the current state machine level is in a degraded state, the state level conditions of each state machine are determined through the determination process until the target state machine level is determined, which will not be elaborated here.

[0255] In other embodiments, determining the target state machine level based on the relationship between the current state machine level, memory capacity, stability, and the state machine level condition includes:

[0256] When the current state machine level is in a stable state, if the memory capacity meets the degraded state level condition, the target state machine level is determined to be in a degraded state; if the memory capacity does not meet the degraded state level condition, whether the first upgrade state level condition is met is determined based on the memory capacity;

[0257] If the first upgrade state level condition is met, the target state machine level is determined to be the upgrade state; if the first upgrade state level condition is not met, whether the second upgrade state level condition is met is determined based on the memory capacity and stability;

[0258] If the second upgrade state level condition is met, the target state machine level is determined to be the upgrade state; if the second upgrade state level condition is not met, the target state machine level is determined to be the stable state.

[0259] Specifically, the step-by-step judgment process in the above embodiment is the same as the step-by-step judgment process in this embodiment. It should be noted that the judgment order here is different from the judgment order in the above embodiment. First, it is judged whether the downgraded state level conditions are met, then it is judged whether the upgraded state level conditions are met, and finally it is judged whether the stable state level conditions are met.

[0260] This embodiment corresponds to the determination process of the target state machine level when the current state machine level is the stable state machine level, ensuring the gradual development of the determination process to improve the accuracy of determining the target state machine level. At the same time, when determining the conditions corresponding to the upgraded state level, the flexibility of the determination is improved through the determination of two upgraded state level conditions.

[0261] In some embodiments, determining a page migration strategy for a target virtual machine based on a current state machine level and a target state machine level includes:

[0262] Obtaining the current state machine level of the target virtual machine, wherein the state machine level is set to an upgraded state when the state machine level is first determined;

[0263] If the current state machine level is in the upgraded state and the target state machine level is in the upgraded state, the upgraded state is maintained and no page migration is performed; if the target state machine level is in the stable state, the state is changed to the stable state and no page migration is performed; if the target state machine level is in the degraded state, the target page of the target virtual machine is migrated from the first memory to the second memory;

[0264] If the current state machine level is in a degraded state and the target state machine level is in an upgraded state, the target page of the target virtual machine is migrated from the second memory to the first memory; if the target state machine level is in a stable state, the state is changed to a stable state without performing page migration; if the target state machine level is in a degraded state, the degraded state is maintained without performing page migration;

[0265] If the current state machine level is stable and the target state machine level is degraded, the target page of the target virtual machine is migrated from the first memory to the second memory; if the target state machine level is degraded, the target page of the target virtual machine is migrated from the second memory to the first memory; if the target state machine is in a level state, the stable state is maintained and no page migration is performed.

[0266] Specifically, Figure 3 A state machine transition diagram of a virtual machine upgrade and downgrade provided by an embodiment of the present invention, such as Figure 3 As shown, when the current state machine level is in the upgraded state and the target state machine level is in the upgraded state, the state remains unchanged and no page migration is performed. When the target state machine level is in the stable state, the state is changed, but no page migration is performed. Only when the target state machine level is in the degraded state, the target page of the target virtual machine needs to be migrated to the secondary memory.

[0267] Similarly, if one of the current state machine level and the target state machine level is in a degraded state and the other is in an upgraded state, the corresponding page migration is required. If one of them is in a stable state, a state change is required, but no page migration is performed.

[0268] Table 2 is the state transition matrix table. As shown in Table 2, the source state is the current state machine level, and the target state is the target state machine level.

[0269] Table 2 State Transition Matrix Table

[0270]

[0271] After the virtual machine is started, it enters the "upgrade" state. If the condition "(UF < P) OR (P <= UF < D AND H is unstable)" is satisfied, it remains in the "upgrade" state; if the condition "P <= UF < D AND H is stable" is satisfied, it enters the "stable" state; if the condition "UF >= D" is satisfied, it enters the "downgrade" state.

[0272] After the virtual machine enters the "downgrade" state, if the condition "(UF < P) OR (P <= UF < D AND H is unstable)" is satisfied, it enters the "upgrade" state; if the condition "P <= UF < D AND H is stable" is satisfied, it enters the "stable state", otherwise it remains in the "downgrade" state.

[0273] After the virtual machine enters the "stable" state, if the condition "UF >= D" is satisfied, it enters the "downgrade" state; if the condition "UF < P OR (P <= UF < D AND H is unstable)" is satisfied, it enters the upgrade state, otherwise it remains in the "stable" state.

[0274] This state machine has three states: "upgrade", "downgrade", and "stable". The upgrade state performs the operation of migrating the virtual machine memory from slow memory to fast memory, the downgrade state is the opposite, and the stable state does not perform any operation.

[0275] The page migration strategy of the target virtual machine determined according to the current state machine level and the target state machine level provided in this embodiment. While multiple custom thresholds (upgrade waterline, downgrade waterline, global frequency threshold) meet the personalized needs in the production environment, the page migration strategy at the state machine level of the virtual machine improves flexibility.

[0276] In some embodiments, the target page of the target virtual machine is migrated and processed according to the page migration strategy and page access frequency in the memory hierarchy to complete page storage, including:

[0277] Obtain the threshold page access frequency;

[0278] When migrating from the second memory to the first memory, obtain the page access frequencies of multiple pages in the second memory based on the array information corresponding to the Bloom filter;

[0279] [[ID=3�]]Filter the target page access frequencies greater than the threshold page access frequency among the multiple page access frequencies;

[0280] A page corresponding to the target page access frequency is used as the target page to be migrated to the first memory.

[0281] Specifically, the page migration strategy corresponds to the change in memory hierarchy, migrating from the second memory to the first memory, and migrating from the first memory to the second memory. In this embodiment, taking into account the upgrade status, it is necessary to batch migrate pages located in the slow memory and greater than the system-level page access frequency threshold T to the fast memory. Obtaining the threshold page access frequency, obtaining multiple page access frequencies of the second memory based on the array information corresponding to the Bloom filter, corresponds to hot page errors stored in the second memory, and the hot pages need to be migrated to the first memory. Therefore, the present invention needs to obtain multiple page access frequencies of the second memory based on the array information corresponding to the Bloom filter to screen the target page access frequency greater than the threshold page access frequency, and migrate its corresponding target page.

[0282] The Bloom filter in this embodiment may be a traditional Bloom filter, or may be improved with respect to a Bloom filter array. In short, the page access frequency is obtained through array information of the Bloom filter.

[0283] The specific access process is as follows:

[0284] FUNC:PromotingAction;

[0285] INPUT: vmpid / / The virtual machine process ID in the upgrade state;

[0286] rCBF = getCBF(vmpid, READ);

[0287] wCBF=getCBF(vmpid,WRITE);

[0288] foreach page in rCBF∪wCBF{

[0289] if(HPA(page)is SMEM && freq(page)>T){

[0290] if(FMEM_USED<90%)Promote2FMEM(page); / / Migrate page to fast memory;

[0291] else T=freq(Page) 2;

[0292] }

[0293] }.

[0294] The frequency-based hot page upgrade method provided in this embodiment accurately identifies virtual machine hot pages in the Bloom filter and maps the elements into a bit array, saving storage space. In addition, the Bloom filter quickly obtains page access frequency, enabling rapid response to query requests.

[0295] In some embodiments, obtaining a plurality of page access frequencies of the second memory based on array information corresponding to the Bloom filter includes:

[0296] Performing mapping processing on the current page using a first hash function to determine a tag value of the index data block;

[0297] Determine the address information of the index data block according to the tag value;

[0298] Obtain K second hash functions;

[0299] Processing the data blocks of the address information using K second hash functions to determine their corresponding values;

[0300] If multiple values and the current page are stored in the index data block, it is convenient to obtain the page access frequency.

[0301] Specifically, traditional Bloom filters use multiple hash functions to map elements to a bit array, using a counter array to record the count of each bit. This embodiment introduces an additional hash function (a first hash function) to map elements to the index position of a data block, improving the locality of data storage in Bloom filters.

[0302] The current page is mapped using the first hash function to determine the tag value of the index data block. The tag value here is the block number corresponding to the data block, that is, block_idx = hash(Page) % block_num. The address information of the index data block is determined based on the tag value, that is, block_addr = block_idx CACHE_LINE_SIZE. Obtain K second hash functions, and use K second hash functions to process the data block of the address information to determine the corresponding value as the offset. Storing multiple values and the current page in the index data block is to aggregate multiple offsets into one data block, ensuring that multiple hash-key data related to this page can be placed in one CACHE_LINE, thereby improving the efficiency of Bloom filter queries. Regarding the cache line size, the CBT is divided into blocks based on the cache line size, so that the hash counters of the same page fall into one cache line, improving insertion and query performance.

[0303] This embodiment provides a process for obtaining page access frequencies through a Bloom engine. By indexing data blocks, data blocks can be quickly located, improving data access efficiency. This ensures that multiple hash key data related to a page can fit into a single cache line, reducing cache miss rates and enabling fast queries.

[0304] In some embodiments, before migrating the target page from the second memory to the first memory, the method further includes:

[0305] determining a current space utilization of the first memory;

[0306] If the current space utilization is greater than the first preset space utilization, the threshold page access frequency is increased, and the process returns to the step of screening a target page access frequency greater than the threshold page access frequency from multiple page access frequencies to redetermine a new target page for migration.

[0307] Specifically, before performing the migration, it is necessary to check the current space utilization of the first memory. If the current space utilization is greater than the first preset space utilization, it means that the remaining space utilization is small, and it is difficult to ensure that all target pages can be migrated to the first memory. Therefore, it is necessary to adjust the threshold page access frequency. The adjustment process here is to increase the threshold page access frequency to achieve an upward adjustment and re-determine the target page for subsequent migration processing. The adjustment in this embodiment can be adjusted step by step or based on a fixed value. There is no limitation here and it can be set according to actual conditions.

[0308] The second memory provided in this embodiment ensures that the remaining space of the first memory can accommodate the target page as much as possible before migrating the second memory to the first memory, so as to ensure the integrity of the migration.

[0309] In some embodiments, migrating a target page of a target virtual machine according to a page migration policy and a page access frequency in a memory hierarchy to complete page storage includes:

[0310] Get the threshold page access frequency;

[0311] When migrating from the first memory to the second memory, scanning the physical address information of the first memory through a linear scanning mechanism;

[0312] Comparing a page access frequency corresponding to the physical address information of the first memory with a threshold page access frequency;

[0313] If the page access frequency is less than the threshold page access frequency, a page corresponding to a target page access frequency less than the threshold page access frequency is used as a target page to be migrated to the second memory.

[0314] Specifically, for a virtual machine in a "degraded" state, the cold pages located in the fast memory are efficiently identified by linearly scanning the virtual machine's memory address space and combining the page access frequency. If the page access frequency is less than the system-level page access frequency threshold T (including the case where the CBT does not contain the page record), the page downgrade migration is performed.

[0315] Considering that the storage of cold pages is not in the Bloom filter and is incorrectly stored in the first memory, it is necessary to linearly scan the virtual machine memory address space to determine the physical address information of the first memory, compare the page access frequency corresponding to the physical address information of the first memory with the threshold page access frequency, and screen out the target page corresponding to the target page access frequency less than the threshold page access frequency, and migrate it to the second memory.

[0316] It should be noted that when a virtual machine is in a degraded state, the least-accessed pages in the virtual machine are migrated to slow memory. Since the least-accessed pages do not appear in the Bloom filter, the virtual machine address space is scanned to obtain the less frequently accessed pages. When scanning the virtual machine memory address space, the last linear scan end address is recorded and batch scans are started to improve linear address scanning efficiency. The last linear scan end address is defined as lastPageAddress.

[0317] The reading process is as follows:

[0318] FUN:DemotingAction;

[0319] INPUT: lastPageAddress, batchSize / / The address at the end of the last scan, batch operation limit;

[0320] OUTPUT:lastPageAddressOut;

[0321] curPageAddress=lastPageAddress;

[0322] pagesDemoted=0;

[0323] while (pagesDemoted <batchSize){

[0324] page=getPage(curPageAddress);

[0325] if(HPA(page) is FMEM&&freq(page) <T){

[0326] Demote2SMEM(page);

[0327] pagesDemoted++;

[0328] }

[0329] curPageAddress=next address in virtual address space;

[0330] / / Exit after scanning the entire linear address space;

[0331] if(curPageAddress==lastPageAddress)

[0332] break;

[0333] }

[0334] if(pagesDemoted==0&&FMEM_USED<50%)T=T / 2;

[0335] lastPageAddress=curPageAddress.

[0336] The cold page demotion method based on linear address space scanning provided in this embodiment accurately identifies cold pages while reducing resource usage caused by scanning.

[0337] In some embodiments, before migrating the target page from the first memory to the second memory, the method further includes:

[0338] determining a current space utilization of the second memory;

[0339] If the current space utilization is less than the second preset space utilization, reduce the threshold page access frequency, and return to the step of comparing the page access frequency corresponding to the physical address information of the first memory with the threshold page access frequency to re-determine a new target page for migration processing.

[0340] Specifically, in combination with the above-mentioned embodiment corresponding to the migration from the second memory to the first memory, the idea of this embodiment is the same. Before the migration, it is necessary to check the current space utilization of the second memory. If the current space utilization is less than the first preset space utilization, it means that the remaining space utilization is small, and it is difficult to ensure that all target pages can be migrated to the second memory. Therefore, it is necessary to adjust the threshold page access frequency. The adjustment process here is to reduce the threshold page access frequency to achieve a downward adjustment and re-determine the target page for subsequent migration processing. The adjustment in this embodiment can be adjusted step by step or based on a fixed value. It is not limited here and can be set according to actual conditions.

[0341] This embodiment ensures that the remaining space of the second memory can accommodate the target page as much as possible before migrating the first memory to the second memory, so as to ensure the integrity of the migration.

[0342] Furthermore, the present invention also provides a virtual machine system, comprising at least one virtual machine, wherein the memory of the at least one virtual machine comprises at least one page; hierarchical storage of the at least one page is completed by the steps of the above-mentioned page storage method.

[0343] Figure 4 A schematic diagram of a virtualization layered system provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown in the figure, it mainly includes three modules: ① page tracking, ② page classification, and ③ page migration. The page tracking module is used to capture the memory access information required for hierarchical management, efficiently discover the target pages read and written by the virtual machine, and count information such as access frequency and hit rate. Low loss and low overhead are the key to page tracking, which is higher than the requirement for statistical information accuracy. The page classification module distinguishes pages based on access patterns to determine which pages should be placed in fast memory. The activity level of pages may change over time, so the storage location of pages needs to be dynamically adjusted to effectively utilize the advantages of fast memory and slow memory. The page migration module is the executor of the page placement strategy and is implemented through the operating system kernel.

[0344] During page tracking, PML log information is recorded. A full log triggers VMEXT, which is then read to trigger VMEXT. Log preprocessing and backup in step 3 are then performed to the log information and Bloom filter arrays. Throughout the page tracking process, page access frequency and VM memory hit rate are calculated. After scanning VM memory during page classification, subsequent migration decisions are made within the hierarchical system, ensuring actual page migration.

[0345] For an introduction to a virtual machine system provided by the present invention, please refer to the above method embodiment. The present invention will not be repeated here. It has the same beneficial effects as the above page storage method. The above detailed description of the various embodiments corresponding to the page storage method, on this basis, the present invention also discloses a page storage device corresponding to the above method, Figure 5 This is a structural diagram of a page storage device provided by an embodiment of the present invention. Figure 5 As shown, the page storage device includes:

[0346] An acquisition module 11 is configured to acquire page information corresponding to read and write operations of a virtual machine memory based on a hardware mechanism; and determine a page hit rate and a page access frequency of the virtual machine based on the page information;

[0347] a determination module 12 for determining a target state machine level based on a relationship between the memory capacity of the target virtual machine allocated to the first memory, the page hit rate of the virtual machine, and a state level condition of the state machine; and determining a page migration strategy for the target virtual machine based on the current state machine level and the target state machine level;

[0348] The migration module 13 is used to migrate the target page of the target virtual machine in the memory hierarchy according to the page migration strategy and the page access frequency to complete page storage; wherein, the memory hierarchy includes a first memory and a second memory; the storage rate of the first memory is greater than the storage rate of the second memory.

[0349] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part please refer to the description of the embodiments of the method part, and will not be repeated here.

[0350] For an introduction to a page storage device provided by the present invention, please refer to the above method embodiment, and the present invention will not be described in detail here. It has the same beneficial effects as the above page storage method. Figure 6 A structural diagram of a page storage device provided by an embodiment of the present invention, such as Figure 6 As shown, the device includes:

[0351] Memory 21, for storing computer programs;

[0352] The processor 22 is configured to implement the steps of the page storage method when executing a computer program.

[0353] The processor 22 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 22 may be implemented in at least one of the following hardware forms: a digital signal processor (DSP), a field-programmable gate array (FPGA), or a programmable logic array. The processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 22 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (AI) processor, which is responsible for processing computing operations related to machine learning.

[0354] The memory 21 may include one or more non-volatile storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, it can implement the relevant steps of the page storage method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include but is not limited to data involved in the page storage method, etc.

[0355] In some embodiments, the page storage device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0356] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation to the page storage device, and may include more or fewer components than shown in the figure.

[0357] The processor 22 implements the page storage method provided by any of the above embodiments by calling the instructions stored in the memory 21 .

[0358] For an introduction to the page storage device provided by the present invention, please refer to the above-mentioned method embodiment. The present invention will not be repeated here. The device has the same beneficial effects as the above-mentioned page storage method. Furthermore, the present invention also provides a non-volatile storage medium having a computer program stored thereon. When the computer program is executed by the processor 22, the steps of the above-mentioned page storage method are implemented.

[0359] It is understandable that if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0360] For an introduction to a non-volatile storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be described in detail here. It has the same beneficial effects as the above page storage method.

[0361] Furthermore, the present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of the page storage method when executed by a processor.

[0362] For an introduction to a computer program product provided by the present invention, please refer to the above method embodiment, and the present invention will not be described in detail here. It has the same beneficial effects as the above page storage method.

[0363] The above is a detailed introduction to a page storage method, virtual machine system, device, medium and product provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0364] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A page storage method, characterized in that: include: Obtain page information corresponding to read and write operations of virtual machine memory based on hardware mechanisms; and determining a page hit rate and a page access frequency of the virtual machine based on the page information; Determining a target state machine level based on a relationship between a memory capacity of the target virtual machine allocated to the first memory, a page hit rate of the virtual machine, and a state level condition of the state machine; The page migration strategy of the target virtual machine is determined based on the current state machine level and the target state machine level. The state machine of the virtual machine is a mechanism for managing the life cycle and state transition of the virtual machine. The state machine defines the different states of the virtual machine and the transition rules between the states, including upgrade, downgrade and stable states. Performing migration processing on the target page of the target virtual machine in a memory hierarchy according to the page migration policy and the page access frequency to complete page storage; wherein the memory hierarchy includes a first memory and a second memory; the storage rate of the first memory is greater than the storage rate of the second memory; The target state machine level is determined based on the relationship between the memory capacity of the target virtual machine allocated to the first memory, the page hit rate of the virtual machine, and the state level condition of the state machine, including: Determining the stability of the current state machine level based on the rate of change of the virtual machine page hit rate; Determining the target state machine level according to a relationship between the current state machine level, the memory capacity, the stability level, and a state machine state level condition; Correspondingly, the state level conditions include an upgrade state level condition, a stable state level condition, and a downgrade state level condition; Among them, the upgrade status level condition includes a first upgrade status level condition and a second upgrade status level condition; the first upgrade status level condition is that the memory capacity is less than the upgrade waterline of the virtual machine memory; the second upgrade status level condition is that the memory capacity is greater than or equal to the upgrade waterline, and less than the demotion waterline of the virtual machine memory, and the stability level is unstable; the stable status level condition is that the memory capacity is greater than or equal to the upgrade waterline, and less than the demotion waterline, and the stability level is stable; the demotion status level condition is that the memory capacity is greater than or equal to the demotion waterline.

2. The page storage method according to claim 1, characterized in that: Obtains page information corresponding to read and write operations of virtual machine memory based on hardware mechanisms, including: Obtaining first page information corresponding to a virtual machine memory write operation based on a page modification log mechanism; Acquire second page information corresponding to the virtual machine memory read operation based on an event precise sampling mechanism; The first page information and the second page information are used as the page information.

3. The page storage method according to claim 1, wherein: Determining the target state machine level according to a relationship between the current state machine level, the memory capacity, the stability level, and a state machine state level condition includes: When the current state machine level is in the upgrade state, if the memory capacity meets the first upgrade state level condition, determining that the target state machine level is in the upgrade state; if the memory capacity does not meet the first upgrade state level condition, determining whether a second upgrade state level condition is met based on the memory capacity and the stability; If the second upgrade state level condition is met, determining the target state machine level to be the upgrade state; if the second upgrade state level condition is not met, determining whether the stable state level condition is met based on the memory capacity and the stability; If the stable state level condition is met, the target state machine level is determined to be stable; if the stable state level condition is not met, whether the degraded state level condition is met is determined based on the memory capacity; If the degraded state level condition is met, the target state machine level is determined to be in a degraded state.

4. The page storage method according to claim 1, wherein: Determining the target state machine level according to a relationship between the current state machine level, the memory capacity, the stability level, and a state machine state level condition includes: When the current state machine level is in a stable state, if the memory capacity satisfies the degraded state level condition, determining that the target state machine level is in a degraded state; if the memory capacity does not satisfy the degraded state level condition, determining whether the first upgraded state level condition is satisfied based on the memory capacity; If the first upgrade state level condition is met, determining the target state machine level to be the upgrade state; if the first upgrade state level condition is not met, determining whether the second upgrade state level condition is met based on the memory capacity and the stability; If the second upgrade state level condition is met, the target state machine level is determined to be the upgrade state; if the second upgrade state level condition is not met, the target state machine level is determined to be the stable state.

5. The page storage method according to any one of claims 1 to 4, characterized in that: Performing migration processing on the target page of the target virtual machine in the memory hierarchy according to the page migration policy and the page access frequency to complete page storage includes: Get the threshold page access frequency; When migrating from the second memory to the first memory, obtaining access frequencies of multiple pages of the second memory based on array information corresponding to the Bloom filter; Screening a target page access frequency greater than the threshold page access frequency from a plurality of page access frequencies; A page corresponding to the target page access frequency is used as a target page to be migrated to the first memory.

6. The page storage method according to claim 5, characterized in that: Acquiring multiple page access frequencies of the second memory based on array information corresponding to the Bloom filter includes: Performing mapping processing on the current page using a first hash function to determine a tag value of the index data block; Determine the address information of the corresponding index data block according to the tag value; Obtain K second hash functions; Processing the data blocks of the address information using K second hash functions to determine their corresponding values; If multiple values and the current page are stored in the index data block, it is convenient to obtain the page access frequency.

7. The page storage method according to any one of claims 1 to 4, characterized in that: Performing migration processing on the target page of the target virtual machine in the memory hierarchy according to the page migration policy and the page access frequency to complete page storage includes: Get the threshold page access frequency; When migrating from the first memory to the second memory, scanning the physical address information of the first memory by a linear scanning mechanism; Comparing the page access frequency corresponding to the physical address information of the first memory with the threshold page access frequency; If the page access frequency is less than the threshold page access frequency, a page corresponding to a target page access frequency less than the threshold page access frequency is used as a target page to be migrated to the second memory.

8. The page storage method according to claim 1, wherein: The process of determining the virtual machine page hit rate includes: Converting the virtual address information of the page information into physical address information; Obtaining a physical address range corresponding to the first memory; Determining a current hit count corresponding to the page information in the first memory according to the physical address information and a physical address range of the first memory; Get the last virtual machine page hit rate and total hit count; Determining an initial virtual machine page hit rate according to the current hit count and the total hit count; The virtual machine page hit rate is determined based on the initial virtual machine page hit rate, the last virtual machine page hit rate, and respective corresponding hit rate weight parameters.

9. The page storage method according to claim 1, characterized in that: The process of determining the page access frequency includes: Obtain the page read operation count, page write operation count, and total access count of the page information; Determine a weight parameter according to the read and write bandwidths corresponding to the first memory and the second memory; Determine a read operation access frequency and a write operation access frequency according to the number of page read operations, the number of page write operations, and the total number of accesses; The page access frequency is determined based on the weight parameter, the read operation access frequency, and the write operation access frequency.

10. The page storage method according to claim 3 or 4, characterized in that: Determining a page migration strategy of the target virtual machine according to the current state machine level and the target state machine level includes: Obtaining a current state machine level of the target virtual machine, wherein the state machine level is set to an upgraded state when the state machine level is determined for the first time; If the current state machine level is in the upgraded state and the target state machine level is in the upgraded state, the upgraded state is maintained without page migration; if the target state machine level is in the stable state, the state is changed to the stable state without page migration; if the target state machine level is in the degraded state, the target page of the target virtual machine is migrated from the first memory to the second memory; If the current state machine level is in a degraded state and the target state machine level is in an upgraded state, the target page of the target virtual machine is migrated from the second memory to the first memory; if the target state machine level is in a stable state, the target state is changed to a stable state without performing page migration; if the target state machine level is in a degraded state, the degraded state is maintained without performing page migration; If the current state machine level is in a stable state and the target state machine level is in a degraded state, the target page of the target virtual machine is migrated from the first memory to the second memory; if the target state machine level is in an upgraded state, the target page of the target virtual machine is migrated from the second memory to the first memory; if the target state machine level is in a stable state, the stable state is maintained and no page migration is performed.

11. The page storage method according to claim 2, characterized in that: Obtaining the first page information corresponding to the virtual machine memory write operation based on the page modification log mechanism includes: Call the first process; Obtaining a virtual machine file descriptor by calling a first function through the first process; Sending a call instruction through a virtual machine file descriptor to set a dirty page tracking flag for the virtual machine memory to enable a dirty page tracking function for the memory of the virtual machine; Dirty page log information is acquired according to a first preset period, and the dirty page log information is used as the first page information.

12. The page storage method according to claim 2, characterized in that: Acquiring second page information corresponding to the virtual machine memory read operation based on an event precise sampling mechanism includes: Call the second process; Configuring and starting memory read event tracing corresponding to the second process; Create a shared ring buffer to store event data; A second function is called to start a tracing function, so as to obtain event data of the shared ring buffer according to a second preset period as the second page information.

13. The page storage method according to claim 9, characterized in that: The aging process for read access frequency and write access frequency includes: Traversing pages corresponding to the read operation access frequency and the write operation access frequency, and performing a union process to obtain a third page; Acquire a read operation count and a write operation count according to the third page; Performing aging operations on the read operation count and the write operation count to obtain updated read operation count and write operation count respectively; and using the updated read operation count and write operation count as the updated fourth page; The read operation access frequency and the write operation access frequency are determined based on the fourth page to complete an aging process.

14. The page storage method according to claim 5, characterized in that: Before migrating the target page from the second memory to the first memory, the method further includes: Determining a current space utilization of the first memory; If the current space utilization is greater than the first preset space utilization, the threshold page access frequency is increased, and the process returns to the step of screening a target page access frequency greater than the threshold page access frequency from multiple page access frequencies to redetermine a new target page for migration processing.

15. A virtual machine system, characterized in that: It includes at least one virtual machine, and the memory of at least one virtual machine includes at least one page; the hierarchical storage of at least one page is completed by the steps of the page storage method according to any one of claims 1 to 14 above.

16. A page storage device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the page storage method according to any one of claims 1 to 14 when executing the computer program.

17. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the page storage method according to any one of claims 1 to 14 are implemented.

18. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the page storage method according to any one of claims 1 to 14 are implemented.

Images