Instruction processing method and device, processor, electronic equipment and storage medium

Abstract

The invention provides an instruction processing method and device, a processor, electronic equipment and a storage medium. The method is applied to computer technology. When the processor obtains the first execution result, if the first execution result is the execution result of the first instruction with the earliest receiving time in the cache region, the first execution result is sent to the first processor; if not, the first execution result is stored in the cache region, and the first execution result is sent to the first processor after all the execution results of the second instruction with the earlier receiving time are sent to the first processor; the receiving time of the second instruction is before the instruction matched with the first execution result. Therefore, the execution result of the received instruction can be firstly sent to the first processor, and the execution result of the received instruction is then sent to the first processor, so that order-preserving transmission of the execution result of the instruction is realized, and adverse effects on normal execution of a current task are avoided.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to an instruction processing method, apparatus, processor, electronic device, and storage medium. Background Art

[0002] In the prior art, a processor usually processes each obtained instruction in a pipeline manner; a typical pipeline usually includes three stages: fetching an instruction, analyzing the instruction, and executing the instruction. If the processing cycle of each instruction is the same, then, by using the pipeline processing method, the instruction fetched first is executed first, and the execution result of this instruction is also returned first.

[0003] However, for some tasks constructed by complex algorithms, there may be multiple instructions, and the processing cycles of these multiple instructions may not be exactly the same. In this case, it may occur that an instruction fetched later is executed first and its execution result is returned first. This out-of-order transmission phenomenon of the execution results of instructions will have an adverse impact on the normal execution of the task. Summary of the Invention

[0004] This application provides an instruction processing method, apparatus, processor, electronic device, and storage medium, and this method can achieve in-order transmission of the execution results of instructions, avoiding adverse effects on the normal execution of the current task.

[0005] In a first aspect, this application provides an instruction processing method, including: when obtaining a first execution result during the process of executing an instruction stored in an execution cache area, determining whether the first execution result is the execution result of a first instruction; where the instruction stored in the cache area is sent by a first processor, the first instruction is the instruction with the earliest reception time in the cache area; all instructions in the cache area are instructions whose execution results have not been sent to the first processor; if so, sending the first execution result to the first processor; if not, storing the first execution result in the cache area; after all execution results of all second instructions are obtained and sent to the first processor, sending the first execution result to the first processor; where the reception time of the second instruction is before the reception time of the instruction matching the first execution result.

[0006] In some embodiments, determining whether the first execution result is the execution result of the first instruction includes: determining whether a second identifier carried by the first execution result is the same as a first identifier of the first instruction; if the same, the first execution result is the execution result of the first instruction; if different, the first execution result is not the execution result of the first instruction.

[0007] In some embodiments, the cache area includes a plurality of cache sub-areas, with one cache sub-area corresponding to one instruction; the instructions sent by the first processor are sequentially stored in consecutive cache sub-areas in the order of reception time; the head pointer of the cache area points to the first non-idle cache sub-area in the consecutive cache sub-areas; the tail pointer of the cache area points to the first idle cache sub-area after the consecutive cache sub-areas.

[0008] In some embodiments, determining whether the second identifier and the first identifier of the first instruction are the same includes: determining that the identifier stored in the cache sub-area pointed to by the head pointer is the first identifier of the first instruction; wherein, the first identifier stored in the cache sub-area pointed to by the head pointer matches the first instruction; and determining whether the first identifier of the first instruction is the same as the second identifier.

[0009] In some embodiments, after sending the first execution result to the first processor, the method further includes: setting the content in the cache sub-area corresponding to the first instruction to an invalid state; and updating the first non-idle cache sub-area pointed to by the head pointer.

[0010] In some embodiments, the method further includes: storing the instruction to be stored in the cache sub-area pointed to by the tail pointer; and updating the first idle cache sub-area pointed to by the tail pointer.

[0011] In some embodiments, executing the instructions stored in the cache area includes: sequentially executing the instructions stored in the cache area in the order from earliest to latest reception time; or sequentially executing the instructions stored in the cache area in a random order.

[0012] In some embodiments, the method further includes: receiving the instruction sent by the first processor; parsing the instruction to determine whether an execution result needs to be returned to the first processor; and when it is determined that an execution result needs to be returned to the first processor, storing the instruction in the cache area.

[0013] In some embodiments, for each of the instructions, the cache area is further configured to store second information of the instruction; wherein, the second information of the instruction includes: the first state, the second state, and the third state of the instruction; wherein, the first state is used to indicate whether the instruction has been executed, the second state is used to indicate whether the execution result of the instruction has been obtained, and the third state is used to indicate whether the execution result of the instruction has been sent to the first processor; wherein, the second information of the instruction is used to monitor the processing status of the instruction.

[0014] In a second aspect, the present application provides an instruction processing device, including: a module for executing the method described in the first aspect.

[0015] In a third aspect, the present application provides a processor configured to execute the method described in the first aspect.

[0016] In a fourth aspect, the present application provides an electronic device including a memory and the processor of the third aspect; wherein, the memory is configured to store computer program instructions; the processor is configured to run the computer program instructions such that the electronic device implements the method described in the first aspect.

[0017] In a fifth aspect, the present application provides a computer-readable storage medium including computer program instructions, and when an electronic device runs the computer program instructions, the electronic device implements the method described in the first aspect.

[0018] In a sixth aspect, an embodiment of the present application provides a chip including an interface circuit and a logic circuit. The interface circuit is configured to receive a signal from another chip outside the chip and transmit it to the logic circuit, or send a signal from the logic circuit to another chip outside the chip. The logic circuit is configured to implement the method described in the first aspect of the present application.

[0019] In a seventh aspect, the present application provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the steps in the method provided in the first aspect.

[0020] The present application provides an instruction processing method, apparatus, processor, electronic device, and storage medium. When obtaining a first execution result, if the first execution result is the execution result of the first instruction with the earliest reception time in the cache area, the first execution result is sent to the first processor; if not, the first execution result is stored in the cache area, and after all the execution results of the second instruction with an earlier reception time are sent to the first processor, the first execution result is sent to the first processor; the reception time of the second instruction is before the instruction matching the first execution result. In this way, it can be ensured that the execution results of the instructions received first are sent to the first processor first, and the execution results of the instructions received later are sent to the first processor later, realizing the in-order transmission of the execution results of the instructions and avoiding adverse effects on the normal execution of the current task. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of data transmission provided by an embodiment of the present application;

[0022] Figure 2 It is a flowchart of the implementation of the instruction processing method provided by an embodiment of the present application;

[0023] Figure 3 It is a schematic diagram of the structure of the second processor provided by an embodiment of the present application;

[0024] Figure 4 This is a flowchart for implementing the instruction processing method provided by the embodiments of the present application;

[0025] Figure 5 This is a flowchart for implementing the instruction processing method provided by the embodiments of the present application;

[0026] Figure 6 This is a flowchart for implementing the instruction processing method provided by the embodiments of the present application;

[0027] Figure 7 This is a flowchart for implementing the instruction processing method provided by the embodiments of the present application;

[0028] Figure 8 This is a flowchart for implementing the instruction processing method provided by the embodiments of the present application;

[0029] Figure 9 This is a structural diagram of the instruction processing apparatus provided by the embodiments of the present application;

[0030] Figure 10 This is a structural diagram of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0031] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, or B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a alone, b alone, or c alone may represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c may be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0032] The orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application.

[0033] The terms "connected" and "linked" should be understood in a broad sense. For example, the "connection" or "linkage" of a circuit structure can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected. It can also be the connection inside two components; a signal connection can be made not only through a circuit for signal connection but also through a media medium for signal connection, such as radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] A coprocessor is a processor extended for the main processor to assist the main processor in completing tasks according to different application scenarios and requirements.

[0035] The coprocessor interacts with the Central Processing Unit (CPU) based on the coprocessor interface. The coprocessor can be, but is not limited to, a Rocket coprocessor (Rocket Chip Coprocessor, ROCC). The ROCC interacts with the main processor through the ROCC interface.

[0036] Figure 1 A schematic diagram showing the principle of data or instruction transmission between the CPU and the coprocessor through the ROCC interface is shown; among them, the CPU can also be described as the main processor. As Figure 1 shown, both data and signaling transmissions between the two follow the valid / ready protocol. Ready and valid are two signal lines; the main processor sends a high-level signal to the coprocessor through the valid line, indicating that the main processor has prepared valid data to be sent; the coprocessor sends a high-level signal to the main processor through the ready line, indicating that the coprocessor is ready to receive the data sent by the main processor; after the above signal interaction between the main processor and the coprocessor, data transmission can be carried out between the main processor and the coprocessor.

[0037] In the prior art, the processing cycle of instructions in the coprocessor is usually fixed and the same, which is convenient for achieving in-order execution; that is, the coprocessor will preferentially execute instructions received earlier and return the execution results to the main processor. However, for tasks constructed by complex algorithms, the number of instructions is large and the processing cycles of the instructions may be different. In this case, for instructions received later with shorter processing cycles, the coprocessor may return the execution results earlier; while for instructions received earlier with longer processing cycles, the coprocessor may return the execution results later; this will lead to out-of-order transmission of execution results, which will have an adverse impact on the normal execution of the task; for example, it will make the abnormal positioning of the task complicated.

[0038] Exemplarily, a computer program includes 3 code snippets: Code snippet 1: DIV R3,R1,R2; Code snippet 2: ADD R4,R3,R5; Code snippet 3: SUB R6,R7,R8. The above 3 code snippets respectively correspond to the following 3 instructions:

[0039] Instruction 1: Calculate the value in register R1 divided by the value in register R2, and store the result in register R3.

[0040] Instruction 2: Calculate the value in register R3 plus the value in register R5, and store the result in register R4.

[0041] Instruction 3: Calculate the value in register R7 minus the value in register R8, and store the result in register R6.

[0042] The main processor sequentially sends the instructions corresponding to the 3 code snippets to the coprocessor, and after receiving the instructions, the coprocessor performs the instruction processing flow.

[0043] Assume R2 = 0. When the computer program executes to code snippet 1, a division-by-zero exception should be triggered, causing the computer program to be interrupted and redirected to the exception handling process. Then, code snippet 2 and code snippet 3 will not be executed, that is, the values in register R4 and register R6 will not be rewritten, and the main processor can perform exception location based on the values in register R4 and register R6.

[0044] Among them, for an instruction, the complete processor cycle of the instruction includes: the coprocessor receives the instruction, decodes the instruction, and executes the instruction.

[0045] The coprocessor usually processes the above three instructions in a pipelined manner. Specifically, in the first clock cycle, the coprocessor receives Instruction 1; in the second clock cycle, the coprocessor decodes Instruction 1 and receives Instruction 2; in the third clock cycle, the coprocessor executes Instruction 1, decodes Instruction 2, and receives Instruction 3, and so on until all instructions are executed.

[0046] The processing cycles of Instruction 1, Instruction 2, and Instruction 3 may be different. Exemplarily, the processing cycle of Instruction 1 is long, and the processing cycles of Instruction 2 and Instruction 3 are short; then, when the coprocessor finishes processing Instruction 2 and Instruction 3, Instruction 1 may not have been executed yet; then, the coprocessor will first return the execution results of Instruction 2 and Instruction 3 to the main processor to rewrite the values in register R6 and register R4; that is, make code snippet 2 and code snippet 3 in the computer program code be executed first.

[0047] After instruction 1 starts to execute, the program is interrupted and diverted to the exception handling process. However, the values of register R6 and register R4 have been rewritten at this time. This makes it difficult for the main processor to determine the exact location and cause of the exception when performing exception location based on three code segments of the computer program, thus making the exception location of the computer program execution very complex and having an adverse impact on the normal execution of the tasks corresponding to the computer program code.

[0048] Due to instructions 2 and 3 received at a relatively late time, the execution results are first returned to the main processor, causing the computer program code segments to execute out of order, thus having an adverse impact on the normal execution of the tasks corresponding to the computer program code. Based on this, the present application provides an instruction processing method. Through the method of the present application, the execution results of the instructions received earlier can be returned to the first processor first; thus, adverse impacts on the normal execution of the tasks can be avoided.

[0049] The embodiments of the present application can be applicable to any electronic device with data processing capabilities and multiple processors. Among them, the first processor can be one of the processors in the electronic device, and the execution subject of the instruction processing method of the present application can be a second processor different from the first processor among the multiple processors. Exemplarily, the first processor is a central processing unit, also known as the main processor; the second processor can be a coprocessor, such as a floating-point unit (FPU), ROCC, etc.

[0050] Figure 3 The structural schematic diagram of the second processor provided by the present application is as Figure 3 shown. The second processor includes a coprocessor interface and an execution module; the execution module is composed of multiple execution units. Among them, the coprocessor interface includes a decoding module, a distribution module, and a cache module. Among them, the distribution module can receive the instructions sent by the first processor, and after the distribution module preliminarily processes the instructions, it sends them to the decoding module. The decoding module decodes the instructions and stores them in the cache area, the distribution module allocates corresponding execution units for the instructions in the cache area, and the execution units execute the instructions.

[0051] Signaling and data interaction can be carried out between the first processor and the second processor through a request channel, a single-cycle response channel, and a multi-cycle response channel. Specifically, the first processor sends instructions to the second processor through the request channel. Each time the second processor receives the instructions sent by the first processor, it stores the first information of the instructions in the cache area. The clock signal and the reset signal are sent to the second processor by the first processor through the global channel.

[0052] The instructions include single-cycle instructions and multi-cycle instructions; the second processor sends the execution result of the single-cycle instruction to the first processor through the single-cycle response channel; and sends the execution result of the multi-cycle instruction to the first processor through the multi-cycle response channel.

[0053] Figure 2 It is the implementation flowchart of the instruction processing method provided by the embodiments of this application. As Figure 2 shown, the method includes:

[0054] S201. When the second processor obtains the first execution result during the process of executing the instructions stored in the execution cache area, determine whether the first execution result is the execution result of the first instruction; if so, execute S202; otherwise, execute S203.

[0055] Among them, the instructions stored in the cache area are sent by the first processor, and the first instruction is the instruction with the earliest reception time in the cache area; the execution results of the instructions in the cache area have not been sent to the first processor.

[0056] Among them, the first execution result is obtained during the process of executing the instructions in the cache area.

[0057] In this application, after the second processor receives the instruction, it performs a parsing operation on the instruction through the decoding module, and the distribution module stores the parsing result as the first information of the instruction in the cache area. Among them, the parsing result includes source data; fields for secondary decoding; and these fields are used for the execution unit to obtain the operation type to be executed.

[0058] In some embodiments, when the second processor receives the instruction sent by the first processor, it assigns a first identifier to the received instruction, and while storing the first information in the cache area, it also stores the first identifier of the instruction in the cache sub-area. The second processor can determine the instruction with the earliest reception time based on the first identifier of the instruction.

[0059] Specifically, for each instruction, when the instruction is executed, the distribution module sends the parsing result corresponding to the instruction and the first identifier to the execution unit corresponding to the instruction. After the execution unit finishes executing the instruction based on the parsing result, it adds the first identifier of the instruction to the execution result. Among them, in order to distinguish from the first identifier stored in the cache area, the first identifier in the execution result is denoted as the second identifier.

[0060] When the second processor executes each instruction, the obtained execution result carries the second identifier. Therefore, the second processor can determine whether the currently obtained first execution result is the execution result of the first instruction based on the matching situation between the second identifier and the first identifier of the first instruction.

[0061] Among them, the first identifier assigned by the second processor to the instruction is related to the reception time of the instruction.

[0062] In some embodiments, for instructions received earlier, the first identifier is smaller. Exemplarily, if instruction 1 is received first, the first identifier "0" is assigned to instruction 1; next, if instruction 2 is received, the first identifier "1" is assigned to instruction 2.

[0063] Regarding the first execution result, if the second identifier carried by the first execution result is the same as the first identifier of the first instruction, it indicates that the first execution result is the execution result of the first instruction.

[0064] If the second identifier carried by the first execution result is different from the first identifier of the first instruction, it indicates that the first execution result is not the execution result of the first instruction.

[0065] The cache area includes multiple cache sub-areas; one cache sub-area corresponds to one instruction, and one cache sub-area is used to store the relevant information of one instruction.

[0066] In this application, the cache sub-areas are divided into an idle state and a non-idle state. Among them, the cache sub-area in which an instruction has been stored is in the non-idle state, and the cache sub-area in the non-idle state can be called a non-idle cache sub-area; the cache sub-area in which no instruction has been stored is in the idle state, and the cache sub-area in the idle state can be called an idle cache sub-area.

[0067] The second processor stores the received instructions in consecutive cache sub-areas in the order of reception time. The instruction stored in the first non-idle cache sub-area among the consecutive cache sub-areas has the earliest reception time, and the instruction stored in the last non-idle cache sub-area has the latest reception time.

[0068] Exemplarily, when the second processor receives the first instruction, it stores the 1st instruction in cache sub-area 1; when it receives the second instruction, it stores the 2nd instruction in cache sub-area 2 adjacent to cache sub-area 1, and when it receives the Mth instruction, it stores the Mth instruction in the Mth cache sub-area adjacent to the (M - 1)th cache sub-area; among them, the addresses of adjacent cache sub-areas are also adjacent. M is a positive integer greater than 1.

[0069] Therefore, the addresses of cache sub-areas 1 to M are consecutive, and all are non-idle cache sub-areas; cache sub-area 1 is the first non-idle cache sub-area, and cache sub-area M is the last non-idle cache sub-area.

[0070] When the second processor executes the instructions stored in the cache area, it sequentially executes the instructions stored in the cache area based on the first information.

[0071] As described above, the first information stores fields and source data for secondary decoding; the execution units in the second processor can further parse the fields to execute corresponding instructions based on the results of the re-parsing and the source data.

[0072] It should be noted that in this application, cache instructions and execution instructions can be executed in parallel. That is to say, during the execution of instructions by the second processor, if a new instruction is received, the second processor can store the new instruction in an idle cache sub-region in parallel without interrupting the execution of the instruction.

[0073] As Figure 3 shown, the second processor includes multiple execution units, and the multiple execution units are respectively connected to the coprocessor interface through execution interfaces; a selection unit is also provided in the second processor, and the selection unit selects an instruction to be executed currently from the cache area in each clock cycle and sends it to the execution unit corresponding to the instruction, and the execution unit executes the instruction.

[0074] Among them, one execution unit can execute one or more instructions in a pipelined manner.

[0075] In some embodiments, the selection unit can select the instruction to be executed currently from the cache area in the order from earliest to latest reception time. After the second processor executes each instruction and obtains the execution result of the instruction, it needs to return the execution result to the first processor at an appropriate time.

[0076] It should be noted that the operation of the second processor executing instructions and the operation of the second processor returning the execution result to the first processor are also parallel.

[0077] As described above, the instructions in the cache area are all instructions whose execution results have not been sent to the first processor, including: unexecuted instructions, instructions that have started execution but have not obtained execution results, and instructions that have been executed and obtained execution results but have not returned the execution results to the first processor.

[0078] The first execution result is the execution result currently obtained by the second processor.

[0079] As described above, the processing flow of instructions generally includes three stages: the second processor receives instructions from the first processor, the second processor parses the instructions, and the second processor executes the instructions; correspondingly, the processing cycle of instructions includes an instruction fetch cycle, a decoding cycle, and an execution cycle. Among them, for different instructions, the processing cycle may be different. Specifically, the execution cycle in the processing cycle may be different.

[0080] Specifically, the execution cycle of an instruction can be one clock cycle or multiple clock cycles.

[0081] Next, takeFigure 4 For example, the process of the second processor executing instructions for instructions with different execution cycles is illustratively described.

[0082] Figure 4 The time when the instruction starts to execute and the time when the execution is completed are shown; as Figure 4 shown, T0, T1, T2,... represent the start times of the first clock cycle, the start time of the second clock cycle, the start time of the third clock cycle; the second processor starts to execute instruction 1 at T0, and the execution cycle of instruction 1 is 5 clock cycles; the second processor starts to execute instruction 2 at T2, and the execution cycle of instruction 2 is 1 clock cycle; the second processor starts to execute instruction 3 at T3; the execution cycle of instruction 3 is 2 clock cycles.

[0083] Then as Figure 4 shown, the second processor completes the execution process of instruction 1 at T5; the second processor completes the execution process of instruction 2 at T2; the second processor completes the execution process of instruction 3 at T4.

[0084] It can be seen that if the second processor executes the received instructions in the order of the earliest received time to the latest received time, the time order of obtaining the execution results may also be different.

[0085] S202. The second processor sends the first execution result to the first processor.

[0086] It can be understood that if the currently obtained first execution result is the instruction result of the first instruction with the earliest received time in the cache area, it means that in the current second processor, the execution results of the instructions with a received time earlier than the first instruction have all been returned to the first processor. Sending the first execution result to the first processor at this moment will not cause the out-of-order return of the instruction execution results.

[0087] S203. The second processor stores the first execution result in the cache area, and waits until all the execution results of the second instructions are obtained and sent to the first processor, and then sends the first execution result to the first processor.

[0088] Among them, the instruction that matches the first execution result is described as the third instruction.

[0089] Among them, the second instruction is the instruction with a received time before the third instruction.

[0090] It can be understood that if the first execution result is not the execution result of the first instruction; it means that in the cache area, the execution result of the first instruction with the earliest received time has not been returned to the first processor yet.

[0091] The execution situation of the first instruction includes:

[0092] (1) The first instruction has not been executed yet;

[0093] (2) The first instruction has been executed but not completed, and no execution result has been obtained;

[0094] (3) The first instruction has been executed and the execution result has been obtained, but the execution result has not been sent to the first processor yet.

[0095] If it belongs to case (1), the second processor executes the first instruction, obtains the execution result of the first instruction, and preferentially returns the execution result of the first instruction to the first processor; if it belongs to case (2), the second processor continues to execute the first instruction, obtains the execution result of the first instruction, and preferentially returns the execution result of the first instruction to the first processor; if it belongs to case (3), the second processor sends the execution result of the first instruction to the first processor.

[0096] In the case of S203, for the first execution result corresponding to the third instruction, after the execution results of all the second instructions whose waiting reception time is before the third instruction are obtained and returned to the first processor, the first execution result is then returned to the first processor. In this way, out-of-order return of the execution results of instructions can be avoided.

[0097] This application provides an instruction processing method. In this application, the first information of the instructions received by the second processor is stored in the cache area, and the instructions in the cache area are executed sequentially based on the first information. Each time the first execution result is obtained, the second processor determines whether the instruction corresponding to the first execution result is the first instruction with the earliest reception time among the instructions in the cache area; wherein, the execution results of the instructions in the cache area have not been sent to the first processor yet. If so, the first execution result is sent to the first processor; if not, the first execution result is cached, and after all the execution results whose waiting reception time is before the first execution result are sent to the first processor, the first execution result is sent to the first processor; in this way, each execution result sent to the first processor is the instruction with the earliest reception time among the instructions in the cache area whose execution results have not been sent to the first processor, ensuring that the instruction with the earliest reception time is sent to the first processor first, ensuring the in-order transmission of the execution results of the instructions, and thus avoiding adverse effects on the normal execution of the current task.

[0098] In the embodiments of this application, the manner in which the second processor executes the instructions stored in the cache area is not limited. In some embodiments, the process of executing the instructions stored in the cache area in S201 can be implemented by S2011 (not shown in the figure):

[0099] S2011. The second processor sequentially executes the instructions stored in the cache area based on the first information in the order from the earliest reception time to the latest reception time.

[0100] As described above, the second processor includes a selection unit. Before each instruction is executed, the selection unit selects an instruction from the cache area, and the distribution unit sends the relevant information of the instruction selected by the selection unit to the corresponding execution unit, and the execution unit executes the instruction based on the relevant information of the instruction.

[0101] Specifically, the selection unit selects the corresponding instructions in the order of the reception time from early to late in each clock cycle and sends them to the execution unit for execution; then the execution unit also executes the instructions in the order of the reception time from early to late.

[0102] In some other embodiments, the process of executing the instructions stored in the execution cache area in S201 can be implemented by the following S2012 (not shown in the figure):

[0103] S2012. The second processor sequentially executes the instructions stored in the cache area based on the first information in a random order.

[0104] Specifically, the selection unit randomly selects an instruction in each clock cycle and sends it to the execution unit to make the execution unit execute the corresponding instruction.

[0105] In this embodiment, the second processor can execute the instructions stored in the cache area in the order of the reception time from early to late, or can execute the instructions stored in the cache area in a random order; regardless of the way of executing the instructions, according to the instruction processing method of the present application, before the second processor obtains the execution result of the earliest received instruction, it will not return the execution results of other instructions to the first processor, so that the execution results of the instructions in the cache area are sequentially returned to the first processor in the order of the reception time of the instructions, realizing the in-order transmission of the execution results of the instructions.

[0106] To facilitate understanding of the technical solution of the present application, next, taking Figure 4 as an example, the process of the second processor realizing the in-order transmission of the execution results of the instructions will be specifically described.

[0107] Among them, the execution cycle of instruction 1 is 5 clock cycles; the execution cycle of instruction 2 is 1 clock cycle; the execution cycle of instruction 3 is 2 clock cycles. The reception time of instruction 1 is later than that of instruction 2, and the reception time of instruction 2 is later than that of instruction 3.

[0108] First, in the first clock cycle, the second processor starts to execute instruction 1.

[0109] In the second clock cycle, the second processor starts to execute Instruction 2. At the end of the second clock cycle (i.e., at the beginning of the third clock cycle), the second processor obtains the execution result 1 of Instruction 2. The second processor judges using the execution result 1 as the first execution result. The second processor determines that the first instruction is Instruction 1, and the execution result 1 is not the execution result of Instruction 1. Therefore, the execution result 1 is stored in the cache area.

[0110] At the beginning of the third clock cycle, the second processor starts to execute Instruction 3. At the end of the fourth clock cycle, the second processor obtains the execution result 2 of Instruction 3. The second processor judges using the execution result 2 as the first execution result. The second processor determines that the first instruction is Instruction 1, and the execution result 2 is not the execution result of Instruction 1; therefore, the execution result 2 is stored in the cache area.

[0111] At the end of the fifth clock cycle, the second processor obtains the execution result 3 of Instruction 1. The second processor judges using the execution result 3 as the first execution result. The second processor determines that the first instruction is Instruction 1, and the execution result 3 is the execution result of Instruction 1; therefore, the execution result 3 is returned to the first processor.

[0112] After the execution result of Instruction 1 is returned to the first processor, the first instruction with the earliest reception time is updated from Instruction 1 to Instruction 2. The second processor determines that the execution results of all instructions (Instruction 1) whose reception time is earlier than Instruction 2 have been returned to the first processor, and then returns the execution result of Instruction 2 to the first processor.

[0113] After the execution result of Instruction 2 is returned to the first processor, the first instruction with the earliest reception time is updated from Instruction 2 to Instruction 3. The second processor determines that the execution results of all instructions (Instruction 1 and Instruction 2) whose reception time is earlier than Instruction 3 have been returned to the first processor, and then returns the execution result of Instruction 3 to the first processor.

[0114] As described above, the first information and the first identifier of the instruction are stored in the cache area of the second processor. Among them, the cache area includes multiple cache sub-areas, and one cache sub-area corresponds to one instruction; the cache sub-area is used to store all information of the corresponding instruction; including the first information, the first identifier of the instruction and the second information of the instruction mentioned below, etc.

[0115] In some embodiments, the first information and the first identifier of the instruction are sequentially stored in consecutive cache sub-areas in the order of the reception time of the instruction.

[0116] Exemplarily, when instruction 1 is received, the first information and the first identifier of instruction 1 are stored in the first cache sub-region of the cache area; when instruction 2 is received, the first information and the first identifier of instruction 2 are stored in the second cache sub-region adjacent to the first cache sub-region; when instruction 3 is received, the first information and the first identifier of instruction 3 are stored in the third cache sub-region adjacent to the second cache sub-region.

[0117] Two pointers for the storage area are set in the second processor, including a head pointer and a tail pointer.

[0118] Among them, the head pointer points to the first non-idle cache sub-region among the non-idle cache sub-regions.

[0119] The tail pointer points to the first idle cache sub-region after the non-idle cache sub-region.

[0120] Since the first instruction with the earliest reception time is stored in the cache sub-region pointed to by the head pointer, the second processor can determine the first instruction through the head pointer to obtain the first identifier of the first instruction.

[0121] Next, through Figure 5 The embodiment exemplarily illustrates how to determine whether the first execution result is the execution result of the first instruction through the head pointer.

[0122] Figure 5 This is the implementation flowchart of the instruction processing method provided by the embodiment of the present application; as Figure 5 shown, in S201, it can be achieved through Sa1 to Sa2 to determine whether the first execution result is the execution result of the first instruction:

[0123] Sa1: The second processor obtains the first identifier stored in the cache sub-region pointed to by the head pointer.

[0124] Among them, the first non-idle cache sub-region pointed to by the head pointer stores the relevant information of the first instruction with the earliest reception time, including the first identifier assigned by the second processor to the first instruction.

[0125] In the present application, the cache area is used to store instructions whose execution results have not been sent to the first processor; for each instruction in the cache area, after the execution result of the instruction is sent to the first processor, the second processor clears all the information corresponding to the instruction in the cache area.

[0126] Sa2: The second processor determines whether the first identifier stored in the cache sub-region pointed to by the head pointer is the same as the second identifier.

[0127] If the first identifier stored in the cache sub-region pointed to by the head pointer is the same as the second identifier, then the first execution result is the execution result of the first instruction; the second processor executes S202.

[0128] If the first identifier stored in the cache sub-region pointed to by the head pointer is different from the second identifier, the first execution result is not the execution result of the first instruction. The second processor executes S203.

[0129] In this embodiment, a head pointer and a tail pointer of the cache region are set in the second processor. Among them, the head pointer points to the cache sub-region corresponding to the instruction with the earliest reception time; thus, when obtaining the first identifier of the first instruction, it is simple and convenient to obtain the first identifier in the first non-idle cache sub-region pointed to by the head pointer as the first identifier of the first instruction.

[0130] In some embodiments, for each instruction, the cache region further includes second information of the instruction. Specifically, the second information is stored in the cache sub-region corresponding to the instruction. Among them, the second information includes: the first state of the instruction, the second state of the instruction, and the third state of the instruction.

[0131] Among them, the first state of the instruction is used to indicate whether the instruction has started to be executed; alternatively, it can be used to indicate whether the instruction has been sent to the execution unit. Exemplarily, the first state is 0, indicating that the instruction has not been sent to the execution unit; after the instruction starts to be executed, the second processor updates the first state from 0 to 1.

[0132] The second state of the instruction is used to indicate whether the instruction has been executed. Exemplarily, the second state is 0, indicating that the instruction is being executed and has not been completed; the second state is 1, indicating that the execution instruction has been completed and the execution result has been obtained.

[0133] After the instruction is executed, the second processor updates the second state from 0 to 1.

[0134] The third state of the instruction is used to indicate whether the execution result of the instruction has been sent to the first processor. Exemplarily, the third state is 0, indicating that the execution result of the instruction has been obtained but not sent to the first processor; the third state is 1, indicating that the execution result of the instruction has been sent to the first processor.

[0135] After the instruction is sent to the first processor, the second processor updates the third state from 0 to 1. Then, all the information of the corresponding instruction in the cache region is deleted to leave an empty cache region to store the instructions that come in later.

[0136] In this application, the first state, the second state, and the third state of the instructions stored in the cache region are used for the second processor to accurately track the processing progress of each instruction, and can provide a reference for subsequent instruction scheduling and resource allocation.

[0137] Next, taking the current received first execution result as the execution result of the first instruction, through Figure 6The embodiments exemplarily illustrate the operations after receiving the first execution result.

[0138] Figure 6 This is the implementation flowchart of the instruction processing method provided by the embodiments of this application. As Figure 6 shown, the method further includes:

[0139] S601. When the second processor obtains the first execution result during the process of executing the instructions stored in the execution cache area, it determines whether the first execution result is the execution result of the first instruction; if so, execute S602; otherwise, execute S605.

[0140] S601 is similar to Figure 2 S201 shown in the Figure 2 embodiments, and the detailed introduction in the

[0141] embodiments can be referred to. For the sake of brevity, it will not be elaborated here.

[0142] It can be understood that if the currently obtained first execution result is the instruction result of the first instruction with the earliest reception time in the cache area, it means that in the current second processor, the execution results of the instructions with a reception time earlier than the first instruction have all been returned to the first processor. Sending the first execution result to the first processor at this moment will not cause the out-of-order return of the instruction execution results.

[0143] S603. The second processor sets the content in the cache sub-area corresponding to the first instruction to an invalid state.

[0144] As described above, consecutive cache sub-areas are used to store the relevant information of the instructions; among them, the first non-idle cache sub-area corresponds to the first instruction with the earliest reception time, and the first information, the first identifier, the second information, etc. of the first instruction are stored in this cache sub-area. After the first execution result is obtained, the execution task of the first instruction is completed, and the relevant information of the first instruction will not be used subsequently. Therefore, the content in the cache sub-area corresponding to the first instruction is set to an invalid state, that is, the content in the first non-idle cache sub-area is cleared, so as to store new instructions subsequently.

[0145] When the content in the cache sub-area corresponding to the first instruction is set to an invalid state, the type of the cache sub-area corresponding to the first instruction becomes an idle cache sub-area.

[0146] In some embodiments, setting the content in the cache sub-area corresponding to the first instruction to an invalid state may be to clear the content in the cache sub-area corresponding to the first instruction; or not to clear the content in the cache sub-area corresponding to the first instruction, but to mark the content as invalid content.

[0147] S604. The second processor updates the first non-idle cache sub-region pointed to by the head pointer.

[0148] It can be understood that after emptying the content in the first non-idle cache sub-region, the first non-idle cache sub-region switches from the non-idle state to the idle state. Since multiple instructions are stored sequentially in chronological order, after emptying the content of the first non-idle cache sub-region, the second non-idle cache sub-region is updated to the first non-idle cache sub-region, and the first instruction with the earliest reception time is updated to the instruction pointed to by the second non-idle cache sub-region (i.e., the updated first non-idle cache sub-region). Therefore, it is necessary to update the head pointer of the cache region so that it points to the second non-idle cache sub-region. In this way, when the first execution result is judged next time, it can be ensured that the obtained first identifier is still the identifier of the instruction with the earliest reception time.

[0149] Among them, updating the head pointer means updating the address variable stored in the head pointer to the address of the first non-idle cache sub-region, so as to achieve that the head pointer points to the first non-idle cache sub-region.

[0150] S605. The second processor stores the first execution result in the cache region, and after all the execution results of the second instructions are obtained and sent to the first processor, the first execution result is sent to the first processor.

[0151] S601 is Figure 2 similar to S203 shown in the Figure 2 embodiment, and the detailed introduction of the

[0152] embodiment can be referred to. For the sake of simplicity, it will not be elaborated here.

[0153] The method of this embodiment can update the instruction with the earliest reception time among the instructions whose execution results have not been sent to the first processor by updating the head pointer, so that the second processor can accurately judge whether the first execution result is the execution result of the instruction with the earliest reception time.

[0154] In some embodiments, the maximum storage space of the cache region is N, where N is greater than 1; it includes N cache sub-regions and can store the relevant information of at most N instructions at the same time; during the process of storing instructions, the first identifier assigned to the instruction to be stored can reuse the first identifier of the deleted instruction.

[0155] Exemplarily, the second processor receives N instructions, and the first identifiers of the N instructions are respectively stored in N cache sub-regions; among them, the first identifier 0 of the first instruction is stored in the first cache sub-region, and the first identifier N of the second instruction to the Nth instruction is stored in the Nth cache sub-region.

[0156] After the second processor sends the execution result of the first instruction to the first processor, it clears the relevant information of the first instruction in the first cache sub-region.

[0157] Next, if the second processor receives a new instruction, the first identifier assigned to the new instruction can reuse the first identifier 0 of the already deleted first instruction, thereby realizing the reuse of the first identifier.

[0158] In some embodiments, before the first processor and the second processor perform instruction transmission, they need to perform a handshake based on the valid / ready protocol first; after the handshake is successful, the operations of S601 and subsequent steps of this application are executed.

[0159] If the number of instructions stored in the cache area reaches the maximum cache number; that is, all cache sub-regions are in a non-idle state; then the second processor sends a low-level signal to the first processor through the ready line, indicating that it no longer receives the instructions sent by the first processor; when there is an idle cache sub-region in the cache area, the second processor sends a high-level signal to the first processor through the ready line to receive instructions.

[0160] As described above, every time the second processor receives an instruction, it stores the first information and the first identifier of the instruction in the cache area; the second processor stores the instruction according to the cache sub-region pointed to by the tail pointer.

[0161] Figure 7 It is a schematic flow chart of the implementation of the instruction processing method provided by this application. Figure 7 The illustrated embodiment mainly introduces the processing method when the second processor receives the instructions sent by the first processor. Please refer to Figure 7 As shown, the method of this embodiment includes:

[0162] S701. The second processor stores the latest received instruction in the first idle cache sub-region pointed to by the tail pointer.

[0163] The second processor assigns an identifier to the newly received instruction to be stored based on the reception time, and stores the first information of the instruction to be stored and the identifier assigned by the second processor in the cache sub-region pointed to by the tail pointer.

[0164] After writing the relevant information of the instruction to be stored into the cache sub-region pointed to by the tail pointer, the cache sub-region currently pointed to by the tail pointer switches from the idle state to the non-idle state.

[0165] S702, the second processor updates the first free cache sub-region pointed to by the tail pointer.

[0166] Since the cache sub-region pointed to by the tail pointer is a non-free cache sub-region, if the tail pointer is not updated, when the next instruction to be stored arrives, due to the incorrect pointing of the tail pointer, the relevant information of the next instruction to be stored will overwrite the relevant information of the currently previously written instruction, which may cause program anomalies. Therefore, after writing the relevant information of an instruction, the tail pointer needs to be updated.

[0167] Among them, updating the tail pointer means updating the address variable stored in the tail pointer to the address of the first free cache sub-region, so as to achieve that the tail pointer points to the first free cache sub-region.

[0168] The method of this embodiment can correctly cache the instructions sent by the first processor to the free cache sub-region by updating the tail pointer, avoiding the situation of instruction overwriting, thereby ensuring the normal execution of the program.

[0169] As described above, this application is used to achieve the in-order transmission of execution results. Then this application is applicable to instructions with execution results. That is to say, the instructions stored in the cache area are all instructions with execution results.

[0170] Based on this, this application provides an instruction processing method. Figure 8 It is the implementation flowchart of the instruction processing method provided by the embodiment of this application. This embodiment specifically uses S101a to S10b to illustrate how to store instructions in the cache area in sequence. Among them, S101a and S101b are synchronized with the steps of the second processor executing instructions in sequence.

[0171] As Figure 8 shown, the method further includes:

[0172] S101a, the second processor receives the instruction sent by the first processor.

[0173] S101b, the second processor parses the instruction to determine whether it is necessary to return the execution result to the first processor.

[0174] Specifically, every time the second processor receives an instruction sent by the first processor, it parses the instruction, and the obtained parsing result further includes the first type of the instruction.

[0175] Among them, the first type is used to indicate whether the second processor needs to return the execution result to the first processor.

[0176] In this application, the execution result can be the calculation result of a mathematical operation. For example, if the instruction is a mathematical operation, then executing this instruction can obtain the calculation result of the mathematical operation, and this calculation result needs to be returned to the first processor.

[0177] In some embodiments, the execution result can also be to change the value of a certain register in the second processor, and this execution result cannot or does not need to be returned to the first processor.

[0178] S101c. When the second processor determines that it needs to return the execution result to the first processor, it stores the instruction in the cache area.

[0179] Specifically, the second processor determines whether it needs to return the execution result to the first processor based on the first type in the parsing result.

[0180] When the second processor stores the instruction in the cache area, specifically, the second processor stores the first information of the instruction in the cache area and stores the first identifier assigned to the instruction in the cache area.

[0181] In some embodiments, after the second processor parses the instruction, the obtained parsing result further includes the second type of the instruction, and the second type is used to indicate whether the execution cycle of the instruction is a single cycle.

[0182] The execution cycle of the instruction being a single cycle means that the execution unit finishes executing the instruction in one clock cycle.

[0183] The execution cycle of the instruction not being a single cycle means that the execution unit finishes executing the instruction in multiple clock cycles.

[0184] In this application, for instructions with an execution cycle that is not a single cycle, the execution result needs to be returned to the first processor.

[0185] Among the instructions with an execution cycle that is a single cycle, there may be cases where the execution result does not need to be returned to the first processor.

[0186] In some cases, if the second type indicates that the execution cycle of the instruction is a single cycle and the first type indicates that the execution result does not need to be returned to the first processor, and when the execution unit currently supports executing this instruction, the execution unit directly executes the instruction without storing the instruction information in the cache area.

[0187] In some embodiments, the execution unit in the second processor includes a low-power interface. When the execution unit is not executing an instruction, the low-power interface turns off the function of the execution module receiving the clock signal to save power.

[0188] In this embodiment, the cache area is designed for instructions that can obtain execution results. Since the execution cycles of instructions are different, the execution results of instructions received earlier may be obtained later, and the execution results of instructions received later may be obtained earlier. To ensure the in-order transmission of the execution results of instructions, a cache area is set in the second processor. The second processor caches the execution results of instructions received later and returns the execution results to the first processor in the order of the reception time from earliest to latest.

[0189] It should be noted that although the steps of the methods in this application are described in a specific order in the drawings, this does not require or imply that these steps must be executed in that specific order, or that all the steps shown must be executed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.; or, the steps in different embodiments may be combined into a new technical solution.

[0190] Based on the foregoing embodiments, an instruction processing apparatus is provided in an embodiment of this application. The apparatus includes each module included and each unit included in each module, and can be implemented by a second processor; of course, it can also be implemented by specific logic circuits.

[0191] Figure 9 is a schematic structural diagram of the instruction processing apparatus provided in an embodiment of this application, as Figure 9 shown, the instruction processing apparatus 90 includes a distribution module 91 and a transmission module 92, where:

[0192] The distribution module 91 is configured to, when obtaining a first execution result during the execution of an instruction stored in the cache area, determine whether the first execution result is the execution result of a first instruction; where the instruction stored in the cache area is sent by a first processor, and the first instruction is the instruction with the earliest reception time in the cache area; the instructions in the cache area are all instructions whose execution results have not been sent to the first processor.

[0193] The transmission module 92 is configured to, if the first execution result is the execution result of the first instruction, send the first execution result to the first processor.

[0194] The distribution module 91 is configured to, if the first execution result is not the execution result of the first instruction, store the first execution result in the cache area; the transmission module 92 is further configured to, after all the execution results of the second instructions are obtained and sent to the first processor, send the first execution result to the first processor; where the reception time of the second instruction is before the reception time of the instruction that the first execution result matches; all the second instructions include the first instruction.

[0195] In some embodiments, the distribution module 91 is further configured to determine whether the second identifier carried in the first execution result is the same as the first identifier of the first instruction; if they are the same, the first execution result is the execution result of the first instruction; if they are different, the first execution result is not the execution result of the first instruction.

[0196] In some embodiments, the cache area includes a plurality of cache sub-areas, and one cache sub-area corresponds to one instruction; the instructions sent by the first processor are sequentially stored in consecutive cache sub-areas in the order of reception time; the head pointer of the cache area points to the first non-idle cache sub-area in the consecutive cache sub-areas; the tail pointer of the cache area points to the first idle cache sub-area after the consecutive cache sub-areas.

[0197] In some embodiments, the distribution module 91 is specifically further configured to determine that the identifier stored in the cache sub-area pointed to by the head pointer is the first identifier of the first instruction; wherein, the first identifier stored in the cache sub-area pointed to by the head pointer matches the first instruction; and determine whether the first identifier of the first instruction is the same as the second identifier.

[0198] In some embodiments, the distribution module 91 is further configured to invalidate the content in the cache sub-area corresponding to the first instruction; and update the first non-idle cache sub-area pointed to by the head pointer.

[0199] In some embodiments, the distribution module 91 is further configured to store the instruction to be stored in the cache sub-area pointed to by the tail pointer; and update the first idle cache sub-area pointed to by the tail pointer.

[0200] In some embodiments, the instruction processing device 90 further includes an execution module, and the execution module is configured to sequentially execute the instructions stored in the cache area in the order from earliest to latest reception time; or, sequentially execute the instructions stored in the cache area in a random order.

[0201] In some embodiments, the instruction processing device 90 further includes a decoding module, and the distribution module 91 is further configured to receive the instruction sent by the first processor and send the instruction to the decoding module; the decoding module is configured to parse the instruction to determine whether an execution result needs to be returned to the first processor; the distribution module 91 is configured to store the instruction in the cache area when it is determined that an execution result needs to be returned to the first processor.

[0202] In some embodiments, for each of the instructions, second information for storing the instructions in the cache area; wherein, the second information of the instructions includes: a first state, a second state, and a third state of the instructions; wherein, the first state is used to indicate whether the instruction has been executed, the second state is used to indicate whether the execution result of the instruction has been obtained, and the third state is used to indicate whether the execution result of the instruction has been sent to the first processor; wherein, the second information of the instruction is used to monitor the processing state of the instruction.

[0203] It should be noted that in the embodiments of the present application Figure 9 The division of the modules by the instruction processing device shown is schematic, only a logical function division, and there may be other division methods in actual implementation. In addition, in each embodiment of the present application, each functional unit may be integrated in a processing unit, may exist independently physically, or two or more units may be integrated in one unit. The above integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software functional unit. It may also be implemented in the form of a combination of software and hardware.

[0204] It should be noted that in the embodiments of the present application, if the above-mentioned instruction processing method is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the related art, may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. And the foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disc that can store program codes. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0205] The embodiments of the present application provide an electronic device Figure 10 is a schematic structural diagram of the electronic device according to the embodiments of the present application. As Figure 10 shown, the electronic device 100 includes a memory 1001 and a processor 1002. The memory 1001 stores a computer program that can run on the processor 1002. When the processor 1002 executes the program, it implements the steps in the instruction processing method provided in the above embodiments. That is, the processor 1002 is the second processor in the present application.

[0206] It should be noted that the memory 1001 is configured to store instructions and applications executable by the processor 1002, and can also cache data to be processed or already processed by each module in the processor 1002 and the electronic device 100 (such as image data, audio data, voice communication data, and video communication data), which can be implemented by flash memory (FLASH) or random access memory 1001 (Random Access Memory, RAM).

[0207] The embodiments of the present application provide a computer program product containing instructions, which when running on a computer, causes the computer to execute the steps in the instruction processing method provided in the above method embodiments.

[0208] It should be pointed out here that the descriptions of the above storage medium and device embodiments are similar to those of the above method embodiments and have similar beneficial effects to the method embodiments. For the technical details not disclosed in the storage medium, storage medium and device embodiments of the present application, please refer to the descriptions of the method embodiments of the present application for understanding.

[0209] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0210] The features disclosed in several device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new device embodiments.

[0211] As mentioned above, the above are only the embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A command processing method, characterized in that: The method comprises: In the process of executing the instruction stored in the cache area, when a first execution result is obtained, it is determined whether the first execution result is the execution result of the first instruction; wherein the instruction stored in the cache area is sent by the first processor, and the first instruction is the instruction with the earliest receiving time in the cache area; the instructions in the cache area are all instructions whose execution results have not been sent to the first processor; If yes, sending the first execution result to the first processor; If not, the first execution result is stored in the cache area; after waiting for the execution results of all the second instructions to be obtained and sent to the first processor, the first execution result is sent to the first processor; wherein the reception time of all the second instructions is before the reception time of the instruction matched by the first execution result.

2. The method according to claim 1, characterized in that The determining whether the first execution result is an execution result of the first instruction includes: Determining whether a second identifier carried by the first execution result is the same as a first identifier of the first instruction; If they are the same, the first execution result is the execution result of the first instruction; If different, the first execution result is not the execution result of the first instruction.

3. The method according to claim 2, characterized in that The cache area includes a plurality of cache sub-areas, one cache sub-area corresponds to one instruction; the instructions sent by the first processor are sequentially stored in consecutive cache sub-areas in the order of receiving time; The head pointer of the cache area points to the first non-free cache sub-area in the continuous cache sub-areas; The tail pointer of the cache area points to the first free cache sub-area after the continuous cache sub-areas.

4. The method according to claim 3, characterized in that The determining whether the second identifier is the same as the first identifier of the first instruction includes: Determine that the identifier stored in the cache sub-region pointed to by the head pointer is the first identifier of the first instruction; wherein the first identifier stored in the cache sub-region pointed to by the head pointer matches the first instruction; Determine whether the first identifier of the first instruction is the same as the second identifier.

5. The method according to claim 4, characterized in that After sending the first execution result to the first processor, the method further includes: Setting the content in the cache sub-area corresponding to the first instruction to an invalid state; The first non-free cache sub-region pointed to by the head pointer is updated.

6. The method according to claim 4, characterized in that The method further comprises: Storing the instruction to be stored in the cache sub-area pointed to by the tail pointer; The first free cache sub-region pointed to by the tail pointer is updated.

7. The method according to claim 1, characterized in that The instructions stored in the execution cache area include: Execute the instructions stored in the cache area in order from earliest to latest reception time; or, The instructions stored in the cache area are executed sequentially in a random order.

8. The method according to claim 1, characterized in that The method further comprises: receiving a to-be-processed instruction sent by the first processor; Parsing the instruction to determine whether it is necessary to return an execution result to the first processor; When it is determined that the execution result needs to be returned to the first processor, the instruction is stored in the cache area.

9. The method according to claim 3, characterized in that: For each of the instructions, the cache area is further used to store second information of the instruction; The second information of the instruction includes: a first state, a second state and a third state of the instruction; wherein the first state is used to indicate whether the instruction has been executed, the second state is used to indicate whether the execution result of the instruction has been obtained, and the third state is used to indicate whether the execution result of the instruction has been sent to the first processor; The second information of the instruction is used to monitor the processing status of the instruction.

10. An instruction processing device, characterized in that: include: A module for executing the method according to any one of claims 1 to 9.

11. A processor, characterized in that: The processor is configured to execute the method according to any one of claims 1 to 9.

12. An electronic device, characterized in that: include: A memory and a processor as claimed in claim 11; The memory is configured to store computer program instructions; the processor is configured to execute the computer program instructions so that the electronic device implements the method according to any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that: include: Computer program instructions; The electronic device runs the computer program instructions so that the electronic device implements the method according to any one of claims 1 to 9.

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