A synchronous startup method for multi-core operating systems based on Cortex-M85 core

Abstract

The present invention relates to a method for synchronously starting a multi-core operating system based on a Cortex-M85 core, comprising the steps of: providing a Cortex-M85 and a multi-core FreeRTOS operating system; configuring the STIR of the NVIC in the Cortex-M85 to implement a software interrupt function for the FreeRTOS operating system, and simultaneously configuring the SysTick peripheral of the Cortex-M85 as a system timer for the FreeRTOS operating system; starting the Cortex-M85 and the FreeRTOS operating system, and initializing the kernel and all cores adaptively to implement software interrupt triggering for each core led by SysTick, and implementing actual task switching for the corresponding core by calling the vTaskSwitchContext function of the FreeRTOS operating system within the software interrupt. The present invention utilizes the task scheduling function of FreeRTOS that can support multi-symmetrical processing and cooperates with the software interrupt function of the Cortex-M85 core to implement simultaneous scheduling of multi-core tasks, thereby improving system throughput and response speed.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded real-time operating systems, and in particular to a method for synchronously starting a multi-core operating system based on a Cortex-M85 core. Background Art

[0002] The Cortex-M85, launched in April 2022 by ARM, is a new-generation embedded processor core based on the Armv8.1-M architecture. It offers the highest scalar and signal processing performance in the Cortex-M series. Leveraging ARM Helium technology (an Arm Cortex-M vector extension for the Armv8-M architecture), the Cortex-M85 demonstrates superior machine learning and digital signal processing capabilities. With its exceptional performance, advanced architecture, and low-power technology, the Cortex-M85 core is primarily targeted at high-performance applications such as automotive electronics, the Internet of Things, and industrial control. These sectors have a strong demand for multi-core processors, as multi-core MCUs can leverage multiple processor cores to execute tasks in parallel, significantly improving system throughput and responsiveness while also achieving load balancing to ensure that each core is fully utilized and avoid overload or idleness.

[0003] In the field of embedded real-time operating systems, real-time operating systems such as FreeRTOS and RT-Thread support single-core applications of the Cortex-M85 core, but there is currently no implementation of a multi-core real-time operating system for the Cortex-M85. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a multi-core operating system synchronous startup method based on the Cortex-M85 core. By utilizing the task scheduling function of FreeRTOS that supports multi-symmetric processing and cooperating with the software interrupt function of the Cortex-M85 core, simultaneous scheduling of multi-core tasks can be achieved, thereby improving system throughput and response speed.

[0005] The present invention is implemented by the following scheme: a method for synchronously starting a multi-core operating system based on the Cortex-M85 core, comprising the steps of:

[0006] Provides Cortex-M85 and multi-core FreeRTOS operating system;

[0007] Configuring the STIR of the NVIC in the Cortex-M85 to implement a software interrupt function for the FreeRTOS operating system, and configuring the SysTick peripheral of the Cortex-M85 as a system timer for the FreeRTOS operating system;

[0008] Start the Cortex-M85 and the FreeRTOS operating system, and initialize the kernel and all cores to trigger the software interrupt of each core led by the SysTick, and implement the actual task switching of the corresponding core by calling the vTaskSwitchContext function of the FreeRTOS operating system within the software interrupt.

[0009] The present invention further improves the method for synchronously starting a multi-core operating system based on the Cortex-M85 core in that the steps of initializing the core and all cores for adaptation include:

[0010] Perform core basic initialization and core interrupt initialization on all cores. The core basic initialization includes initializing peripheral resources and creating running tasks. The interrupt initialization includes initializing PendSVC, SVCall, and YieldCore interrupts and starting the execution of the first task through the SVC interrupt.

[0011] Performing basic kernel initialization on the kernel, wherein the content of the basic kernel initialization further includes creating an idle task and a timer task for all kernels in the FreeRTOS operating system based on the content of the basic kernel initialization;

[0012] After the core basic initialization and core interrupt initialization of all the cores are completed, core interrupt initialization is performed on the core. The content of the core interrupt initialization further includes initializing SysTick interrupt based on the content of the core interrupt initialization.

[0013] A further improvement of the method for synchronously starting a multi-core operating system based on the Cortex-M85 core of the present invention is that the process of initializing the SysTick interrupt includes:

[0014] Configure SysTick interrupt priority;

[0015] Select the clock source of SysTick;

[0016] Clear the SysTick Value register;

[0017] Configure the LOAD register;

[0018] Enable SysTick counting and interrupt.

[0019] A further improvement of the method for synchronously starting a multi-core operating system based on the Cortex-M85 core of the present invention is that when configuring the interrupt priority of SysTick, it is configured as the highest priority.

[0020] The present invention further improves the method for synchronously starting a multi-core operating system based on the Cortex-M85 core in that: when initializing peripheral resources in the basic initialization of the core, only the peripheral resources used individually by the corresponding core are initialized; when initializing peripheral resources in the basic initialization of the core, public peripheral resources are initialized.

[0021] The present invention includes but is not limited to the following beneficial effects:

[0022] 1. By utilizing the multi-symmetric task scheduling function of FreeRTOS and coordinating it with the software interrupt function of the Cortex-M85 core, it is possible to implement simultaneous scheduling of multi-core tasks, improve system throughput and response speed, and provide strong support for high-performance application scenarios.

[0023] 2. Through specific initialization settings and task switching mechanisms, it can ensure that all cores in the entire system can be scheduled, and ensure the stability and efficiency of the system, so that tasks can be seamlessly switched between cores.

[0024] 3. Using SysTick (system timer) in the Cortex-M85 core, there is no need to use a timer peripheral to implement the system clock. Only FreeRTOS needs to be ported at the kernel level. This solution is simple and helps improve porting efficiency and reliability, ensuring that FreeRTOS runs stably on the Cortex-M85 core. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The flowchart of the method for synchronously starting a multi-core operating system of the present invention is shown.

[0026] Figure 2 The figure shows the initialization process of SysTick and the interrupt task processing flow chart in the present invention. DETAILED DESCRIPTION

[0027] FreeRTOS, a widely used software system in the field of embedded real-time operating systems, is an open-source, portable, and compact real-time operating system kernel. It offers advantages such as security, reliability, a small footprint, and wide device support. Currently, FreeRTOS supports the Cortex-M85 single-core operating system and natively supports Symmetrical Multi-Processing (SMP). To achieve simultaneous multi-core startup based on the Cortex-M85 core, the present invention provides a method for simultaneous multi-core startup based on FreeRTOS. By leveraging FreeRTOS's SMP task scheduling functionality and the Cortex-M85 core's software interrupts, simultaneous multi-core task scheduling can be achieved, improving system throughput and response speed.

[0028] The following is a further description of the method for synchronously starting a multi-core operating system based on the Cortex-M85 core using a specific embodiment in conjunction with the accompanying drawings.

[0029] See Figure 1 As shown, a method for synchronously starting a multi-core operating system based on the Cortex-M85 core includes the following steps:

[0030] Step 1. Provide Cortex-M85 and a multi-core FreeRTOS operating system. Specifically, the core of the Cortex-M85 is represented as Core0. The number of cores in the FreeRTOS operating system can be determined according to actual application conditions. In this embodiment, the FreeRTOS operating system includes 3 cores, represented as Core1, Core2, and Core3 respectively.

[0031] Step 2: Configure the STIR (Software Trigger Interrupt Register) of the Cortex-M85's NVIC (Nested Vectored Interrupt Controller) to implement software interrupt functionality for the FreeRTOS operating system. Specifically, use NVIC interrupt 15 as the Core0 task switching interrupt task to facilitate efficient multi-core task switching. Also, configure the Cortex-M85's SysTick (system timer) peripheral as the FreeRTOS operating system's system timer to ensure accurate execution of timed tasks.

[0032] Step 3: Start the Cortex-M85 and the FreeRTOS operating system, and adaptively initialize Core0 and all cores (including Core1, Core2, and Core3) to trigger software interrupts for each core, led by SysTick. Within the software interrupt, the FreeRTOS operating system's vTaskSwitchContext function is called to switch tasks to the corresponding core. This enables simultaneous scheduling of multi-core tasks, improves system throughput and responsiveness, and provides strong support for high-performance application scenarios.

[0033] Specifically, the initialization steps for adapting Core0 and all Cores include:

[0034] Step 3.1. When starting the FreeRTOS operating system, perform basic core initialization and core interrupt initialization on all cores. The basic core initialization includes initializing peripheral resources and creating running tasks. The interrupt initialization includes initializing PendSVC (i.e., Pending Supervisor Call, a suspendable system call), SVCall (i.e., Secure Vector Call, secure vector call), YieldCore interrupt (i.e., software interrupt No. 15), and starting the execution of the first task through the SVC interrupt.

[0035] Specifically, once each core boots up and begins running its main function, the first step is to initialize the peripheral resources required by each core. The second step is to create a running task. Each core creates a task handle to be executed and adds it to the task queue, awaiting task allocation and scheduling. After completing these tasks, cores other than Core 0 call the xPortStartScheduler function to initiate interrupt initialization for each core and trigger an SVC interrupt to initiate the first task's switching schedule.

[0036] Step 3.2: When starting the Cortex-M85, perform basic kernel initialization on Core0. The content of the basic kernel initialization further includes creating idle tasks (i.e., Idle tasks) and timer tasks for all Cores in the FreeRTOS operating system.

[0037] Specifically, during the startup of Core0, after creating the tasks to be executed by itself, it is also necessary to create an Idle task for each Core and assign it a corresponding execution Core. At the same time, a timer task needs to be created for the software timer task implementation of the entire OS (i.e., operating system). It should be noted that since the tasks of each Core in the FreeRTOS operating system are different, some peripheral resources may be used by a certain Core alone. Therefore, when initializing the peripheral resources in the basic initialization of the core, each Core only initializes the peripheral resources that it uses alone. When initializing the peripheral resources in the basic initialization of the kernel, Core0 initializes the common peripheral resources, and the initialization of the common peripheral resources can be completed by Core0.

[0038] Step 3.3: Initialize the kernel interrupt of Core0. The kernel interrupt initialization further includes initializing the SysTick interrupt based on the kernel interrupt initialization, so as to manage the time task scheduling of the entire OS.

[0039] The kernel interrupt initialization process of Core0 is as follows Figure 1 As shown, Core0 first initializes the SysTick interrupt. Specifically, in the Cortex-M85 core, the SysTick interrupt number is -1. To complete the porting, the SysTick peripheral and interrupt must be configured, and the corresponding interrupt service interface functions must be bound to the Cortex-M85 interrupt vector table. Core0 then initializes the PendSVC, SVCall, and YieldCore interrupts. This process involves setting interrupt priorities and binding the corresponding interrupt entry function addresses. After this is complete, Core0 sets the current core's start flag to 1. Core0 then calls the vStartFirstTask function, sets the current core's interrupt vector table (VTOR: Vector Table Offset Register), and sets the corresponding interrupt entry address to the corresponding register. Finally, it triggers an SVCall interrupt to initiate task scheduling within the SVCall interrupt. This process ensures that each core is initialized correctly and efficiently, laying the foundation for stable operation of the entire system.

[0040] This solution takes into account that a SysTick Timer has been implemented in the Cortex-M85 core, which supports the use of processor clock or external clock source, and the count reload value range is 0x00000001-0x00FFFFFF. Therefore, Core0's SysTick is chosen as the system clock of FreeRTOS. Core0 is responsible for implementing the system's clock counting and task switching functions, and other Cores only need to wait for the task switch to be triggered, and then execute their respective tasks. Therefore, the SysTick initialization process is only executed in the initialization task of Core0, and other Cores do not need to initialize their own SysTick. This solution does not need to consider specific MCU platform timer peripherals, but only needs to implement FreeRTOS porting at the kernel level. This simplified solution helps improve porting efficiency and reliability, and ensures that FreeRTOS runs stably on the Cortex-M85 core. Specifically, the SysTick initialization process and interrupt task processing process are as follows, refer to Figure 2 As shown:

[0041] 1. Configure the SysTick interrupt priority. Since the SysTick interrupt number is -1, the corresponding configuration register is bits 28 to 31 of SHPR3. By default, we need to configure it to the highest priority. Since the Cortex-M85 core supports 8 levels of priority, we can directly write data 0.

[0042] 2. Select the SysTick clock source. The Cortex-M85 core supports the internal system clock or the external extended clock. To ensure universal porting, select the system clock as the SysTick clock source. This requires setting bit 2 of the CTRL register to 1.

[0043] 3. Clear the SysTick Value register and set the CURRENT_VALUE register to 0.

[0044] 4. Configure the LOAD register. Configure the LOAD register according to the system clock frequency. Taking the FreeRTOS SysTick period of 1ms as an example, at a main frequency of 100MHz, the value of the LOAD register should be 100*10^6 / 1000-1=99999.

[0045] 5. Enable SysTick counting and interrupts. Set bit 0 and bit 1 of the CTRL register to 1.

[0046] It's important to note that kernel interrupt initialization must begin only after all cores in the core have completed basic initialization and core interrupt initialization. During the multi-core FreeRTOS operating system startup process, SysTick is initialized in Core0, and periodic time-slice task switching is determined and handled by Core0's SysTick interrupt task. Therefore, OS task switching scheduling begins after Core0 completes startup and normal operation. If the assigned core has not started and initialized properly at this point, task execution errors will occur. Therefore, Core0 must wait for all other cores to complete initialization before performing its own interrupt initialization. Once Core0 completes initialization, system task scheduling begins. Furthermore, the xPortStartScheduler function is executed during kernel interrupt initialization. In FreeRTOS's SMP task scheduling implementation, each core maintains its own queue of pending tasks, pxCurrentTCBs. Task switching to the target core can be implemented using the prvYieldCore interface function. This interface is called during the execution of system timer interrupt tasks, bursty high-priority tasks, and other tasks. Its primary purpose is to switch the currently executing task to the target core. This mechanism ensures that tasks can be switched seamlessly between cores, improving system efficiency and responsiveness.

[0047] Accordingly, the initialization process of the xPortStartScheduler function is as follows: First, the currently running CoreID is determined (obtained using the portGET_CORE_ID macro interface). If the currently running CoreID is 0, that is, Core 0 is running, it is necessary to wait for the initialization flags of other Cores. Accordingly, the basic initialization of the cores of other Cores also includes setting the startup completion flag, while the basic initialization of Core 0 also includes waiting for all Cores to complete startup and ending the wait after all Cores have completed startup. This arrangement ensures the coordination and stability of the entire system.

[0048] In summary, in this method, porting kernel task switching primarily involves interrupt initialization and task execution. In FreeRTOS, the vTaskSwitchContext function already contains the main task switching logic. For different kernel operating environments, only the content of the portYIELD_CORE interface function needs to be implemented. Within the portYIELD_CORE interface function, the interrupt triggering the kernel task switch must be implemented. This software triggering is implemented by the Cortex-M85 core's software interrupt function, with interrupt 15 specifically configured for task switching. By configuring the NVIC's STIR function, the interrupt can be software-triggered, and the vTaskSwitchContext function is called in each core's interrupt callback function to implement the actual task switch. Furthermore, normal time-slice polling task switching is led by Core0's SysTick timer. At the end of each time slice, Core0 triggers a task switch for other cores, ensuring that all cores in the system are scheduled. This method easily enables multi-core simultaneous booting of the FreeRTOS operating system on the Cortex-M85 core, providing a FreeRTOS application boot solution for multi-core MCUs based on the Cortex-M85 core. Furthermore, multi-core MCUs can achieve load balancing, ensuring that each core can fully utilize its capabilities and preventing any single core from being overloaded or idle. This simple and easy-to-implement solution optimizes only core operations and is independent of MCU peripheral implementations. This solution is highly reusable and has profound implications for enabling simultaneous multi-core booting of real-time operating systems on the Cortex-M85 core.

[0049] The present invention has been described in detail above with reference to the embodiments of the accompanying drawings. A person skilled in the art can make various modifications to the present invention based on the above description. Therefore, certain details in the embodiments should not be construed as limiting the present invention. The scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A method for synchronously starting a multi-core operating system based on the Cortex-M85 core, characterized in that: Including steps: Provides Cortex-M85 and multi-core FreeRTOS operating system; Configuring the STIR of the NVIC in the Cortex-M85 to implement a software interrupt function for the FreeRTOS operating system, and configuring the SysTick peripheral of the Cortex-M85 as a system timer for the FreeRTOS operating system; Start the Cortex-M85 and the FreeRTOS operating system, and initialize the kernel and all cores to trigger the software interrupt of each core led by SysTick, and implement the actual task switching of the corresponding core by calling the vTaskSwitchContext function of the FreeRTOS operating system within the software interrupt; wherein, The steps to initialize the kernel and all cores for adaptation include: Perform core basic initialization and core interrupt initialization on all cores. The core basic initialization includes initializing peripheral resources and creating running tasks. The core interrupt initialization includes initializing PendSVC, SVCall, YieldCore interrupts and starting the execution of the first task through the SVC interrupt. Performing basic kernel initialization on the kernel, wherein the content of the basic kernel initialization further includes creating an idle task and a timer task for all kernels in the FreeRTOS operating system based on the content of the basic kernel initialization; After the core basic initialization and core interrupt initialization of all cores are completed, core interrupt initialization is performed on the core. The content of the core interrupt initialization further includes initializing SysTick interrupt based on the content of the core interrupt initialization.

2. The method for synchronously starting a multi-core operating system based on the Cortex-M85 core according to claim 1, wherein: The process of initializing SysTick interrupt includes: Configure SysTick interrupt priority; Select the clock source of SysTick; Clear the SysTick Value register; Configure the LOAD register; Enable SysTick counting and interrupt.

3. The method for synchronously starting a multi-core operating system based on the Cortex-M85 core according to claim 2, wherein: When configuring the interrupt priority of SysTick, configure it as the highest priority.

4. The method for synchronously starting a multi-core operating system based on the Cortex-M85 core according to claim 1, wherein: When initializing peripheral resources in the core basic initialization, only the peripheral resources used by the corresponding core are initialized; when initializing peripheral resources in the core basic initialization, public peripheral resources are initialized.

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