Device communication verification method, apparatus, device, storage medium and program product

Abstract

The present application relates to a device communication verification method, apparatus, device, storage medium, and program product. The method comprises: utilizing a first proxy component to send communication configuration information to multiple host devices, the communication configuration information being used to configure the first communication data required for each host device to communicate with a target slave device; utilizing an interface component to receive the first communication data output by each host device based on an integrated circuit bus protocol, and arbitrating and determining second communication data from each first communication data to transmit the second communication data to a second proxy component simulating a target slave device; utilizing a data processing component to obtain the communication configuration information and the second communication data, and verifying, based on the communication configuration information, whether the second communication data is the target communication data to be received by the target slave device. This method can verify the accuracy of data transmission between multiple host devices and slave devices.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a device communication verification method, apparatus, device, storage medium and program product. Background Art

[0002] I2C (Inter-Integrated Circuit) is a multi-master bus that can connect multiple I2C master devices (Master) and multiple slave devices (Slave). Each slave device has an independent address, and the master device can access different devices through these addresses.

[0003] As chip complexity increases, there are scenarios where multiple host devices need to access the same slave device via the same I2C bus to obtain important information. In these situations, data transmission between these multiple host devices and the slave device undergoes data arbitration, which means that only one target host device on the bus can successfully access the slave device. To ensure the accuracy of the data transmitted to the slave device after arbitration, there is an urgent need to verify the accuracy of data transmission between multiple host devices and slave devices. Summary of the Invention

[0004] Based on this, it is necessary to provide a device communication verification method, apparatus, device, storage medium and program product that can verify the accuracy of data transmission between multiple host devices and slave devices to address the above technical problems.

[0005] In a first aspect, the present application provides a device communication verification method. Applied to a verification platform, the verification platform includes a first agent component, an interface component, a second agent component, and a data processing component. The method includes:

[0006] Using the first proxy component to send communication configuration information to multiple host devices, the communication configuration information is used to configure first communication data required for each host device to communicate with the target slave device;

[0007] Using the interface component, first communication data output by each host device is received based on the integrated circuit bus protocol, and second communication data is determined by arbitration from each first communication data, so as to transmit the second communication data to the second agent component simulating the target slave device;

[0008] The data processing component is used to obtain the communication configuration information and the second communication data, and to verify, based on the communication configuration information, whether the second communication data is the target communication data to be received by the target slave device.

[0009] In one embodiment, the first agent component includes a first driver sub-component, a first detection sub-component and a sequencer component; using the first agent component to send communication configuration information to multiple host devices includes: using the first driver sub-component to use the preset sequence data mounted on the sequencer component as the communication configuration information, and transmitting the communication configuration information from the first communication port to the multiple host devices based on a preset transmission protocol; using the first detection sub-component to obtain the communication configuration information transmitted by the first communication port, and transmitting the communication configuration information to the data processing component.

[0010] In one embodiment, the interface component includes a first interface connected between the first agent component and the multiple host devices and a second interface connected between the second agent component and the multiple host devices; the first interface transmits data based on a preset transmission protocol, and the second interface transmits data based on the integrated circuit bus protocol; the interface component is used to arbitrate and determine the second communication data from each first communication data, including: using the second interface, based on the data transmission logic of the integrated circuit bus protocol, processing the clock data and serial data in each first communication data to obtain the second communication data; the method also includes: using the first interface, based on the preset transmission protocol, transmitting the communication configuration information to the multiple host devices.

[0011] In one embodiment, the second agent component includes a second driver sub-component and a second detection sub-component; the method also includes: using the second driver sub-component to simulate the communication behavior of the target slave device to obtain the second communication data transmitted by the interface component from the second communication port, and respond to the host device corresponding to the second communication data according to the second communication data; using the second detection sub-component to obtain the second communication data transmitted by the second communication port, and transmit the second communication data to the data processing component.

[0012] In one embodiment, the second communication data includes at least the first device address, the first read-write bit and the first data bit, and responding to the host device corresponding to the second communication data according to the second communication data includes: determining whether the first device address is the pre-stored device address of the target slave device; if so, returning a response signal to the host device corresponding to the second communication data through the second communication port; transmitting the second communication data to the data processing component includes: transmitting the first device address, the first read-write bit and the first data bit to the data processing component.

[0013] In one embodiment, the data processing component is used to verify whether the second communication data is the target communication data to be received by the target slave device based on the communication configuration information, including: parsing the communication configuration information to obtain the target communication data; the target communication data at least includes the device address, target read-write bit and target data bit of the target slave device; determining whether the first device address is consistent with the device address of the target slave device, determining whether the first read-write bit is consistent with the target read-write bit, and determining whether the first data bit is consistent with the target data bit; if it is determined that the first device address is consistent with the device address of the target slave device, the first read-write bit is consistent with the target read-write bit, and the first data bit is consistent with the target data bit, then determining that the second communication data is the target communication data.

[0014] In one embodiment, the second communication data also includes a first clock frequency for transmitting the second communication data; the method also includes: using the second detection subcomponent to determine a first delay time based on the first clock frequency, and determining whether the first clock frequency meets the expected transmission conditions based on the first delay time and a preset delay expected value.

[0015] In one embodiment, determining whether the first clock frequency meets the expected transmission condition based on the first delay time and the preset delay expected value includes: determining the delay difference between the first delay time and the preset delay expected value; if the delay difference is less than the preset difference threshold, determining that the first clock frequency meets the expected transmission condition; if the delay difference is not less than the preset difference threshold, determining that the first clock frequency does not meet the expected transmission condition.

[0016] In one embodiment, the verification platform also includes a verification environment configuration component; before using the first agent component to send communication configuration information to multiple host devices, the method also includes: using the verification environment configuration component to configure the device address of the target slave device to the second driver sub-component, and configuring the preset delay expected value to the second detection sub-component.

[0017] In one embodiment, the verification platform also includes a register model, which includes multiple simulation registers that are mapped to each control register in each host device, and the identifier of each simulation register is the name of the corresponding control register; the method also includes: determining the target simulation register to be verified from the register model; determining the identifier of each target simulation register to obtain the name of the target control register to be configured in each host device; and determining the preset sequence data based on the name of the target control register to be configured in each host device.

[0018] In a second aspect, the present application also provides a device communication verification apparatus. Applied to a verification platform, the verification platform includes a first agent component, an interface component, a second agent component, and a data processing component. The apparatus includes:

[0019] a configuration module, configured to use the first proxy component to send communication configuration information to a plurality of host devices, wherein the communication configuration information is used to configure first communication data required for each host device to communicate with a target slave device;

[0020] a receiving module, configured to receive, using the interface component, first communication data output by each host device based on the integrated circuit bus protocol, and arbitrate and determine second communication data from each first communication data, so as to transmit the second communication data to the second agent component simulating the target slave device;

[0021] The verification module is used to use the data processing component to obtain the communication configuration information and the second communication data, and verify whether the second communication data is the target communication data to be received by the target slave device according to the communication configuration information.

[0022] In one embodiment, the first agent component includes a first driver sub-component, a first detection sub-component and a sequencer component; the configuration module is specifically used to: utilize the first driver sub-component to use the preset sequence data mounted on the sequencer component as the communication configuration information, and transmit the communication configuration information from the first communication port to the multiple host devices based on a preset transmission protocol; utilize the first detection sub-component to obtain the communication configuration information transmitted by the first communication port, and transmit the communication configuration information to the data processing component.

[0023] In one embodiment, the interface component includes a first interface connected between the first agent component and the multiple host devices and a second interface connected between the second agent component and the multiple host devices; the first interface transmits data based on a preset transmission protocol, and the second interface transmits data based on the integrated circuit bus protocol; the receiving module is specifically used to: utilize the second interface, based on the data transmission logic of the integrated circuit bus protocol, to process the clock data and serial data in each first communication data to obtain the second communication data; the method also includes: utilizing the first interface, based on the preset transmission protocol, to transmit the communication configuration information to the multiple host devices.

[0024] In one embodiment, the second agent component includes a second driver sub-component and a second detection sub-component; the device also includes a response module, which is used to: use the second driver sub-component to simulate the communication behavior of the target slave device to obtain the second communication data transmitted by the interface component from the second communication port, and respond to the host device corresponding to the second communication data according to the second communication data; use the second detection sub-component to obtain the second communication data transmitted by the second communication port, and transmit the second communication data to the data processing component.

[0025] In one embodiment, the second communication data includes at least the first device address, the first read-write bit and the first data bit, and the response module is specifically used to: determine whether the first device address is the pre-stored device address of the target slave device; if so, return a response signal to the host device corresponding to the second communication data through the second communication port; transmit the second communication data to the data processing component, including: transmitting the first device address, the first read-write bit and the first data bit to the data processing component.

[0026] In one embodiment, the verification module is specifically used to: parse and process the communication configuration information to obtain the target communication data; the target communication data at least includes the device address, target read-write bit and target data bit of the target slave device; determine whether the first device address is consistent with the device address of the target slave device, determine whether the first read-write bit is consistent with the target read-write bit, and determine whether the first data bit is consistent with the target data bit; if it is determined that the first device address is consistent with the device address of the target slave device, the first read-write bit is consistent with the target read-write bit, and the first data bit is consistent with the target data bit, then determine that the second communication data is the target communication data.

[0027] In one embodiment, the second communication data also includes a first clock frequency for transmitting the second communication data; the device also includes a condition judgment module, which is used to: use the second detection subcomponent to determine a first delay time according to the first clock frequency, and determine whether the first clock frequency meets the expected transmission condition based on the first delay time and the preset delay expected value.

[0028] In one embodiment, the condition judgment module is specifically used to: determine the delay difference between the first delay time and the preset delay expected value; if the delay difference is less than the preset difference threshold, determine that the first clock frequency meets the expected transmission condition; if the delay difference is not less than the preset difference threshold, determine that the first clock frequency does not meet the expected transmission condition.

[0029] In one embodiment, the verification platform also includes a verification environment configuration component; before using the first agent component to send communication configuration information to multiple host devices, the device also includes a first data module, which is used to: use the verification environment configuration component to configure the device address of the target slave device to the second driver sub-component, and to configure the preset delay expected value to the second detection sub-component.

[0030] In one embodiment, the verification platform also includes a register model, which includes multiple simulation registers that are mapped to each control register in each host device, and the identifier of each simulation register is the name of the corresponding control register; the device also includes a second data module, which is used to: determine the target simulation register to be verified from the register model; determine the identifier of each target simulation register to obtain the name of the target control register to be configured in each host device; and determine the preset sequence data based on the name of the target control register to be configured in each host device.

[0031] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the methods described in the first aspect when executing the computer program.

[0032] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect above.

[0033] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of any one of the methods in the first aspect.

[0034] The device communication verification method, apparatus, device, storage medium, and program product described above are based on a verification platform constructed including a first agent component, an interface component, a second agent component, and a data processing component. The first agent component sends communication configuration information to multiple host devices, where the communication configuration information is used to configure the first communication data required for each host device to communicate with a target slave device. The interface component receives the first communication data output by each host device based on an integrated circuit bus protocol, arbitrates and determines second communication data from each first communication data, and transmits the second communication data to a second agent component simulating a target slave device. The data processing component obtains the communication configuration information and the second communication data, and verifies whether the second communication data is the target communication data to be received by the target slave device based on the communication configuration information. In this way, based on the verification platform, a complex communication scenario between multiple host devices and a single slave device is simulated. In this scenario, the data processing component verifies whether the arbitrated data received by the second agent component simulating the target slave device is the correct target communication data based on standard communication configuration information, thereby verifying the accuracy of data transmission between multiple host devices and a single slave device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 A diagram illustrating an application environment of a device communication verification method in one embodiment;

[0037] Figure 2 1 is a flow chart of a device communication verification method according to an embodiment;

[0038] Figure 3 A schematic diagram of the structure of a verification platform in one embodiment;

[0039] Figure 4 A schematic diagram of a process for sending communication configuration information in one embodiment;

[0040] Figure 5 A schematic diagram of the connection of interface components in a verification platform in one embodiment;

[0041] Figure 6 is a schematic diagram of a process for transmitting second communication data in one embodiment;

[0042] Figure 7 is a schematic diagram of a process of responding to a host device in one embodiment;

[0043] Figure 8 A schematic diagram of a process for verifying second communication data in one embodiment;

[0044] Figure 9 A schematic diagram of the internal interface of a data processing component in one embodiment;

[0045] Figure 10 A schematic diagram of the structure of another verification platform in one embodiment;

[0046] Figure 11 A schematic diagram of a verification method flow chart in one embodiment;

[0047] Figure 12 A structural block diagram of a device communication verification apparatus in one embodiment;

[0048] Figure 13 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned purposes, features and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description to facilitate a full understanding of the present application, but the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0051] It will be understood that "at least one" means one or more, and "a plurality of" means two or more.

[0052] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0053] The I2C bus is a serial, half-duplex bus that transmits data via two bidirectional signal lines (clock line SCL and data line SDA). The I2C bus is a multi-master bus that can connect multiple I2C master devices (Master) and multiple slave devices (Slave). A master device can access different slave devices. When two or more master devices access the same or different slave devices, clock synchronization and data arbitration are performed to ensure that only one master device on the bus can take control of the bus and transmit data with the corresponding slave device. Due to its simple hardware structure, low pin count, and the ability for multiple devices to communicate efficiently while sharing the same bus, the I2C bus has become widely used for communication between multiple devices on a chip.

[0054] As chip complexity increases, GPU (graphics processing unit) chips require multiple master devices to access the same slave device via the same I2C bus. Data transmission between multiple master devices and a single slave often requires arbitration, resulting in only one master successfully accessing the slave. The remaining masters lose bus control and data is lost. To ensure that all master devices can access the same slave effectively, the arbitration process for multi-master data transmission must be clearly understood. This ensures that a master that loses bus control during arbitration can successfully access the slave device during subsequent data transmissions. Currently, it is not possible to verify the accuracy of data transmission between multiple master devices and a single slave device connected on the same I2C bus.

[0055] To address the problem that the accuracy of data transmission between multiple host devices and a single slave device connected on the same I2C bus cannot be verified, an embodiment of the present application proposes a verification platform for communication between multiple host devices and a single slave device connected on the same I2C bus based on the UVM verification methodology. Based on this verification platform, a complex test scenario in which multiple host devices communicate with a single slave device simultaneously or with time intervals is simulated. Using a device communication verification method, clock synchronization and data arbitration between multiple devices are achieved, and the accuracy of data transmission between the multiple host devices and the single slave device is verified.

[0056] The device communication verification method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown in FIG. , the verification platform can be deployed on a computer device 101, and the verification platform includes a first agent component, an interface component, a second agent component, and a data processing component. Multiple host devices 102 communicate with the computer device 101 as DUTs (Design Under Test), thereby communicating with the verification platform.

[0057] The computer device 101 uses a first agent component in the verification platform to send communication configuration information to multiple host devices 102. The communication configuration information is used to configure the first communication data required for each host device 102 to communicate with the target slave device. The interface component receives the first communication data output by each host device 102 based on the integrated circuit bus protocol, and arbitrates and determines second communication data from each first communication data, so as to transmit the second communication data to the second agent component simulating the target slave device. The data processing component obtains the communication configuration information and the second communication data, and verifies whether the second communication data is the target communication data to be received by the target slave device based on the communication configuration information. The computer device 101 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, or servers. The server can be implemented as a standalone server or a server cluster consisting of multiple servers. It is understood that the verification platform includes the first agent component, the interface component, the second agent component, and the data processing component, all of which can be implemented using software algorithms.

[0058] In one embodiment, Figure 2 As shown, a device communication verification method is provided, which is applied to Figure 1 Taking the computer device 101 in the example as an example, the method includes the following steps:

[0059] Step 201: Use a first agent component to send communication configuration information to multiple host devices.

[0060] The communication configuration information is used to configure the first communication data required for each host device to communicate with the target slave device. In other words, each host device sends corresponding first communication data to communicate with the target slave device, and each first communication data is generated based on the communication configuration information.

[0061] Optionally, the communication configuration information is pre-deployed by the developer to the first agent component. Exemplarily, after launching the verification platform, the test case is executed, thereby configuring the communication configuration information contained in the test case to the first agent component. Optionally, the verification platform is built based on the UVM (Universal Verification Methodology) verification framework. For ease of understanding, this example is used below for illustration.

[0062] For example, taking the device to be tested as including host device 1, host device 2 and host device 3, the communication configuration information is used for host device 1 to determine the first communication data 1 required for communicating with the target slave device, for host device 2 to determine the first communication data 2 required for communicating with the target slave device, and for host device 3 to determine the first communication data 3 required for communicating with the target slave device.

[0063] Optionally, each piece of communication data includes data required for the host device to receive information from the target slave device, and / or includes data required for the host device to send information to the target slave device.

[0064] In an optional implementation, the host device communicates with the target slave device to obtain device operation information such as power consumption and temperature of the target slave device.

[0065] Optionally, the communication configuration information is transmitted between the first proxy component and each host device via a preset transmission protocol, wherein the preset transmission protocol may be different from the I2C protocol.

[0066] Step 202: using the interface component to receive first communication data outputted by each host device based on the integrated circuit bus protocol, and arbitrating and determining second communication data from each first communication data, so as to transmit the second communication data to the second agent component simulating the target slave device.

[0067] Optionally, the communication configuration information is received by each host device and written into a control register of each host device, so that each host device can access the target slave device at a corresponding time based on the first communication data in the control register.

[0068] Optionally, each master device may communicate with the target slave device simultaneously or at intervals based on the corresponding first communication data. For example, each master device may simultaneously send to-be-processed data to the target slave device at a first moment based on the corresponding first communication data. It is understood that the to-be-processed data sent by each master device may be different. The first communication data may include clock data and serial data, and the serial data may include the to-be-processed data. The clock data is typically transmitted via the serial clock line (SCL) of the I2C bus, and the serial data is typically transmitted via the serial data line (SDA) of the I2C bus.

[0069] To verify the accuracy of I2C (Integrated Circuit Bus) communication between multiple master devices and a single slave, an interface component was built into the verification platform. This component receives first communication data from each master device based on the I2C bus protocol and arbitrates the data from each first communication data to determine the second communication data. In other words, the interface component simulates the data arbitration process of an actual I2C bus based on the I2C protocol, arbitrating multiple sets of first communication data to obtain a single set of second communication data.

[0070] The verification platform further includes a second proxy component, and the second proxy component can simulate the target slave device to receive data. In this way, the second proxy component can replace the target slave device to obtain the second communication data.

[0071] Step 203: using the data processing component to obtain the communication configuration information and the second communication data, and verifying whether the second communication data is the target communication data to be received by the target slave device according to the communication configuration information.

[0072] In one optional implementation, the first agent component is connected to the data processing component. When the first agent component sends the communication configuration information to each host device, it also sends the communication configuration information to the data processing component. In another optional implementation, after the test case is executed, the communication configuration information is configured to be stored in the data processing component.

[0073] Furthermore, the second proxy component is connected to the data processing component. After acquiring the second communication data, the second proxy component not only responds to the host device based on the second communication data, but also forwards the second communication data to the data processing component.

[0074] Based on this, the data processing component can determine the target communication data that the target slave device should have accurately received according to the communication configuration information, thereby determining whether the second communication data is the target communication data.

[0075] It is understandable that if the second communication data is the target communication data, it means that the transmission between the host device and the target slave device is correct, thereby verifying the effectiveness and accuracy of the communication between the multi-host device and the single slave device.

[0076] The device communication verification method is based on a verification platform constructed including a first agent component, an interface component, a second agent component, and a data processing component. The first agent component sends communication configuration information to multiple host devices. The communication configuration information is used to configure the first communication data required for each host device to communicate with a target slave device. The interface component receives the first communication data output by each host device based on an integrated circuit bus protocol, and arbitrates and determines the second communication data from each first communication data, thereby transmitting the second communication data to a second agent component simulating a target slave device. The data processing component obtains the communication configuration information and the second communication data, and verifies whether the second communication data is the target communication data to be received by the target slave device based on the communication configuration information. In this way, based on the verification platform, a complex communication scenario between multiple host devices and a single slave device is simulated. In this scenario, the data processing component verifies whether the arbitrated data received by the second agent component simulating the target slave device is the correct target communication data based on standard communication configuration information, thereby verifying the accuracy of data transmission between multiple host devices and a single slave device.

[0077] In one embodiment, the preset transmission protocol is the Advanced eXtensible Interface (AXI) protocol. AXI is a bus protocol primarily used for high-performance, high-bandwidth, and low-latency on-chip bus designs. It supports unidirectional or bidirectional data flow and provides multiple addressing modes and flow control mechanisms to accommodate various complex design scenarios.

[0078] In other words, data is transmitted between the first agent and each host device based on the AXI protocol.

[0079] In one embodiment, Figure 3 This example illustrates the structure of a verification platform. A first agent component includes a first driver subcomponent, a first detection subcomponent, and a sequencer component. The interface component includes a first interface connecting the first agent component to multiple host devices and a second interface connecting the second agent component to multiple host devices. The second agent component includes a second driver subcomponent and a second detection subcomponent. The verification platform also includes a verification environment configuration component and a register model.

[0080] Optionally, to facilitate integration, in an embodiment of the present application, the verification platform includes a verification environment component, which encapsulates the first agent component, the second agent component, the register model, and the data processing component. Exemplarily, the verification environment component is constructed using UVM methodologies such as uvm_component, the phase mechanism, and the register model. The top level (environment) of the verification environment component inherits from uvm_env, layering and encapsulating the associated components, which can be reused as a sub-environment in higher-level system-level verification.

[0081] In one embodiment, the verification platform also includes executable test cases. After being executed, the test cases are used to construct verification scenarios for the DUT in the verification platform, including, for example, initializing the DUT through the verification platform, configuring parameters and instantiating verification environment configuration components, instantiating verification environment components, randomizing data packets to be sent, and determining data packets to be sent.

[0082] The following describes each component based on this.

[0083] In one embodiment, Figure 4 A schematic diagram of a process for sending communication configuration information is shown. Using a first agent component to send communication configuration information to multiple host devices includes:

[0084] Step 401: Using a first driver subassembly, the preset sequence data mounted on the sequencer assembly is used as communication configuration information, and the communication configuration information is transmitted from a first communication port to a plurality of host devices based on a preset transmission protocol.

[0085] Step 402: Utilize the first detection subcomponent to obtain the communication configuration information transmitted by the first communication port, and transmit the communication configuration information to the data processing component.

[0086] The first agent component includes a first driver subcomponent, a first detection subcomponent, and a sequencer component. The first driver subcomponent is a driver, the first detection subcomponent is a detector, and the sequencer component is a sequencer.

[0087] The second proxy module accesses the DUT's registers by simulating the AXI bus protocol. Optionally, the sequencer component connects to the first driver subcomponent via a TLM (Transaction Level Modeling Port) communication port in UVM. In a test case, when accessing DUT registers is required, pre-set sequence data (Sequence) is mounted on the sequencer and passed to the first driver subcomponent via the port, allowing it to obtain communication configuration information. The first driver subcomponent then sends stimuli to the DUT's registers via the first communication port with the DUT according to the AXI protocol.

[0088] Furthermore, the first detection subassembly can monitor the first communication port in real time. Thus, when communication configuration information arrives at the first communication port, the first detection subassembly can detect and obtain the communication configuration information. The first detection subassembly is connected to the data processing assembly via the first transmission port, and thus can transmit the communication configuration information to the data processing assembly via the first transmission port.

[0089] Exemplarily, the second agent component inherits from uvm_agent and belongs to the uvm_component component. It simulates the AXI4 bus protocol to configure the registers of the DUT, and then initializes the DUT through the register configuration, so that multiple host devices in the DUT can send first communication data (including clock data and serial data) that conforms to the I2C protocol simultaneously or intermittently.

[0090] During the instantiation of the second agent component, the first driver subcomponent, the first detection subcomponent, and the sequencer component are instantiated during the agent's construction phase. Furthermore, during the initialization phase (connect phase), the uvm_seq_item_pull_port of the first driver subcomponent is connected to the uvm_seq_item_pull_imp port of the sequencer component to enable communication between the first driver subcomponent and the sequencer component. The first driver subcomponent obtains the required communication configuration information from the sequencer component and sends data to the DUT via the first communication interface according to the AXI protocol, for example, based on the AXI4 protocol. The first detection subcomponent simultaneously obtains the communication configuration information by monitoring the first communication port and sends the communication configuration information to the data processing component via the first transmission port, uvm_analysis_port1.

[0091] In the embodiment of the present application, the first driver subcomponent and the first detection subcomponent can be used to connect the first proxy component with different objects, so that both the DUT and the data processing component can obtain communication configuration information, thereby improving the flexibility of data transmission.

[0092] In one embodiment, as described above, the interface component includes a first interface connected between the first agent component and the plurality of host devices and a second interface connected between the second agent component and the plurality of host devices.

[0093] The first interface transmits data based on a preset transmission protocol, and the second interface transmits data based on an integrated circuit bus protocol.

[0094] In one embodiment, an interface component is used to arbitrate and determine second communication data from each first communication data, including: using a second interface, based on the data transmission logic of the integrated circuit bus protocol, processing the clock data and serial data in each first communication data to obtain the second communication data.

[0095] The interface component serves as a bridge for communication between the verification platform and the DUT, and includes a first interface and a second interface. Based on the protocols used by the interfaces, it can be considered that the first interface is an AXI interface and the second interface is an I2C interface. Figure 5 The following is an illustrative diagram of the connection of interface components in the verification platform.

[0096] Exemplarily, the I2C interface receives the first communication data (including SCL data and SDA data) sent by each host device, and through a preset assignment operation statement, the SDA data and SCL data input by multiple host devices are ANDed, and finally a group of data is output to the first proxy component, that is, the second communication data is obtained.

[0097] Optionally, the default assignment statement is the assign statement. The assign statement is used to assign the value of an expression to a signal or variable.

[0098] In one embodiment, the method further includes: utilizing the first interface to transmit the communication configuration information to the plurality of host devices based on a preset transmission protocol.

[0099] In other words, the first interface transmits the communication configuration information output by the first communication port to each host device based on the AXI protocol.

[0100] In the embodiment of the present application, by setting interfaces of different protocols, the route for the first agent component in the verification platform to configure the DUT and the route for the DUT to send data to the second agent component are separated to ensure accurate data transmission.

[0101] In one embodiment, Figure 6 A schematic diagram of a process for transmitting second communication data is shown, and the method further includes:

[0102] Step 601: Use the second driver subassembly to simulate the communication behavior of the target slave device to obtain second communication data transmitted by the interface component from the second communication port, and respond to the host device corresponding to the second communication data according to the second communication data.

[0103] Step 602: Utilize the second detection subcomponent to obtain second communication data transmitted by the second communication port, and transmit the second communication data to the data processing component.

[0104] The second agent component includes a second driving subcomponent and a second detecting subcomponent. The second driving subcomponent is also a driver, and the first detecting subcomponent is also a detector.

[0105] In other words, the second communication data transmitted by the interface component is acquired by the second driving sub-component and the second detecting sub-component via the second communication port.

[0106] Exemplarily, the second agent component inherits from uvm_agent and belongs to the component component. Compared to the first agent component, in the embodiment of the present application, the second agent component acts as a simulation module of the target slave device and responds to data sent by the host device. The generation and transmission of stimuli are achieved by configuring the registers of the DUT, rather than by the second agent component in the verification environment. Therefore, the second agent component in the embodiment of the present application does not need to instantiate a sequencer, and only encapsulates the driver and detector.

[0107] In one embodiment, Figure 7 A schematic diagram of a process for responding to a host device is shown. Responding to the host device corresponding to the second communication data according to the second communication data includes:

[0108] Step 701: Determine whether the first device address is a pre-stored device address of a target slave device.

[0109] Step 702: If yes, return a response signal to the host device corresponding to the second communication data through the second communication port.

[0110] The host device connected to the I2C bus can access different slave devices through the device addresses of the slave devices. Therefore, the second communication data includes the first device address, which represents the device address of the slave device that the host device corresponding to the second communication data needs to access this time.

[0111] In addition, the second communication data further includes a first read / write bit and a first data bit, which are used for the slave device receiving the second communication data to perform a read operation and / or a write operation on the data.

[0112] Exemplarily, the second driver sub-component pre-stores the device address of the target slave device. Therefore, the second driver sub-component can determine whether the first device address is the pre-stored device address of the target slave device. Thus, if the first device address is determined to be the pre-stored device address of the target slave device, it is determined that the second communication data is indeed what the host device needs to send to the target slave device, and the second proxy component simulates the target slave device and should therefore receive the second communication data. Based on this, the second driver sub-component returns a response signal to the host device corresponding to the second communication data via the second communication port. The response signal is used to indicate that the target slave device has received the second communication data.

[0113] Optionally, the second communication data may further include a start bit, a stop bit, etc., which are not fully illustrated here.

[0114] Exemplarily, the second driver subcomponent inherits from uvm_driver and can obtain information such as the first start bit, the first device address, the first read / write bit, the first data bit, and the first stop bit based on the clock data and serial data in the second communication data transmitted from the second communication port. It determines whether a correct response signal is returned based on the received first device address; performs a write or read operation based on the first read / write bit; determines the starting position of the write or read operation based on the first start bit; and determines the ending position of the write or read operation based on the first stop bit. The data to be written or read is determined by the first data bit.

[0115] Exemplarily, the second driver subassembly responds differently based on the clock data and serial data of the second communication data. If a bit in the data is 0, the second driver subassembly drives the SDA data line and weakly pulls up the SDA and SCL data lines of the master and slave devices in the I2C interface through assign statements. This allows the I / O interfaces of multiple master and slave devices to constantly monitor changes in the SCL and SDA data on the I2C bus, thus achieving clock synchronization and data arbitration when multiple I2C master devices communicate with a single slave device.

[0116] In one embodiment, transmitting the second communication data to the data processing component includes transmitting the first device address, the first read / write bit, and the first data bit to the data processing component.

[0117] Optionally, the second detection subassembly can monitor the second communication port in real time, so that the second detection assembly can capture the second communication data when it is transmitted via the second communication port. The second detection subassembly is connected to the data processing assembly via the second transmission port, and thus can transmit the first device address, the first read / write bit, and the first data bit to the data processing assembly via the second transmission port. The second transmission port can be a TLM communication port.

[0118] Exemplarily, the second detection subcomponent is inherited from uvm_monitor, and collects the second communication data, and sends the slave device address, read / write bit, data bit and other data to the data processing component through the second transmission port uvm_analysis_port2.

[0119] In addition, in the embodiment of the present application, the second detection component can also perform clock frequency check on the clock data.

[0120] In an optional implementation, the method further includes: using a second detection subcomponent to determine a first delay time according to the first clock frequency, and determining whether the first clock frequency meets the expected transmission condition according to the first delay time and a preset delay expected value.

[0121] The second communication data further includes a first clock frequency for transmitting the second communication data.

[0122] The second detection subassembly is pre-configured with a clock frequency mapping table that includes multiple sets of correspondences between different clock frequencies and delay times. Therefore, the first delay time can be obtained by querying the clock frequency mapping table based on the first clock frequency. Furthermore, the second detection subassembly stores a preset expected delay value, which serves as the accurate delay time.

[0123] In an optional implementation, determining whether the first clock frequency meets the expected transmission conditions is performed based on the first delay time and the preset delay expected value, including: determining the delay difference between the first delay time and the preset delay expected value; if the delay difference is less than the preset difference threshold, determining that the first clock frequency meets the expected transmission conditions; if the delay difference is not less than the preset difference threshold, determining that the first clock frequency does not meet the expected transmission conditions.

[0124] In other words, the first delay time can be compared with the preset delay expected value to determine whether the delay difference between the first delay time and the preset delay expected value is less than the preset difference threshold. If it is less than, it means that the first delay time is basically consistent with the preset delay expected value, and it is determined that the data transmission frequency between the current host device and the slave device is accurate, that is, it meets the expected transmission conditions; conversely, if it is not less than, it means that the first delay time is significantly different from the preset delay expected value, and it is determined that the data transmission frequency between the current host device and the slave device is inaccurate, that is, it does not meet the expected transmission conditions.

[0125] In one embodiment, the method further includes sampling second communication data from the second communication port according to the first delay time using a second detection subcomponent.

[0126] In one embodiment, the method further includes sampling second communication data from the second communication port according to the first delay time by a second driving subassembly.

[0127] In this way, the verification platform can support different transmission rates of the I2C bus protocol and receive data sent by the host device at different transmission rates.

[0128] In one embodiment, Figure 8 The process of verifying the second communication data is shown as a schematic diagram. The process of verifying whether the second communication data is the target communication data to be received by the target slave device using the data processing component according to the communication configuration information includes:

[0129] Step 801: parse and process the communication configuration information to obtain target communication data.

[0130] The target communication data at least includes a device address of a target slave device, a target read / write bit, and a target data bit.

[0131] Here, the data processing component can determine the first communication data that each host device will send to the target slave device based on the communication configuration information obtained by the first detection sub-component, and can determine the accurate expected data that the target slave device should receive under accurate arbitration. Therefore, the expected data can be used as the target communication data, and finally compared with the second communication data obtained from the second detection sub-component.

[0132] Optionally, the data processing component is a pre-built reference model (Reference model), which is deployed in the verification platform and can perform task processing on each first communication data in the communication configuration information to determine the target communication data that the target slave device should receive under standard conditions.

[0133] Step 802 , determining whether the first device address is consistent with the device address of the target slave device, determining whether the first read / write bit is consistent with the target read / write bit, and determining whether the first data bit is consistent with the target data bit.

[0134] Step 803 : If it is determined that the first device address is consistent with the device address of the target slave device, the first read / write bit is consistent with the target read / write bit, and the first data bit is consistent with the target data bit, then the second communication data is determined to be the target communication data.

[0135] For example, the data processing component inherits from uvm_component. Figure 9 The diagram shows the internal interface of the data processing component. The data processing component instantiates two buffers: a first buffer called uvm_tlm_analysis_fifo(A) and a second buffer called uvm_tlm_analysis_fifo(I). It also instantiates two internal transmission ports: a first internal port called uvm_get_port(A) and a second internal port called uvm_get_port(I). The two buffers each instantiate a set of internal communication ports: a first communication port called uvm_analysis_imp and a second communication port called uvm_get_imp.

[0136] The communication configuration data obtained by the first driver subassembly from the first communication port is output via the first transmission port to the first communication port in the first buffer of the data processing assembly. At this point, the communication configuration data is temporarily stored in the first buffer. The first internal port of the data processing assembly interfaces with the second communication port in the first buffer. Therefore, after the communication configuration data is output from the second communication port in the first buffer, it is retrieved by the data processing assembly via the first internal port. The data processing assembly can then parse and process the communication configuration data to determine the target communication data.

[0137] Similarly, the second driver subassembly receives the second communication data from the second communication port and outputs it to the first communication port in the second buffer of the data processing assembly via the second transmission port. At this point, the second communication data is temporarily stored in the second buffer. The second internal port of the data processing assembly interfaces with the second communication port in the second buffer, allowing the data processing assembly to access the second communication data output from the second communication port in the second buffer via the second internal port. Specifically, the data processing assembly obtains the first device address, the first read / write bit, and the first data bit.

[0138] The data processing component can then compare the target communication data with the second communication data to verify whether the correct data is obtained.

[0139] In one embodiment, before using the first proxy component to send communication configuration information to multiple host devices, the method also includes: using the verification environment configuration component to configure the device address of the target slave device to the second driver subcomponent, and configuring the preset delay expectation value to the second detection subcomponent.

[0140] The verification platform also includes a verification environment configuration component, which is used to configure the second agent component in the verification environment according to the different clock frequencies of the DUT. The configuration content includes the device address of the target slave device and the delay time required by the second driver subcomponent and the second detection subcomponent when driving signals and sampling data at different clock frequencies, that is, the preset delay expected value. This component is also used to configure the aforementioned clock frequency correspondence table in the second detection subcomponent.

[0141] Exemplarily, the verification environment configuration component (Config) inherits from uvm_object and is used to configure the I2C agent, including information such as the slave device address and the delay required under different clock frequencies. Before initializing the verification platform, these configuration parameters are pre-configured to the second driver sub-component and the second detection sub-component through uvm_config_db. In this way, the second detection sub-component can check whether the clock data in the second communication data sent by the DUT meets the requirements based on the configured preset delay expected value.

[0142] Among them, since the preset delay expectation value is pre-configured using the verification environment configuration component, it can be understood that if the transmission rate of the DUT is switched from standard mode to fast mode, that is, the transmission rate changes, then only the preset delay expectation value in the verification environment configuration file can be modified without modifying other components of the verification platform. Based on the new transmission rate, the second communication data can be obtained and communicated with each host device. Therefore, the verification platform has good reusability.

[0143] It can be seen that the verification platform, based on test cases and various verification components, simulates complex test scenarios in which multiple host devices communicate with a single slave device simultaneously or with time intervals at different I2C transmission rates, ensuring the accuracy of data when multiple host devices communicate with a single slave device.

[0144] In one embodiment, as mentioned above, the verification platform further includes a register model, which includes a plurality of simulation registers mapped to control registers in each host device, and the identifier of each simulation register is the name of the corresponding control register.

[0145] In one embodiment, the method further includes: determining a target simulation register to be verified from a register model; determining an identifier of each target simulation register to obtain a name of a target control register to be configured in each host device; and determining preset sequence data based on the name of the target control register to be configured in each host device.

[0146] Test cases are used to instantiate components within the entire test environment and initialize the DUT. When a test case is executed, the target simulation register to be verified is determined based on the register model, and the identifier of the target simulation register can also be determined. The identifier of each target simulation register is the name of the target control register to be configured. Therefore, determining the identifier can yield the name of the target control register to be configured.

[0147] In this way, when the target to be configured (i.e., the name of the target control register to be configured) is determined, the preset sequence data can be determined in combination with other configuration information, and mounted on the sequencer, i.e., the sequencer component of the first agent component, so that the first agent component determines the communication configuration information based on the preset sequence data and configures the DUT.

[0148] It can be understood that when the verification platform is used to verify the communication process between several other host devices and another slave device, it is only necessary to set the names of the control registers in the host devices to be verified to the names of the analog registers pre-stored in the register model, so that the register model can be matched with the registers in the DUT. In this way, each time the DUT is changed for verification, there is no need to modify the register model in the verification platform. Only the names of the registers in the DUT need to be changed, and the verification platform can be reused to verify the DUT. Therefore, the verification platform has higher reusability.

[0149] For example, the verification platform includes a test case component, which contains multiple test cases (Testcases). These can be categorized as basic test cases and functional test cases. The basic test case inherits from uvm_test and includes instantiations of the verification environment configuration component and the verification environment component. The functional test case inherits from the basic test case and includes configuring the target control registers required for DUT initialization and data transmission using the register model. The configuration data in the verification environment configuration component is modified based on the clock frequency required by the DUT to meet the delay time required for driving signals and sampling by the second driver subcomponent and the second detection subcomponent at different clock frequencies.

[0150] Exemplarily, the register model is inherited from uvm_reg_block, and can access the control registers of the DUT through the front door and the back door. The front door access can configure the domains of each register of the DUT separately. In essence, it is to call the preset sequence data to mount it on the sequencer component, and simulate the AXI bus to access the control registers of the DUT through the first driver subcomponent. In the optional embodiment of the present application, the register configuration of the DUT is all accessed through the front door of the register model. In addition, if the back door is used to access the register, the value of the register can be written or read without consuming simulation time. The register model is used to directly send a specific address from the AXI bus to configure the entire register. Subsequent modifications to the register address or changes in the domain only require changing the configuration of the domain in the register model, without having to modify the configuration of the register in the test case, thereby improving the reusability of the test case.

[0151] For ease of understanding, the following describes a complete embodiment of the UVM-based verification platform provided by this application and the device communication verification method for verifying the process of implementing communication between multiple host devices and a single slave device through an I2C bus using the verification platform.

[0152] Please refer to Figure 10 , shows a schematic diagram of the structure of a verification platform. The verification platform includes a verification environment component, an interface component, a verification environment configuration component, and a test case component (not shown in the figure).

[0153] The verification environment component encapsulates multiple reusable verification components and organizes them into related layers. Specifically, the verification environment component consists of an I2C slave agent, an AXI agent, a register model, and a reference model.

[0154] The I2C agent encapsulates the driver and the detector together, and communicates with the device under test (DUT) by simulating the behavior of the slave device. The driver obtains the SCL clock data and SDA data from the I2C interface according to the I2C bus protocol timing, and responds to the host device according to the specific content of the SCL clock data and SDA data; the detector obtains the SCL clock data and SDA data through the I2C interface, and passes the address bit (Address), read / write bit and data bit (Data) information in the data to the reference model through the TLM port of UVM according to the I2C protocol. In addition, the detector also performs frequency check on the SCL clock data.

[0155] The AXI agent consists of a driver, a detector, and a sequencer, simulating the AXI bus protocol to access the DUT's registers. The sequencer connects to the driver via the TLM communication port in UVM. To access DUT registers in a test case, a sequence is attached to the sequencer, which then passes data to the driver via the port. The driver sends stimuli to the DUT's registers via the AXI interface according to the AXI protocol. Furthermore, the detector monitors the AXI interface to acquire data sent by the driver and transmits this data to the reference model.

[0156] The register model contains multiple registers (uvm_reg) and register fields (uvm_reg_field). The register model can be used to access the DUT's registers through the register names instead of directly accessing them through the specific register addresses. Later changes to the register addresses do not affect the use of the register model in the test case, thereby improving the reusability of the test case.

[0157] The reference model receives information such as address bits, read / write bits, and data bits from the I2C detector through a TLM port. It also receives register configuration data from the AXI detector through another TLM port. The reference model processes the data from the AXI detector to obtain expected values ​​and compares them with the data from the I2C detector.

[0158] The Verification Environment Configuration component configures the I2C agent in the verification environment based on the DUT's clock frequency. The configuration includes the slave device address, the delay time required for the driver and detector to drive the signal, and the sampling time at different clock frequencies.

[0159] Interfaces serve as a bridge for data communication between verification environment components and the DUT, including I2C and AXI interfaces. The I2C interface receives SCL and SDA data from the host device, implements clock synchronization and data arbitration through the I2C bus's wired-AND logic, and ultimately outputs a set of arbitrated SCL and SDA data to the I2C agent. The AXI interface is the signal interface between the DUT and the AXI agent, containing the signals required by the AXI protocol.

[0160] The test case component is used to simulate the verification scenario for the DUT under test, including the initialization of the DUT, the configuration and instantiation of the verification environment configuration component, the instantiation of the verification environment component, the randomization of the data packets to be sent, and the sending of data packets.

[0161] In order to verify the communication between multiple host devices and a single slave device, multiple functional test cases are required, which are mainly divided into two cases: multiple host devices writing data to the slave device and multiple host devices reading data from the slave device. In order to more clearly describe the above verification method, the following is an example of the test case of multiple host devices writing data to a single slave device. Figure 11 The following is a flow chart of the verification method:

[0162] Start the verification environment through run_test in the simulation top-level file.

[0163] After the verification environment is started, the uvm_test_top instance of the corresponding test case is created according to the UVM_TEST_NAME input by the simulation, and then the UVM phase mechanism is automatically called to create each uvm_component component to form a UVM tree structure and complete the instantiation of the verification platform.

[0164] a) Based on the required SCL clock frequency and slave device address, the control register address of the DUT is configured through the register model, so that multiple I2C master devices can send SCL clock frequency data that meets the requirements, completing the initialization of the DUT. At the same time, the detector in the AXI agent passes the slave device address and other information to the reference model.

[0165] b) Configure the verification environment configuration file based on the DUT's SCL clock frequency, and pass the configuration information to the detector and driver of the I2C agent through the config_db mechanism in UVM.

[0166] c) The register model configures the data bits to be sent by multiple I2C master devices to the corresponding register addresses. The DUT sends multiple sets of SCL data streams and SDA data streams, and the detector in the AXI agent passes the I2C data bits to the reference model.

[0167] d) The I2C interface receives multiple sets of SCL and SDA data, performs clock synchronization and data arbitration, and passes the processed set of SCL and SDA data to the I2C agent. The driver in the I2C agent obtains the start bit, slave device address, read / write bit, data bit, stop bit, and other information in the I2C protocol based on the data transmitted from the I2C interface. It returns response bit information based on whether the received slave device address is correct and performs write or read operations based on the read / write bit information. In addition, the detector in the I2C agent sends the slave device address, read / write bit, data bit, and other data to the reference model via the TLM communication port and performs clock frequency checks on the SCL clock data.

[0168] e) The reference model processes the acquired register configuration data through a task to obtain the expected value of the slave device address, the expected value of the read / write bit, and the expected value of the data bit. This data is then compared with the data obtained from the detector of the I2C agent to verify the correctness of the data obtained by the I2C agent.

[0169] In the embodiment of the present application, the interface in the verification platform supports the connection of multiple host devices and a single slave device, and supports increasing or decreasing the number of host devices. At the same time, the interface realizes clock synchronization and data arbitration through the line and logic of the I2C bus protocol, and uses the assign statement of the Verilog language to enable the I / O interface of the host device and the slave device to obtain the changes of SCL data and SDA data on the bus, which fully simulates the scenario of multiple host devices and a single slave device being mounted on the same I2C bus for communication. The verification platform supports different transmission rates of the I2C bus protocol. When the transmission rate of the DUT is switched from standard mode to fast mode, only the verification environment configuration file needs to be modified, without modifying other verification platform components, and has good reusability. Through different test cases and verification components, the complex test scenario of multiple host devices communicating with a single slave device at the same time or with time intervals at different I2C transmission rates is simulated, ensuring the accuracy of data when multiple host devices communicate with a single slave device.

[0170] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0171] Based on the same inventive concept, embodiments of the present application also provide a device communication verification apparatus for implementing the aforementioned device communication verification method. The solution provided by this apparatus is similar to the solution described in the aforementioned method. Therefore, the specific limitations in one or more device communication verification apparatus embodiments provided below can be found in the limitations of the device communication verification method above and will not be further elaborated here.

[0172] In one embodiment, Figure 12 As shown, a device communication verification device is provided, which is applied to a verification platform. The verification platform includes a first agent component, an interface component, a second agent component and a data processing component. The device communication verification device 1200 includes: a configuration module 1201, a receiving module 1202 and a verification module 1203, wherein:

[0173] A configuration module 1201 is configured to use the first proxy component to send communication configuration information to multiple host devices, where the communication configuration information is used to configure first communication data required for each host device to communicate with a target slave device;

[0174] a receiving module 1202 configured to receive, using the interface component, first communication data output by each host device based on the integrated circuit bus protocol, and arbitrate and determine second communication data from each first communication data, so as to transmit the second communication data to the second proxy component simulating the target slave device;

[0175] The verification module 1203 is configured to utilize the data processing component to obtain the communication configuration information and the second communication data, and verify whether the second communication data is the target communication data to be received by the target slave device according to the communication configuration information.

[0176] In one embodiment, the first agent component includes a first driver sub-component, a first detection sub-component and a sequencer component; the configuration module 1201 is specifically used to: use the first driver sub-component to use the preset sequence data mounted on the sequencer component as the communication configuration information, and transmit the communication configuration information from the first communication port to the multiple host devices based on a preset transmission protocol; use the first detection sub-component to obtain the communication configuration information transmitted by the first communication port, and transmit the communication configuration information to the data processing component.

[0177] In one embodiment, the interface component includes a first interface connected between the first agent component and the multiple host devices and a second interface connected between the second agent component and the multiple host devices; the first interface transmits data based on a preset transmission protocol, and the second interface transmits data based on the integrated circuit bus protocol; the receiving module 1202 is specifically used to: use the first interface, based on the data transmission logic of the integrated circuit bus protocol, to process the clock data and serial data in each first communication data to obtain the second communication data; the method also includes: using the second interface, based on the preset transmission protocol, to transmit the communication configuration information to the multiple host devices.

[0178] In one embodiment, the second agent component includes a second driver sub-component and a second detection sub-component; the device also includes a response module, which is used to: use the first driver sub-component to simulate the communication behavior of the target slave device to obtain the second communication data transmitted by the interface component from the second communication port, and respond to the host device corresponding to the second communication data according to the second communication data; use the second detection sub-component to obtain the second communication data transmitted by the second communication port, and transmit the second communication data to the data processing component.

[0179] In one embodiment, the second communication data includes at least the first device address, the first read-write bit and the first data bit, and the response module is specifically used to: determine whether the first device address is the pre-stored device address of the target slave device; if so, return a response signal to the host device corresponding to the second communication data through the second communication port; transmit the second communication data to the data processing component, including: transmitting the first device address, the first read-write bit and the first data bit to the data processing component.

[0180] In one embodiment, the verification module 1203 is specifically used to: parse and process the communication configuration information to obtain the target communication data; the target communication data at least includes the device address, target read-write bit and target data bit of the target slave device; determine whether the first device address is consistent with the device address of the target slave device, determine whether the first read-write bit is consistent with the target read-write bit, and determine whether the first data bit is consistent with the target data bit; if it is determined that the first device address is consistent with the device address of the target slave device, the first read-write bit is consistent with the target read-write bit, and the first data bit is consistent with the target data bit, then determine that the second communication data is the target communication data.

[0181] In one embodiment, the second communication data also includes a first clock frequency for transmitting the second communication data; the device also includes a condition judgment module, which is used to: use the second detection subcomponent to determine a first delay time according to the first clock frequency, and determine whether the first clock frequency meets the expected transmission condition based on the first delay time and the preset delay expected value.

[0182] In one embodiment, the condition judgment module is specifically used to: determine the delay difference between the first delay time and the preset delay expected value; if the delay difference is less than the preset difference threshold, determine that the first clock frequency meets the expected transmission condition; if the delay difference is not less than the preset difference threshold, determine that the first clock frequency does not meet the expected transmission condition.

[0183] In one embodiment, the verification platform also includes a verification environment configuration component; before using the first agent component to send communication configuration information to multiple host devices, the device also includes a first data module, which is used to: use the verification environment configuration component to configure the device address of the target slave device to the second driver sub-component, and to configure the preset delay expected value to the second detection sub-component.

[0184] In one embodiment, the verification platform also includes a register model, which includes multiple simulation registers that are mapped to each control register in each host device, and the identifier of each simulation register is the name of the corresponding control register; the device also includes a second data module, which is used to: determine the target simulation register to be verified from the register model; determine the identifier of each target simulation register to obtain the name of the target control register to be configured in each host device; and determine the preset sequence data based on the name of the target control register to be configured in each host device.

[0185] Each module in the device communication verification apparatus described above may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in hardware form, or may be stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0186] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 13As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store device communication verification data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a device communication verification method is implemented.

[0187] Those skilled in the art will understand that Figure 13 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0188] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0189] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0190] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0191] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0192] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0193] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A device communication verification method, characterized in that: The method is applied to a verification platform, the verification platform including a first agent component, an interface component, a second agent component, a register model, and a data processing component, wherein the first agent component includes a first driver subcomponent, a first detection subcomponent, and a sequencer component; the register model includes a plurality of analog registers having a mapping relationship with each control register in a plurality of host devices, and the identifier of each analog register is the name of the corresponding control register; the method includes: Utilizing the first proxy component to send communication configuration information to multiple host devices, the communication configuration information is used to configure the first communication data required for each of the host devices to communicate with the target slave device; wherein each host device communicates with the target slave device simultaneously or at time intervals based on the corresponding first communication data; the data to be processed sent by each host device to the target slave device is different, and the first communication data includes clock data and serial data, and the serial data includes the data to be processed; utilizing the first proxy component to send the communication configuration information to multiple host devices includes: utilizing the first driver subcomponent to use the preset sequence data mounted on the sequencer component as the communication configuration information, and transmitting the communication configuration information from the first communication port to the multiple host devices based on a preset transmission protocol; the preset transmission protocol is the AXI protocol; wherein the process of determining the preset sequence data is as follows: determining the target simulation register to be verified from the register model; determining the identifier of each target simulation register to obtain the name of the target control register to be configured in each of the host devices; and determining the preset sequence data according to the name of the target control register to be configured in each of the host devices; Using the interface component, receiving first communication data output by each of the host devices based on an integrated circuit bus protocol, and arbitrating and determining second communication data from each of the first communication data, so as to transmit the second communication data to the second agent component simulating the target slave device; The data processing component is used to obtain the communication configuration information and the second communication data, and to verify, based on the communication configuration information, whether the second communication data is the target communication data to be received by the target slave device.

2. The method according to claim 1, characterized in that The process of the data processing component acquiring the communication configuration information includes: The communication configuration information transmitted by the first communication port is acquired by utilizing the first detection subcomponent, and the communication configuration information is transmitted to the data processing component.

3. The method according to claim 1, characterized in that The interface component includes a first interface connected between the first proxy component and the plurality of host devices and a second interface connected between the second proxy component and the plurality of host devices; The first interface transmits data based on a preset transmission protocol, and the second interface transmits data based on the integrated circuit bus protocol; arbitrating and determining second communication data from each of the first communication data using the interface component, comprising: Using the second interface, based on the data transmission logic of the integrated circuit bus protocol, the clock data and the serial data in each of the first communication data are processed to obtain the second communication data; The method further comprises: The communication configuration information is transmitted to the plurality of host devices using the first interface based on the preset transmission protocol.

4. The method according to claim 1, wherein The second agent component includes a second driving subcomponent and a second detecting subcomponent; the method further includes: Using the second driver subassembly, simulating the communication behavior of the target slave device to obtain the second communication data transmitted by the interface component from the second communication port, and responding to the host device corresponding to the second communication data according to the second communication data; The second detection subcomponent is used to acquire the second communication data transmitted by the second communication port, and transmit the second communication data to the data processing component.

5. The method according to claim 4, characterized in that The second communication data includes at least a first device address, a first read / write bit, and a first data bit, and responding to a host device corresponding to the second communication data according to the second communication data includes: Determining whether the first device address is a pre-stored device address of the target slave device; If so, returning a response signal to the host device corresponding to the second communication data through the second communication port; The transmitting the second communication data to the data processing component includes: The first device address, the first read / write bit, and the first data bit are transmitted to the data processing component.

6. The method according to claim 5, characterized in that Verifying, by using the data processing component according to the communication configuration information, whether the second communication data is target communication data to be received by the target slave device includes: Parsing the communication configuration information to obtain the target communication data; the target communication data at least includes a device address, a target read / write bit, and a target data bit of the target slave device; Determining whether the first device address is consistent with the device address of the target slave device, determining whether the first read-write bit is consistent with the target read-write bit, and determining whether the first data bit is consistent with the target data bit; If it is determined that the first device address is consistent with the device address of the target slave device, the first read / write bit is consistent with the target read / write bit, and the first data bit is consistent with the target data bit, the second communication data is determined to be the target communication data.

7. The method according to claim 5, characterized in that The second communication data further includes a first clock frequency for transmitting the second communication data; and the method further includes: The second detection subcomponent is used to determine a first delay time according to the first clock frequency, and to determine whether the first clock frequency meets an expected transmission condition according to the first delay time and a preset delay expected value.

8. The method according to claim 7, characterized in that The determining, according to the first delay time and the preset delay expected value, whether the first clock frequency meets the expected transmission condition includes: Determine a delay difference between the first delay time and the preset delay expected value; If the delay difference is less than the preset difference threshold, determining that the first clock frequency meets the expected transmission condition; If the delay difference is not less than the preset difference threshold, it is determined that the first clock frequency does not meet the expected transmission condition.

9. The method according to claim 7, characterized in that The verification platform further includes a verification environment configuration component; and before using the first agent component to send communication configuration information to the plurality of host devices, the method further includes: The verification environment configuration component is utilized to configure the device address of the target slave device to the second driving sub-component, and the preset delay expected value is configured to the second detection sub-component.

10. The method according to claim 3, characterized in that The first interface is an AXI interface, and the second interface is an I2C interface.

11. A device communication verification apparatus, characterized in that: The device is applied to a verification platform, the verification platform including a first agent component, an interface component, a second agent component, a register model, and a data processing component. The first agent component includes a first driver subcomponent, a first detection subcomponent, and a sequencer component. The register model includes multiple analog registers that have a mapping relationship with each control register in multiple host devices, and the identifier of each analog register is the name of the corresponding control register. The device includes: A configuration module is configured to use the first proxy component to send communication configuration information to multiple host devices, the communication configuration information being used to configure first communication data required for each of the host devices to communicate with a target slave device; wherein each host device communicates with the target slave device simultaneously or at time intervals based on the corresponding first communication data; the data to be processed sent by each host device to the target slave device is different, and the first communication data includes clock data and serial data, the serial data including the data to be processed; the configuration module is specifically configured to use the first driver subcomponent to use the preset sequence data mounted on the sequencer component as the communication configuration information, and transmit the communication configuration information from the first communication port to the multiple host devices based on a preset transmission protocol; the preset transmission protocol is the AXI protocol; wherein the process of determining the preset sequence data is as follows: determining a target analog register to be verified from the register model; determining an identifier of each target analog register to obtain a name of a target control register to be configured in each of the host devices; and determining the preset sequence data based on the name of the target control register to be configured in each of the host devices; a receiving module, configured to receive, using the interface component and based on the integrated circuit bus protocol, first communication data output by each of the host devices, and arbitrate and determine second communication data from each of the first communication data, so as to transmit the second communication data to the second agent component simulating the target slave device; A verification module is used to use the data processing component to obtain the communication configuration information and the second communication data, and verify whether the second communication data is the target communication data to be received by the target slave device according to the communication configuration information.

12. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

13. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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