Method and system for designing general architecture of infrared focal plane array digital driving circuit

Abstract

The invention discloses a general architecture design method and system for an infrared focal plane array digital drive circuit. The method comprises the following steps: S1, decomposing the infrared focal plane array digital drive circuit; s2, integrating an interface configuration component, a register file component, an infrared focal plane array configuration component, a time sequence generation component and a control word generation component into an infrared focal plane array digital drive circuit general architecture; and S3, according to the working steps of the infrared focal plane array digital drive circuit, operating the designed universal architecture of the infrared focal plane array digital drive circuit. According to the method and the system for designing the general architecture of the infrared focal plane array digital driving circuit, the infrared focal plane array digital driving circuit is decomposed into a plurality of components, interfaces of the components are designed, and the components are integrated into the general architecture of the infrared focal plane array digital driving circuit; and universal digital driving of the infrared focal plane arrays of different specifications is realized, so that the debugging, testing and application efficiency of the infrared focal plane arrays of different specifications is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of infrared focal plane array digital drive circuit design, and particularly relates to a general architecture design method and system for an infrared focal plane array digital drive circuit. Background Art

[0002] An infrared detector receives infrared radiation and converts it into an electrical signal, realizing the detection and positioning of substances, temperature measurement, and composition analysis. It has the advantages of non-contact, all-weather, anti-interference, long action distance, etc. Infrared detectors can be carried on various platforms such as the ground, vehicles, airplanes, and satellites. They are used for the surveillance, warning, early warning, and tracking of military targets in the military field, for observing celestial activities, water and soil resources in the field of astronomical remote sensing, and are also widely used in civil fields such as industrial monitoring, medical equipment, test measurement, and autonomous driving.

[0003] Developing and producing infrared focal plane arrays of various specifications for different military and civilian applications is an inevitable trend in the domestic development of infrared detectors; adopting a general digital drive for different specifications of infrared focal plane arrays to improve the debugging, testing, and application efficiency of infrared detectors, and thus enhancing the development level of domestic infrared detection systems, is a key issue that needs to be solved in the research, development, production, and wide application of infrared detectors.

[0004] An infrared detector requires multiple control signals for normal operation. Usually, an FPGA with parallelism and arbitrary programmability is selected as the device for generating the detector drive waveform; however, the development steps of large-scale FPGA projects are cumbersome and the compilation is slow, resulting in a long time-consuming debugging stage for infrared detectors and low debugging efficiency; in addition, when testing and applying multiple infrared focal plane arrays, due to different drive timings of different specifications of infrared focal plane arrays, the FPGA code needs to be updated, making the efficiency of testing and applying multiple infrared focal plane arrays low; how to improve the debugging, testing, and application efficiency of infrared detectors caused by the digital drive differences of different specifications of infrared focal plane arrays is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a general architecture design method and system for an infrared focal plane array digital drive circuit, realizing the general digital drive of different specifications of infrared focal plane arrays, thereby improving the debugging, testing, and application efficiency of different specifications of infrared focal plane arrays.

[0006] The technical solution adopted by the present invention is as follows: A general architecture design method for an infrared focal plane array digital drive circuit, the specific steps are as follows: S1: Decompose the digital drive circuit of the infrared focal plane array into an interface configuration component, a register file component, an infrared focal plane array configuration component, a timing generation component, and a control word generation component; S2: Design the interfaces of the interface configuration component, the register file component, the infrared focal plane array configuration component, the timing generation component, and the control word generation component, and integrate the interface configuration component, the register file component, the infrared focal plane array configuration component, the timing generation component, and the control word generation component into a general architecture of the digital drive circuit of the infrared focal plane array; S3: According to the working steps of the digital drive circuit of the infrared focal plane array, run the designed general architecture of the digital drive circuit of the infrared focal plane array to achieve the digital drive of infrared focal plane arrays with different specifications.

[0007] Specifically, in the above S1: The interface configuration component communicates with the external control component, receives the specification parameters and control parameters of the infrared focal plane array to be driven set by the external control component, and sends the current operating parameters of the infrared focal plane array to the external control component; The register file component stores the received specification parameters and control parameters of the infrared focal plane array to be driven, outputs the operating parameters to be updated, generates a control word update request signal, and simultaneously sends the current operating parameters of the infrared focal plane array to the interface configuration component; The infrared focal plane array configuration component completes the assembly and packaging of the control word according to the received operating parameters to be updated, updates the timing control parameter information after the control word takes effect, stores the current operating parameters of the focal plane array, and outputs them to the register file component; The timing generation component generates the main clock, frame synchronization, and line synchronization signals required for the digital drive of the infrared focal plane array to be driven according to the timing control parameters, and simultaneously generates a control word transmission enable signal and a data sampling signal; The control word generation component generates the control word signal required for the digital drive of the infrared focal plane array to be driven according to the control word packetization, and gives a control word transmission completion feedback signal.

[0008] Specifically, in the above S2: The interface of the interface configuration component includes a peripheral bidirectional communication interface with the external control component and a memory mapping control bidirectional interface with the register file component; The bidirectional interface of the register file component interface is a memory mapping control bidirectional interface with the interface configuration component; the input interface is the current operating parameters of the infrared focal plane array from the infrared focal plane array configuration component; the output interfaces include the operating parameters to be updated of the infrared focal plane array for the infrared focal plane array configuration component and the control word update request signal for the control word generation component; The input interface of the infrared focal plane array configuration component interface includes the infrared focal plane array operation parameters to be updated from the register file component and the control word transmission completion feedback from the control word generation component; the output interface includes the timing control parameters for the timing generation component, the control word packet assembly for the control word generation component, and the current infrared focal plane array operation parameters for the register file component. The input interface of the timing generation component interface is the timing control parameters from the infrared focal plane array configuration component; the output interface includes the timing interface for the infrared focal plane array and the data sampling signal for the external detector signal acquisition circuit. The input interface of the control word generation component interface includes the control word packet assembly from the infrared focal plane array configuration component, the control word update request from the register file component, and the control word transmission enable signal from the timing generation component; the output interface includes the control word communication interface for the infrared focal plane array and the control word transmission completion feedback for the infrared focal plane array configuration component.

[0009] Specifically, the working steps of the S3 infrared focal plane array digital drive circuit are as follows: S31: The operator interacts with the external control component to set the specification parameters and control parameters of the infrared focal plane array to be driven, and at the same time queries the operation parameters of the current infrared focal plane array. S32: The interface configuration component receives the specification parameters and control parameters from the external control component through the peripheral bidirectional communication interface with the external control component, outputs the received information to the register file component, and at the same time feeds back the current operation parameters of the infrared focal plane array in the register file to the external control component according to the query requirement of the external control component. S33: The register file component receives the specification parameters and control parameters from the interface configuration component and writes them into the corresponding registers, outputs the operation parameters to be updated to the infrared focal plane array configuration component, generates a control word update request signal and outputs it to the control word generation component, and sends the current focal plane array operation parameters of the infrared focal plane array configuration component to the interface configuration component. S34: The infrared focal plane array configuration component receives the operation parameters to be updated from the register file component, completes the assembly and packaging of the control word and outputs it to the control word generation component. After receiving the control word transmission completion feedback signal from the control word generation component, it saves the operation parameters to be updated as the current focal plane array operation parameters and feeds them back to the register file component, and at the same time updates the timing control parameter information and outputs it to the timing generation component. S35: The timing generation component receives the timing control parameters from the infrared focal plane array configuration component, generates the main clock, frame synchronization signal, and line synchronization signal, outputs the above-mentioned timing signals to the infrared focal plane array to be driven through the timing interface, and generates a data acquisition signal to output to the detector data acquisition circuit; S36: After receiving the control word update request signal output from the register file component and the control word transmission enable signal output from the timing generation component, the control word generation component packs the control word information from the infrared focal plane array configuration component, generates a control word signal according to the length and timing, and outputs it to the infrared focal plane array to be driven through the signal line. At the same time, it sends a control word transmission completion feedback signal to the infrared focal plane array configuration component to update the timing and control parameters; S37: The operator replaces the infrared focal plane array to be driven or updates the control parameters, repeats the steps of S31 - 36, and completes the digital drive of infrared focal plane arrays of different specifications.

[0010] An infrared focal plane array digital drive circuit general architecture design system includes: An infrared focal plane array digital drive circuit decomposition module; used to decompose the infrared focal plane array digital drive circuit into an interface configuration component, a register file component, an infrared focal plane array configuration component, a timing generation component, and a control word generation component; An infrared focal plane array digital drive circuit general architecture integration module; used to design the interfaces of the interface configuration component, register file component, infrared focal plane array configuration component, timing generation component, and control word generation component, and integrate the interface configuration component, register file component, infrared focal plane array configuration component, timing generation component, and control word generation component into the infrared focal plane array digital drive circuit general architecture; An infrared focal plane array digital drive circuit general architecture operation module; used to operate the designed infrared focal plane array digital drive circuit general architecture according to the working steps of the infrared focal plane array digital drive circuit, and realize the digital drive of infrared focal plane arrays of different specifications.

[0011] Due to the above - mentioned technical solution, the present invention has the following advantages: The infrared focal plane array digital drive circuit general architecture design method and system of the present invention decompose the infrared focal plane array digital drive circuit into multiple components, design the interfaces of each component, integrate the multiple components into the infrared focal plane array digital drive circuit general architecture, realize the generalization digital drive of infrared focal plane arrays of different specifications, and thereby improve the debugging, testing, and application efficiency of infrared focal plane arrays of different specifications. Description of the Drawings

[0012] Figure 1Flowchart of the general architecture design method for the infrared focal plane array digital drive circuit provided by the embodiment of the present invention.

[0013] Figure 2 General architecture block diagram of the infrared focal plane array digital drive circuit provided by the embodiment of the present invention.

[0014] Figure 3 Control word group packet output by the general architecture of the infrared focal plane array digital drive circuit provided by the embodiment of the present invention.

[0015] Figure 4 Timing signal output by the general architecture of the infrared focal plane array digital drive circuit provided by the embodiment of the present invention.

[0016] Figure 5 Control word signal output by the general architecture of the infrared focal plane array digital drive circuit provided by the embodiment of the present invention.

[0017] Figure 6 Block diagram of the general architecture design system for the infrared focal plane array digital drive circuit provided by the embodiment of the present invention. Detailed implementation manners

[0018] The present invention will be further explained and illustrated below in conjunction with the accompanying drawings and embodiments. The protection scope of the present invention cannot be limited thereby. The purpose of disclosing the present invention is to protect all technical improvements within the scope of the present invention.

[0019] Combined with the attached Figure 1-6 A general architecture design method for an infrared focal plane array digital drive circuit as shown, the specific steps are as follows: Operation S1: Decompose the infrared focal plane array digital drive circuit into an interface configuration component, a register file component, an infrared focal plane array configuration component, a timing generation component, and a control word generation component.

[0020] According to the embodiment of the present invention, the interface configuration component in operation S1 realizes communication with the external control component, receives the specification parameters and control parameters of the infrared focal plane array to be driven set by the external control component, and sends the current operating parameters of the infrared focal plane array to the external control component.

[0021] According to the embodiment of the present invention, the register file component in operation S1 stores the received specification parameters and control parameters of the infrared focal plane array to be driven, outputs the operating parameters to be updated, generates a control word update request signal, and simultaneously sends the current operating parameters of the infrared focal plane array to the interface configuration component.

[0022] According to an embodiment of the present invention, in operation S1, the infrared focal plane array configuration component assembles and packages the control word according to the received operating parameters to be updated, updates the timing control parameter information after the control word takes effect, saves the current operating parameters of the focal plane array, and outputs them to the register file component.

[0023] According to an embodiment of the present invention, in operation S1, the timing generation component generates the main clock, frame synchronization, and line synchronization signals required for the digital drive of the infrared focal plane array to be driven according to the timing control parameters, and simultaneously generates a control word transmission enable signal and a data sampling signal.

[0024] According to an embodiment of the present invention, in operation S1, the control word generation component generates the control word signal required for the digital drive of the infrared focal plane array to be driven according to the control word packetization, and gives a control word transmission completion feedback signal.

[0025] In operation S2, design the interfaces of the interface configuration component, register file component, infrared focal plane array configuration component, timing generation component, and control word generation component, and integrate the interface configuration component, register file component, infrared focal plane array configuration component, timing generation component, and control word generation component into a general architecture of the infrared focal plane array digital drive circuit.

[0026] According to an embodiment of the present invention, the interface of the interface configuration component in operation S2 includes a peripheral bidirectional communication interface with an external control component and a memory mapped control bidirectional interface with the register file component.

[0027] In one embodiment, the peripheral bidirectional communication interface with the external control component is implemented using a 4-wire SPI full-duplex communication protocol, with a frame length of 32 bits, including 16-bit addresses and commands and 16-bit read / write data.

[0028] According to an embodiment of the present invention, the interface of the register file component in operation S2 has a bidirectional interface that is a memory mapped control bidirectional interface with the interface configuration component, an input interface that is the current operating parameters of the infrared focal plane array from the infrared focal plane array configuration component, and an output interface that includes the operating parameters to be updated for the infrared focal plane array to the infrared focal plane array configuration component and a control word update request signal to the control word generation component.

[0029] In one embodiment, the memory mapped control interface includes 11-bit read / write addresses, 16-bit read / write data, and 1-bit read request and 1-bit write request signals.

[0030] According to an embodiment of the present invention, the infrared focal plane array configuration component interface in operation S2 has an input interface including the infrared focal plane array operation parameters to be updated from the register file component and the control word transmission completion feedback from the control word generation component, and an output interface including the timing control parameters for the timing generation component, the control word packet for the control word generation component, and the current infrared focal plane array operation parameters for the register file component.

[0031] In one embodiment, the operation parameters to be updated include the column size of the focal plane array, the row size of the focal plane array, the starting row address of the window, the starting column address of the window, the effective column number of the window, the effective row number of the window, and the number of output channels.

[0032] According to an embodiment of the present invention, the timing generation component interface in operation S2 has an input interface that is the timing control parameters from the infrared focal plane array configuration component, and an output interface including the timing interface for the infrared focal plane array and the data sampling signal for the external detector signal acquisition circuit.

[0033] In one embodiment, the timing control parameters include the main clock, frame synchronization, and line synchronization.

[0034] According to an embodiment of the present invention, the control word generation component interface in operation S2 has an input interface including the control word packet from the infrared focal plane array configuration component, the control word update request from the register file component, and the control word transmission enable signal from the timing generation component, and an output interface including the control word communication interface for the infrared focal plane array and the control word transmission completion feedback for the infrared focal plane array configuration component.

[0035] In one embodiment, the control word communication interface is implemented using a single - wire synchronous communication interface, and the data is sampled at the falling edge of the main clock.

[0036] In operation S3, according to the working steps of the infrared focal plane array digital drive circuit, the designed general architecture of the infrared focal plane array digital drive circuit is run to achieve the digital drive of infrared focal plane arrays of different specifications.

[0037] According to an embodiment of the present invention, operation S3 includes sub - operations S31 - S36: In sub - operation S31, the operator interacts with the external control component to set the specification parameters and control parameters of the infrared focal plane array to be driven, and can also query the operation parameters of the current infrared focal plane array; In one embodiment, the specification of the infrared focal plane array to be driven is set to 128×128; In sub-operation S32, the interface configuration component receives the specification parameters and control parameters from the external control component through the peripheral bidirectional communication interface with the external control component, outputs the received information to the register file component, and can feedback the current operating parameters of the infrared focal plane array in the register file to the external control component according to the query requirement of the external control component; In one embodiment, the specification parameters and control parameters are received through the SPI interface; In sub-operation S33, the register file component receives the specification parameters and control parameters from the interface configuration component and writes them into the corresponding registers. At the same time, it outputs the operating parameters to be updated to the infrared focal plane array configuration component, generates a control word update request signal and outputs it to the control word generation component, and can send the current focal plane array operating parameters of the infrared focal plane array configuration component to the interface configuration component; In one embodiment, the specification parameter 128 is written into the FPA_COL and FPA_ROW registers respectively, the window start column address 0 is written into the WAX register, the window start row address 0 is written into the WAY register, the window valid column size is written into the WSX register, the window valid row size is written into the WSY register, etc.; In sub-operation S34, the infrared focal plane array configuration component receives the operating parameters to be updated from the register file component, completes the assembly and packaging of the control word and outputs it to the control word generation component. After receiving the control word transmission completion feedback signal from the control word generation component, it saves the operating parameters to be updated as the current focal plane array operating parameters and feedbacks them to the register file component, and at the same time updates the timing control parameter information and outputs it to the timing generation component; In one embodiment, the operating parameters are assembled and packaged into a packet with a total length of 76 bits, including 1 start bit, 8 bits of WAX, 7 bits of WAY, 8 bits of WSX, 8 bits of WSY, etc., as Figure 3 shown; In sub-operation S35, the timing generation component receives the timing control parameters from the infrared focal plane array configuration component, generates timing signals such as the main clock, frame synchronization signal, and line synchronization signal, outputs them to the infrared focal plane array to be driven through the timing interface, and generates a data acquisition signal and outputs it to the detector data acquisition circuit; In one embodiment, the main clock CLK, frame synchronization signal FSYNC, and line synchronization signal LSYNC are generated, as Figure 4 shown; In sub-operation S36, after receiving the control word update request signal output from the register file component and the control word transmission enable signal output from the timing generation component, the control word generation component generates a control word signal from the control word packet information of the infrared focal plane array configuration component according to the length and timing, and outputs it to the infrared focal plane array to be driven through a signal line. At the same time, a control word transmission completion feedback signal is sent to the infrared focal plane array configuration component to update the timing and control parameters; In one embodiment, the generated control word signal DATA is as Figure 5 shown; In sub-operation S37, the operator replaces the infrared focal plane array to be driven or updates the control parameters, and repeats the steps of S31-36 to complete the digital drive of infrared focal plane arrays with different specifications.

[0038] Figure 6 It is a block diagram of the general architecture design system of the infrared focal plane array digital drive circuit provided by the embodiment of the present invention; refer to Figure 6 As shown in, the general architecture design system 600 of the infrared focal plane array digital drive circuit includes an infrared focal plane array digital drive circuit decomposition module 610, an infrared focal plane array digital drive circuit general architecture integration module 620, and an infrared focal plane array digital drive circuit general architecture operation module 630.

[0039] The infrared focal plane array digital drive circuit decomposition module 610, for example, executes S1 to decompose the infrared focal plane array digital drive circuit into an interface configuration component, a register file component, an infrared focal plane array configuration component, a timing generation component, and a control word generation component.

[0040] The infrared focal plane array digital drive circuit general architecture integration module 620, for example, executes S2 to design the interfaces of the interface configuration component, the register file component, the infrared focal plane array configuration component, the timing generation component, and the control word generation component, and integrates the interface configuration component, the register file component, the infrared focal plane array configuration component, the timing generation component, and the control word generation component into the general architecture of the infrared focal plane array digital drive circuit.

[0041] The infrared focal plane array digital drive circuit general architecture operation module 630, for example, executes S3 to run the designed general architecture of the infrared focal plane array digital drive circuit according to the working steps of the infrared focal plane array digital drive circuit, and realizes the digital drive of infrared focal plane arrays with different specifications.

[0042] Parts not detailed in the present invention are prior art.

[0043] The embodiments chosen herein to disclose the inventive objects of the present invention are currently considered to be suitable. However, it should be understood that the present invention is intended to cover all variations and improvements of all embodiments that fall within the scope of this concept and invention.

Claims

1. A general architecture design method for an infrared focal plane array digital drive circuit, characterized in that: The specific steps are: S1: decomposing the infrared focal plane array digital driving circuit into an interface configuration component, a register file component, an infrared focal plane array configuration component, a timing generation component and a control word generation component; S2: Design interface configuration component interface, register file component interface, infrared focal plane array configuration component interface, timing generation component interface and control word generation component interface, and integrate the interface configuration component, register file component, infrared focal plane array configuration component, timing generation component and control word generation component into a general architecture of infrared focal plane array digital drive circuit; S3: According to the working steps of the infrared focal plane array digital driving circuit, the designed infrared focal plane array digital driving circuit general architecture is operated to realize the digital driving of infrared focal plane arrays of different specifications.

2. The method for designing a general architecture of an infrared focal plane array digital driving circuit according to claim 1, characterized in that: Specifically, in S1: the interface configuration component communicates with the external control component, receives specification parameters and control parameters of the infrared focal plane array to be driven set by the external control component, and sends the current operating parameters of the infrared focal plane array to the external control component; The register file component stores the received specification parameters and control parameters of the infrared focal plane array to be driven, outputs the operating parameters to be updated, generates a control word update request signal, and sends the current operating parameters of the infrared focal plane array to the interface configuration component; The infrared focal plane array configuration component completes the assembly and packaging of the control word according to the received operating parameters to be updated, updates the timing control parameter information after the control word takes effect, saves the current operating parameters of the focal plane array, and outputs them to the register file component; The timing generation component generates the main clock, frame synchronization and line synchronization signals required for the digital drive of the infrared focal plane array to be driven according to the timing control parameters, and generates the control word sending enable signal and the data sampling signal at the same time; The control word generation component generates the control word signal required for the digital driving of the infrared focal plane array to be driven according to the control word group packet, and gives a control word sending completion feedback signal.

3. The method for designing a general architecture of an infrared focal plane array digital drive circuit according to claim 1, characterized in that: In said S2: the interface configuration component interface comprises a peripheral bidirectional communication interface with an external control component and a memory mapping control bidirectional interface with a register file component; The bidirectional interface of the register file component interface is a memory mapping control bidirectional interface with the interface configuration component; the input interface is the current infrared focal plane array operating parameters from the infrared focal plane array configuration component; the output interface includes the infrared focal plane array operating parameters to be updated for the infrared focal plane array configuration component and the control word update request signal for the control word generation component; The input interface of the infrared focal plane array configuration component interface includes the infrared focal plane array operating parameters to be updated from the register file component and the control word sending completion feedback from the control word generation component; the output interface includes the timing control parameters for the timing generation component, the control word group package for the control word generation component, and the current infrared focal plane array operating parameters for the register file component; The input interface of the timing generation component interface is the timing control parameters from the infrared focal plane array configuration component; The output interface includes a timing interface for the infrared focal plane array and a data sampling signal for the external detector signal acquisition circuit; The input interface of the control word generation component interface includes a control word group packet from the infrared focal plane array configuration component, a control word update request from the register file component and a control word sending enable signal from the timing generation component; the output interface includes a control word communication interface to the infrared focal plane array and a control word sending completion feedback to the infrared focal plane array configuration component.

4. The method for designing a general architecture of an infrared focal plane array digital drive circuit according to claim 1, characterized in that: The working steps of the S3 mid-infrared focal plane array digital driving circuit are specifically as follows: S31: the operator interacts with the external control component to set the specification parameters and control parameters of the infrared focal plane array to be driven, and queries the current operating parameters of the infrared focal plane array; S32: the interface configuration component receives specification parameters and control parameters from the external control component through the external bidirectional communication interface with the external control component, outputs the received information to the register file component, and feeds back the current operating parameters of the infrared focal plane array in the register file to the external control component according to the query request of the external control component; S33: the register file component receives the specification parameters and control parameters from the interface configuration component and writes them into the corresponding registers, and outputs the operation parameters to be updated to the infrared focal plane array configuration component, generates a control word update request signal and outputs it to the control word generation component, and sends the current focal plane array operation parameters of the infrared focal plane array configuration component to the interface configuration component; S34: the infrared focal plane array configuration component receives the operation parameters to be updated from the register file component, completes the assembly and packaging of the control word and outputs it to the control word generation component, and after receiving the control word sending completion feedback signal from the control word generation component, saves the operation parameters to be updated as the current focal plane array operation parameters and feeds them back to the register file component, and at the same time updates the timing control parameter information and outputs it to the timing generation component; S35: The timing generation component receives the timing control parameters from the infrared focal plane array configuration component, generates a master clock, a frame synchronization signal and a line synchronization signal, outputs the above timing signals to the infrared focal plane array to be driven through the timing interface, and generates a data acquisition signal to output to the detector data acquisition circuit; S36: after receiving the control word update request signal output by the register file component and the control word sending enable signal output by the timing generation component, the control word generation component packages the control word information from the infrared focal plane array configuration component, generates a control word signal according to the length and timing, and outputs it to the infrared focal plane array to be driven through the signal line, and at the same time sends a control word sending completion feedback signal to the infrared focal plane array configuration component for updating the timing and control parameters; S37: The operator replaces the infrared focal plane array to be driven or updates the control parameters, and repeats the steps of S31-36 to complete the digital driving of infrared focal plane arrays of different specifications.

5. A general architecture design system for digital drive circuit of infrared focal plane array, characterized in that: include: Infrared focal plane array digital drive circuit decomposition module; Used to decompose the infrared focal plane array digital driving circuit into an interface configuration component, a register file component, an infrared focal plane array configuration component, a timing generation component and a control word generation component; General architecture integrated module for digital drive circuit of infrared focal plane array; Used to design an interface configuration component interface, a register file component interface, an infrared focal plane array configuration component interface, a timing generation component interface and a control word generation component interface, and integrate the interface configuration component, the register file component, the infrared focal plane array configuration component, the timing generation component and the control word generation component into a general architecture of an infrared focal plane array digital drive circuit; An infrared focal plane array digital drive circuit general architecture operation module is used to operate the designed infrared focal plane array digital drive circuit general architecture according to the infrared focal plane array digital drive circuit working steps to realize digital drive of infrared focal plane arrays of different specifications.

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