IP simulation verification method and system based on SPI communication interface

Abstract

The invention discloses an IP simulation verification method and system based on an SPI communication interface, and the method comprises the following steps: S1, configuring a verification case library which is used for providing verification cases and is provided with at least one verification case; s2, initializing a verification environment; s3, simulation verification is started, and the DUT to be tested communicates with the VIP based on an SPI protocol; and S4, until the verification cases in the verification case library are executed completely, counting execution conditions of all the verification cases, including error statistics of a single case in the simulation process and the verification coverage rate of this time. According to the method, simulation verification can be automatically executed, data check is carried out in real time in the simulation verification communication process, and a simulation check result and a coverage rate report can be automatically generated.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an IP simulation verification method and system based on an SPI communication interface. Background Art

[0002] With the rapid development of the integrated circuit industry in recent years, the chip design ability and chip manufacturing process have been continuously upgraded, promoting the performance improvement and scale expansion of MCU chips (Microprogrammed Control Unit), and also putting forward higher requirements for the communication functions of chips. Due to the increase in the number and types of communication interfaces integrated inside MCU chips, the existing functional verification methods are difficult to meet the verification requirements in actual projects. The traditional verification method is to write specific vectors based on Verilog for verification, which has low functional point coverage, difficult program debugging, and is difficult to transplant between different projects. Therefore, it has become an urgent need in the chip verification process to develop a communication module verification platform with comprehensive function coverage, easy portability and debugging.

[0003] The SPI (Serial Peripheral Interface) communication protocol was introduced by Motorola in 2000. It has multiple configurable communication modes and can perform full-duplex communication by connecting a host and one (or more) slaves through four wires. It has the advantages of high speed, flexibility and simple configuration, which makes the SPI interface become the most widely used standard interface protocol in the world. However, the flexibility and high speed of SPI pose higher requirements for verification work. The multiple communication modes it has are great challenges for the scenario comprehensiveness and functional coverage of verification cases. Based on the characteristics of the above SPI protocol and the problems faced by current conventional verification, the development of new SPI verification methods and VIP (Verification IP) is of great importance.

[0004] Currently, the mainstream SPI verification solutions are mainly constructed using the UVM architecture. A verification platform is constructed through the verification structure and components under the UVM architecture for module-level verification. Most SPI verification platforms using UVM include functions such as constructing a test sequence library, configuring verification parameters, and comparing results. There are problems with the verification level and usability when using UVM for SPI verification. Verifying using the UVM architecture can perform module-level verification on SPI, which is equivalent to verifying the SPI module separately and cannot verify the scenarios when interacting with other modules, such as the scenarios when the SPI module is used together with a bus, a kernel or other peripherals. In addition, the current mainstream simulation verification platforms usually only include communication timing check and result check functions, and do not perform statistics and generation of the coverage after verification is completed, which makes the analysis of verification results inconvenient.

[0005] For example, Chinese Patent Application CN114968793A discloses a UVM-based SPI verification system, which mainly includes a configuration file module, an SPI agent module, and a data comparison module. According to the requirements of the SPI protocol, various UVM-based configuration parameters are set in the configuration file module. The SPI agent module randomly generates reference data according to the configuration parameters of the configuration file module and sends the reference data to the data comparison module. The SPI agent module generates stimuli according to the parameters of the design under test and sends the generated stimuli to the design under test; the data comparison module receives the reference data and the data of the design under test and compares the two data. This solution constructs a verification platform through the verification structure and components under the UVM architecture, and there are problems with verification levels and usability.

[0006] Technical Term Explanation

[0007] MCU chip (Microprogrammed Control Unit, micro control chip);

[0008] SPI interface (Serial Peripheral Interface, serial peripheral interface);

[0009] VIP (Verification IP, verification IP);

[0010] DUT (Design Under Test, design under test);

[0011] Verilog (a programming language for circuit design);

[0012] System Verilog (a programming language for circuit design);

[0013] master_vip (host mode VIP);

[0014] slave_vip (slave mode VIP);

[0015] IP is "IP core" (Intellectual Property Core), that is, the intellectual property module in integrated circuit design. These IP cores are verified, reusable, and integrated circuit modules with specific functions. Summary of the Invention

[0016] A series of simplified concepts are introduced in the Summary of the Invention section. These simplified concepts are all simplified from the prior art in this field and will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0017] The technical problem to be solved by the present invention is to provide an IP simulation verification method and system that can automatically execute simulation verification for the increasing number and types of communication interfaces integrated inside the chip, perform real-time data inspection during the simulation verification communication process, and automatically generate simulation inspection results and coverage reports. It should be noted that the present invention is particularly applicable to MCU simulation verification.

[0018] To solve the above technical problem, the present invention provides an IP simulation verification method based on the SPI communication interface, including the following steps:

[0019] S1, Configure a verification test case library. The verification test case library is used to provide verification test cases, which have at least one verification test case. The verification test case is used to set verification parameters and establish a verification environment; the execution order of the verification test cases is determined by the verification writing script;

[0020] S2, Initialize the verification environment; exemplarily, it includes selecting the required VIP working mode and connecting it to the DUT (Design Under Test), configuring the communication parameters of the DUT and VIP, and generating data during the communication process;

[0021] The VIP is written in SystemVerilog and can be divided into a master mode VIP (master_vip) and a slave mode VIP (slave_vip);

[0022] The setting of the communication parameters includes setting parameters such as the clock polarity, clock phase, and data format of the communication process. Corresponding communication parameters are set for the DUT and VIP to communicate;

[0023] The generation of the communication data includes generating fixed or random verification data and determining the quantity of the verification data; the configuration process can be implemented by simulating the execution of a program by the CPU, which is used to simulate the communication process in a real usage scenario;

[0024] S3. Start simulation verification. The DUT under test communicates with the VIP based on the SPI protocol. Data is written into the DUT under test and the VIP, driving the VIP and the DUT under test to perform two-way data transceiver, and the data received and sent by the DUT under test is used to check the received data of the DUT and the VIP during the communication process and to count the coverage rate of the test cases. The data check is performed in real time during the communication process and is checked once after each round of transmission.

[0025] S4. Until all the verification cases in the verification case library are executed, count the execution status of all verification cases, including: error statistics of a single case during the simulation process and the verification coverage rate of this verification. The coverage rate statistics include the generation of the coverage rate of a single case and the summary of the coverage rates of multiple cases, and different functions can be selected according to the number of verification cases to be verified.

[0026] Preferably, further improve the IP simulation verification method based on the SPI communication interface, and further include

[0027] S5. If the verification coverage rate does not meet the design requirements, return to step S1 to reconfigure the verification case library, adjust the case library according to the coverage rate situation, and perform verification again to finally achieve the convergence of the coverage rate.

[0028] Preferably, further improve the IP simulation verification method based on the SPI communication interface. The verification cases in the verification case library can perform regression verification. The regression verification includes performing automatic regression tests for single, multiple, and all cases, rather than only being able to test specific cases.

[0029] Preferably, further improve the IP simulation verification method based on the SPI communication interface. After starting the simulation verification, the timing and level of the DUT under test are also checked.

[0030] To solve the above technical problems, the present invention provides an IP simulation verification system based on the SPI communication interface, which can be implemented based on computer programming technology means and existing hardware, including:

[0031] A verification case library, which has the verification cases required for the verification scenario and is used to determine the verification scope and start the verification environment. The verification case library can be configured according to requirements, that is, single or multiple verification cases can be added to the verification library for verification according to the verification requirements.

[0032] An initialization module, including a VIP model selector, a communication parameter configurator, and a communication data generator, and loading them into the communication module and the result analysis module for communication and inspection.

[0033] A communication module, which includes a Device Under Test (DUT) to be tested and a VIP. The DUT is a SPI module to be verified in an integrated environment. The VIP is configured according to initialization parameters before communication, and the VIP is used to simulate the functions of the master and slave devices of the SPI protocol to communicate with the DUT under test;

[0034] A result analysis module, which is used to perform communication data check and coverage rate statistics.

[0035] Preferably, further improve the IP simulation verification system based on the SPI communication interface. The verification use case library can use the verification use case name as an index through a supporting script for single verification, or continuous verification of two or more use cases, or regression verification of all verification use cases in the entire verification use case library.

[0036] Preferably, further improve the IP simulation verification system based on the SPI communication interface. The VIP mode selects the master mode or the slave mode according to the verification needs to perform communication

[0037] SPI communication parameters, including: master-slave mode setting under the SPI protocol, clock polarity configuration, clock phase configuration, baud rate configuration, endian mode configuration, chip select signal input / output configuration, number of hosts and number of slaves;

[0038] SPI communication data, including: common data and random data.

[0039] Preferably, further improve the IP simulation verification system based on the SPI communication interface. The communication module is written in the hardware description language Verilog;

[0040] The VIP is written in System Verilog.

[0041] Preferably, further improve the IP simulation verification system based on the SPI communication interface. The communication data check includes checking the data quantity, numerical value, and communication timing on both sides of the DUT and the VIP during the communication process, and comparing with the expected value to judge the correctness of the function of the DUT under test;

[0042] The coverage rate statistics calls the relevant commands of the simulation tool to generate the simulation coverage rate of each module in the DUT under test.

[0043] Preferably, further improve the IP simulation verification system based on the SPI communication interface. If the result analysis module determines that the verification coverage rate does not meet the design requirements, reconfigure the verification use case library to form a verification use case library.

[0044] The main differences between the present invention and the existing technologies are:

[0045] (1) The present invention tests the functions of the SPI module by simulating the actual operation of the analog chip, rather than adopting the UVM architecture for module-level testing. It solves the technical problem in the prior art that when the SPI module is verified separately, the scenarios when interacting with other modules cannot be verified.

[0046] (2) The present invention can specify the usage scenarios for verification by customizing the verification test case library, and perform automatic regression testing for single, multiple, and all test cases, rather than only being able to test specific test cases, which is beneficial to improving the quality of verification testing and reducing the risks of verification testing.

[0047] (3) The present invention can combine VIPs in different modes to test various parameters in the SPI communication process, including master-slave mode setting, clock polarity configuration, clock phase configuration, baud rate configuration, endian mode configuration, chip select signal input / output configuration, etc., providing rich verification function options.

[0048] (4) The present invention can achieve fully automatic inspection and output of verification results, including real-time communication results, timing inspection, and coverage results after all test cases in the test case library are executed.

[0049] (5) The present invention can be widely reused in various chip verification scenarios, including communication process verification that requires VIPs or module verification that does not require VIPs, and only corresponding modifications need to be made to the communication module and the result analysis module.

[0050] In summary, the present invention has the advantages of a simple verification environment, an efficient verification process, a comprehensive verification scope, and strong code reusability. The verification environment structure of the present invention is very clear, and the verification process is completely controlled by the verification test case library, which can comprehensively cover the communication scenarios under actual use without manual intervention; by adding and modifying the composition of the verification test case library, the convergence of module coverage can be achieved. In addition, the present invention can also be reused for other communication IPs, and only the VIP in the communication module needs to be adjusted, having excellent reusability and portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the present invention to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment. The drawings of the present invention should not be construed as limiting or restricting the scope of the numerical values or properties covered by the exemplary embodiments according to the present invention. The present invention will be further described in detail below in conjunction with the drawings and the specific embodiments:

[0052] Figure 1 It is a schematic flowchart of the first embodiment of the verification method of the present invention.

[0053] Figure 2 It is a schematic flowchart of the second embodiment of the verification method of the present invention.

[0054] Figure 3 It is a schematic diagram of the architecture of the verification system of the present invention. Specific embodiments

[0055] The following uses specific specific embodiments to illustrate the implementation manners of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. The details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without departing from the overall design concept of the invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited only to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention complete and thorough, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element. Throughout all the drawings, the same reference numerals always represent the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0056] The first embodiment;

[0057] Referring to Figure 1 as shown, the present invention provides an IP simulation verification method based on an SPI communication interface, which is particularly suitable for MCU simulation verification, and includes the following steps:

[0058] S1. Configure a verification use case library. The verification use case library is used to provide verification use cases. The verification use cases are selected according to verification scenarios. The verification use cases are used to determine the verification scope and start the verification environment, and it has at least one verification use case; the verification use case library is configurable, and single or multiple verification use cases can be added to the verification library for verification according to verification requirements; after the verification use case library is constructed, the verification use case name can be used as an index through a supporting script for single verification, or continuous verification of multiple use cases, or regression verification of the entire verification use case library;

[0059] S2. Initialize the verification environment, which specifically includes three parts: VIP model selection, communication parameter configuration, and communication data generation;

[0060] Among them, the VIP model selection can choose the master mode or the slave mode according to the verification needs for communication; in addition, VIP also has the function of printing verification information in simulation verification.

[0061] SPI communication parameters include parameters such as master-slave mode setting, clock polarity configuration, clock phase configuration, baud rate configuration, endian mode configuration, chip select signal input / output configuration under the SPI protocol. In addition, the number of hosts and slaves in the communication network can also be set through communication configuration, including various communication scenarios such as single host, multiple hosts, single slave, and multiple slaves;

[0062] Communication data generation refers to the ability to generate a specified number of data for the communication process. Common data includes special data such as all 0s, all 5s, all As, and all 1s. In addition, random data within a certain range can also be generated according to needs for communication;

[0063] The initialization configurations such as the selected VIP model, the configured communication parameters, and the generated communication data will be loaded into communication and result analysis for communication and checking;

[0064] S3. Start simulation verification, and the DUT under test communicates with VIP based on the SPI protocol;

[0065] The DUT is the SPI module to be verified in the integrated environment, and it uses the clock signal SCK, chip select signal NSS, host transmit signal MOSI, and slave transmit signal MISO in the standard SPI protocol to communicate with VIP;

[0066] Before VIP communication, it is configured according to the initialization parameters, and can simulate the functions of the host and slave in the SPI protocol to communicate with the DUT under test;

[0067] Furthermore, after starting the simulation verification, the timing and electrical characteristics of the DUT under test are automatically checked;

[0068] S4. Until all the verification cases in the verification case library are executed, count the execution status of all verification cases, including: error statistics of a single case during the simulation process and the coverage rate of this verification, and output the complete verification report of the entire case library.

[0069] Check the data quantity, value, and communication timing on both sides of the DUT and VIP during the communication process, and compare them with the expected values to judge the correctness of the function of the DUT under test;

[0070] The relevant commands of the simulation tool can be called to generate the simulation coverage rate of each module in the DUT under test to check whether the simulation cases are comprehensively verified and evaluate whether the verification effect is good.

[0071] Further improve the above first embodiment, refer toFigure 2 As shown, add the following steps;

[0072] S5. If the verification coverage rate does not meet the design requirements, return to step S1 to reconfigure the verification test case library.

[0073] After the regression of all test cases in the test case library is completed, the verification environment will generate the coverage rate of this verification by calling VCS, so as to modify or supplement the verification test case library. If the verification coverage rate does not meet the requirements, it should return to step S1, adjust the verification test case library and execute the subsequent steps again for iteration.

[0074] Second embodiment;

[0075] Refer to Figure 3 As shown, the present invention provides an IP simulation verification system based on an SPI communication interface, which can be implemented based on existing hardware combined with computer programming technical means, and is especially suitable for MCU simulation verification, including:

[0076] A verification test case library, which has verification test cases required for verification scenarios, and is used to determine the verification scope and start the verification environment;

[0077] The verification test case library is composed of verification test cases, and the verification test cases are used to determine the verification scope and start the verification environment. The verification test case library is configurable, and single or multiple verification test cases can be added to the verification library according to verification requirements for verification; after the verification test case library is constructed, the verification test case name can be used as an index through a supporting script for single verification, or continuous verification of multiple test cases, or regression verification of the entire verification test case library;

[0078] An initialization module, including a VIP model selector, a communication parameter configurator, and a communication data generator, and loading them into the communication module and the result analysis module for communication and inspection;

[0079] The VIP model selector can select the master mode or the slave mode according to verification needs for communication; in addition, the VIP also has the function of printing verification information in simulation verification;

[0080] The communication parameter configurator includes parameters such as master-slave mode setting, clock polarity configuration, clock phase configuration, baud rate configuration, endian mode configuration, chip select signal input / output configuration, etc. under the SPI protocol. In addition, the number of hosts and slaves in the communication network can also be set through communication configuration, including multiple communication scenarios such as single host, multiple hosts, single slave, and multiple slaves;

[0081] The communication data generator can generate a specified number of data for the communication process. Common data includes special data such as all 0s, all 5s, all As, and all 1s. In addition, it can also generate random data within a certain range according to needs for communication;

[0082] A communication module, written in the hardware description language Verilog, which includes a Device Under Test (DUT) and a Verification IP (VIP). The DUT is the SPI module to be verified in an integrated environment, and it communicates with the VIP using the clock signal SCK, chip select signal NSS, master output slave input signal MOSI, and slave output master input signal MISO in the standard SPI protocol.

[0083] The VIP is written in System Verilog and needs to be configured according to initialization parameters before communication. It can simulate the functions of the master and slave in the SPI protocol to communicate with the DUT under test.

[0084] A result analysis module, which is used to perform communication data checking and coverage statistics.

[0085] The communication data checking includes checking the data quantity, value, and communication timing on both sides of the DUT and the VIP during the communication process, and comparing them with the expected values to determine the correctness of the function of the DUT under test.

[0086] The coverage statistics function can call relevant commands of the simulation tool to generate the simulation coverage of each module in the DUT under test, so as to check whether the simulation cases are comprehensive and evaluate whether the verification effect is good.

[0087] Unless otherwise defined, all terms (including technical and scientific terms) used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0088] The present invention has been described in detail above through specific embodiments and examples, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. An IP simulation verification method based on SPI communication interface, characterized in that: The following steps are involved: S1, configure a verification case library, the verification case library is used to provide verification cases, and it has at least one verification case; S2, verification environment initialization; S3, start simulation verification, the DUT to be tested communicates with the VIP based on the SPI protocol; S4, until the verification case in the verification case library is executed, statistics are collected on the execution status of all verification cases, including: error statistics of a single case during the simulation process and the verification coverage rate of this time.

2. The IP simulation verification method based on the SPI communication interface as claimed in claim 1, characterized in that: Also includes S5: If the verification coverage does not meet the design requirements, return to step S1 to reconfigure the verification case library.

3. The IP simulation verification method based on the SPI communication interface as claimed in claim 1, characterized in that: The verification cases in the verification case library can perform regression verification.

4. The IP simulation verification method based on the SPI communication interface as claimed in claim 1, characterized in that: After starting the simulation verification, the timing and level of the DUT under test are also checked.

5. An IP simulation verification system based on SPI communication interface, characterized in that: include: The verification case library contains the verification cases required for the verification scenarios, which are used to determine the verification scope and start the verification environment; Initialization module, including VIP model selector, communication parameter configurator and communication data generator, and loads them into communication module and result analysis module for communication and inspection; The communication module includes a DUT to be tested and a VIP, wherein the DUT is an SPI module to be verified in an integrated environment, and the VIP is configured according to initialization parameters before communication, and the VIP is used to simulate the functions of the SPI protocol master and slave devices to communicate with the DUT to be tested; The result analysis module is used to perform communication data inspection and coverage statistics.

6. The IP simulation verification system based on the SPI communication interface as claimed in claim 5, characterized in that: The verification case library can use the verification case name as an index through the supporting script to perform a single verification, or perform continuous verification on more than two cases, or perform regression verification on all verification cases in the entire verification case library.

7. The IP simulation verification system based on the SPI communication interface as claimed in claim 5, characterized in that: VIP mode selects master mode or slave mode for communication according to verification needs SPI communication parameters, including: master-slave mode settings under the SPI protocol, clock polarity configuration, clock phase configuration, baud rate configuration, big-endian and small-endian mode configuration, chip select signal input and output configuration, number of masters and number of slaves; SPI communication data, including common data and random data.

8. The IP simulation verification system based on the SPI communication interface as claimed in claim 5, characterized in that: The communication module is written in the hardware description language Verilog; VIP is written in System Verilog.

9. The IP simulation verification system based on the SPI communication interface as claimed in claim 5, characterized in that: Communication data check includes checking the data quantity, value and communication timing between the DUT and VIP during the communication process, and comparing them with the expected values ​​to determine the correctness of the DUT function under test; Coverage statistics call the simulation tool related commands to generate the simulation coverage of each module in the DUT under test.

10. The IP simulation verification system based on the SPI communication interface as claimed in claim 5, characterized in that: If the result analysis module determines that the verification coverage does not meet the design requirements, the verification case library is reconfigured to form a verification case library.

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