2.5d package die-to-die simultaneous escape routing method based on pattern matching binary tree

Abstract

This invention discloses a 2.5D packaged die-to-die simultaneous escape routing method based on a pattern-matching binary tree. The method includes: splitting the interconnect network between multiple dies into multiple sets of simultaneous escape routing models for two-die interconnections; and dividing the signal network in each model into multiple network sets based on the separation characteristics of power and ground networks on signal networks; for each network set, performing fan-out routing planning and layer allocation based on a pattern-matching binary tree, specifically including: setting the routing mode, constructing the pattern-matching binary tree, and backtracking the pattern-matching binary tree; finally, completing the routing based on the fan-out routing planning and layer allocation results. This invention proposes a collaborative planning technology for routing sequence planning and layer allocation in 2.5D IC packaged die-to-die simultaneous escape routing, aiming to solve common routing sequence and layer allocation problems in traditional die-to-die routing. This technology, through optimized routing sequence planning and layer allocation strategies, automates the routing process and significantly improves routing quality and efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit wiring technology, and more specifically to a 2.5D package die-to-die simultaneous escape wiring method based on pattern matching binary tree. Background Technology

[0002] As transistor dimensions approach their physical limits, the manufacturing process for semiconductor chips becomes increasingly complex, significantly increasing R&D and manufacturing costs. The semiconductor industry is gradually entering the post-Moore's Law era, with the emergence of 2.5D / 3DIC (Integrated Circuit) technologies. These technologies utilize advanced packaging (interposer, TSV) to achieve die-to-die interconnections. Advanced packaging designs can further reduce the distance between device interconnects, improving electrical performance and enabling diverse integration, including various forms of microsystem packaging through heterogeneous integration.

[0003] In a typical 2.5D IC package, connecting multiple bump pairs on different chips usually involves long and parallel inter-chip networks. These parallel inter-chip networks can cause severe coupling effects between signals, degrading signal integrity and circuit performance. To reduce this interference, power and ground networks (typically power and ground planes) are often used in the design to surround the signal lines, forming a "shielding" structure, such as... Figure 1 As shown. This approach isolates the power and ground signal layers by placing them above, below, or beside the signal lines, thereby reducing the effects of coupling.

[0004] Currently, die-to-die routing in practical industrial applications largely relies on manual operation, which not only leads to long production cycles but also significantly increases production costs. This traditional manual routing method is inefficient, susceptible to human factors, causing extended design cycles, and makes it difficult to guarantee routing accuracy and consistency. Therefore, researching and implementing automated die-to-die routing technology is of paramount importance. Automated routing technology can effectively shorten design cycles, improve the automation level of the routing process, and enhance production efficiency and yield.

[0005] By introducing die-to-die automated routing technology, complex and intricate routing tasks can be completed in a shorter time, significantly accelerating project progress. This not only significantly shortens the design cycle and reduces manual intervention, but also rapidly advances product production and time-to-market while ensuring routing quality. Automated routing can also reduce errors from manual operation, improve routing accuracy and consistency, thereby optimizing production processes and reducing production costs. With the widespread application of automated routing technology, enterprises will be able to improve product development efficiency, accelerate the launch of new products, and thus enhance market competitiveness. In increasingly fierce market competition, automated routing technology will become an important tool for enhancing core competitiveness, helping enterprises shorten development cycles, reduce costs, and ensure product quality and technological leadership.

[0006] However, several technical challenges remain to be addressed in 2.5D IC packaging. Similar to PCB array pin distribution, 2.5D IC packaging presents a more complex and denser pre-assigned netting problem. Netting on different dies typically involves long and parallel topologies. Therefore, existing automatic routing algorithms for PCB simultaneous escape routing cannot be directly applied to the die-to-die routing problem in 2.5D packaging. Currently, research on the die-to-die automatic routing problem in 2.5D IC packaging is still in its early stages, lacking suitable automatic routing algorithms. Therefore, further in-depth research on the die-to-die simultaneous escape routing problem in 2.5D IC packaging is urgently needed. For the 2.5D packaging die-to-die routing scenario, existing research requires further exploration in the following aspects:

[0007] (1) In the Global Routing phase, determining the fan-out sequence at the fan-out boundary is one of the keys to simultaneous escape routing. A correct fan-out sequence is a prerequisite for successful routing in both the channel and fan-out areas. Although existing research has explored simultaneous escape routing sequences in PCB scenarios, the more complex and densely distributed nets in 2.5D IC packages prevent direct application to this scenario. Therefore, further research is needed to determine the fan-out sequence at the fan-out boundary.

[0008] (2) Reasonable planning of layer allocation for all nets can effectively reduce topological crossovers in single-layer cabling and allocate layer resources reasonably. The lack of layer allocation steps may lead to crossovers or local congestion during cabling based on heuristic A* search or line exploration cabling algorithms, resulting in unreasonable resource utilization.

[0009] Therefore, further research and improvement on the above issues are needed, which is crucial for promoting the development of 2.5D IC packaging technology. Summary of the Invention

[0010] The purpose of this invention is to provide a 2.5D package die-to-die simultaneous escape routing method based on pattern matching binary tree, which solves the problems of wiring sequence planning and layer allocation in 2.5D IC package die-to-die simultaneous escape routing.

[0011] The first aspect of the present invention provides a 2.5D encapsulation die-to-die simultaneous escape routing method based on a pattern-matching binary tree, the method comprising:

[0012] The interconnection network between multiple dies is split into multiple sets of simultaneous escape routing models of two dies interconnected. Based on the separation characteristics of power and ground networks on signal networks, the signal networks in each set of models are divided into multiple network sets.

[0013] For each set of nets, fan-out line order planning and layer allocation are performed based on a pattern-matching binary tree, specifically including:

[0014] Define the routing pattern: Let the dies to which the net sets belong be D1 and D2, and the corresponding pad sets be P1 and P2; sort and number P1 according to physical location, and number P2 according to net connection relationship; then the routing patterns include ascending subsequence IS pattern and descending subsequence DS pattern.

[0015] Constructing a pattern matching binary tree: Sort P2 by physical location to obtain the initial sequence with corresponding numbers. Expand the initial sequence into a binary tree according to the routing pattern to construct a pattern matching binary tree, so as to allocate a net set into multiple net sequences and complete the fan-out routing sequence planning. Each node of the pattern matching binary tree corresponds to a net sequence, and each path corresponds to a set of net sequences that satisfy the routing pattern for the net set, thus obtaining multiple sets of net sequences that satisfy the routing pattern.

[0016] Pattern matching binary tree backtracking: By backtracking the pattern matching binary tree, each group of net sequences that meet the routing pattern is combined and assigned to different layers. A group of net sequences is selected with the goal of minimizing the total number of layers to complete the layer assignment.

[0017] Finally, routing is completed based on the fan-out routing plan and layer allocation results.

[0018] In some embodiments, the interconnect network between multiple dies is split into multiple sets of simultaneous escape routing models for two-die interconnects, and based on the separation characteristics of power and ground networks on signal networks, the signal networks in each set are divided into multiple network sets, including:

[0019] Based on the connection relationships between dies, the interconnect network is divided into multiple groups of interconnected dies;

[0020] For each pair of dies, sort the pads in the dies;

[0021] By iterating through all pads in each group, the signal lines separated by the power supply and ground grids are divided into different groups, thus obtaining multiple two-dimensional arrays, each corresponding to a set of wire grids.

[0022] In some embodiments, if P1 is numbered from left to right according to its physical location, and P2 is numbered according to the wire connection relationship, then the ascending subsequence IS mode is that the order on the fan-out boundary increases from left to right according to the order of the Pad numbers in the Die, and is distributed from top to bottom on the boundary; the descending subsequence DS mode is that the order on the fan-out boundary decreases from left to right according to the order of the Pad numbers in the Die, and is distributed from top to bottom on the boundary.

[0023] In some embodiments, the structure of the pattern matching binary tree is as follows:

[0024] (1) Root node of the tree: The root node of the tree is the initial sequence;

[0025] (2) The left child of each node: the increasing subsequence obtained from the sequence of the parent node, the IS pattern of the increasing subsequence, and the remaining sequence in the parent node after removing the increasing subsequence.

[0026] (3) The right child of each node: the descending subsequence obtained from the sequence of the parent node, the DS pattern of the corresponding descending subsequence, and the remaining sequence in the parent node after removing the descending subsequence.

[0027] In some embodiments, constructing a pattern-matching binary tree includes:

[0028] (1) Sort P2 according to its physical location to obtain the initial sequence of corresponding numbers, and set the initial sequence as the root node;

[0029] (2) Find the maximum increasing subsequence LIS for the sequence of the parent node. If the number of wires of the maximum increasing subsequence LIS is greater than the boundary capacity, obtain the increasing subsequence IS according to the increasing subsequence cost function, and remove the increasing subsequence IS from the sequence to obtain the remaining sequence. Place the increasing subsequence IS and the remaining sequence into the left child node.

[0030] The cost function for the increasing subsequence is as follows:

[0031]

[0032] In the formula, cost represents the price paid, and E represents the cost. max Fan out the upper boundary in D2, y i It is the y-coordinate of Pad in the i-th mesh D2. It is the absolute value of the difference between Pad in the i-th group of wire meshes D1 and D2, where α and β are the weights of the two terms;

[0033] The cost of each Pad is calculated using the above formula, and the subsequence IS that meets the boundary capacity is selected by sorting the subsequences from smallest to largest according to their cost values.

[0034] (3) Find the maximum decreasing subsequence LDS for the sequence of the parent node. If the number of wires in the maximum decreasing subsequence LDS is greater than the boundary capacity, obtain the decreasing subsequence DS according to the decreasing subsequence cost function, and remove the decreasing subsequence DS from the sequence to obtain the remaining sequence. Place the decreasing subsequence DS and the remaining sequence into the right child node.

[0035] The cost function for the descending subsequence is as follows:

[0036]

[0037] In the formula, E min Fan out the lower boundary in D2;

[0038] (4) Traverse all leaf nodes without child nodes, and repeatedly expand the left and right child nodes until the remaining sequence of all leaf nodes is empty.

[0039] In some embodiments, pattern matching binary tree backtracking includes:

[0040] (1) Backtrack from the leaf node to the parent node until backtracking to the root node to obtain the IS or DS net sequence of each node on the path;

[0041] (2) Classify the allocated mesh sequences into two categories: Category 1 mesh sequence T1 and Category 2 mesh sequences T2. Category 1 mesh sequence T1 has a mesh count equal to the number of meshes the boundary can accommodate, and is allocated to a single layer. Category 2 mesh sequence T2 has a mesh count less than the number of meshes the boundary can accommodate; this mesh sequence can be allocated to the same layer as other mesh sequences, but must satisfy the following inequality:

[0042]

[0043] In the formula, S size The number of nets in a single type II net sequence is given by: linewdth is the line width, viasize is the aperture size, clearance is the distance between the aperture and the line, C is the total capacity of the boundary, and i is the number of type II net sequences assigned to the same layer.

[0044] (3) Assign the first type of wire mesh sequence to a separate layer;

[0045] (4) Sort all second-type mesh sequences according to the number of meshes, select the sequence with the largest number of meshes in the mesh sequences to be assigned, and combine this sequence with other sequences in turn, requiring that the inequality in step (2) be satisfied, and then remove the several sequences that meet the conditions from the sequence to be assigned.

[0046] (5) Repeat step (4) until the sequence to be assigned is empty;

[0047] (6) Repeat steps (1) to (4) until the layering results of all leaf nodes are obtained, and select the backtracking result of the branch with the smallest required layer as the layer allocation result.

[0048] In some embodiments, routing is completed based on fan-out routing planning and layer allocation results, including:

[0049] Construct a Hanan mesh wiring map;

[0050] Each pad has a fan-out hole drilled into its designated layer;

[0051] Perform coarse-grained routing, avoiding intersections with routing obstacles during the routing process, and setting the routing result of the Pad as a routing obstacle after the routing is completed.

[0052] According to a second aspect of the present invention, a 2.5D IC is provided, wherein the 2.5D IC is routed using the pattern-matching binary tree-based 2.5D package die-to-die simultaneous escape routing method described in any one of the first aspects.

[0053] According to a third aspect of the present invention, a computer device is provided, comprising: a processor and a memory, the memory storing a program or instructions executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern-matching binary tree as described in any one of the first aspects.

[0054] According to a fourth aspect of the invention, a readable storage medium is provided having a program or instructions stored thereon, which, when executed by a processor, implement the steps of the 2.5D packaged die-to-die simultaneous escape routing method based on a pattern-matching binary tree as described in any one of the first aspects.

[0055] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0056] This invention proposes a collaborative planning technique for thread sequence planning and layer allocation in 2.5D IC packaging with simultaneous escape routing in die-to-die configurations. This technique aims to address the common problems of unreasonable thread sequence and layer allocation in traditional die-to-die routing. Through optimized thread sequence planning and layer allocation strategies, this technology not only automates the routing process but also significantly improves routing quality and efficiency. Reasonable thread sequence planning avoids unnecessary routing conflicts and reduces routing path intersections, thereby effectively improving routing performance and reliability. Simultaneously, optimized layer allocation strategies minimize routing resource consumption, greatly improving routing accuracy and reducing routing complexity. This technology effectively overcomes the limitations of traditional routing methods, improves routing performance and reliability, and provides strong technical support for the design and manufacturing of next-generation high-performance integrated circuits. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of a typical structure of a chip in a 2.5D package provided in an embodiment of this application;

[0058] Figure 2 A schematic diagram of the overall flow of a 2.5D encapsulation die-to-die simultaneous escape routing method based on a pattern matching binary tree, provided for embodiments of this application;

[0059] Figure 3 A wiring pattern diagram is provided for an embodiment of this application; wherein, Figure 3 (a) in the diagram is the IS mode diagram of D1. Figure 3 (b) in the diagram is the IS mode diagram of D2. Figure 3 (c) in the diagram is the DS mode diagram of D1. Figure 3 (d) in the diagram represents the DS model of D2;

[0060] Figure 4 This application provides a practical test case diagram for an embodiment of the invention; wherein, Figure 4 (a) in the diagram is an actual measurement example of the left device D1. Figure 4 (b) in the diagram is an actual measurement example of the right device D2;

[0061] Figure 5 A pattern matching binary tree structure diagram provided in this application embodiment;

[0062] Figure 6 This is a schematic diagram of a line sequence allocation result provided in an embodiment of this application;

[0063] Figure 7 This is a schematic diagram of a Hanan mesh construction provided in an embodiment of this application;

[0064] Figure 8 This application provides a global routing diagram for simultaneous die-to-die escape routing in an embodiment; wherein, Figure 8 (a) in the diagram is the wiring diagram for the MB layer. Figure 8 (b) in the diagram is the routing diagram for RDL1 layer. Figure 8 (c) in the diagram is the routing diagram for RDL2 layer;

[0065] Figure 9 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this invention.

[0067] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0068] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0069] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0070] This application designs a global routing plan for simultaneous escape routing in 2.5D IC packaging, specifically involving the layer allocation of escape area nets, the determination of the line sequence of escape boundaries, and the global routing of the Redistribution Layer (RDL) in simultaneous escape routing.

[0071] like Figure 2 As shown, this application proposes a 2.5D encapsulation die-to-die simultaneous escape routing method based on a pattern-matching binary tree, as detailed below:

[0072] 1. Overall Framework

[0073] Overall framework as follows Figure 2As shown, the process is divided into three parts: preprocessing of 2.5D IC package die-to-die net data, a pattern-matching binary tree-based routing planning and layer allocation method, and global routing. First, the preprocessing stage completes the initial grouping based on the given netlist information. Then, in the routing and layer co-planning stage, the routing pattern is determined, and a pattern-matching binary tree is constructed to assign routing patterns to the nets in the current group, planning the net sequence on the fan-out boundaries. Next, in the pattern-matching binary tree backtracking stage, layers are partitioned based on the capacity of the fan-out boundaries and the obtained fan-out order, ensuring that the topology of the fan-out and channel areas of each layer of nets does not intersect. Finally, a Hanan mesh is constructed, and global routing is performed on the nets after routing planning and layer allocation.

[0074] 2. Pretreatment

[0075] The input netlist information may contain interconnections between multiple dies. First, these interconnection models need to be broken down into multiple sets of simultaneous escape routing models for two-die interconnections. This not only simplifies the complexity of the problem but also allows for better handling of routing resource allocation. Due to the large scale of the nets to be processed, during the data preprocessing stage, the signal nets need to be divided into multiple data processing units based on the separation characteristics of power and ground signal layers. Each unit contains a set of pad nets, and each set is processed independently.

[0076] The input to the preprocessing stage is all device information D[1…n] and netlist information N[1…t], and the output is the grouping results of all pads. The main steps of preprocessing are as follows:

[0077] (1) Based on the connection relationship between the devices, divide the devices into pairs into groups G[1…m];

[0078] (2) For each pair of devices, sort the Pads in the devices to obtain P[1…m];

[0079] (3) Traverse all Pads and divide the ordinary signal lines that are separated from the power supply and grounding grid into groups to obtain a two-dimensional array Pgroup[1…m][1…n].

[0080] 3. Escape sequence and layer allocation collaborative planning

[0081] In multi-layer escape routing, the fan-out sequence primarily determines the pin order of each signal line on the fan-out boundary, i.e., the order of the signal fan-out points on the boundary. Layer allocation, on the other hand, determines which layer each signal line is routed on. A reasonable layer allocation can effectively resolve topological crossovers between nets and address situations where the boundary capacity is insufficient to support all net fan-outs. During design, it is crucial to ensure that the signals from these pins can fan out smoothly and effectively to the chip's fan-out boundary, and to guarantee that the channel topology does not cross. For boundary areas with multiple pads requiring fan-out, a reasonable sequence can avoid collisions and overlaps between signal lines, thereby reducing design complexity.

[0082] This application proposes a method for collaborative planning of fan-out routing and layer allocation based on pattern-matching binary trees. In simple terms, for a simultaneous escape routing model of two interconnected dies, a routing pattern is first given. Each preprocessed net set, based on the given routing pattern, can first obtain the fan-out routing allocation in a single layer. The routing pattern also guarantees the completion of signal line routing in the RDL layer. Then, the initial sequence is expanded into a binary tree according to the routing pattern. By backtracking and matching combinations of various patterns, the layer is minimized, thus completing the collaborative planning of fan-out routing and layer allocation.

[0083] 3.1 Wiring Mode

[0084] By pre-setting routing patterns, the allocation of fan-out wires in a single layer can be guided. A routing pattern is essentially a pattern for the fan-out point order of the pads. That is, from a set of pad net sequences, a group of nets conforming to the routing pattern is selected to form a subsequence. The fan-out order of all nets in this subsequence is then determined, and all nets in this subsequence are allocated to the same layer. Routing patterns can avoid potential topology crossovers and congestion during routing by planning the fan-out point order of each pad, and can also improve overall routing efficiency and reduce complexity by optimizing routing paths.

[0085] For a given set of nets N[1…n], the dies to which the two ends of the nets in N belong are D1 and D2, and the pad sets on D1 and D2 are P1 and P2, respectively. First, P1 is sorted from left to right according to its physical location and renumbered. Then, P2 is renumbered according to the net connection relationship. Then the wiring pattern can be defined as:

[0086] (1) The order on the fan-out boundary increases from left to right according to the numbering of the pads within the die, and is distributed from top to bottom on the boundary, i.e., the increasing subsequence (IS), such as... Figure 3 (a) and (b) in the text;

[0087] (2) The order on the fan-out boundary decreases from left to right according to the numbering of the pads within the die, and is distributed from top to bottom on the boundary, i.e., the Decreasing Subsequence (DS), such as... Figure 3 (c) and (d) in the text.

[0088] 3.2 Pattern Matching Binary Tree

[0089] In escape cabling, a reasonable fan-out order can effectively avoid intersecting cabling paths, thereby reducing cabling conflicts and preventing cabling congestion. The construction process of the pattern matching binary tree is the process of allocating the fan-out wire sequence of a single-layer net, and the backtracking process of the pattern matching binary tree is the layer allocation process of allocating the fan-out wire sequence of a single-layer net to a specific layer.

[0090] After renumbering all the nets, rearrange all the nets in D2 from left to right to obtain an initial sequence of nets. Figure 4 This is an example that might be encountered in a real-world scenario, in which... Figure 4 (a) in the diagram is an actual measurement example of the left device D1. Figure 4 (b) in the diagram is an actual test case diagram of the right device D2. For example... Figure 4 As shown, given a set of nets N[1…n], where the capacity of the fan-out boundary is 9, that is, a single layer can accommodate a maximum of 9 nets. First, the nets in the two devices are renumbered. Then, all the nets in D2 are arranged in order of their physical positions from left to right to obtain a net sequence. The initial sequence is 2, 1, 3, 4, 5, 6, 7, 8, 10, 9, 12, 11, 14, 13, 16, 15, 18, 17.

[0091] The root node of the pattern matching binary tree is the initial sequence obtained after renumbering. The left branch of the tree represents the IS pattern, and the right branch represents the DS pattern. Expanding to the left involves calculating the IS of the sequence in the parent node and removing the IS from the sequence to obtain the remaining sequence. Expanding to the right involves calculating the DS of the sequence in the parent node and removing the DS from the sequence to obtain the remaining sequence. This binary tree continues to expand until the remaining sequence of the child node is empty. The tree structure diagram is shown below. Figure 5 .

[0092] The structure of a tree is as follows:

[0093] (1) Root node of the tree: The root node of the tree is the obtained initial sequence initSequence;

[0094] (2) The left child of each node: the increasing subsequence obtained from the sequence of the parent node, corresponding to the IS pattern, and the remaining sequence in the parent node after removing the IS.

[0095] (3) The right child of each node: the descending subsequence obtained from the sequence of the parent node, corresponding to the DS pattern, and the remaining sequence in the parent node after removing the DS.

[0096] Each node in a pattern matching binary tree corresponds to a net sequence, and each path corresponds to a set of net sequences that satisfy the routing pattern. This results in multiple sets of net sequences that satisfy the routing pattern (the number of sets equals the number of paths). Furthermore, the net sequences corresponding to all nodes on each path are combined to form the net set.

[0097] 3.2.1 Construction of Pattern Matching Binary Tree

[0098] First, determine the root node. Set the initial sequence obtained after renumbering and resorting as the root node. Then, expand the root node into two child nodes, left and right. The process of determining the left child node is as follows: find the longest increasing subsequence (LIS) of the parent node's sequence. However, the number of nets in the obtained LIS may be greater than the boundary capacity, which is not allowed. If the number of nets in the obtained LIS is greater than the boundary capacity, calculate the cost of each pad in the LIS, sort them in ascending order of cost, and select the longest increasing subsequence (IS) that meets the boundary capacity. The cost function is:

[0099]

[0100] In the formula, E max Let y be the upper boundary of the fan-out in D2. i It is the y-coordinate of Pad in the i-th mesh D2. It is the absolute value of the difference between Pad in the i-th group of wire meshes D1 and D2, where α and β are the weights of the two terms;

[0101] The process of determining the right child node is similar to that of the left child node. First, the Longest Decreasing Subsequence (LDS) is calculated for the parent node. If the number of LDS meshes is greater than the boundary capacity, then the DS sequence with the lowest cost is selected according to the cost function, which is:

[0102]

[0103] Similar to Equation 3-1, where E min Fan out the lower boundary in D2.

[0104] Then, for each leaf node, determine if the current node's sequence is empty. If it is not empty, continue expanding the node into left and right child nodes as described above, until the remaining sequences of all leaf nodes are empty.

[0105] It should be noted that finding the maximum increasing subsequence or the maximum decreasing subsequence of a sequence is an existing technique.

[0106] The specific steps for constructing a pattern matching binary tree are as follows:

[0107] (1) Sort the Pads in D2 from left to right and from top to bottom to get the initial sequence initSequence, and set the initial sequence as the root node;

[0108] (2) Calculate the LIS of the sequence of the parent node. If the number of wires in the LIS is greater than the boundary capacity, obtain the IS according to Formula 3-1, and remove the IS from the sequence to obtain the remaining sequence. Place the IS and the remaining sequence into the left child node.

[0109] (3) Calculate the LDS of the sequence of the parent node. If the number of wires in the LDS is greater than the boundary capacity, obtain the DS sequence according to Formula 3-2, and remove the DS from the sequence to obtain the remaining sequence. Place the DS and the remaining sequence into the right child node.

[0110] (4) Traverse all leaf nodes without child nodes, and repeatedly expand the left and right child nodes until the remaining sequence of all leaf nodes is empty;

[0111] The pseudocode for constructing a pattern matching binary tree is shown in Table 1.

[0112] Table 1. Pseudocode for constructing a pattern-matching binary tree.

[0113]

[0114]

[0115] 3.2.2 Backtracking of Pattern Matching Binary Trees

[0116] To meet specific topology requirements, multiple net sequences, pre-assigned according to the routing pattern, need to be distributed across different layers within the fan-out boundary capacity. Through routing sequence planning, multiple sets of net sequences satisfying the routing pattern can be obtained. Now, these net sequences need to be combined and distributed across different layers, ensuring that the number of nets distributed in the same layer does not exceed the boundary capacity. This is the backtracking function of the pattern matching binary tree.

[0117] The goal of the pattern matching binary tree backtracking process is to minimize the number of levels. Each child node's IS or DS can be divided into two categories based on the number of nets: The first category is where the number of nets in the sequence equals the number of nets the boundary can accommodate; in this case, the sequence is assigned to a single level, and the required number of levels is fixed. The second category is where the number of nets is less than the boundary capacity; this sequence can be assigned to the same level as other sequence types, but the following inequality must be satisfied:

[0118] ∑i (S size ) * (linewidth + clearance) + (i + 1) * (viasize + clearance) < C Formula 3-3

[0119] Where S size is the number of nets of a single second - type sequence, linewidth is the line width, viasize is the size of the via, clearance is the distance between the via and the line, C is the boundary capacity, and i is the number of second - type sequences assigned to the same layer. The meaning of this formula is that the sum of the number of nets of the second - type sequences assigned to the same layer plus the interval requirements between each group of second - type sequences is less than the boundary capacity. Therefore, the goal of the backtracking process of the pattern - matching binary tree can be simplified as: starting from each leaf node, backtracking to the root node to obtain multiple backtracking results, and reasonably combining and allocating the second - type net sequences among them to minimize the layer resources required by the second - type sequences.

[0120] The combination and allocation of the second - type nets can adopt a greedy strategy, pursuing a locally optimal solution in each step of selection, and finally obtaining a solution close to the globally optimal one. The specific steps of the backtracking process of the pattern - matching binary tree are as follows:

[0121] (1) Backtrack from the leaf node to the parent node until reaching the root node to obtain the IS or DS net sequences N[1…s][1…t] of each node;

[0122] (2) Classify the allocated net sequences N[1…s][1…t] into the first - type and second - type net sequences T1 and T2;

[0123] (3) Allocate the first - type nets to a separate layer;

[0124] (4) Sort all the second - type sequences according to the number of nets, select the sequence with the largest number of nets in the sequences to be allocated, combine this sequence with other sequences in turn, requiring to satisfy Formula 3 - 3, and then remove the several sequences that meet the conditions from the sequences to be allocated;

[0125] (5) Repeat step (4) until the sequences to be allocated are empty.

[0126] (6) Repeat steps (1), (2), (3), (4) until obtaining the layer - by - layer results of all leaf nodes, and select the backtracking result with the smallest required layer as the layer allocation result.

[0127] It should be noted that when combining this sequence with other sequences in turn in step (4), it is also possible not to select the sequence with the largest number of nets in the sequences to be allocated, but to combine them by other methods.

[0128] The pseudocode for the backtracking phase of the pattern matching binary tree is shown in Table 2.

[0129] Table 2. Pseudocode for the backtracking phase of a pattern matching binary tree.

[0130]

[0131]

[0132]

[0133] After the test cases were processed by constructing a pattern-matching binary tree, the final result was: 2, 3, 5, 7, 9, 11, 13, 15, 17 are on the same level; 1, 4, 6, 8, 10, 12, 14, 16, 18 are on the same level. Figure 6 As shown. The line sequence planning and layer allocation results for this test case are as follows: the fan-out order of the nets allocated to the RDL1 layer on the boundary from top to bottom are 2, 3, 5, 7, 9, 11, 13, 15, 17, and the fan-out order of the nets allocated to the RDL2 layer on the boundary from top to bottom are 1, 4, 6, 8, 10, 12, 14, 16, 18.

[0134] 4 Overall Cabling

[0135] The purpose of overall routing is to provide routing guidance for the next stage of detailed routing. Overall routing needs to consider the roamability of detailed routing and has high operating speed. Because most scenarios involve regularly distributed pad arrays, such as Grid PinArray and Staggered Pin Array, Hanan grids are used as the overall routing unit. The construction of Hanan grids is as follows: Figure 7 The white rectangles represent pads, and the blue rectangles represent wireable resources. Using Hanan meshes for coarse-grained routing effectively records the physical location of each trace, prevents trace crossings during routing, calculates congestion levels, and detects potential congestion risks.

[0136] The overall routing algorithm in this application ensures topology compatibility through wire sequence planning and layer allocation. Then, based on Hanan grids as the basic routing units, coarse-grained routing is performed to obtain grid paths. These grid paths guide the routing areas for detailed routing. Each set of nets has a unique path, and the Hanan grids it traverses are determined, thus allowing the calculation of the nets traversed within each Hanan grid.

[0137] The overall routing diagram in this embodiment is represented by G(V, E), where V is composed of the four vertices of a Hanan mesh, containing the position information of the Pad and determining the physical location of a specific Cell through the four vertices. E represents the edge information of each Cell, containing the information of adjacent Cells. In one Cell, another adjacent Cell can be indexed through an edge. Each mesh has only one unique path and leaves a routing trace in the Cell. Whether a routing path intersects with an existing routing path is determined by judging whether the current routing path intersects with an existing routing path.

[0138] The specific steps for overall cabling are as follows:

[0139] (1) Net preprocessing;

[0140] (2) Line sequence planning and layer allocation;

[0141] (3) Construct a Hanan mesh wiring map;

[0142] (4) Drill holes in each Pad to the designated layer of that Pad;

[0143] (5) Perform coarse-grained routing. During the routing process, avoid crossing routing obstacles. After the routing is completed, set the routing result of the Pad as a routing obstacle.

[0144] The overall routing pseudocode is shown in Table 3.

[0145] Table 3 Overall Wiring Pseudocode

[0146]

[0147]

[0148] 5. Final Results Display

[0149] The overall routing result based on this algorithm is as follows: Figure 8 As shown, Figure 8 (a) shows the metal bonding (MB) layer traces. The MB layer includes rectangular pads, MB layer traces, and fan-out vias. Figure 8 (b) represents the RDL1 layer. Holes drilled in the pads of the RDL2 layer will penetrate the RDL1 layer, thus leaving holes in the RDL1 layer. The RDL1 layer includes holes in the pads of the RDL1 layer, holes in the pads of the RDL2 layer, and traces in the RDL1 layer. Figure 8 (c) in the figure represents the RDL2 layer, which includes vias allocated in the RDL2 layer Pad and the RDL2 layer traces.

[0150] In addition, combined Figure 2The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree described in this application embodiment can be implemented by a computer device. Figure 9 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application. Figure 9 As shown, the device may include a processor 301 and a memory 302 storing computer program instructions.

[0151] Specifically, the processor 301 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0152] Memory 302 may include a mass storage device for data or instructions. For example, and not limitingly, memory 302 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), flash memory, an optical disk drive, a magneto-optical disk drive, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 302 may include removable or non-removable (or fixed) media. Where appropriate, memory 302 may be internal or external to a data processing device. In a particular embodiment, memory 302 is non-volatile memory. In a particular embodiment, memory 302 includes read-only memory (ROM) and random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable read-only memory (PROM), an erasable read-only ROM (EPROM), an electrically erasable read-only ROM (EEPROM), an electrically alterable read-only ROM (EAROM), or flash memory, or a combination of two or more of these. Where appropriate, the RAM can be Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM). DRAM can be Fast Page Mode Dynamic Random-Access Memory (FPMDRAM), Extended Data Out Dynamic Random-Access Memory (EDODRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0153] The memory 302 can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor 301.

[0154] The processor 301 reads and executes computer program instructions stored in the memory 302 to implement any of the 2.5D packaged die-to-die simultaneous escape routing methods based on pattern matching binary trees in the above embodiments.

[0155] In some embodiments, the point cloud generation device may further include a communication interface 303 and a bus 300. Wherein, as... Figure 9 As shown, the processor 301, memory 302, and communication interface 303 are connected through bus 300 and complete communication with each other.

[0156] The communication interface 303 is used to enable communication between the various modules, devices, units, and / or equipment in the embodiments of this application. The communication interface 303 can also enable data communication with other components such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations.

[0157] Bus 300 includes hardware, software, or both, that couples the components of the point cloud generation device together. Bus 300 includes, but is not limited to, at least one of the following: data bus, address bus, control bus, expansion bus, and local bus. For example, and not as a limitation, bus 300 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 300 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnection.

[0158] The computer device can execute the pattern-matching binary tree-based 2.5D encapsulation die-to-die simultaneous escape routing method in this application embodiment based on the rendering device, thereby achieving a combination of... Figure 2 The described method is a 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary trees.

[0159] Furthermore, in conjunction with the pattern-matching binary tree-based 2.5D packaged die-to-die simultaneous escape routing method described in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the pattern-matching binary tree-based 2.5D packaged die-to-die simultaneous escape routing methods described in the above embodiments.

[0160] In summary, the proposed 2.5D IC packaging die-to-die simultaneous escape routing technique, combining routing sequence planning and layer allocation, aims to address the common problems of unreasonable routing sequence and layer allocation in traditional die-to-die routing. Through optimized routing sequence planning and layer allocation strategies, this technique not only automates the routing process but also significantly improves routing quality and efficiency. Reasonable routing sequence planning avoids unnecessary routing conflicts and reduces routing path intersections, thereby effectively improving routing performance and reliability. Simultaneously, optimized layer allocation strategies minimize routing resource consumption, greatly improving routing accuracy and reducing routing complexity. This technique effectively overcomes the limitations of traditional routing methods, enhances routing performance and reliability, and provides strong technical support for the design and manufacturing of next-generation high-performance integrated circuits.

[0161] It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. In addition, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of steps / components can be combined into new steps / components to achieve the purpose of this application.

[0162] It will be readily understood by those skilled in the art that the above-described embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary trees, characterized in that, The method includes: The interconnection network between multiple dies is split into multiple sets of simultaneous escape routing models of two dies interconnected. Based on the separation characteristics of power and ground networks on signal networks, the signal networks in each set of models are divided into multiple network sets. For each set of nets, fan-out line order planning and layer allocation are performed based on a pattern-matching binary tree, specifically including: Define the routing pattern: Let the dies to which the net sets belong be D1 and D2, and the corresponding pad sets be P1 and P2; sort and number P1 according to physical location, and number P2 according to net connection relationship; then the routing patterns include ascending subsequence IS pattern and descending subsequence DS pattern. Constructing a pattern matching binary tree: Sort P2 by physical location to obtain the initial sequence with corresponding numbers. Expand the initial sequence into a binary tree according to the routing pattern to construct a pattern matching binary tree, so as to allocate a net set into multiple net sequences and complete the fan-out routing sequence planning. Each node of the pattern matching binary tree corresponds to a net sequence, and each path corresponds to a set of net sequences that satisfy the routing pattern for the net set, thus obtaining multiple sets of net sequences that satisfy the routing pattern. Pattern matching binary tree backtracking: By backtracking the pattern matching binary tree, each group of net sequences that meet the routing pattern is combined and assigned to different layers. A group of net sequences is selected with the goal of minimizing the total number of layers to complete the layer assignment. Finally, routing is completed based on the fan-out routing plan and layer allocation results.

2. The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that, The interconnect network between multiple dies is split into multiple sets of simultaneous escape routing models for interconnecting two dies. Based on the separation characteristics of power and ground networks on signal networks, the signal networks in each set are further divided into multiple network sets, including: Based on the connection relationships between dies, the interconnect network is divided into multiple groups of interconnected dies; For each pair of dies, sort the pads in the dies; By iterating through all pads in each group, the signal lines separated by the power supply and ground grids are divided into different groups, thus obtaining multiple two-dimensional arrays, each corresponding to a set of wire grids.

3. The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that, If P1 is numbered from left to right according to its physical location, and P2 is numbered according to the network connection relationship, then the ascending subsequence IS pattern is that the order on the fan-out boundary increases from left to right according to the order of the Pad numbers in the Die, and is distributed from top to bottom on the boundary; the descending subsequence DS pattern is that the order on the fan-out boundary decreases from left to right according to the order of the Pad numbers in the Die, and is distributed from top to bottom on the boundary.

4. The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that, The structure of a pattern matching binary tree is as follows: (1) Root node of the tree: The root node of the tree is the initial sequence; (2) The left child of each node: the increasing subsequence obtained from the sequence of the parent node, the IS pattern of the increasing subsequence, and the remaining sequence in the parent node after removing the increasing subsequence. (3) The right child of each node: the descending subsequence obtained from the sequence of the parent node, the DS pattern of the corresponding descending subsequence, and the remaining sequence in the parent node after removing the descending subsequence.

5. The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that, Construct a pattern-matching binary tree, including: (1) Sort P2 according to its physical location to obtain the initial sequence of corresponding numbers, and set the initial sequence as the root node; (2) Find the maximum increasing subsequence LIS for the sequence of the parent node. If the number of wires of the maximum increasing subsequence LIS is greater than the boundary capacity, obtain the increasing subsequence IS according to the increasing subsequence cost function, and remove the increasing subsequence IS from the sequence to obtain the remaining sequence. Place the increasing subsequence IS and the remaining sequence into the left child node. The cost function for the increasing subsequence is as follows: In the formula, cost represents the price paid, and E represents the cost. max Fan out the upper boundary in D2, y i It is the y-coordinate of Pad in the i-th mesh D2. It is the absolute value of the difference between Pad in the i-th group of wire meshes D1 and D2, where α and β are the weights of the two terms; The cost of each Pad is calculated using the above formula, and the subsequence IS that meets the boundary capacity is selected by sorting the subsequences from smallest to largest according to their cost values. (3) Find the maximum decreasing subsequence LDS for the sequence of the parent node. If the number of wires in the maximum decreasing subsequence LDS is greater than the boundary capacity, obtain the decreasing subsequence DS according to the decreasing subsequence cost function, and remove the decreasing subsequence DS from the sequence to obtain the remaining sequence. Place the decreasing subsequence DS and the remaining sequence into the right child node. The cost function for the descending subsequence is as follows: In the formula, E min Fan out the lower boundary in D2; (4) Traverse all leaf nodes without child nodes, and repeatedly expand the left and right child nodes until the remaining sequence of all leaf nodes is empty.

6. The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that, Pattern matching binary tree backtracking includes: (1) Backtrack from the leaf node to the parent node until backtracking to the root node to obtain the IS or DS net sequence of each node on the path; (2) Classify the allocated mesh sequences into two categories: Category 1 mesh sequence T1 and Category 2 mesh sequences T2. Category 1 mesh sequence T1 has a mesh count equal to the number of meshes the boundary can accommodate, and is allocated to a single layer. Category 2 mesh sequence T2 has a mesh count less than the number of meshes the boundary can accommodate; this mesh sequence can be allocated to the same layer as other mesh sequences, but must satisfy the following inequality: In the formula, S size The number of nets in a single type II net sequence is given by: linewidth is the line width, viasize is the size of the via, clearance is the distance between the via and the line, C is the total capacity of the boundary, and i is the number of type II net sequences assigned to the same layer. (3) Assign the first type of wire mesh sequence to a separate layer; (4) Sort all second-type mesh sequences according to the number of meshes, select the sequence with the largest number of meshes in the mesh sequences to be assigned, and combine this sequence with other sequences in turn, requiring that the inequality in step (2) be satisfied, and then remove the several sequences that meet the conditions from the sequence to be assigned. (5) Repeat step (4) until the sequence to be assigned is empty; (6) Repeat steps (1) to (4) until the layering results of all leaf nodes are obtained, and select the backtracking result of the branch with the smallest required layer as the layer allocation result.

7. The 2.5D encapsulation die-to-die simultaneous escape routing method based on pattern matching binary tree according to claim 1, characterized in that, The routing is completed based on the fan-out routing plan and layer allocation results, including: Construct a Hanan mesh wiring map; Each pad has a fan-out hole drilled into its designated layer; Perform coarse-grained routing, avoiding intersections with routing obstacles during the routing process, and setting the routing result of the Pad as a routing obstacle after the routing is completed.

8. A 2.5D IC, characterized in that, The 2.5D IC is routed using the pattern-matching binary tree-based 2.5D package die-to-die simultaneous escape routing method as described in any one of claims 1 to 7.

9. A computer device, characterized in that, include: A processor and a memory, wherein the memory stores a program or instructions that can run on the processor, and when the program or instructions are executed by the processor, implement the steps of the 2.5D packaged die-to-die simultaneous escape routing method based on a pattern-matching binary tree as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that, It stores a program or instructions that, when executed by a processor, implement the steps of the 2.5D encapsulation Die-to-Die simultaneous escape routing method based on a pattern-matching binary tree as described in any one of claims 1 to 7.

Images