Display substrate, driving method thereof and display device

Abstract

The invention provides a display substrate, a driving method thereof and a display device. The display substrate comprises a plurality of sub-pixels; the sub-pixel comprises a sub-pixel driving circuit, and the sub-pixel driving circuit comprises a driving transistor, a data writing transistor, a first capacitor and a second capacitor; a first pole plate of the first capacitor is coupled with a grid electrode of the driving transistor, a second pole plate of the first capacitor is coupled with a second pole of the data write-in transistor, and a first pole of the data write-in transistor is coupled with a corresponding data line; the first pole plate of the second capacitor is coupled with the second pole plate of the first capacitor, and the second pole plate of the second capacitor is coupled with the corresponding power line; in the sub-pixel driving circuits located in the same row in the first direction, second pole plates of second capacitors included in all the sub-pixel driving circuits are sequentially arranged in the first direction, and spacer regions are arranged between the second pole plates of the adjacent second capacitors. The orthographic projection of the data line on the substrate is at least partially overlapped with the orthographic projection of the spacer region on the substrate.

Description

[0001] Cross - reference to related applications

[0002] This application is a divisional application of a Chinese patent application with an application date of November 13, 2023, an application number of 202380011665.X, and an invention title of "Display Substrate, Driving Method Thereof, and Display Device". Technical field

[0003] The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a driving method thereof, and a display device. Background art

[0004] Organic Light - Emitting Diode (OLED) display products have advantages such as high brightness and self - emission, and are widely used in various fields. However, the current OLED display products have a low refresh rate and are not suitable for high - refresh - rate scenarios. In order to achieve high - frequency display of OLED display products, a scheme of using a separate sub - pixel driving circuit in the OLED display product is adopted, that is, the compensation stage and the data writing stage of the sub - pixel driving circuit are independently controlled, and this control method realizes high - frequency display to a certain extent. Summary of the invention

[0005] The purpose of the present disclosure is to provide a display substrate, a driving method thereof, and a display device.

[0006] To achieve the above purpose, the present disclosure provides the following technical solutions:

[0007] A first aspect of the present disclosure provides a display substrate, including: a substrate substrate, and a power line, a data line, and a plurality of sub - pixels all disposed on the substrate substrate; the sub - pixels include a sub - pixel driving circuit and a light - emitting element coupled to each other, and the sub - pixel driving circuit includes a driving transistor, a data - writing transistor, a first capacitor, and a second capacitor;

[0008] A first electrode plate of the first capacitor is coupled to a gate of the driving transistor, a second electrode plate of the first capacitor is coupled to a second pole of the data - writing transistor, and a first pole of the data - writing transistor is coupled to the corresponding data line;

[0009] A first electrode plate of the second capacitor is coupled to the second electrode plate of the first capacitor, and a second electrode plate of the second capacitor is coupled to the corresponding power line;

[0010] In the sub-pixel driving circuits located in the same row along the first direction, the second plates of the second capacitors included in each sub-pixel driving circuit are arranged in sequence along the first direction, and there is a spacer region between the second plates of adjacent second capacitors. The positive projection of the data line on the substrate substrate overlaps at least partially with the positive projection of the spacer region on the substrate substrate.

[0011] Optionally, the second plates of the second capacitors adjacent along the first direction are coupled through a plate connection portion. Between the second plates of adjacent second capacitors, the spacer region and the plate connection portion are arranged in a second direction, and the second direction intersects with the first direction; the positive projection of the data line on the substrate substrate overlaps at least partially with the positive projection of the plate connection portion on the substrate substrate.

[0012] Optionally, the display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes a first compensation transistor and a first reset transistor; the first pole of the first compensation transistor is coupled to the second pole of the driving transistor, and the second pole of the first compensation transistor is coupled to the gate of the driving transistor; the first pole of the first reset transistor is coupled to the corresponding first initialization signal line, and the second pole of the first reset transistor is coupled to the gate of the driving transistor; the first compensation transistor includes a first compensation active layer, and the first reset transistor includes a first reset active layer;

[0013] The plate connection portion includes a connected main body portion and a connected extension portion that are coupled. The connected main body portion is respectively coupled to the second plates of adjacent second capacitors. The positive projection of the connected extension portion on the substrate substrate overlaps at least partially with the positive projection of the first compensation active layer included in one sub-pixel driving circuit among two adjacent sub-pixel driving circuits along the first direction on the substrate substrate, and / or overlaps at least partially with the positive projection of the first reset active layer included in the other sub-pixel driving circuit among two adjacent sub-pixel driving circuits along the first direction on the substrate substrate;

[0014] The positive projection of the data line on the substrate substrate overlaps at least partially with the positive projection of the connected main body portion on the substrate substrate; and / or the positive projection of the data line on the substrate substrate overlaps at least partially with the positive projection of the connected extension portion on the substrate substrate.

[0015] Optionally, the first compensation active layer includes two first compensation channel portions and first compensation conductor portions respectively coupled to the two first compensation channel portions; the first reset active layer includes two first reset channel portions and first reset conductor portions respectively coupled to the two first reset channel portions;

[0016] The orthographic projection of the connection extension portion on the substrate substrate overlaps at least partially with the orthographic projection of the first compensation conductor portion included in one of the two sub-pixel driving circuits adjacent in the first direction on the substrate substrate, and / or overlaps at least partially with the orthographic projection of the first reset conductor portion included in the other of the two sub-pixel driving circuits adjacent in the first direction on the substrate substrate.

[0017] Optionally, the display substrate further includes a plurality of first reference signal connection lines and a plurality of second reference signal connection lines, and the first reference signal connection lines and the second reference signal connection lines are alternately arranged along the first direction; the orthographic projection of at least part of the data lines on the substrate substrate is located between the orthographic projection of the adjacent first reference signal connection lines on the substrate substrate and the orthographic projection of the second reference signal connection lines on the substrate substrate; the data lines and the first reference signal connection lines are arranged on different layers; and / or the data lines and the second reference signal connection lines are arranged on different layers.

[0018] Optionally, the display substrate further includes a plurality of first reference signal lines; the sub-pixel driving circuit further includes a second reset transistor, a first pole of the second reset transistor is coupled to the corresponding first reference signal line, and a second pole of the second reset transistor is coupled to a second electrode plate of the first capacitor; the first reference signal connection line is respectively coupled to the plurality of first reference signal lines.

[0019] Optionally, the display substrate further includes a plurality of second reference signal lines; the sub-pixel driving circuit further includes a third reset transistor, a first pole of the third reset transistor is coupled to the corresponding second reference signal line, and a second pole of the third reset transistor is coupled to a first pole of the driving transistor; the second reference signal connection line is respectively coupled to the plurality of second reference signal lines.

[0020] Optionally, the display substrate further includes a plurality of first initialization signal connection lines and a plurality of second initialization signal connection lines, and the first initialization signal connection lines and the second initialization signal connection lines are alternately arranged along the first direction; the orthographic projection of at least part of the data lines on the substrate substrate is located between the orthographic projection of the adjacent first initialization signal connection lines on the substrate substrate and the orthographic projection of the second initialization signal connection lines on the substrate substrate; the data lines and the first initialization signal connection lines are arranged on different layers; and / or the data lines and the second initialization signal connection lines are arranged on different layers.

[0021] Optionally, the display substrate further includes a plurality of first initialization signal lines; the sub-pixel driving circuit further includes a first reset transistor, a first pole of the first reset transistor is coupled to the corresponding first initialization signal line, a second pole of the first reset transistor is coupled to a gate of the driving transistor; the first initialization signal connection line is respectively coupled to the plurality of first initialization signal lines.

[0022] Optionally, the display substrate further includes a plurality of second initialization signal lines; the sub-pixel driving circuit further includes a fourth reset transistor, a first pole of the fourth reset transistor is coupled to the corresponding second initialization signal line, a second pole of the fourth reset transistor is coupled to an anode of the light-emitting element; the second initialization signal connection line is respectively coupled to the plurality of second initialization signal lines.

[0023] Optionally, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially stacked in a direction away from the substrate.

[0024] The data line is provided with the same layer and the same material as the third source-drain metal layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line, and the second initialization signal connection line are all provided with the same layer and the same material as the second source-drain metal layer.

[0025] Optionally, the display substrate further includes a plurality of data line leads; the display substrate includes a plurality of data lines arranged along the first direction, and the plurality of data lines are divided into a first group of data line groups, a second group of data line groups, and a third group of data line groups arranged along the first direction;

[0026] The data lines in the first group of data line groups are coupled to the corresponding data line leads, and the data line leads extend from the position where the data lines to which they are coupled to the middle area of the display substrate and extend from the middle area to the lower border area of the display substrate;

[0027] The data lines in the third group of data line groups are coupled to the corresponding data line leads, and the data line leads extend from the position where the data lines to which they are coupled to the middle area and extend from the middle area to the lower border area.

[0028] Optionally, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially stacked in a direction away from the substrate.

[0029] The data line is provided on the same layer and with the same material as the second source-drain metal layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line, and the second initialization signal connection line are all provided on the same layer and with the same material as the third source-drain metal layer.

[0030] Optionally, the display substrate includes a light-shielding layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially stacked in a direction away from the substrate.

[0031] The data line is provided on the same layer and with the same material as the light-shielding layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line, and the second initialization signal connection line are all provided on the same layer and with the same material as the second source-drain metal layer.

[0032] Optionally, the display substrate further includes a plurality of power connection lines, and the power connection lines include at least a part extending along the first direction, and the power connection lines are respectively coupled to the plurality of power supply lines.

[0033] Optionally, the power connection line includes a plurality of first power parts and a plurality of second power parts, and the first power parts and the second power parts are alternately arranged along the first direction;

[0034] The first power part includes a first sub-part and a second sub-part, the first sub-part is respectively coupled to the second sub-part and the power supply line, adjacent second sub-parts and second power parts are coupled to each other, the width of the second power part along the second direction is greater than the width of the second sub-part, and the orthographic projection of the second power part on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0035] Optionally, the sub-pixel further includes a first scan line and a control signal line; the sub-pixel driving circuit further includes a first compensation transistor and a second compensation transistor, the gate of the first compensation transistor is coupled to the corresponding first scan line, the first pole of the first compensation transistor is coupled to the second pole of the driving transistor, and the second pole of the first compensation transistor is coupled to the gate of the driving transistor; the gate of the second compensation transistor is coupled to the corresponding control signal line, the first pole of the second compensation transistor is coupled to the corresponding power supply line, and the second pole of the second compensation transistor is coupled to the first pole of the driving transistor.

[0036] Optionally, in the same sub-pixel driving circuit, the control signal line to which the gate of the second compensation transistor is coupled is multiplexed as the first scan line to which the gate of the first compensation transistor is coupled.

[0037] Optionally, the multiple sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels. The driving transistor included in the sub-pixel driving circuit in the red sub-pixels has a first channel width-to-length ratio, the driving transistor included in the sub-pixel driving circuit in the green sub-pixels has a second channel width-to-length ratio, and the driving transistor included in the sub-pixel driving circuit in the blue sub-pixels has a third channel width-to-length ratio;

[0038] The third channel width-to-length ratio is greater than the first channel width-to-length ratio; and / or, the third channel width-to-length ratio is greater than the second channel width-to-length ratio.

[0039] Based on the technical solution of the above display substrate, a second aspect of the present disclosure provides a display device, including the above display substrate.

[0040] Based on the technical solution of the above display substrate, a third aspect of the present disclosure provides a driving method for a display substrate, for driving the above display substrate, the driving method includes:

[0041] In the data writing stage, the data writing transistor is turned on, and the data signal transmitted by the data line is written into the second electrode plate of the first capacitor, and the first capacitor couples the potential jump amount of its second electrode plate to the first electrode plate included therein.

[0042] Optionally, in the following case: the sub-pixel driving circuit further includes a first compensation transistor and a second compensation transistor. In the same sub-pixel driving circuit, the control signal line coupled to the gate of the second compensation transistor is multiplexed as the first scan line coupled to the gate of the first compensation transistor; the driving method further includes:

[0043] In the compensation stage, the control signal transmitted by the control signal line is at an effective level, and the control signal controls both the first compensation transistor and the second compensation transistor to be turned on; there is a first time interval t1 between the end time of the effective level of the control signal and the time when the data writing transistor is controlled to be turned on, and t1 satisfies: t1 ≤ m, where m represents a first threshold. Description of the Drawings

[0044] The drawings described herein are used to provide a further understanding of the present disclosure, and constitute a part of the present disclosure. The schematic embodiments of the present disclosure and their descriptions are used to explain the present disclosure, and do not constitute an improper limitation to the present disclosure. In the drawings:

[0045] Figure 1 It is a first circuit structure diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0046] Figure 2 It is a first driving timing diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0047] Figure 3 Schematic diagram of the second circuit structure of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0048] Figure 4 Schematic diagram of the third circuit structure of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0049] Figure 5 Second driving timing diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0050] Figure 6 Schematic diagram of the active layer layout of the driving transistor in the related art;

[0051] Figure 7 First layout diagram of the active layer of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0052] Figure 8 Second layout diagram of the active layer of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0053] Figure 9 First layout diagram of the active layer and the first gate metal layer of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0054] Figure 10 First layout diagram of the second gate metal layer of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0055] Figure 11 In Figure 9 First layout diagram of adding the second gate metal layer on the basis of;

[0056] Figure 12 In Figure 11 First layout diagram of adding the via holes of the first source-drain metal layer and the interlayer insulating layer on the basis of;

[0057] Figure 13 For Figure 12 First layout diagram of the via holes of the first source-drain metal layer and the interlayer insulating layer added in;

[0058] Figure 14 In Figure 12 First layout diagram of adding the via holes of the second source-drain metal layer and the first planarization layer on the basis of;

[0059] Figure 15 For Figure 14 First layout diagram of the via holes of the second source-drain metal layer and the first planarization layer added in;

[0060] Figure 16 For Figure 14 Cross-sectional view along the F1F2 direction in;

[0061] Figure 17 The second layout schematic diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0062] Figure 18 is Figure 17 The cross-sectional schematic diagram along the F3F4 direction in

[0063] Figure 19 The third layout schematic diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0064] Figure 20 is Figure 19 The cross-sectional schematic diagram along the F5F6 direction in

[0065] Figure 21 The fourth layout schematic diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0066] Figure 22 The layout schematic diagram of the light-shielding layer provided by the embodiment of the present disclosure;

[0067] Figure 23 is Figure 21 The cross-sectional schematic diagram along the F7F8 direction in

[0068] Figure 24 The fifth layout schematic diagram of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0069] Figure 25 is Figure 24 The layout schematic diagram of the first source-drain metal layer in

[0070] Figure 26 The third layout schematic diagram of the active layer of the sub-pixel driving circuit provided by the embodiment of the present disclosure;

[0071] Figure 27 is on the basis of Figure 26 The layout schematic diagram with the addition of the first gate metal layer;

[0072] Figure 28 is on the basis of Figure 27 The layout schematic diagram with the addition of the second gate metal layer;

[0073] Figure 29 is on the basis of Figure 28 The layout schematic diagram with the addition of the via holes of the first source-drain metal layer and the interlayer insulating layer;

[0074] Figure 30 is on the basis of Figure 29 The layout schematic diagram with the addition of the via holes of the second source-drain metal layer and the first planarization layer;

[0075] Figure 31 For Figure 30 Schematic layout diagram of the via holes of the second source-drain metal layer and the first planar layer added in

[0076] Figure 32 Fourth schematic layout diagram of the active layer of the sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0077] Figure 33 Fifth schematic layout diagram of the active layer of the sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0078] Figure 34 Schematic layout diagram of the data line and the data line lead provided by an embodiment of the present disclosure. Detailed implementation manners

[0079] In order to further illustrate the display substrate, its driving method, and the display device provided by the embodiments of the present disclosure, the following will be described in detail with reference to the accompanying drawings of the specification.

[0080] An embodiment of the present disclosure provides a display substrate, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a sub-pixel driving circuit and a light-emitting element coupled to each other.

[0081] As Figure 1 shown, exemplarily, the sub-pixel driving circuit adopts a 9T2C circuit structure (including 9 transistors and 2 capacitors), but is not limited thereto.

[0082] The display substrate further includes: a first reference signal line Vref1, a second reference signal line Vref2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a power supply line VDD, a data line DA, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a first scan line Scan1, a second scan line Scan2, a third scan line Scan3, and a fourth scan line Scan4.

[0083] The 9T2C circuit structure includes: a data writing transistor T1, a first compensation transistor T2, a driving transistor T3, a first reset transistor T4, a power supply control transistor T5, a light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T9, a fourth reset transistor T8, a first capacitor C1, and a second capacitor C2.

[0084] The gate of the data writing transistor T1 is coupled to the corresponding fourth scan line Scan4, the first pole of the data writing transistor T1 is coupled to the corresponding data line DA, and the second pole of the data writing transistor T1 is coupled to the second electrode plate C12 of the first capacitor C1.

[0085] The gate of the first compensation transistor T2 is coupled to the corresponding first scan line Scan1. The first pole of the first compensation transistor T2 is coupled to the second pole of the driving transistor T3. The second pole of the first compensation transistor T2 is coupled to the gate T3-g (N1 node) of the driving transistor T3.

[0086] The gate of the first reset transistor T4 is coupled to the corresponding second scan line Scan2. The first pole of the first reset transistor T4 is coupled to the corresponding first initialization signal line Vinit1. The second pole of the first reset transistor T4 is coupled to the gate T3-g of the driving transistor T3.

[0087] The gate of the power control transistor T5 is coupled to the corresponding first emission control signal line EM1. The first pole of the power control transistor T5 is coupled to the corresponding power supply line VDD. The second pole of the power control transistor T5 is coupled to the first pole of the driving transistor T3.

[0088] The gate of the emission control transistor T6 is coupled to the corresponding second emission control signal line EM2. The first pole of the emission control transistor T6 is coupled to the second pole of the driving transistor T3. The second pole of the emission control transistor T6 is coupled to the anode of the light-emitting element.

[0089] The gate of the second reset transistor T7 is coupled to the corresponding first scan line Scan1. The first pole of the second reset transistor T7 is coupled to the corresponding first reference signal line Vref1. The second pole of the second reset transistor T7 is coupled to the second electrode plate C12 of the first capacitor C1.

[0090] The gate of the third reset transistor T9 is coupled to the corresponding third scan line Scan3. The first pole of the third reset transistor T9 is coupled to the corresponding second reference signal line Vref2. The second pole of the third reset transistor T9 is coupled to the first pole of the driving transistor T3.

[0091] The gate of the fourth reset transistor T8 is coupled to the corresponding third scan line Scan3. The first pole of the fourth reset transistor T8 is coupled to the corresponding second initialization signal line Vinit2. The second pole of the fourth reset transistor T8 is coupled to the anode of the light-emitting element. The cathode of the light-emitting element receives the negative power supply signal line VSS.

[0092] The first electrode plate C11 of the first capacitor C1 is coupled to the gate T3-g of the driving transistor T3. The second electrode plate C12 of the first capacitor C1 is coupled to the first electrode plate C21 of the second capacitor C2. The second electrode plate C22 of the second capacitor C2 is coupled to the corresponding power supply line VDD.

[0093] As Figure 2 shown, the driving method of the sub-pixel driving circuit includes: a first reset stage A, a compensation stage B, a data writing stage C, a second reset stage D, and a light emitting stage E.

[0094] In the first reset stage A, the second scan signal transmitted by the second scan line Scan2 is at an effective level, and the first reset transistor T4 is turned on to reset the gate T3-g of the driving transistor T3, so that the voltage value of the gate T3-g of the driving transistor T3 is the same as the voltage value of the first initialization signal transmitted by the first initialization signal line Vinit1, and the driving transistor T3 is turned on.

[0095] In the compensation stage B, the first light emission control signal transmitted by the first light emission control signal line EM1 is at an effective level, the first scan signal transmitted by the first scan line Scan1 is at an effective level, and the second reset transistor T7, the compensation transistor, and the power supply control transistor T5 are all turned on. At this time, the voltage value of the second electrode plate C12 of the first capacitor C1 is the same as the voltage value of the first reference signal transmitted by the first reference signal line Vref1. In this stage, the power supply signal transmitted by the power supply line VDD is written into the gate T3-g of the driving transistor T3. When the potential of the gate T3-g of the driving transistor T3 becomes Vdd+Vth, the driving transistor T3 is turned off, and the compensation ends; Vdd represents the voltage value of the power supply signal, and Vth represents the threshold voltage of the driving transistor T3.

[0096] In the data writing stage C, the fourth scan signal transmitted by the fourth scan line Scan4 is at an effective level, and the data writing transistor T1 is turned on. At this time, the voltage value of the second electrode plate C12 of the first capacitor C1 becomes Vdata, where Vdata represents the voltage value of the data signal transmitted by the data line DA. The jump value of the voltage of the second electrode plate C12 of the first capacitor C1 is Vdata-V1, where V1 represents the voltage value of the first reference signal, and the voltage of the gate T3-g of the driving transistor T3 is Vdd+Vth+Vdata-V1.

[0097] In the second reset stage D, the third scan signal transmitted by the third scan line Scan3 is at an effective level, and the third reset transistor T9 and the fourth reset transistor T8 are turned on to reset the first pole of the driving transistor T3 and the anode of the light emitting element.

[0098] In the light-emitting stage E, the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 is at an effective level, and the second light-emitting control signal transmitted by the second light-emitting control signal line EM2 is at an effective level. The power control transistor T5 and the light-emitting control transistor T6 are both turned on, and the gate-source voltage Vgs of the driving transistor T3 satisfies: Vgs = Vth + Vdata - V1. The light-emitting element emits light, and the generated leakage current is k / 2(Vdata - V1). 2 .

[0099] Between the compensation stage and the data writing stage, there is a floating stage without signal writing (such as Figure 2 the solid-line box in). In this stage, no signal is written to the N1 node, and the potential of the N1 node is easily disturbed by the data signal (for example: the data signal line can affect the potential of the N1 node by affecting the first capacitor C1) and is recorded in the N1 node, thereby affecting the display effect. More specifically, the conventional sub-pixel driving circuit does not have the above problem because the fluctuations of the data signal in one light-emitting cycle are all recorded in the compensation process, and the integral of the change of the data signal has little influence on the potential of the N1 node. In the separate circuit, since the instantaneous change of the data signal is recorded in the N1 node after the compensation ends, the influence is relatively large.

[0100] In order to reduce the influence of the data signal on the potential of the N1 node in the floating stage. It is considered to set a functional layer with a constant potential around the data line DA to reduce the influence of the data signal jump on the N1 node. However, while the above method reduces the influence of the data signal on the N1 node, it will increase the loading of the data line DA, making the potential at the far end of the data line DA lower, thereby affecting the display uniformity of the display product.

[0101] Please refer to Figure 3 、 Figures 7 to 16 , an embodiment of the present disclosure provides a display substrate, including: a substrate substrate, and a power supply line VDD, a data line DA, and a plurality of sub-pixels all disposed on the substrate substrate; the sub-pixels include a sub-pixel driving circuit and a light-emitting element coupled to each other, and the sub-pixel driving circuit includes a driving transistor T3, a data writing transistor T1, a first capacitor C1, and a second capacitor C2;

[0102] A first electrode plate C11 of the first capacitor C1 is coupled to a gate T3-g of the driving transistor T3, a second electrode plate C12 of the first capacitor C1 is coupled to a second pole of the data writing transistor T1, and a first pole of the data writing transistor T1 is coupled to the corresponding data line DA;

[0103] The first electrode plate C21 of the second capacitor C2 is coupled to the second electrode plate C12 of the first capacitor C1, and the second electrode plate C22 of the second capacitor C2 is coupled to the corresponding power supply line VDD;

[0104] In the sub-pixel driving circuits arranged in the same row along the first direction, the second electrode plates C22 of the second capacitors C2 included in each sub-pixel driving circuit are arranged in sequence along the first direction, and there is a spacer region J1 between adjacent second electrode plates C22 of the second capacitors C2, and the positive projection of the data line DA on the substrate at least partially overlaps with the positive projection of the spacer region J1 on the substrate.

[0105] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along the second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the second direction. Exemplarily, the first direction and the second direction intersect. For example: the first direction includes the horizontal direction, and the second direction includes the vertical direction.

[0106] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is configured to provide a driving signal for the light-emitting element to drive the light-emitting element to emit light.

[0107] Exemplarily, the display substrate includes a plurality of power supply lines VDD and a plurality of data lines DA. The plurality of power supply lines VDD are arranged in sequence along the first direction, and the power supply line VDD includes at least a part extending along the second direction. The plurality of data lines DA are arranged along the first direction, and the data line DA includes at least a part extending along the second direction.

[0108] Exemplarily, the plurality of power supply lines VDD correspond to the multiple columns of sub-pixel driving circuits one by one, and the power supply line VDD is respectively coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits. The plurality of data lines DA correspond to the multiple columns of sub-pixel driving circuits one by one, and the data line DA is respectively coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits.

[0109] Exemplarily, the orthographic projection of the first electrode plate C11 of the first capacitor C1 on the substrate overlaps at least partially with the orthographic projection of the second electrode plate C12 of the first capacitor C1 on the substrate. The orthographic projection of the first electrode plate C21 of the second capacitor C2 on the substrate overlaps at least partially with the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate.

[0110] Exemplarily, the first electrode plate C11 of the first capacitor C1 is reused as the gate T3-g of the driving transistor T3, but is not limited thereto.

[0111] Exemplarily, the width of the spacer J1 in the second direction is less than or equal to the width of the second electrode plate C22 of the second capacitor C2.

[0112] Exemplarily, as Figure 6 and Figure 7 shown, Figure 6 schematically shows the layout diagram of the driving active layer 23' included in the driving transistor T3 in the related art. Figure 7 schematically shows the layout diagram of the driving active layer 23 included in the driving transistor T3 in the present application. By comparison, it is found that the driving active layer 23 in the present application protrudes towards the light-emitting control active layer 26 and the power control active layer 25, which is beneficial to reducing the overall layout space occupied by the active layers in the sub-pixel driving circuit, and thus beneficial to the development of high resolution of the display substrate.

[0113] Exemplarily, as Figure 7 and Figure 8 shown, Figure 7 one ends (the ends coupled to the first reference signal line) of the second reset active layers 27 included in each sub-pixel driving circuit located in the same row along the first direction are formed into an integrated structure. This setting method can reduce the number of connection vias for connecting the first reference signal line and one end of the second reset active layer 27, and thus is beneficial to reducing the layout space occupied by the sub-pixel driving circuit. Figure 8 the second reset active layers 27 included in each sub-pixel driving circuit located in the same row along the first direction are independent of each other. This setting method can connect one end of each second reset active layer 27 to the first reference signal line through a connection via.

[0114] Exemplarily, as Figure 3 、 Figures 12 to 14 shown, a parasitic capacitor C3 is formed between the second conductive connection portion 32 and the power supply line VDD, which well improves the stability of the second conductive connection portion 32 and the structures coupled thereto.

[0115] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiments of the present disclosure, when a functional layer with a constant potential is disposed around the data line DA to reduce the influence of data signal jumps on the N1 node, by setting at least partial overlap between the orthographic projection of the data line DA on the substrate and the orthographic projection of the spacer J1 on the substrate, the overlap area between the orthographic projection of the data line DA on the substrate and the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate is reduced, achieving a reduction in the loading of the data line DA while reducing the influence of the data signal on the N1 node, thereby avoiding a decrease in the potential at the far end of the data line DA and ensuring the display uniformity of the display product.

[0116] As Figures 9 to 16 shown, in some embodiments, the second electrode plates C22 of the second capacitors C2 adjacent along the first direction are coupled together through the electrode plate connection portion 10. Between the second electrode plates C22 of the adjacent second capacitors C2, the spacer J1 and the electrode plate connection portion 10 are arranged along the second direction, and the second direction intersects with the first direction; at least partial overlap exists between the orthographic projection of the data line DA on the substrate and the orthographic projection of the electrode plate connection portion 10 on the substrate.

[0117] Exemplarily, the electrode plate connection portion 10 and the second electrode plate C22 of the second capacitor C2 to which it is coupled are formed as an integral structure, but not limited thereto.

[0118] Exemplarily, the greater the width of the portion of the electrode plate connection portion 10 between the second electrode plates C22 of the adjacent second capacitors C2 along the first direction, the smaller the width of the spacer J1 along the first direction; the smaller the width of the portion of the electrode plate connection portion 10 between the second electrode plates C22 of the adjacent second capacitors C2 along the first direction, the greater the width of the spacer J1 along the first direction.

[0119] In the display substrate provided by the above embodiments, the second electrode plate C22 of the second capacitor C2 is coupled to the power supply line VDD. By connecting the second electrode plates C22 of the second capacitors C2 adjacent along the first direction through the electrode plate connection portion 10, the second electrode plates C22 of the second capacitor C2 can jointly form a grid-like structure with the power supply line VDD. This grid-like structure is used to transmit a power signal with a stable potential, which is beneficial for reducing the loading of the power supply line VDD and improving the uniformity of the power signal.

[0120] As Figures 7 to 16As shown, in some embodiments, the display substrate further includes a first initialization signal line Vinit1; the sub-pixel driving circuit further includes a first compensation transistor T2 and a first reset transistor T4; a first pole of the first compensation transistor T2 is coupled to a second pole of the driving transistor T3, and a second pole of the first compensation transistor T2 is coupled to a gate T3-g of the driving transistor T3; a first pole of the first reset transistor T4 is coupled to the corresponding first initialization signal line Vinit1, and a second pole of the first reset transistor T4 is coupled to the gate T3-g of the driving transistor T3; the first compensation transistor T2 includes a first compensation active layer 22, and the first reset transistor T4 includes a first reset active layer 24;

[0121] The plate connection portion 10 includes a connected main body portion 101 and a connected extension portion 102 that are coupled to each other. The connected main body portion 101 is respectively coupled to second plates C22 of adjacent second capacitors C2. A positive projection of the connected extension portion 102 on the substrate at least partially overlaps a positive projection of the first compensation active layer 22 included in one sub-pixel driving circuit among two adjacent sub-pixel driving circuits along a first direction on the substrate, and / or at least partially overlaps a positive projection of the first reset active layer 24 included in the other sub-pixel driving circuit among two adjacent sub-pixel driving circuits along the first direction on the substrate.

[0122] Exemplarily, the first compensation active layer 22 includes two first compensation channel portions, and first compensation conductor portions respectively coupled to the two first compensation channel portions; the first reset active layer 24 includes two first reset channel portions, and first reset conductor portions respectively coupled to the two first reset channel portions; a positive projection of the connected extension portion 102 on the substrate at least partially overlaps a positive projection of the first compensation conductor portion included in one sub-pixel driving circuit among two adjacent sub-pixel driving circuits along a first direction on the substrate, and / or at least partially overlaps a positive projection of the first reset conductor portion included in the other sub-pixel driving circuit among two adjacent sub-pixel driving circuits along the first direction on the substrate.

[0123] In the display substrate provided in the above embodiments, both the first compensation transistor T2 and / or the first reset transistor T4 include double-gate transistors, and the connected extension portion 102 can shield the corresponding conductor portions included in the first compensation transistor T2 and / or the first reset transistor T4, thereby ensuring the working stability of the first compensation transistor T2 and / or the first reset transistor T4.

[0124] Such as Figure 14As shown, in some embodiments, a positive projection of the data line DA on the substrate substrate and a positive projection of the connection main body portion 101 on the substrate substrate at least partially overlap; and / or, the positive projection of the data line DA on the substrate substrate and the positive projection of the connection extension portion 102 on the substrate substrate at least partially overlap.

[0125] Exemplarily, the connection main body portion 101 and the connection extension portion 102 are formed as an integral structure, and the connection main body portion 101 is located between the second electrodes C22 of the adjacent second capacitors C2.

[0126] Since both the connection main body portion 101 and the connection extension portion 102 have stable potentials, the above arrangement is beneficial to reducing the influence of data signal jumps on the N1 node. At the same time, by providing a spacer region J1 between the second electrodes C22 of the adjacent second capacitors C2, a positive projection of the data line DA on the substrate substrate and a positive projection of the spacer region J1 on the substrate substrate at least partially overlap, achieving a reduction in the influence of the data signal on the N1 node while reducing the loading of the data line DA, thereby avoiding a decrease in the potential at the distal end of the data line DA and ensuring the display uniformity of the display product.

[0127] As Figures 10 to 15 As shown, in some embodiments, the display substrate further includes a plurality of first reference signal connection lines Vref1' and a plurality of second reference signal connection lines Vref2', and the first reference signal connection lines Vref1' and the second reference signal connection lines Vref2' are alternately arranged along the first direction; a positive projection of at least part of the data line DA on the substrate substrate is located between a positive projection of the adjacent first reference signal connection lines Vref1' on the substrate substrate and a positive projection of the second reference signal connection lines Vref2' on the substrate substrate.

[0128] Exemplarily, the first reference signal connection line Vref1' is used to transmit a first reference signal with a stable voltage, and the second reference signal connection line Vref2' is used to transmit a second reference signal with a stable voltage.

[0129] Exemplarily, the plurality of first reference signal connection lines Vref1' are arranged along the first direction, and the first reference signal connection line Vref1' includes at least part extending along the second direction. The plurality of second reference signal connection lines Vref2' are arranged along the first direction, and the second reference signal connection line Vref2' includes at least part extending along the second direction.

[0130] In the display substrate provided in the above embodiments, by setting the positive projection of at least part of the data line DA on the substrate, it is located between the positive projection of the adjacent first reference signal connection line Vref1' on the substrate and the positive projection of the second reference signal connection line Vref2' on the substrate; such that signal lines for transmitting stable signals are provided on both sides of the data line DA, which is beneficial to reducing the influence of data signal jumps on the N1 node.

[0131] Exemplarily, the data line DA is provided on the same layer as the first reference signal connection line Vref1'; or, the data line DA is provided on a different layer from the first reference signal connection line Vref1';

[0132] Exemplarily, the data line DA is provided on the same layer as the second reference signal connection line Vref2'; or, the data line DA is provided on a different layer from the second reference signal connection line Vref2'.

[0133] Exemplarily, the data line DA is provided on a different layer from the first reference signal connection line Vref1'; and / or, the data line DA is provided on a different layer from the second reference signal connection line Vref2'.

[0134] The above setting method can, while reducing the influence of data signal jumps on the N1 node, flexibly layout the first reference signal connection line Vref1' and the second reference signal connection line Vref2', thereby effectively reducing the layout difficulty of the display substrate.

[0135] As Figures 10 to 15 shown, in some embodiments, the display substrate further includes a plurality of first reference signal lines Vref1; the sub-pixel driving circuit further includes a second reset transistor T7, a first pole of the second reset transistor T7 is coupled to the corresponding first reference signal line Vref1, and a second pole of the second reset transistor T7 is coupled to a second electrode plate C12 of the first capacitor C1; the first reference signal connection line Vref1' is respectively coupled to the plurality of first reference signal lines Vref1.

[0136] Exemplarily, the plurality of first reference signal lines Vref1 are arranged along a second direction, and the first reference signal line Vref1 includes at least a part extending along the first direction. The plurality of first reference signal lines Vref1 correspond to multiple rows of sub-pixel driving circuits one by one, and the first reference signal line Vref1 is respectively coupled to each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits.

[0137] The above setting couples the first reference signal connection line Vref1' to the plurality of first reference signal lines Vref1 respectively, so that the first reference signal connection line Vref1' can form a grid-like structure with the first reference signal lines Vref1, which is beneficial to reducing the Loading of the first reference signal lines Vref1 and ensuring the uniformity of the first reference signal transmitted thereon.

[0138] As Figures 10 to 15 shown, in some embodiments, the display substrate further includes a plurality of second reference signal lines Vref2; the sub-pixel driving circuit further includes a third reset transistor T9, a first pole of the third reset transistor T9 is coupled to the corresponding second reference signal line Vref2, and a second pole of the third reset transistor T9 is coupled to a first pole of the driving transistor T3; the second reference signal connection line Vref2' is coupled to the plurality of second reference signal lines Vref2 respectively.

[0139] Exemplarily, the plurality of second reference signal lines Vref2 are arranged along a second direction, and the second reference signal line Vref2 includes at least a part extending along the first direction. The plurality of second reference signal lines Vref2 correspond to the multi-row sub-pixel driving circuits one by one, and the second reference signal line Vref2 is coupled to each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits respectively.

[0140] The above setting couples the second reference signal connection line Vref2' to the plurality of second reference signal lines Vref2 respectively, so that the second reference signal connection line Vref2' can form a grid-like structure with the second reference signal lines Vref2, which is beneficial to reducing the Loading of the second reference signal lines Vref2 and ensuring the uniformity of the second reference signal transmitted thereon.

[0141] As Figures 10 to 15 shown, in some embodiments, the display substrate further includes a plurality of first initialization signal connection lines Vinit1' and a plurality of second initialization signal connection lines Vinit2', the first initialization signal connection lines Vinit1' and the second initialization signal connection lines Vinit2' are alternately arranged along the first direction; a positive projection of at least part of the data line DA on the substrate is located between a positive projection of the adjacent first initialization signal connection lines Vinit1' on the substrate and a positive projection of the second initialization signal connection lines Vinit2' on the substrate; the data line DA and the first initialization signal connection line Vinit1' are arranged in different layers; and / or, the data line DA and the second initialization signal connection line Vinit2' are arranged in different layers.

[0142] Exemplarily, the first initialization signal connection line Vinit1' is used to transmit a first initialization signal with a stable voltage, and the second initialization signal connection line Vinit2' is used to transmit a second initialization signal with a stable voltage.

[0143] Exemplarily, the multiple first initialization signal connection lines Vinit1' are arranged along the first direction, and the first initialization signal connection line Vinit1' includes at least a part extending along the second direction. The multiple second initialization signal connection lines Vinit2' are arranged along the first direction, and the second initialization signal connection line Vinit2' includes at least a part extending along the second direction.

[0144] In the display substrate provided by the above embodiment, by setting the positive projection of at least part of the data line DA on the substrate, to be located between the positive projections of the adjacent first initialization signal connection lines Vinit1' and the second initialization signal connection lines Vinit2' on the substrate; such that signal lines for transmitting stable signals are arranged on both sides of the data line DA, which is beneficial to reducing the influence of data signal jump on the N1 node.

[0145] Exemplarily, the data line DA and the first initialization signal connection line Vinit1' are arranged on the same layer; or, the data line DA and the first initialization signal connection line Vinit1' are arranged on different layers;

[0146] Exemplarily, the data line DA and the second initialization signal connection line Vinit2' are arranged on the same layer; or, the data line DA and the second initialization signal connection line Vinit2' are arranged on different layers.

[0147] Exemplarily, the data line DA and the first initialization signal connection line Vinit1' are arranged on different layers; and / or, the data line DA and the second initialization signal connection line Vinit2' are arranged on different layers.

[0148] The above setting method can, while achieving the reduction of the influence of data signal jump on the N1 node, flexibly layout the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2', thereby effectively reducing the layout difficulty of the display substrate.

[0149] Such as Figures 10 to 15As shown, in some embodiments, the display substrate further includes a plurality of first initialization signal lines Vinit1; the sub-pixel driving circuit further includes a first reset transistor T4, a first pole of the first reset transistor T4 is coupled to the corresponding first initialization signal line Vinit1, and a second pole of the first reset transistor T4 is coupled to a gate T3-g of the driving transistor T3; the first initialization signal connection line Vinit1' is respectively coupled to the plurality of first initialization signal lines Vinit1.

[0150] Exemplarily, the plurality of first initialization signal lines Vinit1 are arranged along a second direction, and the first initialization signal line Vinit1 includes at least a part extending along the first direction. The plurality of first initialization signal lines Vinit1 correspond to multiple rows of sub-pixel driving circuits one by one, and the first initialization signal line Vinit1 is respectively coupled to each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits.

[0151] The above setting that the first initialization signal connection line Vinit1' is respectively coupled to the plurality of first initialization signal lines Vinit1 enables the first initialization signal connection line Vinit1' to form a grid-like structure with the first initialization signal line Vinit1, thereby facilitating reducing the Loading of the first initialization signal line Vinit1 and ensuring the uniformity of the first initialization signal transmitted thereon.

[0152] As Figures 10 to 15 As shown, in some embodiments, the display substrate further includes a plurality of second initialization signal lines Vinit2; the sub-pixel driving circuit further includes a fourth reset transistor T8, a first pole of the fourth reset transistor T8 is coupled to the corresponding second initialization signal line Vinit2, and a second pole of the fourth reset transistor T8 is coupled to an anode of the light-emitting element; the second initialization signal connection line Vinit2' is respectively coupled to the plurality of second initialization signal lines Vinit2.

[0153] Exemplarily, the plurality of second initialization signal lines Vinit2 are arranged along a second direction, and the second initialization signal line Vinit2 includes at least a part extending along the first direction. The plurality of second initialization signal lines Vinit2 correspond to multiple rows of sub-pixel driving circuits one by one, and the second initialization signal line Vinit2 is respectively coupled to each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits.

[0154] The above setting makes the second initialization signal connection line Vinit2' coupled to the multiple second initialization signal lines Vinit2 respectively, so that the second initialization signal connection line Vinit2' can form a grid-like structure with the second initialization signal lines Vinit2, which is beneficial to reducing the Loading of the second initialization signal lines Vinit2 and ensuring the uniformity of the second initialization signals transmitted thereon.

[0155] As Figures 10 to 15 shown, in some embodiments, the multiple first reference signal connection lines Vref1' and the multiple second reference signal connection lines Vref2' are divided into multiple groups of reference signal connection line groups arranged along a first direction, and each group of reference signal connection line groups includes one of the first reference signal connection lines Vref1' and one of the second reference signal connection lines Vref2'. The multiple first initialization signal connection lines Vinit1' and the multiple second initialization signal connection lines Vinit2' are divided into multiple groups of initialization signal connection line groups arranged along the first direction, and each group of initialization signal connection line groups includes one of the first initialization signal connection lines Vinit1' and one of the second initialization signal connection lines Vinit2'. The reference signal connection line groups and the initialization signal connection line groups are alternately arranged along the first direction.

[0156] Exemplarily, a part of the data lines DA in the display substrate correspond to the multiple groups of reference signal connection line groups one by one, and the orthographic projection of the data line DA on the substrate is located between the orthographic projection of the first reference signal connection line Vref1' in the corresponding reference signal connection line group on the substrate and the orthographic projection of the second reference signal connection line Vref2' on the substrate. Exemplarily, another part of the data lines DA in the display substrate correspond to the multiple groups of initialization signal connection line groups one by one, and the orthographic projection of the data line DA on the substrate is located between the orthographic projection of the first initialization signal connection line Vinit1' in the corresponding initialization signal connection line group on the substrate and the orthographic projection of the second initialization signal connection line Vinit2' on the substrate.

[0157] The above setting method can reduce the Loading of the first reference signal line Vref1, the second reference signal line Vref2, the first initialization signal line Vinit1, and the second initialization signal line Vinit2 while more reasonably planning the layout space of the display substrate, thereby reducing the layout difficulty of the display substrate.

[0158] As Figure 17 and Figure 18As shown, in some embodiments, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially stacked in a direction away from the substrate substrate;

[0159] The data line DA is provided on the same layer and made of the same material as the third source-drain metal layer, and the first reference signal connection line Vref1’, the second reference signal connection line Vref2’, the first initialization signal connection line Vinit1’, and the second initialization signal connection line Vinit2’ are all provided on the same layer and made of the same material as the second source-drain metal layer.

[0160] Exemplarily, the display substrate includes a light-shielding layer LS, an insulating layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a first planarization layer, a second source-drain metal layer, a second planarization layer, a third source-drain metal layer, a third planarization layer, an anode layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, etc. The display substrate may further include a passivation layer, but is not limited thereto.

[0161] The above arrangement enables the data line DA to be formed simultaneously with the third source-drain metal layer in the same patterning process; the first reference signal connection line Vref1’, the second reference signal connection line Vref2’, the first initialization signal connection line Vinit1’, and the second initialization signal connection line Vinit2’ can all be formed simultaneously with the second source-drain metal layer in the same patterning process; thus effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate. Moreover, the above arrangement makes the distance between the data line DA and the N1 node farther, and can better shield the influence of data signal jump on the N1 node.

[0162] As Figure 34 As shown, in some embodiments, the display substrate further includes a plurality of data line leads DA’; the display substrate includes a plurality of data lines DA arranged in the first direction, and the plurality of data lines DA are divided into a first group of data line groups, a second group of data line groups, and a third group of data line groups arranged in the first direction;

[0163] The data line DA in the first group of data line groups is coupled to the corresponding data line lead DA’, and the data line lead DA’ extends from the position where the data line DA to which it is coupled to the middle area of the display substrate and extends from the middle area to the lower border area of the display substrate;

[0164] The data line DA in the third group of data line groups is coupled to the corresponding data line lead DA', and the data line lead DA' extends from the position where the coupled data line DA is located to the middle area, and extends from the middle area to the lower border area.

[0165] Exemplarily, the data line lead DA' is disposed on a different layer from the data line DA.

[0166] Exemplarily, the display substrate includes a display area and a peripheral area located around the display area, and the peripheral area includes an upper border area, a lower border area, a left border area, and a right border area; the first group of data line groups is close to the left border area, and the third data line group is close to the right border area.

[0167] The above setting method enables the data lines DA near the left border area and the right border area of the display substrate to be coupled to the driving chip in the display substrate through the data line leads DA', avoiding directly extending the data lines DA near the left border area and the right border area of the display substrate to the lower border area through fan-out lines, thereby effectively narrowing the width of the lower border area of the display substrate.

[0168] As Figure 19 and Figure 20 shown, in some embodiments, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the substrate substrate;

[0169] The data line DA is disposed on the same layer and made of the same material as the second source-drain metal layer, and the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1', and the second initialization signal connection line Vinit2' are all disposed on the same layer and made of the same material as the third source-drain metal layer.

[0170] The above setting method enables the data line DA to be formed simultaneously with the second source-drain metal layer in the same patterning process; the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1', and the second initialization signal connection line Vinit2' can all be formed simultaneously with the third source-drain metal layer in the same patterning process; thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0171] As Figures 21 to 23 shown, in some embodiments, the display substrate includes a light-shielding layer LS, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the substrate substrate;

[0172] The data line DA is provided on the same layer and made of the same material as the light-shielding layer LS, and the first reference signal connection line Vref1’, the second reference signal connection line Vref2’, the first initialization signal connection line Vinit1’ and the second initialization signal connection line Vinit2’ are all provided on the same layer and made of the same material as the second source-drain metal layer.

[0173] Exemplarily, the light-shielding layer LS is further configured to shield the driving transistor T3, so as to achieve the effect of stabilizing the driving transistor T3.

[0174] The above setting method enables the data line DA and the light-shielding layer LS to be formed simultaneously in the same patterning process; the first reference signal connection line Vref1’, the second reference signal connection line Vref2’, the first initialization signal connection line Vinit1’ and the second initialization signal connection line Vinit2’ can all be formed simultaneously in the same patterning process with the second source-drain metal layer; thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0175] The above setting method provides the data line DA on the same layer and made of the same material as the light-shielding layer LS, which is beneficial to reducing the layout space occupied by the sub-pixels, thereby improving the resolution of the display substrate.

[0176] As Figures 13 to 15 shown, in some embodiments, the display substrate further includes a plurality of power connection lines VDD’, the power connection lines VDD’ include at least a part extending along the first direction, and the power connection lines VDD’ are respectively coupled to the plurality of power lines VDD.

[0177] Exemplarily, the power connection line VDD’ is provided on the same layer and made of the same material as the first source-drain metal layer, but is not limited thereto.

[0178] Exemplarily, the plurality of power connection lines VDD’ are arranged along the second direction.

[0179] Setting the power connection lines VDD’ to be respectively coupled to the plurality of power lines VDD enables the power connection lines VDD’ and the power supply to form a grid-like structure, thereby reducing the Loading of the power line VDD and improving the uniformity of the power signal.

[0180] As Figure 24 and Figure 25 shown, in some embodiments, the power connection line VDD’ includes a plurality of first power parts VDD1’ and a plurality of second power parts VDD2’, and the first power parts VDD1’ and the second power parts VDD2’ are alternately arranged along the first direction;

[0181] The first power supply part VDD1’ includes a first sub - part VDD11’ and a second sub - part VDD12’. The first sub - part VDD11’ is coupled to the second sub - part VDD12’ and the power supply line VDD respectively. The adjacent second sub - part VDD12’ and the second power supply part VDD2’ are coupled to each other. Along the second direction, the width of the second power supply part VDD2’ is greater than the width of the second sub - part VDD12’. The positive projection of the second power supply part VDD2’ on the substrate at least partially overlaps with the positive projection of the data line DA on the substrate.

[0182] Exemplarily, the first power supply part VDD1’ and the second power supply part VDD2’ are formed as an integral structure.

[0183] Exemplarily, the first sub - part VDD11’ extends along the second direction, but is not limited thereto.

[0184] The above - mentioned setting method makes the power connection line VDD’ widened near the area overlapping with the data line DA, further reducing the influence of data signal changes on the N1 node. At the same time, it further reduces the Loading of the power supply line VDD and improves the uniformity of the power signal.

[0185] Such as Figure 3 、 Figure 4 、 Figure 5 、 Figures 26 to 31 As shown, in some embodiments, the sub - pixel further includes a first scan line Scan1 and a control signal line GC; the sub - pixel driving circuit further includes a first compensation transistor T2 and a second compensation transistor T10. The gate of the first compensation transistor T2 is coupled to the corresponding first scan line Scan1. The first pole of the first compensation transistor T2 is coupled to the second pole of the driving transistor T3. The second pole of the first compensation transistor T2 is coupled to the gate T3 - g of the driving transistor T3. The gate of the second compensation transistor T10 is coupled to the corresponding control signal line GC. The first pole of the second compensation transistor T10 is coupled to the corresponding power supply line VDD. The second pole of the second compensation transistor T10 is coupled to the first pole of the driving transistor T3.

[0186] Exemplarily, in the same sub - pixel driving circuit, the control signal line GC to which the gate of the second compensation transistor T10 is coupled is multiplexed as the first scan line Scan1 to which the gate of the first compensation transistor T2 is coupled.

[0187] More specifically, the main reason for the data signal change affecting the N1 node is that there is a floating stage between the compensation stage and the data writing stage. If only the compensation time is simply increased, it is necessary to adjust the turn-on duration (i.e., the effective level duration) of the first light emission control signal transmitted by the first light emission control signal line EM1. This adjustment method is likely to increase the number of pulses of the first light emission control signal, increase the loading of the first light emission control signal, affect the turn-on sensitivity of the first light emission control signal at the far end, and cause uneven display.

[0188] In the display substrate provided by the above embodiment, a control signal line GC and a second compensation transistor T10 are added. The control signal line GC is set to control the first compensation transistor T2 and the second compensation transistor T10. During the compensation stage, the control signal transmitted by the control signal line GC is at an effective level, and the control signal controls both the first compensation transistor T2 and the second compensation transistor T10 to conduct; there is a first time interval t1 between the end time of the effective level of the control signal and the time to control the turn-on of the data writing transistor T1, and t1 satisfies: t1 ≤ m, where m represents a first threshold. The above setting method enables the effective level of the control signal to cover the compensation stage and at least part of the floating stage, thereby improving the influence of the data signal change on the N1 node. More specifically, the above setting method is equivalent to extending the time of the compensation stage and shortening the time of the floating stage.

[0189] In the display substrate provided by the above embodiment, by adding the control signal line GC and the second compensation transistor T10 to improve the influence of the data signal change on the N1 node, it is not necessary to adjust the turn-on duration of the first light emission control signal transmitted by the first light emission control signal line EM1, which ensures the turn-on sensitivity of the first light emission control signal and the display uniformity of the display substrate.

[0190] It should be noted that when t1 ≤ m, t1 can take a negative value, that is, the compensation stage and the data writing stage can partially overlap. The value of the first threshold should be such that it can improve the influence of the data signal change on the N1 node.

[0191] Adding the T10 transistor does not add an extra mask, and adding this transistor does not increase the process difficulty. T10 and T2 are controlled by the same gate line.

[0192] Such as Figure 32 and Figure 33As shown, in some embodiments, the plurality of sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The driving transistor T3 included in the sub-pixel driving circuit of the red sub-pixel has a first channel width-to-length ratio. The driving transistor T3 included in the sub-pixel driving circuit of the green sub-pixel has a second channel width-to-length ratio. The driving transistor T3 included in the sub-pixel driving circuit of the blue sub-pixel has a third channel width-to-length ratio;

[0193] The third channel width-to-length ratio is set to be greater than the first channel width-to-length ratio; and / or, the third channel width-to-length ratio is greater than the second channel width-to-length ratio.

[0194] Since the luminous efficiency of the blue sub-pixel is relatively low, the above setting method enables the blue sub-pixel to have a larger driving current, effectively improving the brightness of the blue sub-pixel and enhancing the uniformity of the display substrate.

[0195] More specifically, as Figure 6 and Figure 7 shown, it schematically shows the data writing active layer 21 included in the data writing transistor T1, the first compensation active layer 22 included in the first compensation transistor T2, the driving active layer 23 included in the driving transistor T3, the first reset active layer 24 included in the first reset transistor T4, the power control active layer 25 included in the power control transistor T5, the light emission control active layer 26 included in the light emission control transistor T6, the second reset active layer 27 included in the second reset transistor T7, the third reset active layer 29 included in the third reset transistor T9, and the fourth reset active layer 28 included in the fourth reset transistor T8. As Figure 26 shown, it also schematically shows the second compensation active layer 20 included in the second compensation transistor T10. Exemplarily, the above active layers all adopt low-temperature polycrystalline silicon (LTPS) active layers, but are not limited thereto.

[0196] Exemplarily, the driving active layer 23 included in the driving transistor T3 adopts an inverted "Ji" shape structure. Adopting this channel design is beneficial to reducing the area occupied by the sub-pixel driving circuit. For high-refresh-rate display products, an important application scenario is to reduce the size occupied by the sub-pixel driving circuit, and this design can improve the display resolution.

[0197] As Figure 9 and Figure 27As shown, the first gate metal layer is located on the side of the active layer away from the substrate. To reduce the leakage current of nodes N1 and N2 in the sub-pixel driving circuit, the data writing transistor T1, the second reset transistor T7, the first compensation transistor T2, and the first reset transistor T4 all adopt double-gate LTPS transistors. In other embodiments, the data writing transistor T1, the second reset transistor T7, the first compensation transistor T2, and the first reset transistor T4 may also adopt oxide transistors. The gates of the data writing transistor T1, the second reset transistor T7, the first compensation transistor T2, and the first reset transistor T4 and the scan lines coupled thereto can be arranged in layers. Since the alternating frequency of the signals connected by these four transistors is relatively high, in a display device with NB size, the scan lines can be made of a first source-drain metal layer with a smaller resistivity to reduce the Loading caused by signal changes and improve the uniformity of NB size display products. The material of the first gate metal layer includes Mo, but is not limited thereto.

[0198] It should be noted that when doping the active layer, the first gate metal layer can be used as a mask to implement the doping process, or an independent mask layer can be formed, which is not limited here. Taking Figure 9 as an example, the first light emission control signal line EM1 and the second light emission control signal line EM2 can only form a power control transistor T5 and a light emission control transistor T6 with the active layer, without forming other abnormal transistors. When using the first gate metal layer as a mask to implement the doping process, in order to avoid forming other abnormal transistors, the signal lines located in the areas where abnormal transistors may be formed can be jumped with the first source-drain metal layer to avoid the formation of abnormal transistors.

[0199] As Figure 10 , Figure 11 and Figure 28 shown, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference signal line Vref1, and the second reference signal line Vref2 are all arranged on the second gate metal layer. At the same time, the second electrode plates C12 and C22 are both arranged on the second gate metal layer. The second electrode plates C12 and C22 both include openings for exposing the first electrode plates C11 and C21 to realize the connection between the first electrode plates C11 and C21 and the first source-drain metal layer. As Figure 9 and Figure 11 shown, the second reference signal line may include a covering portion for covering the conductorized portion of the active layer between the double gates of the data writing transistor T1 and the second reset transistor T7. This setting can reduce the leakage current of the double-gate transistor and improve the stability of the transistor.

[0200] Exemplarily, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference signal line Vref1, and the second reference signal line Vref2 are all constant electrical signals. For example, the voltages of the signals transmitted by the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are negative values, and the voltages of the signals transmitted by the first reference signal line Vref1 and the second reference signal line Vref2 are positive values.

[0201] Exemplarily, the second gate metal layer can use a stacked structure of Ti / Al / Ti, which is beneficial to reducing the Loading of NB size display products.

[0202] As Figure 12 , Figure 13 and Figure 29 shown, the black dots in the figure represent vias. The first scan line Scan1, the second scan line Scan2, and the fourth scan line Scan are all arranged on the first source-drain metal layer. Implementing a different layer setting from other signal lines is beneficial to improving the crosstalk problem between signal lines. Considering that the signal transition process Loading of the first scan line Scan1, the second scan line Scan2, and the fourth scan line Scan is relatively large, in the case where the first source-drain metal layer adopts a stacked structure of Ti / Al / Ti, the above setting method is beneficial to improving the problem of large Loading.

[0203] As Figure 12 , Figure 13 and Figure 29 shown, the fourth scan line Scan4 is coupled to the gate of the data writing transistor T1 through the first via Via1. The first scan line Scan1 is coupled to the gate of the second reset transistor T7 through the second via Via2.

[0204] The second conductive connection portion 32 is coupled to the second pole of the data writing transistor T1 and the second pole of the second reset transistor T7 through the third via Via3. The second conductive connection portion 32 is coupled to the first electrode plate C21 of the second capacitor C2 through the seventh via Via7. The second conductive connection portion 32 is coupled to the second electrode plate C12 of the first capacitor C1 through the ninth via Via9.

[0205] The third conductive connection portion 33 is coupled to the first reference signal line Vref1 through the fourth via Via4. The third conductive connection portion 33 is coupled to the first pole of the second reset transistor T7 through the fifth via Via5.

[0206] The first conductive connection portion 31 is coupled to the first pole of the data writing transistor T1 through the sixth via Via6. As Figure 14 and Figure 15 shown, the first conductive connection portion 31 is coupled to the data line DA through the twenty-first via Via21.

[0207] The power supply connection line VDD’ is coupled to the second plate C22 of the second capacitor C2 through the eighth via Via8. The second scan line Scan2 is coupled to the gate of the first reset transistor T4 through the tenth via Via10. The first scan line Scan1 is coupled to the gate of the first compensation transistor T2 through the thirteenth via Via13.

[0208] The fourth conductive connection portion 34 is coupled to the first plate C11 of the first capacitor C1 through the eleventh via Via11, and the fourth conductive connection portion 34 is coupled to the second pole of the first compensation transistor T2 through the twelfth via Via12.

[0209] The fifth conductive connection portion 35 is coupled to the first pole of the first reset transistor T4 through the fourteenth via Via14. The fifth conductive connection portion 35 is coupled to the first initialization signal line Vinit1 through the fifteenth via Via15.

[0210] The sixth conductive connection portion 36 is coupled to the second initialization signal line Vinit2 through the sixteenth via Via16, and the sixth conductive connection portion 36 is coupled to the first pole of the fourth reset transistor T8 through the seventeenth via Via17.

[0211] The seventh conductive connection portion 37 is coupled to the second reference signal line Vref2 through the eighteenth via Via18, and the seventh conductive connection portion 37 is coupled to the first pole of the third reset transistor T9 through the nineteenth via Via19.

[0212] As Figure 14 and Figure 15 shown, the black dots in the figure represent vias. The power supply line VDD is made of the second source-drain metal layer. The power supply line VDD is used to shield the N1 node (corresponding to the position of the fourth conductive connection portion 34) and the N2 node (corresponding to the position of the second conductive connection portion 32) to prevent voltage jumps at these two nodes.

[0213] As Figure 14 and Figure 15As shown, the second reference signal connection line Vref2’ is coupled to the second reference signal line Vref2 through the 20th via Via20. The first reference signal connection line Vref1’ is coupled to the first reference signal line Vref1 through the 22nd via Via22. The power supply line VDD is coupled to the power supply connection line VDD’ through the 23rd via Via23. The power supply line VDD is coupled to the first pole of the power control transistor T5 through the 24th via Via24. The first initialization signal connection line Vinit1’ is coupled to the first initialization signal line Vinit1 through the 26th via Via26. The second initialization signal connection line Vinit2’ is coupled to the second initialization signal line Vinit2 through the 27th via Via27.

[0214] As Figure 31 shown, the power supply line VDD is coupled to the first pole of the second compensation transistor T10 through the 28th via Via28.

[0215] The embodiment of the present disclosure also provides a display device, including the display substrate provided in the above embodiment.

[0216] It should be noted that the display device may be: a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, or any product or component with a display function. Among them, the display device further includes a flexible circuit board, a printed circuit board, a backplane, etc.

[0217] Exemplarily, the display device is applicable to a notebook-sized display device, and is particularly applicable to a large and medium-sized OLED display device with a high refresh rate.

[0218] In the display substrate provided in the above embodiment, when a functional layer with a constant potential is provided around the data line DA to reduce the influence of data signal jump on the N1 node, by setting the positive projection of the data line DA on the substrate to at least partially overlap the positive projection of the spacer J1 on the substrate, the overlapping area between the positive projection of the data line DA on the substrate and the second electrode plate C22 of the second capacitor C2 on the substrate is reduced. While reducing the influence of the data signal on the N1 node, the loading of the data line DA is reduced, thereby avoiding the low potential at the far end of the data line DA and ensuring the display uniformity of the display product.

[0219] When the display device provided in the embodiment of the present disclosure includes the above display substrate, it also has the above beneficial effects, which will not be elaborated here.

[0220] The embodiment of the present disclosure also provides a driving method for a display substrate, used to drive the display substrate provided in the above embodiment. The driving method includes:

[0221] During the data writing stage, the data writing transistor T1 is turned on, and the data signal transmitted by the data line DA is written into the second electrode plate C12 of the first capacitor C1. The first capacitor C1 couples the potential jump amount of its second electrode plate to the first electrode plate included therein.

[0222] As Figure 4 and Figure 5 shown, in some embodiments, in the following cases: the sub-pixel driving circuit further includes a first compensation transistor T2 and a second compensation transistor T10. In the same sub-pixel driving circuit, the control signal line GC coupled to the gate of the second compensation transistor T10 is multiplexed as the first scan line Scan1 coupled to the gate of the first compensation transistor T2; the driving method further includes:

[0223] During the compensation stage, the control signal transmitted by the control signal line GC is at an effective level, and the control signal controls both the first compensation transistor T2 and the second compensation transistor T10 to be turned on; there is a first time interval t1 between the end time of the effective level of the control signal and the time to control the data writing transistor T1 to turn on, and t1 satisfies: t1 ≤ m, where m represents a first threshold.

[0224] In the driving method provided by the above embodiments, the effective level of the control signal can cover the compensation stage and at least part of the floating stage, thereby improving the influence of the data signal change on the N1 node. More specifically, the above setting method is equivalent to extending the time of the compensation stage and shortening the time of the floating stage.

[0225] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is in the shape of a line, a line segment or a strip, the main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0226] It should be noted that the "same layer" in the embodiments of the present disclosure may refer to a film layer on the same structural layer. Or for example, the film layers in the same layer may be film layers formed by the same film forming process for forming a specific pattern, and then the layer structure formed by patterning the film layer using the same mask through a single patterning process. According to the different specific patterns, the single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0227] In the method embodiments of the present disclosure, the sequence numbers of the steps do not limit the order of the steps. For those of ordinary skill in the art, without creative efforts, the changes in the order of the steps are also within the protection scope of the present disclosure.

[0228] It should be noted that the embodiments in this specification are all described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for method embodiments, since they are basically similar to product embodiments, they are described relatively simply, and the relevant parts can be referred to the partial description of the product embodiments.

[0229] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure belongs. The "first", "second" and similar terms used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0230] It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0231] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0232] As mentioned above, the above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized in that, comprising: a substrate substrate, and a plurality of control signal lines, a plurality of power lines, and a plurality of sub-pixels disposed on the substrate substrate; the sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled to each other, and the sub-pixel driving circuit includes a driving transistor, a first compensation transistor, and a second compensation transistor; the sub-pixel driving circuit further includes a first compensation transistor and a second compensation transistor, a gate of the first compensation transistor is coupled to the corresponding control signal line, a first pole of the first compensation transistor is coupled to a second pole of the driving transistor, and a second pole of the first compensation transistor is coupled to a gate of the driving transistor; a gate of the second compensation transistor is coupled to the corresponding control signal line, a first pole of the second compensation transistor is coupled to the corresponding power line, and a second pole of the second compensation transistor is coupled to a first pole of the driving transistor; the gates of the first compensation transistor and the second compensation transistor in the same sub-pixel driving circuit are coupled to the same control signal line.

2. The display substrate according to claim 1, characterized in that, the display substrate further includes a plurality of data lines; the sub-pixel driving circuit further includes a first capacitor, a second capacitor, and a data writing transistor; a first plate of the first capacitor is coupled to a gate of the driving transistor, a second plate of the first capacitor is coupled to a second pole of the data writing transistor, and a first pole of the data writing transistor is coupled to the corresponding data line; a first plate of the second capacitor is coupled to a second plate of the first capacitor, and a second plate of the second capacitor is coupled to the corresponding power line.

3. The display substrate according to claim 2, characterized in that, the display substrate further includes a plurality of third scan lines; the sub-pixel driving circuit further includes a third reset transistor and a fourth reset transistor; a gate of the third reset transistor is coupled to the corresponding third scan line, and the third reset transistor is used to reset a first pole of the driving transistor; a gate of the fourth reset transistor is coupled to the corresponding third scan line, and the fourth reset transistor is used to reset an anode of the light-emitting element.

4. The display substrate according to claim 3, characterized in that, the display substrate further includes a plurality of second reference signal lines; a first pole of the third reset transistor is coupled to the corresponding second reference signal line, and a second pole of the third reset transistor is coupled to a first pole of the driving transistor; the display substrate further includes a plurality of second initialization signal lines; a first pole of the fourth reset transistor is coupled to the corresponding second initialization signal line, and a second pole of the fourth reset transistor is coupled to an anode of the light-emitting element.

5. The display substrate according to claim 2, characterized in that, the display substrate further includes a plurality of first scan lines, a plurality of second scan lines, a plurality of first initialization signal lines, and a plurality of first reference signal lines; the sub-pixel driving circuit further includes a first reset transistor and a second reset transistor; The gate of the first reset transistor is coupled to the corresponding second scan line, a first pole of the first reset transistor is coupled to the corresponding first initialization signal line, and a second pole of the first reset transistor is coupled to the gate of the driving transistor; The gate of the second reset transistor is coupled to the corresponding first scan line, a first pole of the second reset transistor is coupled to the corresponding first reference signal line, and a second pole of the second reset transistor is coupled to the second electrode plate of the first capacitor.

6. The display substrate according to claim 5, wherein, the sub-pixel driving circuit further includes a second conductive connection portion, and the second conductive connection portion is respectively coupled to a second pole of the data writing transistor, a second pole of the second reset transistor, the second electrode plate of the first capacitor, and a first electrode plate of the second capacitor; a positive projection of the second conductive connection portion on the substrate overlaps at least partially with a positive projection of the power supply line on the substrate.

7. The display substrate according to claim 5, wherein, at least one of the data writing transistor, the first compensation transistor, the first reset transistor, and the second reset transistor includes a double-gate transistor.

8. The display substrate according to claim 1, wherein, the display substrate further includes a plurality of first light emission control signal lines and a plurality of second light emission control signal lines; the sub-pixel driving circuit further includes a power supply control transistor and a light emission control transistor; the gate of the power supply control transistor is coupled to the corresponding first light emission control signal line, a first pole of the power supply control transistor is coupled to the corresponding power supply line, and a second pole of the power supply control transistor is coupled to a first pole of the driving transistor; the gate of the light emission control transistor is coupled to the corresponding second light emission control signal line, a first pole of the light emission control transistor is coupled to a second pole of the driving transistor, and a second pole of the light emission control transistor is coupled to the anode of the light emitting element.

9. A driving method for a display substrate, wherein, for driving the display substrate according to any one of claims 1 to 8; in the case where the first compensation transistor and the second compensation transistor are coupled to the same control signal line in the same sub-pixel driving circuit: the driving method includes: In a compensation stage, a control signal transmitted by the control signal line is at an effective level, and the control signal controls both the first compensation transistor and the second compensation transistor to be turned on.

10. The driving method for a display substrate according to claim 9, wherein, in the case where the sub-pixel driving circuit further includes a first capacitor, a second capacitor, and a data writing transistor, a first time interval t1 exists between a time when the effective level of the control signal ends and a time when the data writing transistor is controlled to be turned on, and t1 satisfies: t1 ≤ m, where m represents a first threshold.

11. The driving method for a display substrate according to claim 10, wherein, the driving method further includes: During the data writing stage, the data writing transistor is turned on, and the data signal transmitted by the data line is written into the second electrode plate of the first capacitor. The first capacitor couples the potential jump amount of its second electrode plate to the first electrode plate included therein.

12. A display device, characterized in that it includes a display substrate as described in any one of claims 1 to 8.

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