Memory controller, method of controlling memory controller, and memory device

Abstract

The invention relates to a memory controller, a method of controlling the memory controller, and a memory device. A memory controller for issuing read and write commands for accessing a plurality of memories sharing data signals, the memory controller comprising: a hold circuit configured to hold an access request to the commands; and a control circuit configured to select an access request from among the access requests held in the holding circuit and issue a command, in a case where a command is issued to a second memory different from the first memory to which the command is immediately previously issued. The control circuit controls which command is preferentially issued based on a respective predetermined period preset for each set of types of commands immediately previously issued to the first memory and types of commands to be issued to the second memory.

Description

Technical Field

[0001] The present disclosure relates to a memory controller, a method of controlling the memory controller, and a memory device, and more particularly, to a technique in which a memory controller connected to a dynamic random access memory (DRAM) selects an arbitrary memory access request from a plurality of memory access requests and issues a command. Background Art

[0002] DRAM is generally used as a main storage device of a computer system. As the performance and functional sophistication of computer systems increase, the performance requirements for DRAM are also increasing, and various methods of memory controllers have been proposed to maximize such performance.

[0003] In a case where transmissions are performed in different transmission directions, such as a write command after a read command or a read command after a write command, a command interval needs to be set aside compared to a case where transmissions continue in the same transmission direction, which results in a reduction in memory utilization efficiency.

[0004] Japanese Patent No. 6950149 discloses determining a priority transmission direction, outputting all transmissions in the priority transmission direction from a command queue, and then switching the priority transmission direction to another transmission direction.

[0005] However, the technique described in Japanese Patent No. 6950149 does not mention a case where a memory controller switches which memory to issue a read / write command for multiple memories of shared data. For example, in the case of switching the access destination memory, depending on the type of the immediately previous issued command, when continuing a command in the same direction, a command interval may be required even more than when issuing a command for a different transmission direction (e.g., read after write), which may result in a reduction in memory utilization efficiency. Summary of the Invention

[0006] In view of the above problems, some embodiments of the present disclosure have been made, and a technique for suppressing a reduction in memory utilization efficiency is provided.

[0007] According to one aspect of the present disclosure, there is provided a memory controller for issuing read and write commands for accessing a plurality of memories of a shared data signal, the memory controller including: a holding circuit configured to hold access requests for commands; and a control circuit configured to select an access request from the access requests held in the holding circuit and issue a command, wherein, in a case of issuing a command to a second memory different from a first memory to which a command was immediately previously issued, the control circuit controls which command to issue preferentially based on respective preset time periods for each set of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory.

[0008] According to one aspect of the present disclosure, a method for controlling a memory controller is provided. The memory controller is configured to issue read and write commands for accessing a plurality of memories sharing a data signal. The method includes: holding an access request for a command in a holding circuit; and performing control to select an access request from the access requests held in the holding circuit and issue a command. In the control, when issuing a command to a second memory different from a first memory to which a command was immediately previously issued, which command to issue preferentially is controlled based on respective preset time periods for each set of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory.

[0009] According to one aspect of the present disclosure, a memory device is provided, including: a plurality of memories sharing a data signal; and a memory controller configured to issue read and write commands for accessing the plurality of memories. The controller includes: a holding circuit configured to hold an access request for a command; and a control circuit configured to select an access request from the access requests held in the holding circuit and issue a command. In the case of issuing a command to a second memory different from a first memory to which a command was immediately previously issued, the control circuit controls which command to issue preferentially based on respective preset time periods for each set of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory.

[0010] From the following description of exemplary embodiments (with reference to the accompanying drawings), other features of various embodiments will become apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a configuration diagram of a memory controller according to an embodiment.

[0012] Figure 2 is a configuration diagram of an access holding circuit entry according to an embodiment.

[0013] Figure 3 is a configuration diagram of a read / write control circuit according to an embodiment.

[0014] Figures 4A to 4C is a view illustrating an operation example 1 of selecting a memory access request according to an embodiment.

[0015] Figures 5A to 5C is a view illustrating an operation example 2 of selecting a memory access request according to an embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of each embodiment. Multiple features are described in the embodiments, but the embodiments are not limited to those that require all of these features, and multiple of these features can be appropriately combined. In addition, in the accompanying drawings, the same or similar configurations are given the same reference numerals, and redundant descriptions thereof are omitted.

[0017] (Embodiment)

[0018] This embodiment can be used in various memory controllers that connect to a DRAM, select a memory access request from multiple memory access requests, and issue a command.

[0019] <Memory Controller Configuration>

[0020] Figure 1 is a configuration diagram of a memory controller 100 according to an embodiment. The memory controller 100 issues read or write commands to access multiple memories sharing data signals. The memory controller 100 is connected to a DRAM 110 composed of multiple banks and a bus master 120. The DRAM 110 consists of two memory devices (Memory 0 and Memory 1), and Memory 0 and Memory 1 share data signals. In this embodiment, it is configured such that data signals are shared by two DRAMs, but the number of DRAMs sharing data signals is not limited to two and can be three or more. The bus master 120 sends a memory access request including address information and write data to the memory controller 100. The memory controller 100 generates a DRAM command based on the memory access request received from the bus master 120 and sends the generated command to one of the multiple DRAMs 110. In addition, the memory controller 100 performs data transfer with the DRAM 110 based on the sent DRAM command.

[0021] The memory controller 100 includes an access hold circuit 101, a read / write control circuit 102, a page control circuit 103, a bank status management circuit 104, and a command selector 105.

[0022] <Operation of the Access Hold Circuit 101>

[0023] First, the operation of the access hold circuit 101 will be described. The access hold circuit 101 is a buffer that holds multiple memory access requests. The access hold circuit 101 consists of m (m >= 2) entries. Note that this embodiment does not depend on the number of m.

[0024] Figure 2Configuration diagram of access hold circuit entry 1011 according to an embodiment. In this embodiment, in the access hold circuit 101, there are m access hold circuit entries 1011. As Figure 2 shown, the access hold circuit entry 1011 includes fields 10111 to 10116, which are used for access type, target memory, target bank, target page, target column, and remaining read / write command count. The access hold circuit 101 converts the memory access requests received from the bus master 120 so as to correspond to each field, and holds the converted memory access requests. The information stored in each field is as follows.

[0025] (a) Access type field 10111:

[0026] This indicates the access type of the memory access request stored in the entry.

[0027] WRITE: The memory access request is for writing (data write).

[0028] READ: The memory access request is for reading (data read).

[0029] (b) Target memory field 10112:

[0030] This indicates the memory to be accessed by the memory access request stored in the entry.

[0031] (c) Target bank field 10113:

[0032] This indicates the bank address to be accessed by the memory access request stored in the entry.

[0033] (d) Target page field 10114:

[0034] This indicates the page address to be accessed by the memory access request stored in the entry.

[0035] (e) Target column field 10115:

[0036] This indicates the head column address to be accessed by the memory access request stored in the entry.

[0037] (f) Remaining read / write command number field 10116:

[0038] This indicates the number of remaining DRAM read / write commands to be executed according to the memory access request stored in the entry.

[0039] When a memory access request is stored in the access hold circuit 101, the memory access request is stored in an entry after the last stored memory access request. When reading a memory access request from the access hold circuit 101, it can be read from any entry.

[0040] Next, the entry control signal input from the read / write control circuit 102 to the access hold circuit 101 will be described. The entry control signal is composed of an entry number field, a delete field, and an update field. When 1 is set in the delete field, the access hold circuit 101 deletes the entry indicated by the entry number field. When 1 is set in the update field, the access hold circuit 101 updates the column field of the entry indicated by the entry number field to the head column address to be accessed by the next DRAM command. In addition, the remaining read / write command number field is updated to a value obtained by subtracting 1.

[0041] <Operation of the read / write control circuit 102>

[0042] Next, the operation of the read / write control circuit 102 will be described. The read / write control circuit 102 can refer to all memory access requests stored in the access hold circuit 101. The read / write control circuit 102 selects a memory access request from the memory access requests stored in the access hold circuit 101 for which the page to be accessed is open and there will be no command issue wait due to memory switching. Whether the page to be accessed by the memory access request is open is determined based on the target memory field 10112, the target bank field 10113, the target page field 10114 of the access hold circuit entry 1011, and the bank state generated by the bank state management circuit 104 (to be described later).

[0043] The read / write control circuit 102 generates a read command or a write command based on the selected memory access request and outputs the command to the command selector 105. The read / write control circuit 102 of the present embodiment has a function of selecting memory access requests so as to continuously issue read commands and write commands to the same memory, thereby suppressing the read / write switching penalty.

[0044] Next, the process of the read / write control circuit 102 generating the entry control signal will be described. When the last read command or write command executed according to the memory access request is issued, the processing of the corresponding memory access request is completed. Therefore, the read / write control circuit 102 generates an entry control signal to delete the corresponding entry from the access hold circuit 101. On the other hand, when a read command or write command that is not the last one is issued, the read / write control circuit 102 generates an entry control signal to update the corresponding entry of the access hold circuit 101.

[0045] However, in the case of issuing the last read command or write command, there is no need to update the corresponding entry. It can be determined whether the issued read command or write command is the last one based on whether the remaining read / write command digit field 10116 of the access hold circuit entry 1011 is 1.

[0046] <Operation of page control circuit 103>

[0047] Next, the operation of the page control circuit 103 will be described. The page control circuit 103 can refer to all memory access requests stored in the access hold circuit 101. The inputs to the page control circuit 103 are the memory access requests stored in the access hold circuit 101 and the bank state output from the bank state management circuit 104. The page control circuit 103 generates page control commands such as activation commands or precharge commands based on the bank state and the memory access requests stored in the access hold circuit 101, and outputs the page control commands to the command selector 105.

[0048] <Operation of bank state management circuit 104>

[0049] Next, the operation of the bank state management circuit 104 will be described. The bank state management circuit 104 updates the bank state based on the command issue state input from the command selector 105. The command issue state consists of the type of command issued to the DRAM 110 and the memory, bank, and page for which the command is issued. The bank state includes whether a page is open for each bank constituting the DRAM 110 and the address of the open page.

[0050] <Operation of command selector 105>

[0051] Finally, the operation of the command selector 105 will be described. The command selector 105 selects one of the read / write commands input from the read / write control circuit 102 and the page control commands input from the page control circuit 103 and issues it to the DRAM 110. Although not described in this embodiment, commands such as refresh can also be selected. In addition, the command selector 105 outputs the command issue state to the read / write control circuit 102 and the bank state management circuit 104, which is composed of the command type of the command issued to the DRAM 110 and the memory, bank, and page for which the command is issued.

[0052] <Configuration of read / write control circuit 102>

[0053] Figure 3It is a configuration diagram of the read / write control circuit 102 according to an embodiment. The read / write control circuit 102 includes a page open determination circuit 1051, a priority access type determination circuit 1052, a memory switching determination circuit 1053, a memory access request selection circuit 1054, and timers 1055, 1056, 1057, and 1058.

[0054] Timer 1055 corresponds to the read command for memory 0 among the plurality of DRAMs 110, and timer 1056 corresponds to the write command for memory 0. Timer 1057 corresponds to the read command for memory 1 among the plurality of DRAMs 110, and timer 1058 corresponds to the write command for memory 1.

[0055] The page open determination circuit 1051 determines whether the target bank of the target memory has opened the target page for each memory access request stored in the access hold circuit 101 based on the bank state. The page open determination circuit 1051 outputs only the memory access requests for which the target page is opened among the memory access requests stored in the access hold circuit 101 to the priority access type determination circuit 1052, and masks other memory access requests.

[0056] The priority access type determination circuit 1052 determines whether the access type of each memory access request output by the page open determination circuit 1051 corresponds to the priority access type. The priority access type is generated by the priority access type determination circuit 1052 based on the memory access requests stored in the access hold circuit 101 and the bank state, and indicates whether it is a period during which a read command or a write command is to be issued preferentially. The priority access type determination circuit 1052 outputs only the memory access requests corresponding to the priority access type among the memory access requests output by the page open determination circuit 1051 to the memory switching determination circuit 1053, and masks all other memory access requests.

[0057] When the command issue status indication output from the command selector 105 indicates that a read or write command is issued to a memory other than memory 0, the timer 1055 sets a period during which a read command cannot be issued to a different memory after the command is issued. Note that the period to be set is different depending on whether the command issued from the command selector 105 is a read or a write. The value of the timer 1055 decreases as time elapses except for the set time, and stops at 0. In this embodiment, a period during which a read command cannot be issued to a different memory after a read command or a write command is issued to a certain memory is set in the timer, but some embodiments are not limited thereto. The period during which a read / write command cannot be issued to a different memory after a read / write command is issued to a certain memory can be increased or decreased, thereby adjusting the relationship between the frequency of memory switching and the memory access request waiting time.

[0058] When the command issue status indication output from the command selector 105 indicates that a read or write command is issued to any memory other than memory 0, the timer 1056 sets a period during which a write command cannot be issued to a memory other than a specific memory after the command is issued. Other behaviors are the same as those of the timer 1055.

[0059] When the command issue status indication output from the command selector 105 indicates that a read or write command is issued to any memory other than memory 1, the timer 1057 sets a period during which a read command cannot be issued to a different memory after the command is issued to a specific memory. Other behaviors are the same as those of the timer 1055.

[0060] When the command issue status indication output from the command selector 105 indicates that a read or write command is issued to any memory other than memory 1, the timer 1058 sets a period during which a write command cannot be issued to a different memory after the command is issued to a specific memory. Other behaviors are the same as those of the timer 1055.

[0061] The memory switching determination circuit 1053 determines whether a timing constraint for waiting for memory switching is required for each memory access request output by the priority access type determination circuit 1052. Whether a memory access request requires a timing constraint for waiting for memory switching is determined based on whether the value of the timer corresponding to the target memory of the memory access request is not 0. When the target memory of the memory access request is memory 0 and it is a read, the timer 1055 is referred to. When the target memory of the memory access request is memory 0 and it is a write, the timer 1056 is referred to. When the target memory of the memory access request is memory 1 and it is a read, the timer 1057 is referred to. When the target memory of the memory access request is memory 1 and it is a write, the value of the timer 1058 is referred to.

[0062] The memory switching determination circuit 1053 outputs only the memory access requests in the memory access requests output by the priority access type determination circuit 1052 that do not cause a command issuance wait due to memory switching to the memory access request selection circuit 1054. The memory access requests that cause a command issuance wait are masked.

[0063] The memory access request selection circuit 1054 selects an arbitrary memory access request from the memory access requests output by the memory switching determination circuit 1053. Then, it generates a read command or a write command for the selected memory access request and outputs it to the command selector 105.

[0064] <Operation>

[0065] Figures 4A to 4C And Figures 5A to 5C is a view exemplifying an exemplary operation of selecting a memory access request in the present embodiment. Figures 4A to 4C Exemplarily shows a memory access request selection when a read command is issued to another memory after a write command according to the present embodiment. Figures 5A to 5C Exemplarily shows a memory access request selection when a read command is issued to another memory after a read command according to the present embodiment.

[0066] Figure 4A And Figure 5A Exemplarily shows the state of the access holding circuit 101 being accessed in a given cycle. For ease of explanation, memory access requests 0 to 2 and identifiers are respectively assigned to each memory access request held in the access holding circuit 101.

[0067] Figure 4B And Figure 5B Exemplarily shows the period (predetermined time segment) that should be opened between each command. Figure 4B The timing constraints shown in are as follows.

[0068] · tCCD = 2cycle @ dram_clock.

[0069] · The period during which a read command cannot be issued to a different memory after a write command = 4cycle @ dram_clock.

[0070] · The period during which a write command cannot be issued to a different memory after a write command = 6cycle @ dram_clock.

[0071] · The period during which a write command cannot be issued to the same memory after a read command = 4cycle @ dram_clock.

[0072] Meanwhile,Figure 5B The timing constraints shown in the figure are as follows.

[0073] · tCCD = 2 cycles @ dram_clock.

[0074] · Period during which a read command cannot be issued to a different memory after a read command = 4 cycles @ dram_clock.

[0075] · Period during which a write command cannot be issued to a different memory after a read command = 6 cycles @ dram_clock.

[0076] · Period during which a write command cannot be issued to the same memory after a read command = 4 cycles @ dram_clock.

[0077] Figure 4C and Figure 5C chronologically illustrates the command issuance states of memory bank 0 and memory bank 1 of DRAM 110 and the count values of the RD timer 1057 and the WR timer 1058 of memory bank 1. As a prerequisite for these operation examples, it is assumed that the target page of the memory access request held in the access hold circuit 101 has been opened for the target memory bank of the target memory.

[0078] First, using Figures 4A to 4C , an exemplary memory access request selection when a read command is issued to another memory after a write command will be described.

[0079] At T1, the relatively older received memory access request 0 and the relatively newer received memory access request 1 are held. In memory access request 0, access type = WR, target memory = 0, target memory bank = "don't care", target page = "don't care", target column = "don't care", and remaining read / write command count = 2. In memory access request 1, access type = WR, target memory = 1, target memory bank = "don't care", target page = "don't care", target column = "don't care", and remaining read / write command count = 1.

[0080] At T1, the read / write control circuit 102 can select the write memory access request 0 for memory 0 or the write memory access request 1 for memory 1. In this operation example, it is assumed that a write command is issued for the previously received memory access request 0. Therefore, the RD timer 1057 of memory 1 sets the period (4 cycles) during which a read command cannot be issued to a different memory after a read command is issued to a certain memory, and starts to decrement. Similarly, the WR timer 1058 of memory 1 sets the period (6 cycles) during which a write command cannot be issued to a different memory after a read command is issued to a certain memory, and starts to decrement.

[0081] At T3, since the timer 1057 and the timer 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0. More specifically, since the memory access request 1 is a write for memory 1, the WR timer 1058 for memory 1 is referenced. Since the timer 1058 is not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0.

[0082] During the time from T4 to T7, only the memory access request 1 is held in the access hold circuit 101. However, since the timer 1057 and the timer 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 does not select the memory access request. More specifically, since the memory access request 1 is a write for memory 1, the WR timer 1058 for memory 1 is referenced. Since the timer 1058 is not 0, the memory access request 1 is masked. In addition, since there is no other memory access request, the read / write control circuit 102 does not select the memory access request.

[0083] Assume that at T8, the read memory access request 2 for memory 1 is stored in the access hold circuit 101. Since the timer 1058 is not 0, the memory access request 1 is masked. However, since the RD timer 1057 of memory 1 is 0, the read / write control circuit 102 selects the read memory access request 2 for memory 1. Thereafter, at T15, the WR timer 1058 of memory 1 becomes 0, the masking of the memory access request 1 is cancelled, and the read / write control circuit 102 selects the memory access request 1.

[0084] Next, using Figures 5A to 5C , an exemplary memory access request selection when a read command is issued to another memory after a read command will be described.

[0085] At T1, the relatively older memory access request 0 in the receive order and the relatively newer memory access request 1 in the receive order are held. In memory access request 0, access type = RD, target memory = 0, target bank = "don't care", target page = "don't care", target column = "don't care", and remaining read / write command count = 2. In memory access request 1, access type = WR, target memory = 1, target bank = "don't care", target page = "don't care", target column = "don't care", and remaining read / write command count = 1.

[0086] At T1, the read / write control circuit 102 can select the write memory access request 0 for memory 0 or the write memory access request 1 for memory 1. In this operation example, it is assumed that a read command is issued for the previously received memory access request 0. Therefore, the RD timer 1057 of memory 1 sets a period (4 cycles) during which a read command cannot be issued to a different memory after issuing a read command to a certain memory, and starts to decrement. Similarly, the WR timer 1058 of memory 1 sets a period (6 cycles) during which a write command cannot be issued to a different memory after issuing a read command to a certain memory, and starts to decrement.

[0087] At T3, since the timer 1057 and the timer 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0. More specifically, since the memory access request 1 is a write for memory 1, the WR timer 1058 for memory 1 is referred to. Similarly, since the timer 1058 is not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0.

[0088] During the time from T4 to T7, only the memory access request 1 is held in the access hold circuit 101. However, since the timer 1057 and the timer 1058 are not 0, the memory access request 1 is masked, and the read / write control circuit 102 does not select the memory access request. More specifically, since the memory access request 1 is a write for memory 1, the WR timer 1058 for memory 1 is referred to. Since the timer 1058 is not 0, the memory access request 1 is masked. In addition, since there are no other memory access requests, the read / write control circuit 102 does not select the memory access request.

[0089] Assume that at T8, the read memory access request 2 for memory 1 is stored in the access hold circuit 101. Since the timer 1058 is not 0, the memory access request 1 is masked. However, since the RD timer 1057 of memory 1 is 0, the read / write control circuit 102 selects the read memory access request 2 for memory 1. Thereafter, at T15, the WR timer 1058 of memory 1 becomes 0, the masking of the memory access request 1 is cancelled, and the read / write control circuit 102 selects the memory access request 1.

[0090] As described above, in the present embodiment, in the case of issuing a command to a second memory different from the first memory to which a command was immediately previously issued, the read / write control circuit 102 controls which command to issue preferentially based on the corresponding preset predetermined time periods for each set of the type of the command immediately previously issued to the first memory and the type of the command to be issued to the second memory. For example, after the shortest predetermined time period has elapsed since the immediately previous command was issued, the command corresponding to the shortest predetermined time period is preferentially issued.

[0091] In the case of issuing a command to a second memory different from the first memory to which a command was immediately previously issued, the read / write control circuit 102 may issue a read command prior to a write command. As Figure 4B and Figure 5B shown, in the case where the immediately previous command is a read command and a read command is to be issued to a different memory, the cycle time is four cycles. Further, in the case where the immediately previous command is a read command and a write command is to be issued to a different memory, the cycle time is six cycles. Since 6 cycles > 4 cycles, the read command takes precedence over the write command. Similarly, in the case where the immediately previous command is a write command and a read command is to be issued to a different memory, the cycle time is four cycles. Further, in the case where the immediately previous command is a write command and a write command is to be issued to a different memory, the cycle time is six cycles. Since 6 cycles > 4 cycles, the read command takes precedence over the write command in this case.

[0092] In other words, in the case of issuing a read command to a second memory different from the first memory to which a write command was immediately previously issued, the read / write control circuit 102 performs control to issue the read command to the second memory in response to the elapse of a predetermined time period (e.g., four cycles) since the write command was issued. In the case of issuing a write command to a second memory different from the first memory to which a write command was immediately previously issued, control is performed to issue the write command to the second memory in response to the elapse of a predetermined time period (e.g., six cycles) since the write command was issued.

[0093] In addition, in a case where a read command is issued to a second memory different from a first memory to which a read command was immediately previously issued, the read / write control circuit 102 performs control to issue a read command to the second memory in response to a lapse of a predetermined period (e.g., four cycles) from the issuance of the read command. Further, in a case where a read command is issued to a second memory different from a first memory to which a write command was immediately previously issued, control is performed to issue a write command to the second memory in response to a lapse of a predetermined period (e.g., six cycles) from the issuance of the read command.

[0094] As described above, in the present embodiment, in a case where a switching of an access destination memory occurs, a command in a transmission direction (write → read, read → write, etc.) having a shorter command interval is preferentially issued according to the type of the immediately previously issued command (write, read). That is, a memory access request having a short command issuance waiting time due to the memory switching is preferentially issued. This makes it possible to suppress a decrease in memory utilization efficiency.

[0095] [Modification Example]

[0096] When issuing a read command or a write command, the read / write control circuit 102 may perform control to preferentially issue a command having the shortest predetermined period among (1) a predetermined period (a command loss period that cannot be selected) set for different memories and different transmission directions, (2) a predetermined period set for different memories and the same transmission direction, (3) a predetermined period set for the same memory and different transmission directions, and (4) a predetermined period set for the same memory and the same transmission direction.

[0097] For example, the predetermined period set for different memories and different transmission directions may be nine cycles, and the predetermined period set for different memories and the same transmission direction (e.g., write → write) may be 13 cycles. Similarly, the predetermined period set for the same memory and different transmission directions may be 23 cycles, and the predetermined period set for the same memory and the same transmission direction (e.g., write → write) may be four cycles.

[0098] According to the present disclosure, a decrease in memory utilization efficiency can be suppressed.

[0099] Other Embodiments

[0100] One or more embodiments of the present disclosure can also be implemented by a computer of a system or apparatus that reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a "non-transitory computer-readable storage medium") to perform the functions of one or more of the above-described embodiments and / or includes one or more circuits (e.g., an application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiments, and by a method executed by the computer of the system or apparatus by, for example, reading and executing computer-executable instructions from the storage medium to perform the functions of one or more of the above-described embodiments and / or controlling one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessing unit (MPU)), and may include a network of separate computers or separate processors to read and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or a storage medium. The storage medium may include, for example, one or more of a hard disk, a random access memory (RAM), a read only memory (ROM), a storage device of a distributed computing system, an optical disk (such as a compact disk (CD), a digital versatile disk (DVD), or a Blu-ray disk (BD) TM ), a flash device, a memory card, etc.

[0101] Embodiments of the present invention can also be implemented by the following method, that is, by providing software (a program) that performs the functions of the above-described embodiments to a system or apparatus through a network or various storage media, and the method of the computer or the central processing unit (CPU) or the microprocessing unit (MPU) of the system or apparatus reading and executing the program.

[0102] Although the present disclosure has described exemplary embodiments, it should be understood that some embodiments are not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications as well as equivalent structures and functions.

Claims

1. A memory controller for issuing read and write commands for accessing a plurality of memories sharing a data signal, the memory controller comprising: a holding circuit configured to hold an access request to the command; as well as A control circuit is configured to select an access request from the access requests held in the holding circuit and issue a command, wherein In the case of issuing a command to a second memory that is different from the first memory to which a command was issued immediately previously, the control circuit controls which command is issued first based on a corresponding predetermined time period pre-set for each set of the type of command issued immediately previously to the first memory and the type of command to be issued to the second memory.

2. The memory controller according to claim 1, wherein: When issuing a command to a second memory different from the first memory to which the command was issued immediately previously, the control circuit preferentially issues a command corresponding to the shortest predetermined period among pre-set predetermined periods after a lapse of the shortest predetermined period since the command was issued immediately previously.

3. The memory controller according to claim 1, wherein: In the case of issuing a command to a second memory different from a first memory to which a command was immediately previously issued, the control circuit issues a read command in preference to a write command.

4. The memory controller according to claim 1, wherein: In the case where a write command or a read command is issued to a second memory different from a first memory to which a write command was immediately previously issued, the control circuit issues the read command in preference to the write command.

5. The memory controller according to claim 1, wherein: In the case where a write command or a read command is issued to a second memory different from a first memory to which a read command was immediately previously issued, the control circuit issues the read command in preference to the write command.

6. The memory controller according to claim 1, wherein The control circuit performs control to: in a case where a read command is issued to a second memory different from the first memory to which the write command was issued immediately previously, in response to a first predetermined period of time having passed since the issuance of the write command, issuing the read command to the second memory, and In a case where a write command is issued to a second memory different from the first memory to which the write command was issued immediately previously, in response to a second predetermined period of time having passed since the issuance of the write command, issuing the write command to the second memory, and The second predetermined period of time is longer than the first predetermined period of time.

7. The memory controller according to claim 1, wherein: In the case where a write command is issued to the first memory immediately following the previously issued read command, the control circuit issues the write command to the first memory in response to a lapse of a third predetermined period of time from the issuance of the read command.

8. The memory controller according to claim 1, wherein: The control circuit performs control to: in a case where a read command is issued to a second memory different from the first memory to which the read command was issued immediately previously, in response to a fourth predetermined period of time having passed since the issuance of the read command, issuing the read command to the second memory, and In a case where a write command is issued to a second memory different from the first memory to which the read command was issued immediately previously, in response to a fifth predetermined period of time having passed since the issuance of the read command, issuing a write command to the second memory, and The fifth predetermined period of time is longer than the fourth predetermined period of time.

9. The memory controller according to claim 1, wherein: In the case where a write command is issued to the first memory immediately prior to the read command being issued to the first memory, the control circuit issues the write command to the first memory in response to a sixth predetermined period of time having passed since the issuance of the read command.

10. A method for controlling a memory controller for issuing read and write commands for accessing a plurality of memories sharing a data signal, the method comprising: maintaining an access request for the command in a holding circuit; as well as Control is performed to select an access request from access requests held in a holding circuit and issue a command, wherein In the control, in the case of issuing a command to a second memory different from the first memory to which a command was issued immediately previously, control is performed on which command is issued first based on a corresponding predetermined time period pre-set for each set of the type of command issued immediately previously to the first memory and the type of command to be issued to the second memory.

11. A memory device comprising: Multiple memories sharing data signals; as well as A memory controller for issuing read and write commands for accessing the plurality of memories, the controller comprising: a holding circuit configured to hold an access request to the command; as well as A control circuit is configured to select an access request from the access requests held in the holding circuit and issue a command, wherein In the case of issuing a command to a second memory that is different from the first memory to which a command was issued immediately previously, the control circuit controls which command is issued first based on a corresponding predetermined time period pre-set for each set of the type of command issued immediately previously to the first memory and the type of command to be issued to the second memory.

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