Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the steps that a first to-be-packaged structure comprising at least one first electrical element is attached to a carrier plate, the first to-be-packaged structure comprises at least two electrodes arranged at intervals, and the functional leading-out ends of the electrodes are far away from the carrier plate; forming a first plastic packaging layer at least packaging the side surface of the first to-be-packaged structure; the carrier plate is removed, a rewiring layer is formed on the first plastic packaging layer, and the rewiring layer is located on the side, away from the functional leading-out end, of the first to-be-packaged structure; forming a plurality of exposed re-wiring layer return through holes in the first plastic packaging layer, wherein the functional leading-out end is exposed; forming a conductive part in the through hole, and enabling the rewiring layer to be electrically connected with the conductive part; a second to-be-packaged structure is arranged on the side, away from the rewiring layer, of the first plastic packaging layer, the second to-be-packaged structure comprises a chip and a conductive structure, and the conductive structure is electrically connected with the conductive part and the functional leading-out end; and forming a second plastic packaging layer at least packaging the side surface of the second to-be-packaged structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] In common semiconductor packaging technologies, lead frames or conductive copper pillars are usually used to achieve electrical connection between the front and back of a chip. The chip packaging technology may include the following process: First, the chip and the lead frame or conductive copper pillar are mounted on a carrier board, and then thermoplastic encapsulation is performed.

[0003] However, during the thermoplastic encapsulation of the chip and the lead frame or conductive copper pillar, the lead frame and the conductive copper pillar are prone to deformation and displacement, which may lead to problems such as short circuit or open circuit between the redistribution layer on the front of the chip and the lead frame or conductive copper pillar, affecting the yield of the product. Summary of the Invention

[0004] Embodiments of this application provide a manufacturing method of a semiconductor structure and a semiconductor structure.

[0005] In a first aspect of the embodiments of this application, a manufacturing method of a semiconductor structure is provided. The manufacturing method includes:

[0006] Mounting a first structure to be encapsulated on a carrier board, where the first structure to be encapsulated includes at least one first electrical component, the first structure to be encapsulated includes at least two electrodes arranged at intervals, the electrodes include functional lead-out ends, and the functional lead-out ends are far from the carrier board;

[0007] Forming a first encapsulation layer that at least encapsulates the side surfaces of the first structure to be encapsulated;

[0008] Removing the carrier board, and forming a redistribution layer on the first encapsulation layer, where the redistribution layer is located on a side of the first structure to be encapsulated away from the functional lead-out ends;

[0009] Forming a plurality of through holes in the first encapsulation layer, where the through holes expose the redistribution layer; the functional lead-out ends are exposed;

[0010] Forming a conductive part in the through holes to electrically connect the redistribution layer and the conductive part;

[0011] Arranging a second structure to be encapsulated on a side of the first encapsulation layer away from the redistribution layer, where the second structure to be encapsulated includes a chip and a conductive structure located on a side of the chip facing the first encapsulation layer and electrically connected to the circuit of the chip, and the conductive structure is electrically connected to the conductive part and the functional lead-out ends respectively;

[0012] A second encapsulation layer is formed, and the second encapsulation layer encapsulates at least the side surfaces of the second structure to be encapsulated.

[0013] In one embodiment, there is a gap on a side of the adjacent electrodes away from the function lead-out end; after removing the carrier board and before forming the redistribution layer on the first encapsulation layer, the manufacturing method of the semiconductor structure further includes: providing an insulating layer on a side of the first structure to be encapsulated away from the function lead-out end, the insulating layer covering the side of the first structure to be encapsulated away from the function lead-out end and filling the gap between the adjacent electrodes; and / or,

[0014] Before forming the second encapsulation layer, the manufacturing method of the semiconductor structure further includes: filling a filler between the second structure to be encapsulated and the first encapsulation layer to form a filling structure.

[0015] In one embodiment, forming the conductive portion in the through hole includes: filling the through hole with a flowing conductive material, and the conductive portion is formed after the conductive material is cured;

[0016] The conductive material includes at least one of solder and silver paste.

[0017] In one embodiment, the redistribution layer includes a plurality of first trace structures and second trace structures located on a side of each of the first trace structures away from the first encapsulation layer, and at least one of the second trace structures extends beyond the corresponding first trace structure to form a step structure; each through hole corresponds to one of the step structures, a positive projection of the through hole on a plane where a surface of the first encapsulation layer away from the redistribution layer is located entirely falls within a positive projection of the redistribution layer on the plane, and a positive projection of the through hole on the plane and a portion of the second trace structure extending beyond the first trace structure in the corresponding step structure at least partially overlap on the plane.

[0018] In one embodiment, before forming a plurality of through holes in the first encapsulation layer, the first encapsulation layer encapsulates the function lead-out end; each of the through holes penetrates through the first encapsulation layer, and at least one of the through holes exposes both the redistribution layer and the function lead-out end; or,

[0019] Before forming a plurality of through holes in the first encapsulation layer, the first encapsulation layer encapsulates the function lead-out end; the manufacturing method of the semiconductor structure further includes: forming an opening on a side of the first encapsulation layer away from the redistribution layer, the opening exposing the function lead-out end; forming a conductive pillar in the opening; and electrically connecting the conductive structure to the conductive pillar; or,

[0020] The functional lead-out terminal is flush with the surface of the first encapsulation layer away from the redistribution layer, and the through hole only exposes the redistribution layer.

[0021] In one embodiment, the first structure to be encapsulated only includes the electrical component, the electrical component is a passive device, and the electrode of the first structure to be encapsulated is the pin of the electrical component; the passive device includes at least one of an inductor, a resistor, and a capacitor; or,

[0022] The first structure to be encapsulated further includes an encapsulation layer encapsulating the electrical component and a conductive post exposing the encapsulation layer, the conductive post is the electrode of the first structure to be encapsulated, and the conductive post is electrically connected to the pin of the electrical component; the electrical component includes at least one of an inductor, a resistor, a capacitor, and a chip.

[0023] According to a second aspect of the embodiments of the present application, a semiconductor structure is provided, and the semiconductor structure includes:

[0024] A first encapsulation structure, including at least one first electrical component, and the first encapsulation structure includes at least two electrodes arranged at intervals;

[0025] A first encapsulation layer, encapsulating at least the side surface of the first encapsulation structure; the first encapsulation layer is provided with a plurality of through holes;

[0026] A conductive part, located in the through hole;

[0027] A redistribution layer, located on the first encapsulation layer and on one side of the electrical connection end of the first electrical component away from the electrode; the redistribution layer is electrically connected to the conductive part;

[0028] A second encapsulation structure, located on the side of the first encapsulation layer away from the redistribution layer, the second encapsulation structure includes a chip and a conductive structure located on the side of the chip facing the first encapsulation layer and electrically connected to the circuit of the chip, and the conductive structure is electrically connected to the conductive part and the functional lead-out terminal respectively;

[0029] A second encapsulation layer, encapsulating at least the side surface of the second encapsulation structure.

[0030] In one embodiment, the semiconductor structure further includes an insulating layer located between the first encapsulation layer and the redistribution layer, the insulating layer covers the side of the first encapsulation structure away from the functional lead-out terminal, and fills the gap between adjacent electrodes; and / or,

[0031] The semiconductor structure further includes a filling structure located between the second encapsulation structure and the first encapsulation layer.

[0032] In one embodiment, the material of the conductive portion includes at least one of solder and silver paste;

[0033] The redistribution layer includes a plurality of first trace structures and second trace structures located on a side of each of the first trace structures away from the first encapsulation layer. At least one of the second trace structures extends beyond the corresponding first trace structure to form a stepped structure; each via hole corresponds to one of the stepped structures. A positive projection of the via hole on a plane where a surface of the first encapsulation layer away from the redistribution layer is located entirely falls within a positive projection of the redistribution layer on the plane, and a positive projection of the via hole on the plane at least partially overlaps with a positive projection on the plane of a portion where the second trace structure in the corresponding stepped structure extends beyond the first trace structure.

[0034] In one embodiment, a positive projection on the plane of a portion where an edge of the via hole does not contact the redistribution layer is located inside an edge of a positive projection on the plane of a portion where the second trace structure in the corresponding stepped structure extends beyond the first trace structure; and / or,

[0035] The thickness range of the first trace structure is 10 μm to 60 μm.

[0036] In one embodiment, the first encapsulation structure only includes the electrical component, the electrical component is a passive device, and an electrode of the first encapsulation structure is a lead of the electrical component; the passive device includes at least one of an inductor, a resistor, and a capacitor; or,

[0037] The first encapsulation structure further includes an encapsulation layer encapsulating the electrical component and a conductive post exposing the encapsulation layer. The conductive structure is an electrode of the first encapsulation structure, and the conductive post is electrically connected to a lead of the electrical component; the electrical component includes at least one of an inductor, a resistor, a capacitor, and a chip.

[0038] The main technical effects achieved by the embodiments of the present application are:

[0039] The manufacturing method of a semiconductor structure and the semiconductor structure provided by an embodiment of the present application form a redistribution layer on a first encapsulation layer encapsulating a first structure to be encapsulated, and the redistribution layer is located on a side of the first structure to be encapsulated away from a functional lead-out end of an electrical component included therein. A conductive portion in a through hole of the first encapsulation layer is electrically connected to the redistribution layer, and conductive structures of a second structure to be encapsulated on a side of the first encapsulation layer away from the redistribution layer are respectively electrically connected to the conductive portion and the functional lead-out end of the electrical component. Thus, the electrical component of the first structure to be encapsulated and the chip of the second structure to be encapsulated are both electrically connected to the redistribution layer, realizing the interconnection between the electrical component and the chip. By forming the conductive portion in the through hole of the first encapsulation layer, there is no need to provide a lead frame or conductive posts during the preparation process of the semiconductor structure, which can avoid the problems of deformation and offset of the lead frame and conductive posts, resulting in an open circuit between the redistribution layer and the conductive portion, and is helpful for improving the product yield. Description of the Drawings

[0040] Figure 1 is a flowchart of a manufacturing method of a semiconductor structure provided by an exemplary embodiment of the present application;

[0041] Figure 2 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0042] Figure 3 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0043] Figure 4 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0044] Figure 5 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0045] Figure 6 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0046] Figure 7 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;

[0047] Figure 8 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;

[0048] Figure 9 is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;

[0049] Figure 10 is a partial cross-sectional view of an eighth intermediate structure provided by another exemplary embodiment of the present application;

[0050] Figure 11 It is a partial cross-sectional view of an eighth intermediate structure provided by another exemplary embodiment of the present application;

[0051] Figure 12 It is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;

[0052] Figure 13 It is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0053] Figure 14 It is a partial cross-sectional view of an eleventh intermediate structure provided by an exemplary embodiment of the present application;

[0054] Figure 15 It is a partial cross-sectional view of a twelfth intermediate structure provided by an exemplary embodiment of the present application;

[0055] Figure 16 It is a partial cross-sectional view of a thirteenth intermediate structure provided by an exemplary embodiment of the present application;

[0056] Figure 17 It is a partial cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0057] Figure 18 It is a partial cross-sectional view of a fourteenth intermediate structure provided by an exemplary embodiment of the present application;

[0058] Figure 19 It is a partial cross-sectional view of a fifteenth intermediate structure provided by an exemplary embodiment of the present application;

[0059] Figure 20 It is a partial cross-sectional view of a sixteenth intermediate structure provided by an exemplary embodiment of the present application;

[0060] Figure 21 It is a partial cross-sectional view of a seventeenth intermediate structure provided by an exemplary embodiment of the present application;

[0061] Figure 22 It is a partial cross-sectional view of an eighteenth intermediate structure provided by an exemplary embodiment of the present application;

[0062] Figure 23 It is a partial cross-sectional view of a nineteenth intermediate structure provided by an exemplary embodiment of the present application;

[0063] Figure 24 It is a partial cross-sectional view of a twentieth intermediate structure provided by an exemplary embodiment of the present application;

[0064] Figure 25 It is a partial cross-sectional view of a semiconductor structure provided by another exemplary embodiment of the present application. Specific Embodiments

[0065] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0066] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0067] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0068] Some embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0069] An embodiment of the present application provides a method for manufacturing a semiconductor structure. Refer to Figure 1 , the method for manufacturing the semiconductor structure includes the following steps 110 to 170.

[0070] In step 110, a first structure to be encapsulated is mounted on a carrier board. The first structure to be encapsulated includes at least one first electrical component. The first structure to be encapsulated includes at least two electrodes spaced apart from each other. The electrode includes a functional lead-out end, and the functional lead-out end is away from the carrier board.

[0071] In step 120, a first encapsulation layer is formed, and the first encapsulation layer encapsulates at least the side surface of the first structure to be encapsulated.

[0072] In step 130, the carrier board is removed, and a redistribution layer is formed on the first encapsulation layer. The redistribution layer is located on a side of the first structure to be encapsulated away from the functional lead-out end.

[0073] In step 140, a plurality of vias are formed on the first encapsulation layer, and the vias expose the redistribution layer; the functional lead-out terminals are exposed.

[0074] In step 150, a conductive part is formed in the via, and the redistribution layer is electrically connected to the conductive part.

[0075] In step 160, a second structure to be encapsulated is disposed on a side of the first encapsulation layer away from the redistribution layer. The second structure to be encapsulated includes a chip and a conductive structure located on a side of the chip facing the first encapsulation layer and electrically connected to a circuit of the chip. The conductive structure is electrically connected to the conductive part and the functional lead-out terminal respectively.

[0076] In step 170, a second encapsulation layer is formed, and the second encapsulation layer encapsulates at least a side surface of the second structure to be encapsulated.

[0077] In the manufacturing method of the semiconductor structure provided by the embodiment of the present application, by forming a redistribution layer on the first encapsulation layer encapsulating the first structure to be encapsulated, and the redistribution layer is located on a side of the first structure to be encapsulated away from the functional lead-out terminals of the electrical components included therein, the conductive part in the via of the first encapsulation layer is electrically connected to the redistribution layer, and the conductive structures of the second structure to be encapsulated located on a side of the first encapsulation layer away from the redistribution layer are electrically connected to the conductive part and the functional lead-out terminals of the electrical components respectively. Thus, the electrical components of the first structure to be encapsulated and the chips of the second structure to be encapsulated are both electrically connected to the redistribution layer, realizing the interconnection of the electrical components and the chips; by forming the conductive part in the via of the first encapsulation layer, a lead frame or conductive posts do not need to be provided during the preparation process of the semiconductor structure, which can avoid the problems of deformation and offset of the lead frame and conductive posts, resulting in an open circuit between the redistribution layer and the conductive part, and is helpful for improving the product yield.

[0078] Next, each step of the manufacturing method of the semiconductor structure provided by the embodiment of the present application will be introduced in detail.

[0079] In step 110, the first structure to be encapsulated is mounted on a carrier. The first structure to be encapsulated includes at least one first electrical component. The first structure to be encapsulated includes at least two electrodes disposed at intervals. The electrodes include functional lead-out terminals, and the functional lead-out terminals are away from the carrier.

[0080] Through this step, the first intermediate structure as shown in Figure 2 can be obtained. As shown in Figure 2 , the first structure to be encapsulated 10 is mounted on the carrier 22 through the bonding layer 21. Figure 2Only one first structure to be encapsulated 10 mounted on the carrier 22 is schematically shown. In practice, multiple first structures to be encapsulated 10 can be mounted on the carrier 22. The functional lead-out end of the electrode refers to the end of the electrode for electrically connecting with the conductive structure.

[0081] In one embodiment, as Figure 2 shown, the first structure to be encapsulated 10 only includes the electrical component 11. The electrical component 11 is a passive device. The electrode 101 of the first structure to be encapsulated 10 is the pin of the electrical component 11. The passive device includes at least one of an inductor, a resistor, and a capacitor. The electrical component 11 includes a body 12 and at least two pins 13 located on the side of the body 12. The opposite ends of the pins 13 can respectively extend beyond the body 12. One end of the pins 13 is the functional lead-out end for electrically connecting with the conductive structure of the second structure to be encapsulated. There are gaps between adjacent pins 13 on the opposite sides of the electrical component 11. In other embodiments, the first structure to be encapsulated 10 can include an electrical component, an encapsulation layer encapsulating the electrical component, and conductive posts exposing the encapsulation layer. The conductive posts are the electrodes of the first structure to be encapsulated. The conductive posts are electrically connected to the pins of the electrical component. The exposed ends of the conductive posts are the functional lead-out ends for electrically connecting with the conductive structure of the second structure to be encapsulated. The electrical component includes at least one of an inductor, a resistor, a capacitor, and a chip. When the electrical component in the first structure to be encapsulated is a chip, the function of this chip can be the same as or different from the function of the chip in the second structure to be encapsulated.

[0082] In one embodiment, the bonding layer 21 can be made of an easily peelable material to facilitate the subsequent peeling of the carrier 22. For example, the bonding layer 21 can be made of a thermal separation material that can lose its adhesiveness by heating.

[0083] In one embodiment, the shape of the carrier 22 can be circular, rectangular, or other shapes. The carrier 22 can be a small-sized wafer substrate or a larger-sized carrier, such as a stainless steel plate substrate, a polymer substrate, etc.

[0084] In step 120, a first encapsulation layer is formed, and the first encapsulation layer at least encapsulates the side surface of the first structure to be encapsulated.

[0085] Through step 120, the second intermediate structure as Figure 3 shown can be obtained. As Figure 3 shown, the first encapsulation layer 30 is formed on the first structure to be encapsulated 10 and the exposed carrier 22, encapsulating the side surface of the first structure to be encapsulated 10 and its surface away from the carrier 22 to reconstruct a flat structure, so that after the carrier 22 is peeled off, re-wiring can continue on the reconstructed flat structure.

[0086] In one embodiment, before forming the first encapsulation layer 30, some pre - treatment steps can be performed, such as chemical cleaning, plasma cleaning and other steps, to remove impurities on the surface of the first structure to be encapsulated 10 and the carrier board 22, so that the first encapsulation layer 30 can be more closely connected to the first structure to be encapsulated 10 and the carrier board 22, and no delamination or cracking phenomenon will occur.

[0087] In one embodiment, the material of the first encapsulation layer 30 can be polymer resin, resin composite material, polymer composite material, etc. For example, the first encapsulation layer 30 can be a resin with fillers, where the fillers can be inorganic particles. The first encapsulation layer 30 can be formed by injection molding, compression molding or transfer molding and other methods.

[0088] In step 130, the carrier board is removed, and a redistribution layer is formed on the first encapsulation layer. The redistribution layer is located on the side of the first structure to be encapsulated away from the functional lead - out end.

[0089] In one embodiment, as Figure 3 shown, there is a gap on the side of the adjacent electrodes 101 away from the functional lead - out end; after the step of removing the carrier board and before the step of forming the redistribution layer on the first encapsulation layer, the manufacturing method of the semiconductor structure further includes the following steps: an insulating layer is provided on the side of the first structure to be encapsulated away from the functional lead - out end, the insulating layer covers the side of the first structure to be encapsulated away from the functional lead - out end, and fills the gap between the adjacent electrodes.

[0090] In one embodiment, the step of providing an insulating layer on the side of the first structure to be encapsulated away from the functional lead - out end, where the insulating layer covers the side of the first structure to be encapsulated away from the functional lead - out end and fills the gap between the adjacent electrodes, includes the following process:

[0091] First, the structure obtained by removing the carrier board is mounted on the first carrier board, and the functional lead - out ends of the electrodes of the electrical components face the carrier board.

[0092] Through this step, a third intermediate structure as Figure 4 shown can be obtained. As Figure 4 shown, the first encapsulation layer 30 is mounted on the first carrier board 24 through the bonding layer 23. The bonding layer 23 can be made of an easily peelable material to facilitate the subsequent peeling of the first carrier board 24. For example, the bonding layer 23 can be a thermal separation material that loses its adhesiveness when heated.

[0093] Subsequently, an insulating layer is provided on the side of the first structure to be encapsulated away from the functional lead - out end, the insulating layer covers the side of the first structure to be encapsulated away from the functional lead - out end, and fills the gap between the adjacent electrodes.

[0094] Through this step, a fourth intermediate structure as shown in Figure 5 can be obtained. As shown in Figure 5 , the insulating layer 40 covers the side of the first structure to be encapsulated 10 away from the functional lead-out terminal and the surface of the first encapsulation layer 30 on the same side, and fills the gap between adjacent electrodes 101; the surfaces of the insulating layer 40 away from the first encapsulation layer 30 are substantially flush. Since the insulating layer 40 fills the gap between adjacent electrodes 101, it is possible to avoid the existence of a gap between adjacent electrodes 101, which may cause the conductive material to flow into the gap between adjacent electrodes 101 during the subsequent formation of the conductive part with a flowing conductive material, resulting in a short circuit between adjacent electrodes 101, and during the welding of the conductive structure of the second structure to be encapsulated and the conductive part, the molten conductive material flows into the gap between adjacent electrodes 101, resulting in a short circuit between adjacent electrodes 101; it is also possible to avoid the material of the redistribution layer from entering the gap between adjacent electrodes 101 during the subsequent formation of the redistribution layer, resulting in a short circuit between adjacent electrodes 101; since the surfaces of the insulating layer 40 away from the first encapsulation layer 30 are substantially flush, the quality of the redistribution layer formed on the surface of the insulating layer 40 away from the first encapsulation layer 30 can be ensured.

[0095] Through step 130, a fifth intermediate structure as shown in Figure 6 can be obtained. As shown in Figure 6 , the redistribution layer 50 is located on the side of the insulating layer 40 away from the first encapsulation layer 30. The redistribution layer 50 includes a plurality of trace structures 51 and conductive studs 52 located on the side of the trace structures 51 away from the first encapsulation layer 30. At least one trace structure 51 is provided with a conductive stud 52 on the side away from the first encapsulation layer 30.

[0096] In one embodiment, after step 130, the method for manufacturing the semiconductor structure further includes: forming a dielectric layer that covers the redistribution layer, and the surface of the conductive stud away from the first chip is exposed from the dielectric layer.

[0097] Through this step, a sixth intermediate structure as shown in Figure 7 can be obtained. As shown in Figure 7 , the dielectric layer 83 covers the redistribution layer 50, and the surface of the conductive stud 52 away from the first encapsulation layer 30 is flush with the surface of the dielectric layer 83 on the same side. The dielectric layer 83 can protect the redistribution layer 50.

[0098] In step 140, a plurality of through holes are formed in the first encapsulation layer, and the through holes expose the redistribution layer; the functional lead-out terminals are exposed.

[0099] In one embodiment, before step 140, the method for manufacturing the semiconductor structure further includes: removing the first carrier plate, mounting the obtained structure on a second carrier plate, and the redistribution layer faces the second carrier plate.

[0100] Through this step, the seventh intermediate structure as shown in Figure 8 can be obtained. As shown in Figure 8 , the dielectric layer 83 is mounted on the second carrier 26 through the adhesive layer 25. The adhesive layer 25 can be made of an easily peelable material to facilitate the subsequent peeling of the second carrier 26. For example, the adhesive layer 25 can be a thermal separation material that loses its adhesiveness when heated.

[0101] In one embodiment, as shown in Figure 8 , before the step of forming a plurality of through-holes in the first encapsulation layer, the first encapsulation layer 30 encapsulates the functional lead-out ends of the electrical components 10. Through step 140, the eighth intermediate structure as shown in Figure 9 can be obtained. As shown in Figure 9 , each of the through-holes 31 penetrates through the first encapsulation layer 30, and at least one of the through-holes 31 exposes a part of the trace structure 51 of the redistribution layer 50 and the functional lead-out ends of the electrical components 10 at the same time. When the through-hole 31 exposes the trace structure 51 and the functional lead-out ends of the electrical components 10 at the same time, the side surface of the electrode is also exposed by the through-hole 31. Since at least one of the through-holes 31 exposes a part of the trace structure 51 and the functional lead-out ends of the electrical components 10 at the same time, the number of through-holes 31 can be reduced.

[0102] In another embodiment, as shown in Figure 8 , before the step of forming a plurality of through-holes in the first encapsulation layer 30, the first encapsulation layer 30 encapsulates the functional lead-out ends of the electrical components 10. The through-holes only expose the trace structure of the redistribution layer; the manufacturing method of the semiconductor structure further includes: forming an opening on the first encapsulation layer on the side of the functional lead-out ends away from the redistribution layer, and the opening exposes the functional lead-out ends.

[0103] Through this step, the eighth intermediate structure as shown in Figure 10 can be obtained. As shown in Figure 10 , the depth of the opening 32 is less than the thickness of the first encapsulation layer 30, and the through-hole 31 only exposes a part of the trace structure 51 of the redistribution layer 50.

[0104] In still another embodiment, before step 140, the manufacturing method of the semiconductor structure further includes: thinning the side of the first encapsulation layer away from the redistribution layer so that the functional lead-out ends of the electrical components 10 are flush with the surface of the first encapsulation layer away from the redistribution layer. Through step 140, the eighth intermediate structure as shown in Figure 11 can be obtained. As shown in Figure 11As shown, the functional lead-out terminal of the electrical component 11 is flush with the surface of the first encapsulation layer 30 away from the redistribution layer 50, and only a part of the trace structure 51 is exposed by the via hole 31. By thinning the first encapsulation layer 30, it helps to reduce the thickness of the finally obtained semiconductor structure and can reduce the manufacturing difficulty of the via hole 31.

[0105] In one embodiment, as Figures 9 to 11 shown, when an insulating layer 40 is formed between the first encapsulation layer 30 and the redistribution layer 50, the via hole 31 penetrates through the insulating layer 40.

[0106] In step 150, a conductive portion is formed in the via hole to electrically connect the redistribution layer and the conductive portion.

[0107] In one embodiment, when the eighth intermediate structure is as Figure 9 shown, the ninth intermediate structure as Figure 12 shown can be obtained through step 150. As Figure 12 shown, conductive portions 60 are respectively formed in each via hole 31, and at least one conductive portion 60 is in contact with both the trace structure 51 of the redistribution layer 50 and the functional lead-out terminal of the electrode 101 of the electrical component. When the via hole 31 exposes the trace structure 51 of the redistribution layer 50, the functional lead-out terminal of the electrode 101, and a part of the side surface of the electrode 101 at the same time, the conductive portion 60 located in the via hole 31 is in contact with and electrically connected to the trace structure 51, the electrical connection terminal of the electrode 101, and the side surface of the electrode 101 at the same time, which helps to improve the reliability of the electrical connection between the conductive portion 60 and the electrode 101.

[0108] In one embodiment, the step of forming the conductive portion in the via hole includes the following process: filling the via hole with a flowing conductive material, and the conductive material forms the conductive portion after curing. By filling the via hole with a flowing conductive material, the via hole can be filled with the conductive material, ensuring that the conductive portion obtained after the conductive material cures has a good electrical connection effect with the redistribution layer. Compared with the solution of forming a conductive portion in the via hole by electroplating process, it can improve the problems that the conductive material cannot be plated on the hole wall of the via hole in the electroplating process and the short circuit of the conductive portions in adjacent via holes caused by the alignment deviation of the mask layer in the electroplating process, which helps to improve the product yield.

[0109] In one embodiment, the conductive material includes at least one of solder paste and silver paste. Solder paste and silver paste have good fluidity at room temperature and are more likely to fill the via holes in the first encapsulation layer, ensuring a better electrical connection effect between the conductive portions formed in the via holes of the first encapsulation layer and the redistribution layer. Among them, solder paste is a paste-like mixture formed by mixing solder powder, flux, and other surfactants, thixotropic agents, etc., and silver paste is prepared from silver or its compounds, fluxing agents, binders, and diluents.

[0110] In one embodiment, when the conductive material is solder paste or silver paste or a mixture of both, the conductive material can be melted by heating the conductive material and then solidified by cooling.

[0111] In one embodiment, the step of filling the through hole with the flowing conductive material includes the following process: filling the through hole with the flowing conductive material by using a screen printing process.

[0112] During the screen printing process, first place the screen on the side of the eighth intermediate structure facing away from the first carrier 26, and then print the conductive material through the mesh holes of the screen into the through hole 31. After the conductive material is solidified, a conductive part is formed. Since the screen has a certain thickness, some of the conductive material will be filled in the mesh holes of the screen during the printing process of the conductive material. Then, the surface of the finally formed conductive part facing away from the redistribution layer 50 exceeds the surface of the first encapsulation layer 30 facing away from the redistribution layer 50, that is, the conductive part exceeds the through hole 31. This facilitates welding the conductive part to the conductive structure of the second structure to be encapsulated in subsequent steps. During the screen printing process, the printing pressure and printing speed can be controlled so that the through hole 31 is substantially completely filled with the conductive material. In some embodiments, the range of the printing pressure can be 4 kg to 10 kg, and the range of the printing speed can be 20 mm / s to 100 mm / s.

[0113] In another embodiment, the step of filling the through hole with the flowing conductive material includes the following process: filling the through hole with the flowing conductive material by using a dispensing process.

[0114] In this embodiment, the flowing conductive material is injected into the through hole 31 by using a dispensing process, and the finally formed conductive part may or may not exceed the encapsulation layer 30.

[0115] In one embodiment, when the eighth intermediate structure is as Figure 10 shown, the manufacturing method of the semiconductor structure further includes: forming a conductive pillar in the opening. In this step, the conductive pillar and the conductive part can be formed simultaneously, that is, the through hole 31 and the opening 32 are filled with the flowing conductive material at the same time, and the conductive material in the opening 32 is solidified to form a conductive pillar.

[0116] In step 160, a second structure to be encapsulated is disposed on the side of the first encapsulation layer away from the redistribution layer. The second structure to be encapsulated includes a chip and a conductive structure located on the side of the chip facing the first encapsulation layer and electrically connected to the circuit of the chip. The conductive structure is electrically connected to the conductive part and the functional lead-out end respectively.

[0117] After the second structure to be encapsulated is placed on the side of the first encapsulation layer away from the redistribution layer, the following can be obtained asFigure 13 The tenth intermediate structure shown. As Figure 13 shown, two second structures to be encapsulated 70 are provided on the side of the first encapsulation layer 30 away from the redistribution layer 50. The second structure to be encapsulated 70 includes a chip 71 and a conductive structure 73 located on the side of the chip 71 facing the first encapsulation layer 30 and electrically connected to the circuit of the chip 71. The conductive structure 73 leads out the circuit inside the chip 71. One of the second structures to be encapsulated 70 further includes a redistribution layer 72 located between the chip 71 and the conductive structure 73, and an encapsulation material layer 74 encapsulating the chip 71 and the redistribution layer 72. The conductive structure 73 is electrically connected to the circuit of the chip 71 through the redistribution layer 72. The redistribution layer 72 may include multiple layers of traces.

[0118] In one embodiment, the material of the conductive structure 73 is solder, for example, it may include tin.

[0119] The eleventh intermediate structure shown can be obtained through step 160. As Figure 14 shown, the second structure to be encapsulated 70 is welded to the conductive part 60 through the conductive structure. Figure 14 As

[0120] In one embodiment, after step 160 and before step 170, the manufacturing method of the semiconductor structure further includes the following step: filling a filler between the second structure to be encapsulated and the first encapsulation layer to form a filling structure.

[0121] The twelfth intermediate structure shown can be obtained through this step. As Figure 15 shown, the surface of the filling structure 81 facing away from the first encapsulation layer 30 abuts against the second structure to be encapsulated 70, and the surface of the filling structure 90 facing the first encapsulation layer 30 abuts against the first encapsulation layer 30. In this way, first, a filler is filled between the second structure to be encapsulated 70 and the first encapsulation layer to form a filling structure 81, and then a second encapsulation layer is formed to encapsulate the second structure to be encapsulated 70, which can reduce the probability of voids existing at the bottom of the second structure to be encapsulated 70 after the second encapsulation layer is formed, that is, it can achieve that there are smaller voids or no voids at the bottom of the second structure to be encapsulated 70 after encapsulation, and the filling effect at the bottom of the second structure to be encapsulated 70 is better, further reducing the risk of short - circuit between adjacent solder bumps of the second structure to be encapsulated 70. Figure 15 As

[0122] Both the filler for forming the filling structure 81 and the material of the second encapsulation layer may have filler particles, and the size of the filler particles in the filling structure 81 is smaller than the size of the filler particles in the second encapsulation layer. In this way, it is more conducive to reducing the probability of voids existing at the bottom of the second structure to be encapsulated 70, improving the filling effect at the bottom of the second structure to be encapsulated 70, and reducing the risk of short - circuit between adjacent solder bumps of the second structure to be encapsulated 70.

[0123] In step 170, a second encapsulation layer is formed, and the second encapsulation layer encapsulates at least the side surfaces of the second structure to be encapsulated.

[0124] Through this step, the thirteenth intermediate structure as shown in Figure 16 can be obtained. As shown in Figure 16 , the second encapsulation layer 82 encapsulates the side surfaces and the surface away from the first encapsulation layer 30 of the second structure to be encapsulated 70.

[0125] In one embodiment, before forming the second encapsulation layer 82, some pre-treatment steps can be performed, such as chemical cleaning, plasma cleaning and other steps, to remove the impurities on the surface of the second structure to be encapsulated 70 and the impurities on the surface of the first encapsulation layer 30 facing away from the redistribution layer 50, so that the second encapsulation layer 82 can be more closely connected to the second structure to be encapsulated 70 and the first encapsulation layer 30, and there will be no delamination or cracking phenomenon.

[0126] In one embodiment, the material of the second encapsulation layer 82 can be polymer resin, resin composite material, polymer composite material, etc. For example, the second encapsulation layer 82 can be a resin with fillers, and the fillers can be inorganic particles. The second encapsulation layer 82 can be formed by injection molding, compression molding or transfer molding and other methods.

[0127] In one embodiment, after step 170, the manufacturing method of the semiconductor structure further includes the following steps: removing the second carrier plate, and forming a plurality of conductive balls on the side of the redistribution layer facing away from the second structure to be encapsulated by using a ball mounting process. After removing the second carrier plate, the surface of the redistribution layer facing away from the first chip is exposed, so that the ball mounting can be performed on the surface of the redistribution layer facing away from the first chip.

[0128] Through this step, the semiconductor structure as shown in Figure 17 can be obtained. As shown in Figure 17 , a conductive ball 90 is respectively formed on the surface of each conductive bump 52 of the redistribution layer 50 facing away from the second structure to be encapsulated 70. The semiconductor structure can be welded to the circuit board through the conductive balls 90, which is convenient for the connection between the semiconductor structure and the circuit board. The material of the conductive balls 90 can be solder paste, metallic tin or tin alloy.

[0129] In one embodiment, the preparation method of the semiconductor structure further includes: cutting the semiconductor structure to obtain a plurality of semiconductor sub-structures, and each semiconductor sub-structure includes at least one first structure to be encapsulated and at least one second structure to be encapsulated.

[0130] The present application also provides another manufacturing method of a semiconductor structure. Only the differences between the manufacturing method of the semiconductor structure in this embodiment and the aforementioned manufacturing method of the semiconductor structure are introduced below, and the same parts will not be introduced again.

[0131] In this embodiment, the redistribution layer includes a plurality of first trace structures and second trace structures located on a side of each first trace structure away from the first encapsulation layer, and at least one second trace structure extends beyond the corresponding first trace structure to form a step structure.

[0132] Through step 130, the fourteenth intermediate structure as shown in Figure 18 can be obtained. As shown in Figure 18 , the redistribution layer 50 includes a plurality of first trace structures 53 and second trace structures 54 located on a side of each first trace structure 53 away from the first encapsulation layer 30. The first trace structure 53 is in contact with the insulating layer 40. A part of the second trace structure 40 is in contact with the first trace structure 53, and there is a gap between the part extending beyond the first trace structure 53 and the insulating layer 40; the redistribution layer 50 is provided with a plurality of step structures 501 facing the first encapsulation layer 30.

[0133] In one embodiment, step 130 may include the following process:

[0134] First, a seed layer is formed on a side of the insulating layer away from the first encapsulation layer. The seed layer can be formed by a sputtering process.

[0135] Subsequently, a first insulating film layer is provided on a side of the seed layer facing away from the first encapsulation layer. The first insulating film layer can be provided by pressing a dry film on a side of the seed layer facing away from the first chip.

[0136] Subsequently, the first insulating film layer is exposed and developed to form a plurality of first openings.

[0137] Subsequently, electroplating is performed to form sub-trace structures in each of the first openings.

[0138] Subsequently, a second insulating film layer is provided on a side of the sub-trace structure facing away from the first encapsulation layer. The second insulating film layer can be provided by pressing a dry film.

[0139] Subsequently, the second insulating film layer is exposed and developed to form a plurality of second openings. The second openings correspond to the first openings one by one, and the size of at least one second opening is larger than the size of the first opening.

[0140] Subsequently, electroplating is performed to form second trace structures in each of the second openings.

[0141] Subsequently, the first insulating film layer and the second insulating film layer are removed. Chemical reagents can be used to react with the first insulating film layer and the second insulating film layer to remove the first insulating film layer and the second insulating film layer. Since a part of the first insulating film layer is located below the second trace structure, in order to completely remove the first insulating film layer, the chemical reagents can be made to react with the first insulating film layer and the second insulating film layer under ultrasonic conditions.

[0142] Subsequently, the portion of the seed layer not covered by the sub-trace line structure is etched away, and the portions of the remaining seed layer in contact with each sub-trace line structure and the sub-trace line structure are the first trace line structure.

[0143] In one embodiment, the insulating layer includes a cutting area. After step 130 and before step 140, the method for manufacturing the semiconductor structure further includes: removing the first carrier plate and placing the obtained structure on a support member. The support member includes a plate portion and a support portion extending from one side of the plate portion. The support portion is in contact with the cutting area of the insulating layer, and the redistribution layer faces the plate portion and there is a gap between the redistribution layer and the plate portion.

[0144] Through the above steps, the fifteenth intermediate structure shown in FIG. 19 can be obtained. As Figure 19 shown, the support portion 242 of the support member 24 is in contact with the cutting area 41 of the insulating layer 40, and there is a gap between the plate portion 241 of the support member 24 and the redistribution layer 40. The support member 24 may include a plurality of support portions 242. The cutting area 41 of the insulating layer 40 is the position for subsequent cutting of the insulating layer 40.

[0145] The support member 24 can provide a support function, facilitating the subsequent process steps; since the support portion 241 is in contact with the cutting area 41 of the insulating layer 40, it can be avoided that the support portion 241 contacts other areas and causes deformation of other areas due to force, affecting the quality of the semiconductor structure; since the redistribution layer 50 has a stepped structure, the strength of the redistribution layer 50 is relatively small. By providing a gap between the plate portion 242 and the redistribution layer 50, it can be avoided that the redistribution layer 50 contacts the support member 24 and the redistribution layer 50 is deformed due to force.

[0146] In one embodiment, the support portion 241 of the support member 24 is provided with a vacuum pumping channel, and the gas between the support portion 241 and the cutting area 41 of the insulating layer 40 can be pumped out through the vacuum pumping channel, so that the support portion 241 and the cutting area 41 of the insulating layer 40 are vacuum adsorbed. In this way, it is convenient to separate the support member 24 from the insulating layer 40 subsequently. In other embodiments, the support portion 241 and the insulating layer 40 can be adhered together through an adhesive layer, and the adhesive layer can adopt an easily peelable material, so as to peel off the support member subsequently. For example, the adhesive layer can adopt a thermal separation material that can lose its viscosity by heating.

[0147] In one embodiment, after step 140, the sixteenth intermediate structure shown in Figure 20 can be obtained. As Figure 20As shown, each of the through holes 31 corresponds to a step structure 501. The positive projection of the through hole 501 on the plane of the surface of the first encapsulation layer 30 away from the redistribution layer 50 completely falls within the positive projection of the redistribution layer 50 on the plane, and the positive projection of the through hole 31 on the plane at least partially overlaps with the positive projection of the part where the second trace structure 54 in the corresponding step structure 501 exceeds the first trace structure 53 on the plane.

[0148] By providing the step structure 501 facing the first encapsulation layer 30 in the redistribution layer 50, and at least partially overlapping the positive projection of the part where the second trace structure 54 in the step structure 501 exceeds the first trace structure 53 with the positive projection of the corresponding through hole 31 on this plane, during the process of welding the conductive part 60 to the conductive structure of the second structure to be encapsulated, the gas in the through hole 31 can be discharged through the channel between the part where the second trace structure 54 in the step structure 501 exceeds the first trace structure 53 and the insulating layer 40, which can avoid the existence of gas in the through hole 31 causing voids in the conductive part 60 and affecting the quality of the semiconductor structure.

[0149] In one embodiment, the positive projection of the part of the edge of the through hole 31 that does not contact the redistribution layer 50 on the plane is located inside the edge of the positive projection of the part where the second trace structure 54 in the corresponding step structure 501 exceeds the first trace structure 53 on the plane. With such a setting, in the direction parallel to the above plane, for the part where the second trace structure 54 exceeds the edge of the corresponding through hole 31 and does not contact the redistribution layer 50, when filling the flowing conductive material into the through hole 31 subsequently, the flowing conductive material flows out from the part of the through hole 31 not blocked by the step structure 401 and flows onto the surface of the part of the second trace structure 54 that does not contact the insulating layer 40, which can avoid the conductive material flowing to the surface of the encapsulation layer 30 and causing electrical connection between two adjacent first trace structures 42, thus affecting the performance of the semiconductor structure.

[0150] In one embodiment, the thickness range of the first trace structure 53 is 10μm - 60μm. The thickness of the first trace structure 53 is also the distance between the second trace structure 54 and the insulating layer 40. With such a setting, it can be avoided that the distance between the surface of the second trace structure 54 that does not contact the insulating layer 40 and the insulating layer 40 is too small, which is not conducive to the discharge of the gas in the through hole 31 in subsequent steps, and it can also be avoided that the distance between the surface of the second trace structure 54 and the insulating layer 40 is too large, resulting in a greater difficulty in the preparation process of the redistribution layer. In some embodiments, the thickness of the first trace structure 53 can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, etc.

[0151] In one embodiment, after step 150, what can be obtained is as Figure 21The seventeenth intermediate structure shown. As Figure 21 shown, the conductive portion 60 extends beyond the surface of the insulating layer 40 away from the first encapsulation layer 30, and the conductive portion 60 is in contact with both the first trace structure 53 and the second trace structure 54 of the corresponding stepped structure 501.

[0152] In one embodiment, after step 160 and after the step of filling a filler between the second structure to be encapsulated and the first encapsulation layer to form a filling structure, the following can be obtained as Figure 22 the eighteenth intermediate structure shown.

[0153] In one embodiment, after step 170, the following can be obtained as Figure 23 the nineteenth intermediate structure shown.

[0154] In one embodiment, after step 170, the manufacturing method of the semiconductor structure further includes the following steps:

[0155] First, remove the support member to form an insulating material layer covering the redistribution layer.

[0156] Through this step, the following can be obtained as Figure 24 the twentieth intermediate structure shown. As Figure 24 shown, the insulating material layer 84 covers the redistribution layer 50 and covers the surface of the redistribution layer 50 away from the first encapsulation layer 30.

[0157] Subsequently, form a plurality of openings in the insulating material layer, and each opening exposes at least a part of the surface of a second trace structure of the redistribution layer.

[0158] Subsequently, form conductive blocks in the openings of the insulating material layer and a redistribution structure on the side of the insulating material layer away from the redistribution layer. The redistribution structure includes a plurality of redistributions and conductive material portions on the side of at least one redistribution away from the redistribution layer, and the redistributions are electrically connected to the conductive blocks.

[0159] Subsequently, form an insulating film layer covering the redistribution structure.

[0160] Subsequently, form conductive balls on the side of each of the conductive material portions away from the insulating material layer.

[0161] Through the above steps, the following can be obtained as Figure 25 the semiconductor structure shown. As Figure 25As shown, a conductive block 86 is provided in an opening of a portion of the insulating material layer 84 on a side away from the first encapsulation layer 30 of the redistribution layer 50; a redistribution structure 85 is located on a side of the insulating material layer 84 away from the redistribution layer 50, and includes a redistribution line 851 electrically connected to the conductive block 86 and a conductive material portion 852 located on a side of the redistribution line 851 away from the redistribution layer 50; an insulating film layer 87 covers the redistribution structure 85, and a surface of the conductive material portion 852 is exposed from the insulating film layer 87; a conductive ball 90 is located on a side of the conductive material portion 852 away from the insulating material layer 84.

[0162] An embodiment of the present application further provides a semiconductor structure. As Figure 17 and Figure 25 shown, the semiconductor structure includes a first encapsulation structure 10, a first encapsulation layer 30, a conductive portion 60, a redistribution layer 50, a second encapsulation structure 70, and a second encapsulation layer 82.

[0163] The first encapsulation structure 10 includes at least one first electrical component 11, and the first encapsulation structure 10 includes at least two electrodes 101 spaced apart. The first encapsulation layer 30 at least encapsulates a side surface of the first encapsulation structure 10; the first encapsulation layer 30 is provided with a plurality of through holes 31. The conductive portion 60 is located in the through holes 31. The redistribution layer 50 is located on the first encapsulation layer 30 and on a side of the first electrical component 11 away from an electrical connection end of the electrode 101, and the redistribution layer 50 is electrically connected to the conductive portion 60. The second encapsulation structure 70 is located on a side of the first encapsulation layer 30 away from the redistribution layer 50, and the second encapsulation structure 70 includes a chip 71 and a conductive structure 72 located on a side of the chip 71 facing the first encapsulation layer 30 and electrically connected to a circuit of the chip 71, and the conductive structure 72 is electrically connected to the conductive portion 60 and the functional lead-out end. The second encapsulation layer 82 at least encapsulates a side surface of the second encapsulation structure 70.

[0164] In one embodiment, as Figure 17 and Figure 25 shown, the semiconductor structure further includes an insulating layer 40 located between the first encapsulation layer 30 and the redistribution layer 50, and the insulating layer 40 covers a side of the first encapsulation structure 10 away from the functional lead-out end and fills a gap between adjacent electrodes 101.

[0165] In one embodiment, as Figure 17 and Figure 25 shown, the semiconductor structure further includes a filling structure 81 located between the second encapsulation structure 70 and the first encapsulation layer 30.

[0166] In one embodiment, the material of the conductive portion includes at least one of solder and silver paste.

[0167] Further, as Figure 25 shown, the redistribution layer 50 includes a plurality of first trace structures 53 and second trace structures 54 located on a side of each of the first trace structures 53 away from the first encapsulation layer 30. At least one of the second trace structures 54 extends beyond the corresponding first trace structure 53 to form a step structure 501; each via 31 corresponds to one of the step structures 501. A positive projection of the via 31 on a plane where a surface of the first encapsulation layer 30 away from the redistribution layer 50 is located entirely falls within a positive projection of the redistribution layer 50 on the plane, and a positive projection of the via 31 on the plane and a positive projection of a portion of the second trace structure 54 that extends beyond the first trace structure 53 in the corresponding step structure 501 at least partially overlap on the plane.

[0168] Further, a positive projection of a portion of the edge of the via 31 that does not contact the redistribution layer 50 on the plane is located inside an edge of a positive projection of a portion of the second trace structure 54 that extends beyond the first trace structure 53 on the plane.

[0169] Further, a thickness range of the first trace structure 53 is 10 μm to 60 μm.

[0170] In one embodiment, as Figure 17 and Figure 25 shown, the first encapsulation structure 10 only includes the electrical component 11. The electrical component 11 is a passive device, and an electrode 101 of the first encapsulation structure 10 is a lead of the electrical component 111; the passive device includes at least one of an inductor, a resistor, and a capacitor.

[0171] In another embodiment, the first encapsulation structure further includes an encapsulation layer encapsulating the electrical component and conductive pillars exposing the encapsulation layer. The conductive structure is an electrode of the first encapsulation structure, and the conductive pillars are electrically connected to leads of the electrical component; the electrical component includes at least one of an inductor, a resistor, a capacitor, and a chip.

[0172] An embodiment of a manufacturing method of the semiconductor structure provided by an embodiment of this application and an embodiment of the semiconductor structure belong to the same inventive concept. Descriptions of relevant details and beneficial effects can be referred to each other, and will not be elaborated here.

[0173] It should be noted that in the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or an intermediate layer may be present. Additionally, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or more than one intermediate layer or element may be present. Further, it will be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or more than one intermediate layer or element may also be present. Like reference numerals throughout the specification indicate like elements.

[0174] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the disclosure herein. The present application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present application are pointed out by the following claims.

[0175] It should be understood that the present application is not limited to the exact structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is limited only by the appended claims.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, the manufacturing method includes: mounting a first structure to be encapsulated on a carrier board, the first structure to be encapsulated including at least one first electrical component, the first structure to be encapsulated including at least two electrodes arranged at intervals, the electrodes including functional lead-out ends, and the functional lead-out ends being away from the carrier board; forming a first encapsulation layer, the first encapsulation layer at least encapsulating the side surfaces of the first structure to be encapsulated; removing the carrier board, and forming a redistribution layer on the first encapsulation layer, the redistribution layer being located on a side of the first structure to be encapsulated away from the functional lead-out ends; forming a plurality of through holes in the first encapsulation layer, the through holes exposing the redistribution layer; and the functional lead-out ends being exposed; forming a conductive portion in the through holes to electrically connect the redistribution layer and the conductive portion; arranging a second structure to be encapsulated on a side of the first encapsulation layer away from the redistribution layer, the second structure to be encapsulated including a chip and a conductive structure located on a side of the chip facing the first encapsulation layer and electrically connected to the circuit of the chip, and the conductive structure being electrically connected to the conductive portion and the functional lead-out ends respectively; forming a second encapsulation layer, the second encapsulation layer at least encapsulating the side surfaces of the second structure to be encapsulated.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, there is a gap on a side of adjacent electrodes away from the functional lead-out ends; after removing the carrier board and before forming the redistribution layer on the first encapsulation layer, the manufacturing method of the semiconductor structure further includes: arranging an insulating layer on a side of the first structure to be encapsulated away from the functional lead-out ends, the insulating layer covering the side of the first structure to be encapsulated away from the functional lead-out ends and filling the gap between adjacent electrodes; and / or, before forming the second encapsulation layer, the manufacturing method of the semiconductor structure further includes: filling a filler between the second structure to be encapsulated and the first encapsulation layer to form a filling structure.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, forming the conductive portion in the through holes includes: filling the through holes with a flowing conductive material, and the conductive material forms the conductive portion after curing; the conductive material includes at least one of solder and silver paste.

4. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, the redistribution layer includes a plurality of first trace structures and second trace structures located on a side of each first trace structure away from the first encapsulation layer, and at least one of the second trace structures extends beyond the corresponding first trace structure to form a step structure; each through hole corresponds to a step structure, a positive projection of the through hole on a plane where a surface of the first encapsulation layer away from the redistribution layer is located entirely falls within a positive projection of the redistribution layer on the plane, and a positive projection of the through hole on the plane at least partially overlaps with a positive projection of a portion where the second trace structure extends beyond the first trace structure in the corresponding step structure on the plane.

5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, before forming a plurality of through holes on the first encapsulation layer, the first encapsulation layer encapsulates the function lead-out terminals; each of the through holes penetrates the first encapsulation layer, and at least one of the through holes exposes the redistribution layer and the function lead-out terminals at the same time; or, before forming a plurality of through holes on the first encapsulation layer, the first encapsulation layer encapsulates the function lead-out terminals; the manufacturing method of the semiconductor structure further includes: forming an opening on the first encapsulation layer on a side of the function lead-out terminals away from the redistribution layer, the opening exposing the function lead-out terminals; forming a conductive pillar in the opening; the conductive structure is electrically connected to the conductive pillar; or, the function lead-out terminals are flush with the surface of the first encapsulation layer away from the redistribution layer, and the through holes only expose the redistribution layer.

6. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the first structure to be encapsulated only includes the electrical components, the electrical components are passive devices, and the electrodes of the first structure to be encapsulated are the pins of the electrical components; the passive devices include at least one of an inductor, a resistor and a capacitor; or, the first structure to be encapsulated further includes an encapsulation layer encapsulating the electrical components and conductive pillars exposing the encapsulation layer, the conductive pillars are the electrodes of the first structure to be encapsulated, and the conductive pillars are electrically connected to the pins of the electrical components; the electrical components include at least one of an inductor, a resistor, a capacitor and a chip.

7. A semiconductor structure, characterized in that, the semiconductor structure includes: a first encapsulation structure including at least one first electrical component, the first encapsulation structure including at least two electrodes arranged at intervals; a first encapsulation layer encapsulating at least the side surface of the first encapsulation structure; the first encapsulation layer is provided with a plurality of through holes; a conductive part located in the through holes; a redistribution layer located on the first encapsulation layer and on a side of the first electrical component away from the electrical connection end of the electrode; the redistribution layer is electrically connected to the conductive part; a second encapsulation structure located on a side of the first encapsulation layer away from the redistribution layer, the second encapsulation structure including a chip and a conductive structure located on a side of the chip facing the first encapsulation layer and electrically connected to the circuit of the chip, the conductive structure being electrically connected to the conductive part and the function lead-out terminals respectively; a second encapsulation layer encapsulating at least the side surface of the second encapsulation structure.

8. The semiconductor structure according to claim 7, characterized in that, the semiconductor structure further includes an insulating layer located between the first encapsulation layer and the redistribution layer, the insulating layer covering a side of the first encapsulation structure away from the function lead-out terminals and filling the gap between adjacent electrodes; and / or, the semiconductor structure further includes a filling structure located between the second encapsulation structure and the first encapsulation layer.

9. The semiconductor structure according to claim 7, characterized in that, the material of the conductive part includes at least one of solder and silver paste; The redistribution layer includes a plurality of first trace structures and second trace structures located on a side of each of the first trace structures away from the first encapsulation layer, and at least one of the second trace structures extends beyond the corresponding first trace structure to form a stepped structure; Each of the vias corresponds to one of the stepped structures. A positive projection of the via on a plane where a surface of the first encapsulation layer away from the redistribution layer is located entirely falls within a positive projection of the redistribution layer on the plane, and the positive projection of the via on the plane at least partially overlaps with a positive projection on the plane of a portion of the second trace structure that extends beyond the first trace structure in the corresponding stepped structure.

10. The semiconductor structure according to claim 9, wherein, a positive projection on the plane of a portion of the edge of the via that is not in contact with the redistribution layer is located inside an edge of a positive projection on the plane of a portion of the second trace structure that extends beyond the first trace structure in the corresponding stepped structure; and / or, a thickness range of the first trace structure is 10 μm to 60 μm.

11. The semiconductor structure according to claim 7, wherein, the first encapsulation structure only includes the electrical component, the electrical component is a passive device, and an electrode of the first encapsulation structure is a lead of the electrical component; the passive device includes at least one of an inductor, a resistor, and a capacitor; or, the first encapsulation structure further includes an encapsulation layer encapsulating the electrical component and conductive posts exposing the encapsulation layer, the conductive structure is an electrode of the first encapsulation structure, and the conductive posts are electrically connected to leads of the electrical component; the electrical component includes at least one of an inductor, a resistor, a capacitor, and a chip.

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