Microelectronic assembly with pre-cut single edge features in glass core

Abstract

A microelectronic assembly having a pre-cut single edge feature in a glass core. Various techniques for mitigating crack formation and propagation in glass, and related apparatus and methods, are disclosed. The techniques are based on providing various edge features prior to singulating a glass panel into individual glass units. In one aspect, the edge feature may be an opening in an edge region of the glass core that extends from one of the faces of the glass core toward an opposite face of the glass core and includes a filler material, such as an insulator material, a polymer, or a conductive material. In another aspect, the edge feature may be an anchor including a first pad over one of the faces of the glass core, a second pad over an opposite face of the glass core, and a pin attached to and extending from the first pad into the glass core.

Description

BACKGROUND OF THE INVENTION

[0001] For the past several decades, the scaling of integrated circuit (IC) features has been the driving force behind the growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Shrinking to ever-smaller features enables an increased density of functional units to be realized on the limited real estate of a semiconductor chip. For example, reduced transistor size allows an increased number of memory or logic devices to be incorporated on a chip, thus contributing to the manufacture of products with increased capacity. However, the drive for ever-increasing capacity is not without problems. The need to optimize the fabrication and performance of each component (e.g., of each transistor) is becoming increasingly important.

[0002] In parallel with the optimization at the transistor level, the advanced IC packaging landscape is evolving rapidly to meet the performance expectations and requirements of the ever-shrinking transistor sizes. Nowadays, multiple IC dies are often coupled together in a multi-die IC package to integrate features or functionality and to facilitate connection to other components such as a package substrate. For example, an IC package can include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.

[0003] Integrating multiple dies in a single IC package has significant benefits, but it adds additional complexity due to placing materials with different material properties in close proximity to each other. When an IC package undergoes multiple processing steps involving various temperature and pressure loads, the individual materials within the package can behave differently from each other, resulting in out-of-plane deformation of the various layers, referred to as "package warpage". One way to address package warpage is to use a stiffer core to which the different IC chips are attached. Recently, glass cores have been developed as an alternative to organic resin-based cores (e.g., cores based on the use of Ajinomoto Build-up Film (ABF)). Glass is considered to be stiffer than organic resin-based materials and has several advantages such as excellent thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with advanced semiconductor properties. However, a major challenge in the widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and / or thermal stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments will be readily understood by reference to the following detailed description in conjunction with the accompanying drawings. For the sake of convenience in this description, like reference numerals designate like structural elements. In the figures of the accompanying drawings, the embodiments are illustrated by way of example and not by way of limitation.

[0005] Figure 1Is a schematic side cross-sectional view of an exemplary microelectronic component in accordance with some embodiments of the present disclosure.

[0006] Figure 2 Is a schematic side cross-sectional view of another exemplary microelectronic component in accordance with some embodiments of the present disclosure.

[0007] Figure 3 Illustrates a glass panel during dicing.

[0008] Figures 4A-4B Illustrates an approximate position of an edge feature in a glass core in accordance with some embodiments of the present disclosure.

[0009] Figures 5A-5D Provides a cross-sectional side view of a glass core in accordance with some embodiments of the present disclosure, the cross-sectional side view of the glass core illustrating a process including edge features in the form of continuous trenches.

[0010] Figure 6 Illustrates a glass panel in accordance with some embodiments of the present disclosure, the glass panel having edge features in the form of continuous trenches in an edge region of a glass cell.

[0011] Figures 7A-7D Provides a cross-sectional side view of a glass core in accordance with some embodiments of the present disclosure, the cross-sectional side view of the glass core illustrating different cross-sectional shapes of edge features in the form of continuous trenches.

[0012] Figure 8 Illustrates a glass panel in accordance with some embodiments of the present disclosure, the glass panel having edge features in the form of discontinuous openings in an edge region of a glass cell.

[0013] Figures 9A-9B Provides a top-down view of a glass core in accordance with some embodiments of the present disclosure, the top-down view of the glass core illustrating different examples of edge features in the form of offset discontinuous openings in multiple rows.

[0014] Figures 10A-10E Provides a top-down view of a glass core in accordance with some embodiments of the present disclosure, the top-down view of the glass core illustrating further examples of edge features in the form of discontinuous openings in multiple rows.

[0015] Figure 11 Illustrates a glass panel in accordance with some embodiments of the present disclosure, the glass panel having edge features in the form of discontinuous openings in an edge region of a glass cell and in an edge region of the glass panel.

[0016] Figures 12A-12CA cross-sectional side view of a glass core according to some embodiments of the present disclosure is provided, and the cross-sectional side view of the glass core illustrates different examples of edge features in the form of openings filled with a self-healing material.

[0017] Figures 13A-13B A top-down view of a glass core according to some embodiments of the present disclosure is provided, and the top-down view of the glass core illustrates different examples of edge features in the form of grooves filled with a self-healing material.

[0018] Figures 14A-14B A top-down view of a glass core according to some embodiments of the present disclosure is provided, and the top-down view of the glass core illustrates different examples of edge features in the form of discontinuous openings along a saw track.

[0019] Figures 15A-15B A top-down view of a glass core according to some embodiments of the present disclosure is provided, and the top-down view of the glass core illustrates different examples of edge features in the form of continuous and discontinuous anchors in an edge region.

[0020] Figures 16A-16D A cross-sectional side view of a portion of a glass core according to some embodiments of the present disclosure is provided, and the cross-sectional side view of the portion of the glass core illustrates different examples of edge features in the form of anchors in an edge region.

[0021] Figures 17A-17B A top-down view of a glass core according to some embodiments of the present disclosure is provided, and the top-down view of the glass core illustrates different examples of edge features in the form of continuous and discontinuous anchors extending through a build-up layer.

[0022] Figures 18A-18D A cross-sectional side view of a portion of a glass core according to some embodiments of the present disclosure is provided, and the cross-sectional side view of the portion of the glass core illustrates different examples of edge features in the form of anchors extending through a build-up layer.

[0023] Figures 19A-19B A top-down view of a glass panel according to some embodiments of the present disclosure is provided, and the top-down view of the glass panel illustrates different examples of edge features in the form of daisy chain links.

[0024] Figures 20A-20C A cross-sectional side view of a portion of a glass core according to some embodiments of the present disclosure is provided, and the cross-sectional side view of the portion of the glass core illustrates different examples of cross-sectional profiles of daisy chain links.

[0025] Figures 21A-21BA top-down view and a cross-sectional side view of a glass core according to some embodiments of the present disclosure are provided, and the top-down view and the cross-sectional side view of the glass core illustrate a first example of an edge feature in the form of an edge clamp.

[0026] Figures 22A-22B A top-down view and a cross-sectional side view of a glass core according to some embodiments of the present disclosure are provided, and the top-down view and the cross-sectional side view of the glass core illustrate a second example of an edge feature in the form of an edge clamp.

[0027] Figure 23 A top view of a wafer and a die according to some embodiments of the present disclosure, where the wafer and the die may be included in a microelectronic component having a glass core according to any one of the embodiments disclosed herein.

[0028] Figure 24 A side cross-sectional view of an IC device according to some embodiments of the present disclosure, where the IC device may be included in a microelectronic component having a glass core according to any one of the embodiments disclosed herein.

[0029] Figure 25 A side cross-sectional view of an IC device assembly according to some embodiments of the present disclosure, where the IC device assembly may include a glass core according to any one of the embodiments disclosed herein.

[0030] Figure 26 A block diagram of an exemplary communication device according to some embodiments of the present disclosure, where the exemplary communication device may include a microelectronic component having a glass core according to any one of the embodiments disclosed herein. Detailed Description

[0031] As mentioned above, a major challenge in the widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and / or thermal stress. One source of mechanical and thermal stress in glass is the singulation process (sometimes referred to as "scribe cut" or "dicing") that occurs during the manufacture of the glass core. Singulation is the process in which a cutting tool (e.g., a glass cutter, diamond blade, or saw) applies a mechanical force to the surface of a glass panel in order to separate (e.g., scribe cut or dice) the panel into individual glass units having a smaller form factor compared to the panel. The mechanical force applied by the cutting tool can create localized stress concentrations (e.g., regions of higher stress) at or near the surface where the cutting tool contacts the glass, such as at or near the edge of an individual glass unit, where the term "edge" as used herein refers to the sidewalls / sides between the top and bottom surfaces of a glass unit, glass core, or glass panel. Because glass is a brittle material characterized by its lack of ductility (e.g., characterized by its limited ability to undergo significant plastic deformation prior to fracture), localized stress concentrations often result in the formation of cracks at the edges of singulated glass units. In addition to applying mechanical stress to the glass, singulation can also generate thermal stress due to friction between the cutting tool and the glass, thereby heating the cut surface. The heat can cause localized expansion and contraction of the glass, further promoting crack formation and propagation.

[0032] Singulation is not the only source of stress and damage that can affect a glass core. The presence of materials having different CTEs (e.g., metals of conductive paths and / or dielectric materials of build-up layers) on the top and / or bottom of the glass core adds stress in the glass (such stress is referred to as "CTE mismatch-induced stress"), further exacerbating the problem of crack formation. Even if cracks do not form immediately during singulation, cutting a brittle material such as glass often results in individual glass units having rough, jagged, or otherwise non-uniform edges. During the repeated thermal cycling during the operation of a microelectronic component that includes a glass core having such edges, the glass surface can be gradually weakened due to CTE mismatch-induced stress, resulting in the formation of cracks at that time. Furthermore, even before singulation, the glass may have minute surface flaws or defects that can act as initial points for crack formation, where additional mechanical and / or thermal stress increases the severity of crack growth.

[0033] Once cracks begin to form, they tend to propagate through the glass where additional mechanical and / or thermal stresses increase the severity of crack propagation. In particular, stress concentrations at the edges of the glass unit encourage cracks to further extend into the glass, and the inherent brittleness of the glass makes it particularly vulnerable to crack propagation. Crack propagation may even cause the glass volume to divide into two halves about a plane parallel to the top / bottom surfaces of the glass volume and approximately in the middle of the glass volume, with one half being the lower half and the other half being the upper half which is considered a single structure.

[0034] As described previously, crack formation and propagation in glass compromise the structural integrity of the glass, making microelectronic components with a glass core particularly prone to failure over time. Embodiments of the present disclosure relate to various techniques, as well as related devices and methods, for mitigating (e.g., alleviating or reducing) crack formation and propagation in glass. In particular, embodiments of the present disclosure are based on providing various edge features prior to singulating a glass panel into individual glass units. Thus, these edge features may be referred to as "pre-singulation" edge features, but for brevity, they are simply referred to herein as "edge features". The individual glass units may be used as the glass core of a microelectronic component, and the edge features may help to alleviate or reduce crack formation and / or propagation in the glass core. As used herein, "edge features" refer to any features located in a region at or near the edge of the glass core (e.g., the glass unit after singulation). The region at or near the edge of the glass core is referred to herein as the "edge region" and is understood to extend from the edge into the glass core a distance less than approximately 10% of the width of the glass core (e.g., less than approximately 7% or less than approximately 5%). In one aspect of the present disclosure, the edge feature may be an opening in the edge region of the glass core, the opening extending from one of the faces of the glass core toward the opposite face of the glass core and including a filling material such as an insulator material, a polymer, a conductive material, or ABF. In another aspect, the edge feature may be an anchor, which includes a first pad above one of the faces of the glass core, a second pad above the opposite face of the glass core, and a pin, wherein the pin is attached to the first pad and extends from the first pad into the glass core. In yet another aspect, the edge feature may be a daisy chain structure embedded in the glass core near the edge of the glass core, the daisy chain structure having a first portion in a recess in one of the faces of the glass core and a second portion in a recess in the opposite face of the glass core. In still another aspect, the edge feature may be a clamp structure surrounding the edge, the clamp structure having a first portion at one of the faces of the glass core, a second portion at the opposite face, and a third portion that warps around the edge, wherein the third portion is attached to the first portion and the second portion.

[0035] Among other things, integrating layers of different materials (e.g., multiple dies, redistribution layers, package substrates) in a single IC package or microelectronic component is challenging due to, among other things, package warpage. Providing a glass core with one or more edge features as described herein for an IC package or microelectronic component can help. Relative to conventional methods, various embodiments in the embodiments disclosed herein can help achieve reliable integration of multiple layers of different materials within a single microelectronic component at lower cost and / or with greater design flexibility. Relative to microelectronic components without a glass core, various microelectronic components in the microelectronic components disclosed herein can exhibit reduced warpage. The microelectronic components disclosed herein can be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).

[0036] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The same reference numerals always designate the same components, and embodiments are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense.

[0037] Any one of the features discussed with reference to any one of the accompanying drawings herein can be combined with any other feature to form, as appropriate, a microelectronic component 100, a glass core 110, an IC device 1600, an IC device assembly 1700, or a communication device 1800. For convenience, the expression "die 114" can be used to refer to a collection of dies 114-1, 114-2, etc. A collection of drawings labeled with different letters may be referred to without the letters, e.g., Figures 5A-5D the collection of can be referred to as "FIG. 5", Figures 7A-7D the collection of can be referred to as "FIG. 7", and so on. Multiple elements with the same reference numeral in the drawings can be shared between different drawings; for ease of discussion, the description of these elements provided with respect to one of the drawings is not repeated for the other drawings, and these elements can take the form of any one of the embodiments disclosed herein. To avoid cluttering the drawings, if multiple instances of a particular element are illustrated, only some of the elements may be labeled with reference numerals (e.g., Figure 1 multiple conductive contacts 122 are shown in, but only one of them is labeled with a reference numeral). Also to avoid cluttering the drawings, not all reference numerals shown in one of the drawings are shown in other similar drawings.

[0038] The accompanying drawings are not necessarily to scale. Although many of the drawings illustrate linear structures with flat walls and right-angled corners, this is merely for ease of illustration and may not reflect real-life processing limitations that can cause various features to appear less "ideal" when using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images to examine any of the structures described herein. In such images of real structures, possible processing defects may also be visible, e.g., imperfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners, or thickness variations of different material layers. There may be other defects not listed herein but common in the field of semiconductor device fabrication and packaging. Examining the layout and mask data using, for example, optical microscopes, TEM, or SEM and reverse-engineering portions of the device to reconstruct the circuit, and / or examining cross-sections of the device using, for example, physical failure analysis (PFA) to detect the shape and location of the various device elements described herein will allow determination of the presence of a glass core having one or more edge features as described herein.

[0039] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase "between X and Y" represents a range that includes X and Y. When used to describe the position of an element, the phrase "between X and Y" represents the region that is spatially between element X and element Y. Based on the context of a particular value described herein or known in the art, the terms "substantially", "close to", "approximate", "near", and "about" generally refer to within + / - 20%, e.g., within + / - 5% or within + / - 2%. Similarly, terms indicating the orientation of various elements, such as "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between elements, generally refer to within + / - 10% of the exact orientation, e.g., within + / - 5% or within + / - 2%.

[0040] The description uses the phrases "in one embodiment" or "in embodiments", each of which may refer to one or more of the same or different embodiments. Further, the terms "comprising", "including", "having", and the like as used with respect to the embodiments of this disclosure are synonymous. As used herein, the terms "package" and "IC package" are synonymous, and the terms "die" and "IC die" are also synonymous. Further, the terms "chip", "dielet", "die", and "IC die" may be used interchangeably herein.

[0041] Although a particular element may be referred to herein in the singular, such an element may include a plurality of sub-elements. For example, a "dielectric material" may include one or more dielectric materials, or an "insulating material" may include one or more insulating materials. The terms "oxide", "carbide", "nitride", etc. refer to compounds that contain oxygen, carbon, nitrogen, etc., respectively. The term "high-k dielectric" refers to a material having a dielectric constant higher than that of silicon oxide, while the term "low-k dielectric" refers to a material having a dielectric constant lower than that of silicon oxide. Unless otherwise specified, the term "insulated" and its variants (e.g., "insulation" or "insulator") mean "electrically insulated", and the term "conductive" and its variants (e.g., "conductivity" or "conductor") mean "electrically conductive". In the case of optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conductive" may also mean "optically conductive". The term "insulating material" refers to a solid material that is substantially non-conductive (and / or a liquid material that cures after processing as described herein). By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glass, silicon, and alumina or combinations thereof. They may include dielectric materials, high polarizability materials, and / or piezoelectric materials. Without departing from the scope of the present disclosure, they may be transparent or opaque. Further examples of insulating materials are underfill and molding or molding-like materials used in encapsulation applications, including, for example, materials used in organic interlayers, encapsulation supports, and other such components.

[0042] Figure 1FIG. 0 is a schematic side cross-sectional view of an example microelectronic component 100 in accordance with some embodiments of the present disclosure, in which a glass core having one or more edge features as described herein may be implemented. The microelectronic component 100 may include a substrate 107 having a bilateral bridge die 114-1 in a cavity 119 of the substrate 107, and the die 114-1 may be electrically coupled to a conductive path, such as a conductive trace 108A or a conductive via 108B, in a metal layer N-1 of the substrate 107 below the bottom of the cavity 119. The substrate 107 may include a dielectric material 112 (e.g., as shown, a first dielectric material layer 112A and a second dielectric material layer 112B, together referred to as "one or more dielectric material layers 112") and a conductive material 108 disposed in the one or more dielectric material layers 112 to provide a conductive path (e.g., conductive trace 108A and conductive via 108B) through the substrate 107, as well as to provide conductive pads and contacts. The substrate 107 may include a first surface 120-1 and an opposite second surface 120-2. The die 114-1 may be surrounded by the dielectric material 112 of the substrate 107. The die 114-1 may include a bottom surface (e.g., a surface facing the first surface 120-1) having a first conductive contact 122, an opposite top surface (e.g., a surface facing the second surface 120-2) having a second conductive contact 124, and a through-silicon via (TSV) 125 coupling the respective first and second conductive contacts 122, 124. In some embodiments, the pitch of the first conductive contacts 122 on the first die 114-1 may be between 25 micrometers and 250 micrometers. As used herein, pitch is measured center-to-center (e.g., from the center of a conductive contact to the center of an adjacent conductive contact). In some embodiments, the pitch of the second conductive contacts 124 on the first die 114-1 may be between 25 micrometers and 100 micrometers. The dies 114-2, 114-3 may include a set of conductive contacts 122 on a die bottom surface (e.g., a surface facing the first surface 120-1). The die 114 may include other conductive paths (e.g., including lines and vias) and / or to other circuits (not shown) coupled to respective conductive contacts (e.g., conductive contacts 122, 124) on the surface of the die 114. As used herein, the terms "die," "microelectronic component," and similar variants may be used interchangeably. As used herein, the terms "interconnect component," "bridge die," and similar variants may be used interchangeably. The bridge die 114-1 may be electrically coupled to the dies 114-2, 114-3 through a die-to-die (DTD) interconnect 130 at the second surface 120-2. In particular, the conductive contacts 124 on the top surface of the die 114-1 may be coupled to the conductive contacts 122 on the bottom surfaces of the dies 114-2, 114-3 through conductive vias 108B that pass through the second dielectric material layer 112B.

[0043] As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an electrical interface (e.g., part of a conductive interconnect) between different components; the conductive contact may be recessed from, flush with, or extend from the surface of the component (e.g., having a columnar shape), and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive wire or via). In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, the term "interconnect" includes both electrical and optical interconnects. The nature of the described interconnects is to be understood herein with reference to the signal medium associated therewith. Thus, when used in reference to an electronic device (such as an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to and / or between one or more elements associated with the IC. In such cases, the term "interconnect" may refer to conductive traces (sometimes also referred to as "metal traces", "lines", "metal lines", "wires", "metal wires", "trenches" or "metal trenches") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "metal traces" and "metal vias" respectively, to highlight the fact that these elements include a conductive material such as metal. Similarly, when used in reference to a device such as a photonic IC (PIC) that also operates on optical signals, "interconnect" may also describe any element formed of an optically conductive material for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, splitters, combiners, couplers, and optical vias.

[0044] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and a plurality of conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photoimageable dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 114 may include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the die 114 may include conductive traces and / or conductive vias and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on the same surface or different surfaces of the die 114). Example structures that may be included in the die 114 disclosed herein are discussed below with reference to the IC device 1600. The conductive paths in the die 114 may be delimited by a liner material such as an adhesion liner and / or a barrier liner, as appropriate. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, fan-out or fan-in packaged die, or a die stack (e.g., a wafer stack, a die stack, or a multi-layer die stack).

[0045] In some embodiments, the die 114 may include conductive paths to route power, ground, and / or signals to / from other dies 114 included in the microelectronic component 100. For example, the die 114-1 may include a TSV 125 that includes a conductive via (such as a metal via) isolated from the surrounding silicon or other semiconductor material by a barrier oxide, or through which power, ground, and / or signals may be routed between the package substrate 102 and one or more dies 114 on the "top" of the die 114-1 (e.g., in Figure 1In an embodiment, other conductive paths are transmitted between die 114-2 and / or 114-3. In some embodiments, die 114-1 may not route power and / or ground to die 114-2 and 114-3; instead, die 114-2, 114-3 may be directly coupled to the power line and / or ground line in package substrate 102 through substrate to package substrate (STPS) interconnect 150, the conductive path provided by conductive material 108 in substrate 107, and die to substrate (DTS) interconnect 140. In some embodiments, die 114-1 may be thicker than die 114-2, 114-3. In some embodiments, die 114-1 may be a memory device or a high-frequency serializer and deserializer (SerDes), such as a fast peripheral component interconnect (PCI). In some embodiments, die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, die 1142 and / or die 114-3 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, die 114 may be as described below with reference to Figure 23 die 1502 of

[0046] The dielectric material 112 of substrate 107 may be formed in layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material, such as an organic stack film. In some embodiments, for example, the dielectric material 112 may include ceramics, an epoxy resin film with filler particles therein, glass, an inorganic material, or a combination of organic and inorganic materials. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, substrate 107 may include layers of dielectric material 112 / conductive material 108, where the wire / trace / pad / contact (e.g., conductive trace 108A) of the conductive material 108 in one layer is electrically coupled to the wire / trace / pad / contact (e.g., conductive trace 108A) of the conductive material 108 in an adjacent layer through a via (e.g., 108B) of the conductive material 108 extending through the dielectric material 112. The conductive trace 108A may be referred to herein as a "wire", "conductive element", "conductive pad", or "conductive contact". For example, substrate 107 including such layers may be formed using printed circuit board (PCB) manufacturing techniques.

[0047] An individual dielectric material layer 112 (e.g., the first dielectric material layer 112A) may include a cavity 119, and the via die 114-1 may be at least partially nested within the cavity 119. The via die 114-1 may be surrounded (e.g., embedded) by the next individual dielectric material layer 112 (e.g., the second dielectric material layer 112B). In some embodiments, the cavity 119 is tapered and narrows towards the bottom surface of the cavity 119 (e.g., towards the surface of the first surface 120-1 of the substrate 107). The cavity 119 may be indicated by a seam between the dielectric material 112A and the dielectric material 112B. As Figure 1 shown, in the case where the via die 114-1 is partially nested within the cavity 119, the top surface of the via die 114-1 may extend above the top surface of the dielectric material 112A. In the case where the via die 114-1 is fully nested within the cavity 119 (not shown), the top surface of the via die 114-1 may be coplanar with or lower than the top surface of the dielectric material 112A.

[0048] The substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to 1. In Figure 1 it, the layers are marked in descending order from the second surface 120-2 (e.g., the top surface) of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). In particular, as Figure 1 shown, the substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layer may include a conductive contact 121 at the second surface 120-2 of the substrate 107, which is coupled to a conductive contact 122 at the bottom surface of the dies 114-2, 114-3 through the DTS interconnect 140. The N-2 metal layer may include a conductive trace 108A having a top surface (e.g., the surface facing the second surface 120-2 of the substrate 107), an opposite bottom surface (e.g., the surface facing the first surface 120-1 of the substrate 107), and a lateral surface extending between the top and bottom surfaces of the conductive trace 108A. The substrate 107 may further include an N-1 metal layer above the N-2 metal layer and below the N metal layer, where a portion of the N-1 metal layer includes a metal ring 118 exposed at the perimeter of the bottom of the cavity 119. As shown, the metal ring 118 may be coplanar with the conductive trace 108A of the N-1 metal layer and may be close to the edge of the cavity 119.

[0049] Although specific numbers and arrangements of dielectric material 112 / conductive material 108 layers are shown in the various figures in the accompanying drawings, these specific numbers and arrangements are merely illustrative, and any desired number and arrangement of dielectric material 112 / conductive material 108 may be used. Further, although a specific number of layers (e.g., four layers) are shown in substrate 107, these layers may only represent a portion of substrate 107, e.g., there may be further layers (e.g., layers N-4, N-5, N-6, etc.).

[0050] As Figure 1 shown, substrate 107 may further include a glass core 110 having through-glass vias (TGVs) 115, and further layers 111 may be present under the glass core 110 and coupled to the package substrate 102 via interconnects 150. As used herein, the term "glass core" refers to a layer (e.g., a glass layer) or structure (e.g., a portion of a glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, borofloat glass, lead borate glass, photosensitive glass, non-photosensitive glass, or glass-ceramic. In particular, the glass core 110 may be a bulk glass or a solid volume / glass layer, as opposed to a material that may include glass particles, such as a glass fiber-reinforced polymer (e.g., a substrate / plate composed of glass fibers and an epoxy binder). Such glass materials are typically non-crystalline and often transparent amorphous solids. In some embodiments, the glass core 110 may be an amorphous solid glass layer. In some embodiments, the glass core 110 may include a material containing silicon and oxygen and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 110 may include a material, such as any of the materials described above, wherein the weight percentage of silicon is at least about 0.5%, e.g., between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the glass core 110 is fused quartz, the weight percentage of silicon may be about 47%. In some embodiments, the glass core 110 may include a material having at least 23% silicon and / or at least 26% oxygen by weight, and in some further embodiments, the glass core 110 may further include at least 5% aluminum by weight. In some embodiments, the glass core 110 may include any of the materials described above and may further include one or more additives, such as Al 2 O 3 、B 2 O 3 、MgO, CaO, SrO, BaO, SnO 2 、Na2 O, K 2 O, SrO, P 2 O 3 , ZrO 2 , Li 2 O, Ti, and Zn. In some embodiments, the glass core 110 may be a glass layer that does not include an organic binder or organic material. The glass core 110 may be distinguishable from, for example, a "prepreg" or "RF4" core of a PCB substrate, which typically includes glass fibers embedded in a resin organic material such as epoxy resin. In such a conventional core / substrate including glass fibers and epoxy resin, the diameter of the glass fibers is generally in the range of 5 microns to 200 microns. In contrast, the glass core 110 may be a glass layer that is approximately 10 millimeters on one side to approximately 250 millimeters on one side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some embodiments, Figure 1 the cross-section of the glass core 110 in the x-z plane, y-z plane, and / or x-y plane of the exemplary coordinate system 105 shown in may be substantially rectangular (the axes shown in subsequent figures refer to the axes of the coordinate system 105). In such an embodiment, in a top-down view of the glass core 110 (e.g., the x-y plane of the coordinate system 105), the glass core 110 may have a first length in the range of 10 millimeters to 250 millimeters, and a second length in the range of 10 millimeters to 250 millimeters, the first length being perpendicular to the second length. The thickness of the glass core 110 (e.g., the dimension measured along the z-axis of the coordinate system 105) may be in the range of approximately 50 microns to 1.4 millimeters. In some embodiments, the glass core 110 may be a glass core substrate, where the thickness of the glass core substrate is in the range of approximately 50 microns to 1.4 millimeters. In some embodiments, the glass core 110 may be a glass layer including a rectangular prism volume. In some such embodiments, the rectangular prism volume may have a first side and a second side perpendicular to the first side, the length of the first side being in the range of 10 millimeters to 250 millimeters, and the length of the second side being in the range of 10 millimeters to 250 millimeters. In some embodiments, the glass core 110 may be a rectangular prism volume having segments (e.g., vias) removed and filled with other materials (e.g., metal), such as, for example, TGV 115. In some embodiments, the glass core 110 may be a glass layer having a thickness in the range of 50 microns to 1.4 millimeters, a first length in the range of 10 millimeters to 250 millimeters, and a second length in the range of 10 millimeters to 250 millimeters, the first length being perpendicular to the second length.

[0051] In some implementations, the substrate 107 including the glass core 110 and the die 114 may be collectively referred to as the "multi-layer die subassembly 104". The glass core 110 may provide mechanical stability to the multi-layer die subassembly 104, the substrate 107, and / or the microelectronic assembly 100. The glass core 110 may reduce warping and may provide a more robust surface for the multi-layer die subassembly 104 to be attached to the package substrate 102 or other substrates (e.g., an interposer or a circuit board).

[0052] In some implementations, the dielectric material 112 of the substrate 107 and the glass core 110 together may be referred to as a "multi-layer glass substrate". In some such embodiments, the multi-layer glass substrate may be a coreless substrate. In some such embodiments, the glass core 110 may be a glass layer having a thickness in the range of about 25 micrometers to 50 micrometers. In some embodiments, the further layer 111 may also be part of the multi-layer glass substrate.

[0053] The TGV 115 may be a through-hole extending between a first side and a second side of the glass core 110 (e.g., between the bottom surface and the top surface of the glass core 110), the through-hole including any suitable conductive material, such as a metal, such as for example copper, silver, nickel, gold, aluminum, or other metal or alloy. The TGV 115 may be formed using any suitable process, including for example direct laser drilling or laser-induced deep etching processes. In some embodiments, the TGV 115 disclosed herein may have a pitch between 50 micrometers and 500 micrometers, e.g., as measured from the center of one TGV 115 to the center of an adjacent TGV 115. The TGV 115 may have any suitable size and shape. In some embodiments, the TGV 115 may have a circular, rectangular, or other shaped cross-section. In some embodiments, at least some of the TGV 115s may have an hourglass shape, e.g., as Figure 2 shown therein. In some embodiments, at least some of the TGV 115s may taper from one face of the glass core 110 to another face, e.g., from the top surface of the glass core 110 to the bottom surface of the glass core 110.

[0054] The substrate 107 (e.g., a further layer 111) can be coupled to the package substrate 102 via the STPS interconnect 150. In particular, the top surface of the package substrate 102 can include a collection of conductive contacts 146. The conductive contacts 144 on the bottom surface of the substrate 107 can be electrically and mechanically coupled to the conductive contacts 146 on the top surface of the package substrate 102 via the STPS interconnect 150. The package substrate 102 can include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths to route power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias as shown). In some embodiments, the insulating material of the package substrate 102 can be a dielectric material such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with inorganic fillers, or a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and organic polymer dielectric). In particular, when the package substrate 102 is formed using standard PCB processing, the package substrate 102 can include FR-4, and the conductive paths in the package substrate 102 can be formed by patterned copper sheets separated by stacked layers of FR-4. Optionally, the conductive paths in the package substrate 102 can be delimited by liner materials such as adhesive liners and / or barrier liners. In some embodiments, the package substrate 102 can be formed using a via encapsulation process defined by lithography. In some embodiments, the package substrate 102 can be manufactured using standard organic package manufacturing processes, and thus the package substrate 102 can take the form of an organic package. In some embodiments, the package substrate 102 can be a collection of redistribution layers formed on a panel carrier by laminating or spin-coating a dielectric material, and conductive vias and lines are created by laser drilling and electroplating. In some embodiments, the package substrate 102 can be formed on a removable carrier using any suitable technique such as redistribution layer technology. Any method known in the art for manufacturing the package substrate 102 can be used, and such methods will not be discussed further in detail herein for the sake of brevity.

[0055] In some embodiments, the encapsulation substrate 102 may be a lower density medium, and the die 114 may be a higher density medium or have regions with a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower density medium are larger and / or have a larger pitch compared to the conductive paths in the higher density medium. In some embodiments, the higher density medium may be fabricated using a modified semi-additive process or a semi-additive build-up process utilizing advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processing), while the lower density medium may be a printed circuit board (PCB) fabricated using standard PCB processing (e.g., a standard subtractive process using an etching chemistry to remove unwanted copper regions and having rough vertical interconnect features formed by standard laser processing). In other embodiments, semiconductor manufacturing processes may be used to fabricate the higher density medium, such as single damascene or dual damascene processes. In some embodiments, additional dies may be disposed on the top surfaces of dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surfaces of dies 114-2, 114-3. Additional passive components, such as surface mount resistors, capacitors, and / or inductors, may be disposed on the top or bottom surface of the encapsulation substrate 102 or embedded within the encapsulation substrate 102.

[0056] Figure 1The microelectronic component 100 may further include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102 around the associated STPS interconnect 150. In some embodiments, the underfill material 127 may extend between the top surfaces of the substrate 107 around different dies in the top dies 114-2, 114-3 and the associated DTS interconnects 140, and between the top dies 114-2, 114-3 around the bridge die 114-1 and the DTD interconnect 130. The underfill material 127 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 may include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that, when forming the STPS interconnect 150, helps solder the multi-die subassembly 104 to the package substrate 102 and then polymerizes and encapsulates the STPS interconnect 150. The underfill material 127 may be selected to have a CTE that may relieve or minimize the stress between the substrate 107 and the package substrate 102 resulting from non-uniform thermal expansion in the microelectronic component 100. In some embodiments, the CTE of the underfill material 127 may have a value intermediate between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the die 114 and / or dielectric material 112 of the substrate 107.

[0057] The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, the set of STPS interconnects 150 may include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form the STPS interconnects 150), e.g., as Figure 1 shown, the STPS interconnect 150 may include solder between a conductive contact 144 on the bottom surface of the substrate 107 and a conductive contact 146 on the top surface of the package substrate 102. In some embodiments, the set of STPS interconnects 150 may include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive adhesives. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material.

[0058] The DTD interconnects 130 disclosed herein can take any suitable form. In a microelectronic component, the DTD interconnects 130 can have a finer pitch than the STPS interconnects 150. In some embodiments, the die 114 on either side of the set of DTD interconnects 130 can be an unpackaged die, and / or the DTD interconnects 130 can include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have a pitch that is too fine to be directly coupled to the package substrate 102 (e.g., too fine to be used as DTS interconnects 140 or STPS interconnects 150). In some embodiments, the set of DTD interconnects 130 can include solder. In some embodiments, the set of DTD interconnects 130 can include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 can be used as data transfer channels, while the STPS interconnects 150 can be used for, among other things, power and ground lines, etc. In some embodiments, some or all of the DTD interconnects 130 in the microelectronic component 100 can be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or electroplated interconnects). In such embodiments, the DTD interconnects 130 can be bonded together (e.g., at elevated pressure and / or temperature) without using an intermediate solder or anisotropic conductive material. Any conductive contact disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) can include, for example, a bonding pad, a solder bump, a conductive post, or any other suitable conductive contact. In some embodiments, some or all of the DTD interconnects 130 and / or DTS interconnects 140 in the microelectronic component 100 can be solder interconnects that include solder having a higher melting point compared to some or all of the solder included in the STPS interconnects 150. For example, when the DTD interconnects 130 and DTS interconnects 140 in the microelectronic component 100 are formed before the STPS interconnects 150 are formed, the solder-based DTD interconnects 130 and DTS interconnects 140 can use a higher temperature solder (e.g., having a melting point above 200 degrees Celsius), while the STPS interconnects 150 can use a lower temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the higher temperature solder can include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder can include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, the lower temperature solder can include indium, indium and tin, or gallium.

[0059] In the microelectronic component 100 disclosed herein, some or all of the DTS interconnects 140 and STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. Due to greater material similarity between the different dies 114 on either side of the set of DTD interconnects 130 than between the substrate 107 and the top dies 114-2, 114-3 on either side of the set of DTS interconnects 140 and between the substrate 107 and the package substrate 102 on either side of the set of STPS interconnects 150, the DTD interconnects 130 may have a smaller pitch than the STPS interconnects 150. In particular, due to the heat generated during operation (and the heat applied during various manufacturing operations), differences in the material composition of the substrate 107 and the die 114 or the package substrate 102 may cause different expansion and contraction. To mitigate damage (e.g., cracking, solder bridging, etc.) caused by this different expansion and contraction, the DTS interconnects 140 and STPS interconnects 150 may be formed larger and farther apart than the DTD interconnects 130, and due to the greater material similarity of the pairs of dies 114 on either side of the DTD interconnects, the DTD interconnects 130 may be subject to less thermal stress. In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 1000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 25 microns and 100 microns.

[0060] Figure 1 The microelectronic component 100 may further include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board by a second-level interconnect at the bottom surface of the package substrate 102. The second-level interconnect may be any suitable second-level interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. For example, the circuit board may be a motherboard and may have other components attached thereto. As is known in the art, the circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the second-level interconnect may not couple the package substrate 102 to the circuit board, but instead may couple the package substrate 102 to another IC package, an interposer, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to the package substrate 102, but instead may be coupled to a circuit board, such as a PCB.

[0061] Although Figure 1depicts a microelectronic component 100 having a substrate with a particular number of die 114 and conductive paths provided by conductive material 108 coupled to the other die 114, but this number and arrangement are merely illustrative and the microelectronic component 100 may include any desired number and arrangement of die 114. Although Figure 1 die 114-1 is shown as a bilateral die and die 114-2, 114-3 are shown as unilateral die, die 114-2, 114-3 may be bilateral die and die 114 may be single-pitch die or mixed-pitch die. In some embodiments, additional components may be provided on the top surface of die 114-2 and / or 114-3. In this context, a bilateral die refers to a die having connections on both of these surfaces. In some embodiments, a bilateral die may include connections formed on both surfaces via TSVs. The active surface of a bilateral die - which is the surface that contains one or more active devices and most of the interconnections - may face either direction depending on design and electrical requirements.

[0062] Figure 1 many elements of the microelectronic component 100 are included in other accompanying figures in the accompanying drawings; when discussing these figures, the discussion of these elements is not repeated and any of these elements may take any form disclosed herein. Further, various elements are Figure 1 illustrated as being included in the microelectronic component 100, but in various embodiments, some of these elements may not be included. For example, in various embodiments, further layer 111, underfill material 127, and package substrate 102 may not be present in the microelectronic component 100. In some embodiments, individual microelectronic components in the microelectronic component 100 disclosed herein may be used as a system-in-package (SiP) that includes multiple die 114 having different functionality. In such an embodiment, the microelectronic component 100 may be referred to as a SiP.

[0063] Figure 2 is a schematic cross-sectional view of another example microelectronic component 100 according to some embodiments of the present disclosure. Except for the differences further described, the configuration of the embodiment shown in the figure is similar to Figure 1 the configuration of. Instead of including a glass core 110 as part of the substrate 107 as shown in Figure 1 , Figure 2 the microelectronic component 100 of Figure 2In this case, the multi-layer die sub-assembly 104 includes the glass core 110 and multiple dies 114 as described above. The multi-layer die sub-assembly 104 may have a first surface 160-1 (e.g., bottom surface) and an opposite second surface 160-2 (e.g., top surface). The glass core 110 may provide mechanical stability to the Figure 2 multi-layer die sub-assembly 104 and / or the microelectronic assembly 100, reduce warping, and provide a more robust surface for attaching the multi-layer die sub-assembly 104 to the package substrate 102 or other substrates (e.g., an interposer or a circuit board).

[0064] The glass core 110 may include a cavity 129 having an opening facing the second surface 160-2, and the die 114-1 may be fully or at least partially nested in the cavity 129. As Figure 2 shown, in the case where the die 114-1 is fully nested in the cavity 129, the top surface of the die 114-1 may be coplanar with or lower than the top surface of the glass core 110. In the case where the die 114-1 is partially nested in the cavity 129, the top surface of the die 114-1 may extend above the top surface of the glass core 110. As described above, the cavity 129 may be at least partially filled with a dielectric material 112A or 112B. The die 114-1 may be attached to the bottom surface of the cavity 129 through a die attach film (DAF) 132. The DAF 132 may be any suitable material, including a non-conductive adhesive, a die attach film, a B-stage underfill material, or a polymer film having adhesive properties. The DAF 132 may have any suitable size. For example, in some embodiments, the DAF 132 may have a thickness (e.g., height or z-height) between 5 microns and 10 microns.

[0065] Die 114-1 can be coupled to dies 114-2, 114-3 in a layer above die 114-1 via DTD interconnects 130. The DTD interconnects 130 can be disposed between some of the conductive contacts 122 at the bottom of dies 114-2, 114-3 and some of the conductive contacts 124 at the top of die 114-1. Some other conductive contacts 122 at the bottom of die 114-2 and / or 114-3 can further couple one or more of dies 114-2, 114-3 to glass core 110 via glass core to die (GCTD) interconnects 142. The GCTD interconnects 142 can be disposed between some of the conductive contacts 122 at the bottom of dies 114-2, 114-3 and some of the conductive contacts 128 at the top of glass core 110. As described above, the GCTD interconnects 142 can be similar to the DTS interconnects 140. In some embodiments, the underfill material 127 can extend between different dies 114 in die 114 around the associated DTD interconnects 130 and / or GCTD interconnects 142. In some embodiments, die 114-2 and / or die 114-3 can be embedded in an insulating material 133. In some embodiments, the overall thickness (e.g., z-height) of the insulating material 133 can be between 200 microns and 800 microns (e.g., substantially equal to the thickness of die 114-2 or 114-3 and the underfill material 127). In some embodiments, the insulating material 133 can form multiple layers (e.g., dielectric materials formed in multiple layers as known in the art), and one or more dies 114 can be embedded in one layer. In some embodiments, the insulating material 133 can be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, or a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and organic polymer dielectric). In some embodiments, the insulating material 133 can be a molding material, such as an organic polymer having inorganic silica particles).

[0066] As Figure 2 shown, the glass core 110 can further include conductive contacts 126 at the bottom of the glass core 110, and the TGV 115 can extend between the conductive contacts 126 at the bottom of the glass core 110 and the conductive contacts 128 at the top of the glass core 110 and be electrically coupled to the conductive contacts 126 and conductive contacts 128. The conductive contacts 126, 128 can be similar to other conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146), and can include, for example, bonding pads, solder bumps, conductive pillars, or any other suitable conductive contacts. As Figure 2As shown, in some embodiments, at least some of the TGVs 115 may have an hourglass shape. For example, at least some of the TGVs 115 may have a first width at a first side of the glass core 110 (e.g., at the bottom surface of the glass core 110), a second width at a second side of the glass core 110 (e.g., at the top surface of the glass core 110), and a third width between the first and second sides of the glass core 110, where the third width is less than the first width and the second width.

[0067] Die 114-2, 114-3 may be electrically coupled to the package substrate 102 through the TGV 115 and the glass core to package substrate (GCTPS) interconnect 152, and the glass core to package substrate (GCTPS) interconnect 152 may be a power delivery interconnect or a high-speed signal interconnect. As described above, the GCTPS interconnect 152 may be similar to the STPS interconnect 150. The top surface of the package substrate 102 may include a set of conductive contacts 146, the multi-layer die subassembly 104 may include a set of conductive contacts 126 on the first surface 160-1, and the GCTPS interconnect 152 may be between and couple a corresponding one of the conductive contacts 146 with a corresponding one of the conductive contacts 126. In some embodiments, the underfill material 127 may extend around the associated GCTPS interconnect 152 between the glass core 110 and the package substrate 102.

[0068] As referenced Figure 1 or Figure 2 The glass core 110 included in the microelectronic component 100 or the glass core 110 included in any other microelectronic component or device as described may be subject to edge stress and thus vulnerable to crack formation and propagation. For example, Figure 3 illustrates the singulation of a glass panel, which may cause edge stress in the glass core. As Figure 3 shown, during the singulation process, a cutting tool 180 (e.g., a glass cutter, a diamond blade, or a saw) may be used to cut the glass panel 182 along some or all of the saw lines 184 to separate the glass panel 182 into individual glass units 186 or smaller pieces of two or more glass units 186. The saw lines 184 are referred to herein as "saw lines", although they may also be referred to as "score lines", "saw wires", or "single cut lines / tracks".

[0069] After singulation, any one of the glass units 186 can be used as the glass core 110. However, as a result of the cutting, the surfaces of the glass units 186 along the saw lanes 184 (i.e., at least some of the edges of the glass units 186) may be subject to edge stress and may as a result have cracks or fractures, have a high surface roughness or serrated edges, or may be non-uniform in other ways. One or more of the edge features described herein can be implemented in the glass panel 182 prior to the singulation process such that, after singulation, crack formation and / or propagation in the glass core 110 formed from one of the singulated glass units 186 can be reduced. Figures 4A-4B Illustrates an approximate location of an edge feature in the glass core 110 in accordance with some embodiments of the present disclosure. In particular, Figure 4A illustrates a cross-sectional side view of the glass core 110, while Figure 4B illustrates a top-down view of the glass core 110 (not to scale with the glass core 110 shown in Figure 4A ). As shown in Figure 4A , the glass core 110 can include a first face 190-1 and an opposing second face 190-2, which can be, for example, the bottom and top surfaces of the glass core 110 when the glass core 110 is included in the microelectronic assembly 100. When TGVs are formed in the glass core 110, such as the TGV 115 described above, openings 192 can first be formed in the glass core 110, extending between the first face 190-1 and the second face 190-2, where the openings 192 can then be filled with one or more conductive materials, such as copper. Figure 4A Also illustrated are opposing edges 194-1 and 194-2, and Figure 4B further illustrated is another pair of opposing edges 194-3 and 194-4 (the four edges 194-1, 194-2, 194-3, and 194-4, collectively referred to herein as "edges 194"), where the edges 194 are the surfaces of the glass core 110 that extend between the first face 190-1 and the second face 190-2. Figure 4A Further illustrated are edge zones 196-1 and 196-2 (collectively referred to herein as "edge zones 196"), where one or more of the edge features described herein can be implemented. As shown in Figure 4AAs shown, the edge region 196-1 is a region that includes the edge 194-1 and extends from the edge 194-1 to a specific depth 198-1 in the glass core 110 (i.e., extends toward the opposite edge 194-2), while the edge region 196-2 is a region that includes the edge 194-2 and extends from the edge 194-2 to a specific depth in the glass core 110 (i.e., extends toward the opposite edge 194-1). In various embodiments, the depths 198-1, 198-2 can be less than approximately 10% (e.g., less than approximately 7% or less than approximately 5%) of the total width 199 of the glass core 110 (e.g., the dimension of the glass core 110 measured in the same direction as the depths 198-1, 198-2). Figure 4B Illustrated is a single edge region 196 that can be defined as a closed contour that follows each of the edges 194 of the glass core 110 and extends from the edge 194 of the glass core 110 a specific depth 198 (the depth 198 measured in a direction perpendicular to the respective edge 194). Such a single edge region 196 can be similar to a ring surrounding the effective region 197 of the glass core 110, except that the shape of its coverage area (e.g., from top to bottom) is not circular as in a ring, but rectangular. The effective region 197 can be the region where the TGV 115 is implemented, and / or the region where other components are coupled to the glass core 110. Generally, the edge region 196 only occupies a portion of the total area of the face 190 of the glass core 110, e.g., less than approximately 20% (e.g., less than approximately 10% or less than approximately 5%) of the total area of the face 190 of the glass core 110. Figure 4B Illustrated is an edge region 196 having four portions along the four edges 194, where all portions have the same depth 198, but this can be different in other embodiments, as the edge regions 196 along different edges 194 can have different depths 198.

[0070] One or more of the edge features described herein can be implemented in any one or more of the edge regions 196. At a high level, the edge features described herein can be classified as edge features based on reducing crack propagation in the glass core 110 (e.g., the edge features illustrated in FIGS. 5-13), edge features based on reducing crack formation in the glass core 110 (e.g., the edge features illustrated in FIG. 14), and edge features based on reducing edge stress in the glass core 110 (e.g., the edge features illustrated in FIGS. 15-22). Edge features based on reducing crack propagation in the glass core 110 can be further classified as edge features based on setting crack propagation barriers (e.g., the edge features illustrated in FIGS. 5-11) and edge features based on repairing cracks (e.g., the edge features illustrated in FIG. 12). Edge features based on setting crack propagation barriers can even be further classified as continuous edge features along the edge (e.g., the edge features illustrated in FIGS. 5-7) and discontinuous edge features along the edge (e.g., Figures 8-11 the edge features illustrated in). Edge features based on reducing edge stress in the glass core 110 can be further classified as anchors (e.g., the edge features illustrated in FIGS. 15-18), daisy chain features (e.g., the edge features illustrated in FIGS. 19-20), and edge clamp features (e.g., the edge features illustrated in FIGS. 21-22). In some embodiments, each of the edge features described herein can be implemented as an independent edge feature in the glass core 110 to help mitigate or reduce crack formation and / or propagation. In other embodiments, two or more different edge features described herein can be implemented for the glass core 110 in any combination. Details of the various techniques will now be described. It should be noted that although the drawings of various embodiments illustrating edge features show the glass core 110 (e.g., Figures 5A-5D ), it should be understood that the same features can be applied to the glass panel 182 or a structure smaller than the glass panel 182 but larger than the glass core 110, e.g., a structure including a plurality of individual glass units 186 (e.g., half of the glass panel 182 or a quarter of the glass panel 182). Although FIGS. 5-22 do not show the TGV 115 in any of the glass cores 110 and do not show other components that can be coupled to the glass core 110, this is only to avoid cluttering the drawings, and generally, the glass core 110 shown in any of FIGS. 5-22 can be the glass core 110 as described with reference to, for example, Figure 1 or Figure 2 .

[0071] Figures 5A-5D A cross-sectional side view of a glass core 110 is provided in accordance with some embodiments of the present disclosure, which illustrates a process including an edge feature in the form of a continuous trench as part of a singulation preparation. InFigures 5A-5D and in other figures showing similar illustrations (e.g., Figures 7A-7D or Figures 12A-12C ), only the edge 194-2 and the edge region 196-2 are labeled and discussed, and the edges 194-1 and the regions 196-1 are not labeled so as not to clutter the figures, but the same considerations apply to the edges 194-1 and the regions 196-1 as those provided here.

[0072] Figure 5A It is illustrated that the process can start with forming a trench 202-1 in the first face 190-1 of the glass core 110 and a trench 202-2 in the second face 190-2. In various embodiments, processes such as dry etching, wet etching, or wet etching after laser modification can be used to form the trenches 202-1 and 202-2 (collectively referred to as "trenches 202"). As Figure 5A shown, the trenches 202 are provided in the edge region 196-2, adjacent to the edge 194-2. In some embodiments, the distance between the nearest one of the trenches 202-1 and 202-2 to the nearest edge 194 (e.g., to the edge 194-2 of the edge region 196-2) can be less than about 3% of the total width 199 of the glass core 110, e.g., less than about 1% or less than about 0.5%. The trenches 202-1 and 202-2 can be offset from each other, which means that for a given edge region 196, the distance from the trench 202-1 to the nearest edge 194 can be different from the distance from the trench 202-2 to the nearest edge 194. Figure 6 It is illustrated a glass panel 182 having a trench 202-2 as Figure 5A shown, the trench 202-2 being provided in the second face 190-2 (the trenches 202-1 are Figure 6 not visible in the view of Figure 6It is shown that the trench 202 can be a continuous trench, exactly located inside the saw track 194. In some embodiments, the depth of the trench 202 (i.e., the dimension measured along the z-axis of the coordinate system 105) can be slightly greater than about half of the thickness of the glass core 110, for example, between about 51% and 99% of the thickness of the glass core 110, or between about 51% and 60% of the thickness of the glass core 110. Achieving that the trenches 202-1 and 202-2 are offset from each other and each trench extends to a depth greater than about half of the thickness of the glass core 110 can help ensure that if cracks form at the edge 194-2, they cannot propagate into the glass core 110 further than the edge region 196-2, because the trenches 202-1 and 202-2 will be in their propagation path and will impede the propagation of the cracks. In other embodiments, the depth of the trench 202 can be equal to or less than half of the thickness of the glass core 110, for example, between about 25% and 50% of the thickness of the glass core 110, or between about 35% and 50% of the thickness of the glass core 110. Such embodiments may be less effective in reducing crack propagation, but are advantageous in terms of simpler manufacturing because the trench 202 is shallower.

[0073] In some embodiments, the trench 202 can be filled with a filler material 204, and the overlying layer of the filler material 204 (i.e., the portion deposited on the first surface 190-1 and the second surface 190-2) can be removed using any suitable planarization process such as chemical mechanical polishing (CMP), for example. The result of this case is shown in Figure 5B . The filler material 204 can include any material that can be easily deposited into the trench 202 (e.g., using lamination, molding, or liquid coating such as spin coating, dip coating, or spraying, or other deposition techniques). In some embodiments, the filler material 204 can include ABF, molding materials, polymer materials, or organic or inorganic insulator materials. In some embodiments, the filler material 204 can be a material with a relatively low Young's modulus, for example, between about 1 gigapascal (GPa) and 10 GPa, where Young's modulus can be defined as the ratio of stress to strain in a material undergoing deformation. Such embodiments can help better dissipate pressure. In some embodiments, the filler material 204 can be a material with a relatively low Poisson's ratio, for example, less than about 0.25, where Poisson's ratio can be defined as the negative ratio of transverse strain to axial strain. Such embodiments can also help better dissipate pressure.

[0074] In some embodiments, the filling material 204 can be a material with a relatively low CTE. CTE is a measure of how a material expands or contracts with changes in temperature and is typically defined as the fractional increase in length per unit increase in temperature, e.g., measured in parts per million (ppm) per Kelvin (K) or ppm / K. Materials that can be used for the glass core and metals (e.g., the metals filling the TGVs in the glass core) have significantly different CTEs. Metals have a relatively high CTE, meaning they can expand and contract significantly with changes in temperature. On the other hand, glass has a much lower CTE and is less responsive to temperature changes. For example, the CTE of glass can be on the order of about 3.5 ppm / K, while the CTE of a metal such as copper can be on the order of about 15 ppm / K. When a metal is in close contact with glass (e.g., the metal within the TGVs in the glass core) and the assembly is exposed to temperature variations such as heating or cooling, the metal will heat or cool much faster and to a greater extent than the glass. This results in significant thermal stress being generated at the interface between the two materials. High thermal stress can exceed the strength of the glass, leading to the formation of cracks, which can then propagate and compromise the structural integrity of the glass. Even if cracks do not form immediately, repeated thermal cycling can gradually weaken the glass surface, potentially leading to the development of surface flaws or microcracks. Prolonged exposure to stress caused by CTE mismatch can cause gradual degradation of the glass, making it more prone to failure over time. Including the filling material 204 as a material with a lower CTE than the metals used in other parts of the glass core 110 (e.g., in the TGV 115, not specifically shown in FIG. 5 and other figures depicting various edge features) can help reduce problems associated with stress caused by CTE mismatch. In some embodiments, the filling material 204 can be a material with a CTE below about 15 ppm / K, e.g., below about 10 ppm / K or below about 7 ppm / K.

[0075] In some embodiments, the trench 202 can be completely filled with the filling material 204. In other embodiments, the trench 202 can be partially filled with the filling material 204 (e.g., only on the sidewalls) and have a gap in the center, where the gap can be left substantially empty (i.e., as a void) or can be filled with some other material that is not a metal. In some embodiments, the filling material 204 can be at least 50% or at least 75% of the volume of the trench 202. In some embodiments, the trench 202 can not include any metal.

[0076] Figure 5CIllustrated is that, in some embodiments, after the trench 202 has been formed and filled with the filling material 204, the build-up layer 206 may be provided on the first side 190-1, the second side 190-2, or both sides 190. The build-up layer 206 may take the embodiment of the dielectric material layer 112, a further layer 111 below the glass core 110, and may be implemented as part of the substrate 107 above and below the glass core 110, as referenced Figure 1 described. In some embodiments utilizing the build-up layer 206, the covering layer of the filling material 204 does not have to be removed as Figure 5B shown, because the filling material 204 deposited on the sides 190 may be the first layer of the build-up layer 206.

[0077] Figure 5D Illustrated is that the cutting tool 180, as described above, starts cutting the glass core 110 (or rather, the glass panel 182 including the glass core 110) along the saw track 184. In Figure 5D , the horizontal arrows extending away from the saw track 184 and into the glass core 110 illustrate an example propagation direction of cracks that may form at the cutting edge during the cutting process. As Figure 5D shown, the trenches 202-1 and 202-2 block the path of crack propagation, thus helping to reduce crack propagation in the glass core 110.

[0078] Including other variations of the idea of edge features in the form of continuous trenches as Figures 5A-5D shown are possible, all within the scope of the present disclosure. For example, although Figures 5A-5D illustrates the trenches 202 on both sides 190 of the glass core 110, in some embodiments, the trench 202-1 or the trench 202-2 may be absent. Compared with having the trenches 202 on both sides 190, such embodiments may hinder crack propagation to a lesser extent, but may have the advantage of simplified manufacturing because the trench 202 only needs to be provided on one of the sides 190. In such embodiments, the trench 202 may extend deeper into the glass core 110, for example, to a depth of about 60-80% of the thickness of the glass core 110. In another example, the trenches 202-1 and 202-2 may extend to a depth less than half of the thickness of the glass core 110, for example, as Figure 7A shown, which is additionally the same as Figure 5B described above. Compared with extending the trench 202 to a depth greater than about half of the thickness of the glass core 110, such embodiments may hinder crack propagation to a lesser extent, but may have the advantage of simplified manufacturing because the trench 202 is shallower. In yet another example, the trench 202 does not have to be filled with the filling material 204 and may be left as a void. Further,Figures 5A-5D It is illustrated that the groove 202 has a circular shape in its cross-sectional profile because such a shape is expected to perform better than a rectangular shape or other shapes with sharp corners due to stress concentration factors. However, in other embodiments, the cross-sectional profile of the groove 202 can be different. For example, Figures 7B-7C It is illustrated that the same glass core 110 as shown in Figure 5B is shown, but in which the groove 202 has a square ( Figure 7B ), trapezoidal ( Figure 7C ), and triangular ( Figure 7D ) cross-sectional profile.

[0079] Instead of the edge feature as a continuous groove near the edge 194 of the glass core 110, in some embodiments, the edge feature can be provided in the form of discontinuous openings just inserted from the saw track 184, as shown in Figure 8 . In the figure, the discontinuous opening 212 is illustrated as a through hole. In some embodiments, the discontinuous opening 212 can be at least partially filled with a filling material 204, but in other embodiments, the discontinuous opening 212 can be left empty (e.g., made into an opening or void, similar to the embodiments described above for the groove 202). The further considerations regarding the amount of the filling material 204 in the groove 202 provided above apply to the filling of the discontinuous opening 212 with the filling material 204, and for the sake of brevity, they are not repeated.

[0080] In some embodiments, the discontinuous opening 212 can follow the profile of the groove 202-2 described above and can be a blind opening (e.g., a blind through hole). For example, the discontinuous opening 212 can extend from the second surface 190-2 towards the first surface 190-1, but does not reach the first surface 190-1. In some such embodiments, additional discontinuous openings 212 can also be provided on the other surface 190 of the glass core 110, for example, following the profile of the groove 202-1 described above. For example, such additional discontinuous openings 212 can extend from the first surface 190-1 towards the second surface 190-2, but do not reach the second surface 190-2. In other embodiments, the discontinuous opening 212 can be an opening penetrating the glass (e.g., a TGV) and can extend all the way through the thickness of the glass core 110, i.e., extend between the first surface 190-1 and the second surface 190-2. For example, as shown in Figure 9A in the cross-sectional side view (x-z plane). Figures 9A-9B The cross-sectional side view shown in Figures 9A-9B is a cross-section along the plane AA shown in the top-down view of . In some embodiments where the discontinuous opening 212 is an opening penetrating the glass, they can be at least partially filled with a metal such as copper, which can help hold the glass core 110 together and prevent it from splitting / layering.

[0081] In some embodiments, the discontinuous openings 212 may be provided in multiple rows along a given edge 194, and the multiple rows may be offset with respect to each other, as shown in the top-down view of Figure 9A , where two rows of discontinuous openings 212 are along a given edge 194. For example, as described above, the rows may follow the contours of the trenches 202-1 and 202-2, but the trenches 212 may be replaced with discontinuous openings 212, e.g., discontinuous openings 212 implemented as TGVs (as shown in the cross-sectional side view of Figure 9A ). In terms of blocking the crack propagation path starting from the edge 194 and entering the glass core 110, offsetting the individual rows of discontinuous openings 212 with respect to each other can be particularly advantageous. In other embodiments, the discontinuous openings 212 may be provided in multiple rows but not offset with respect to each other, as shown in Figure 10B . In still other embodiments, the discontinuous openings 212 may be provided in more than two rows along a given edge 194, e.g., as shown in Figure 10A , having three rows of discontinuous openings 212 along a given edge 194.

[0082] Although Figure 8 , Figure 9A , Figure 10A and Figure 10B illustrate the discontinuous openings 212 as vias, in other embodiments, the discontinuous openings 212 may have other shapes. For example, Figure 9B illustrates an example where the discontinuous opening 212 is sickle-shaped in its top-down view, Figure 10C illustrates an example where the discontinuous opening 212 is rectangular in its top-down view, and Figure 10D illustrates an example where the discontinuous opening 212 is oval in its top-down view. Further, in some embodiments where the discontinuous openings 212 are provided in multiple rows along a given edge 194, the shape of the discontinuous openings 212 may be different in different rows, as shown in Figure 10E .

[0083] Although Figure 8-1 0 illustrates the discontinuous openings 212 in an individual glass core 110, in some embodiments, similar discontinuous openings may be provided near the edge of the glass panel 182. According to some embodiments of the present disclosure, Figure 11An example of this is illustrated in the figure, showing a glass panel 182 having edge features in the form of discontinuous openings 212 in the edge region of a glass unit 186 (which later becomes the glass core 110), as well as discontinuous openings 214 in the edge region of the glass panel 182. All descriptions provided regarding the discontinuous opening 212 apply to the discontinuous opening 214, and for the sake of brevity, they are not repeated. Further, the description provided for the edge region 196 of the glass core 110 applies to the description of the edge region of the glass panel 182. In particular, the description of the size and position of the edge region 196 provided regarding the glass core 110 applies to the size and position of the edge region regarding the glass panel 182.

[0084] Figures 12A-12C A cross-sectional side view of a glass core 110 according to some embodiments of the present disclosure is provided, which illustrates different examples of edge features in the form of openings filled with a self-healing agent / material. Such openings may be referred to as "self-healing openings", and in Figures 12A-12Cis shown as a self-healing opening 222. As used herein, "self-healing" refers to the ability of a material to at least partially autonomously repair its damage and maintain its structural integrity. To this end, nanomaterials and nanostructures in the polymer provide a large surface area, abundant functional groups, and unique properties that can facilitate the repair process in the glass. Thus, in some embodiments, the self-healing opening 222 can include a matrix 224 in which self-healing particles 226 can be dispersed. The matrix 224 can include any suitable polymer, such as an epoxy resin. In some embodiments, the matrix 224 can include a thermosetting material, i.e., a type of polymer that undergoes a chemical reaction that irreversibly cures or "sets" once formed. In some embodiments, such a process can be induced by heat, a catalyst, or a combination of both. Thermosetting materials can include one or more polymeric materials, such as phenolic resins, alkyd resins, vinyl esters, unsaturated polyesters, polyurethanes, or aminoplastics. The self-healing particles 226 can include any suitable nanomaterial or nanostructure filled with a repair agent, such as microcapsules or nanocapsules. The repair agent can include materials such as poly(urea-formaldehyde) (PUF), polyurethane, poly(melamine-urea-formaldehyde) (PMUF), or poly(melamine-formaldehyde) (PMF). The polymerization and / or crosslinking of the repair agent, possibly in the presence of a catalyst, can patch the crack region and prevent further crack growth. If used, the catalyst can include materials such as the Hoveyda-Grubbs catalyst. In some embodiments, the catalyst can include ruthenium. In some embodiments, the catalyst can be dispersed in the glass core 110 rather than in the self-healing opening 222. During crack growth, the microcapsules or nanocapsules of the self-healing particles 226 can rupture, and the repair agent can be released into the crack in the glass core 110. The repair agent will then contact the catalyst dispersed in the glass core 110, which will initiate the polymerization / crosslinking of the repair agent, thereby filling the crack. In other embodiments, the catalyst can be coated on the edge 194 of the glass core 110 and / or on the sidewalls of the self-healing opening 222. In still other embodiments, the catalyst can be coated on the outer shell of the self-healing particles 226. In all of these embodiments, during crack growth, the microcapsules or nanocapsules of the self-healing particles 226 can rupture, and the repair agent will contact the catalyst, which will initiate the polymerization / crosslinking of the repair agent and at least partially fill the crack. The breaking of the polymer can involve the breaking of chemical and physical bonds, and the reformation of these bonds results in self-healing. Self-healing by chemical methods can utilize dynamic covalent bonds from reactions such as the Diels-Alder reaction and disulfide bond formation, while self-healing by physical methods can utilize intermolecular interactions, such as hydrogen bonds.Incorporation of nanomaterials in self-healing systems can advantageously provide large interfacial surface areas, enhanced electrical and mechanical properties, improved responses to external stimuli, and increased conversion efficiency of electromagnetic energy to heat.

[0085] Figure 12A An embodiment is illustrated in which the self-healing opening 222 is a TGV filled with a matrix 224 and self-healing particles 226 . Figure 12B An embodiment is illustrated in which the self-healing opening 222 filled with the matrix 224 and the self-healing particles 226 may further include an opening 228 filled with a material, such as a metal (eg, copper) or a filler material 204 as described above. Figure 12C An embodiment is illustrated in which the self-repairing opening 222 may include a self-repairing opening 222-1 and a self-repairing opening 222-2. The self-repairing opening 222-1 is provided at the first face 190-1 of the glass core 110 and extends toward the second face 190-2, but does not reach the second face 190-2. The self-repairing opening 222-2 is provided at the second face 190-2 of the glass core 110 and extends toward the first face 190-1, but does not reach the first face 190-1.

[0086] Figure 12A and 12B The self-repairing opening 222 shown in FIG. 1 is shown as a through hole extending all the way through the thickness of the glass core 110, while Figure 12C The self-repairing opening 222 shown in FIG. 2 is shown as a blind through hole. All of the descriptions provided above regarding the discontinuous opening 212 are applicable to the self-repairing opening 222. In other words, in FIG. Figures 8-11 In a further embodiment of FIG. 5-7 , instead of a filling material 204, the discontinuous opening 212 may be at least partially filled with a self-healing material, as described for the self-healing opening 222. All of the descriptions provided above with respect to the trench 202 apply to the self-healing opening 222. In other words, in a further embodiment of FIG. 5-7 , instead of a filling material 204, the trench 202 may be at least partially filled with a self-healing material, as described for the self-healing opening 222. Figures 13A-13B A further illustration of a self-healing opening 222 implemented as a trench that may be filled with a self-healing material is provided. Figure 13A A self-healing opening 222 is illustrated as a single continuous groove proximate edge 194. For example, such a groove may be similar to groove 202-2 described above, although it may extend all the way through the thickness of glass core 110 in some embodiments. Figure 13B The self-healing openings 222 are shown as two continuous grooves near the edge 194. For example, Figure 13BThe outer groove (i.e., the groove closer to the edge 194) marked as the self-healing opening 222-2 in can be similar to the groove 202-2 described above, although in some embodiments it can extend all the way through the thickness of the glass core 110. In Figure 13B The inner groove (i.e., the groove farther from the edge 194) marked as the self-healing opening 222-1 in can be similar to the groove 202-1 described above, although in some embodiments it can also extend all the way through the thickness of the glass core 110.

[0087] Turning to the edge features based on reducing crack formation in the glass core 110, Figures 14A-14B A top-down view of the glass panel 182 is provided, which illustrates different examples of edge features in the form of discontinuous openings 232 along the saw track 184 according to some embodiments of the present disclosure. As described above, the singulation process causes crack formation and damage to the glass core, especially if the singulation is performed after a buildup layer has been formed on the top and / or bottom of the glass. In the past, mitigation plans have been proposed to address this problem by optimizing the singulation process (including developing new equipment or cutting techniques) or by changing the type of buildup material. Such solutions take a long time to fully develop and are very expensive. The alternative proposed herein is based on the recognition that if discontinuous openings 232 are first created along the saw track 184 and filled with a filling material 234 before a buildup layer is formed around the glass, then the effective area of the glass being cut during singulation will be reduced, thereby reducing the chance of crack formation. In some embodiments, the discontinuous opening 232 can be a through-hole, as Figure 14A shown in. In other embodiments, the discontinuous opening 232 can be a groove, as Figure 14B shown in. The formation of the discontinuous opening 232 is a much gentler process than singulation because the opening 232 can be formed using processes such as dry etching, wet etching, or wet etching after laser modification. The filling material 234 can include any of the materials described with reference to the filling material 204. In various embodiments, the filling material 234 can partially or fully fill the discontinuous opening 232. The further considerations provided above regarding the amount of the filling material 204 in the groove 202 apply to filling the discontinuous opening 232 with the filling material 234, and for the sake of brevity, will not be repeated. The discontinuous opening 232 can extend all the way through the thickness of the glass core 110, i.e., extend between the first surface 190-1 and the second surface 190-2. For example, as Figures 14A-14B shown in the cross-sectional side view (x-z plane) at the bottom. Figures 14A-14B The cross-sectional side view shown in is along Figures 14A-14BThe cross-section of plane AA as shown in the top-down view. Once the discontinuous opening 232 has been formed along the saw track 184 and filled with the filling material 234, any conventional process can be applied to provide the build-up layer, followed by any conventional singulation process. In the final glass core 110 obtained from such a process, the portion of the discontinuous opening 232 with the filling material 234 can be detectable along the edge 194.

[0088] Turning to the last category of edge features, namely edge features based on reducing the edge stress in the glass core 110, FIGS. 15-18 illustrate examples of edge features in the form of anchors.

[0089] Figures 15A-15B A top-down view of a glass core 110 according to some embodiments of the present disclosure is provided, which illustrates continuous ( Figure 15A ) and discontinuous ( Figure 15B ) different examples of edge features in the form of anchors 242 in the edge region 196 of the glass core 110. In Figures 15A-15B , according to some embodiments of the present disclosure, the dashed contour illustrates a portion 240 of the glass core 110, and various examples of the cross-sectional side view are shown for this portion in Figures 16A-16D . As shown in Figures 16A-16D , the anchor 242 can include a first portion 244-1 on the first face 190-1 of the glass core 110, a second portion 244-2 on the second face 190-2 of the glass core 110, and in some embodiments, further includes a third portion 244-3 embedded in the glass core 110 (e.g., between the first face 190-1 and the second face 190-2). Any two or more of the portions 244-1, 244-2, and 244-3 can be collectively referred to as "portion 244". In some embodiments, the dimension of the first and / or second portions 244-1 and / or 244-2 in the direction perpendicular to the nearest edge 194 can be greater than the dimension of the third portion 244-3. The portion 244 of the anchor 242 can be or can include a metal, such as copper, or any other suitable material that can counteract the stress applied to the glass core 110, such as counteracting the stress applied by the CTE mismatch of the dielectric material of the build-up layer later placed on the top and / or bottom of the glass core 110.

[0090] The portion 244 of the anchor 242 can be arranged in any suitable manner to help hold the glass core 110 together, reduce the direct edge stress in the glass core 110, and / or prevent the glass core 110 from separating. In some embodiments, the third portion 244-3 can be attached to the second portion 244-2 (e.g., can be substantially continuous with the second portion 244-2), as shown in Figure 16Aas shown. In other embodiments, the third portion 244-3 may be attached to the first portion 244-1 (e.g., may be substantially continuous with the first portion 244-1), as Figure 16B shown. In still other embodiments, the third portion 244-3 may extend through the thickness of the glass core 110 and be attached to both the first portion 244-1 and the second portion 244-2 (e.g., may be substantially continuous with the first portion 244-1 and the second portion 244-2), as Figure 16C shown. In yet other embodiments, the anchor 242 may have the first and second portions 244-1, 244-2 but not include the third portion 244-3, as Figure 16D shown. Figure 15A and 15B illustrate that the anchor 242 may extend around the periphery of the glass core 110, e.g., along the edge 194 in the edge region 196 of the glass core 110. In some embodiments, the anchor 242 may extend as a continuous anchor around at least one of the edges 194 (e.g., the anchor 242 at one of the edges 194 in Figure 15A ), or as a continuous anchor around two or more of the edges 194 (e.g., the anchor 242 extends continuously along all of the edges 194, as Figure 15A shown). In such embodiments, the continuous anchor 242 may extend similarly to the trench 202 or the embodiments of the continuous self-healing opening 222 described above. In other embodiments, the anchor 242 may also extend along at least one of the edges 194 but in a discontinuous form, as Figure 15B shown. In such embodiments, the discontinuous anchor 242 may extend similarly to the discontinuous opening 212 or the embodiments of the discontinuous self-healing opening 222 described above. In some embodiments, the dimension of the anchor 242 along the direction parallel to the nearest edge 194 may be greater than the dimension of the anchor 242 along the direction perpendicular to the nearest edge 194. In various embodiments, any of the anchors 242 implemented as a continuous anchor or a discontinuous anchor may include Figures 16A-16D a combination of cross-sectional profiles shown. For example, in some embodiments, a single continuous portion of the anchor 242 (such as the anchor 242 along the entire edge 194 as Figure 15A shown or the continuous portion of the anchor 242 along a portion of the edge 194 as Figure 15B shown) may include a continuous first portion 244-1 and a continuous second portion 244-2, but the third portion 244-3 may vary between two or more variants along the length of the continuous portion of the anchor 242, as Figures 16A-16D shown.

[0091] Although Figures 15A-15B and Figures 16A-16D FIGS. illustrate the anchor 242 in the edge region 196 of the glass core 110, the anchor 242 as described herein can also be provided in the edge region of the glass panel 182 (e.g., around multiple glass cores 110). Thus, the anchor 242 as described herein can be provided as a continuous or discontinuous anchor 242 in the periphery (i.e., in the edge region) of the glass panel 182 including two or more individual glass units 186 or individual glass cores 110.

[0092] Figures 17A-17B A top - down view of a glass core 110 according to some embodiments of the present disclosure is provided, which illustrates various examples of edge features in the form of continuous ( Figure 17A ) and discontinuous ( Figure 17B ) anchors 252 extending through the stack layer 206 in the edge region 196 of the glass core 110. In Figures 17A-17B , the dashed contour illustrates a portion 250 of the glass core 110 according to some embodiments of the present disclosure, and various examples of cross - sectional side views are shown for the portion 250 in Figures 18A-18D . The anchor 252 is similar to the anchor 242 in that they include portions 244 - 1, 244 - 2, and 244 - 3 as described above, except that the first portion 244 - 1 of the anchor 252 is provided on top of the stack layer 206 above the first face 190 - 1 of the glass core, and the second portion 244 - 2 of the anchor 252 is provided on top of the stack layer 206 above the second face 190 - 2 of the glass core. As shown in Figures 18A-18D , the anchor 252 can include a first portion 244 - 1 above the stack layer 206 on the first face 190 - 1 of the glass core 110, a second portion 244 - 2 above the stack layer 206 on the second face 190 - 2 of the glass core 110, and a third portion 254 - 3 embedded in the glass core 110 (e.g., between the first face 190 - 1 and the second face 190 - 2). As shown in Figures 18A-18DAs further shown, the anchor 252 may further include a first stacked portion 254-1 extending through the stacked layer 206 on the first face 190-1 of the glass core 110, and a second stacked portion 254-2 extending through the stacked layer 206 on the second face 190-2 of the glass core 110. The first stacked portion 254-1 may be attached to the first portion 244-1 (e.g., may be substantially continuous with the first portion 244-1), while the second stacked portion 254-2 may be attached to the second portion 244-2 (e.g., may be substantially continuous with the second portion 244-2). The portions 254-1 and 254-2 may be collectively referred to as "portion 254". Similar to portion 244, the portion 254 of the anchor 252 may be or may include a metal, such as copper, or any other suitable material that can offset the stress applied to the glass core 110, such as offsetting the stress applied by the CTE mismatch of the dielectric material of the stacked layer later placed on the top and / or bottom of the glass core 110.

[0093] The portions 244 and 254 of the anchor 252 may be arranged in any suitable manner that may help hold the glass core 110 together, reduce direct edge stress in the glass core 110, and / or prevent the glass core 110 from separating. In some embodiments, a third portion 244-3 may be attached to the second stacked portion 254-2 (e.g., may be substantially continuous with the second stacked portion 254-2), as Figure 18A and Figure 18C shown. In other embodiments, the third portion 244-3 may be attached to the first portion 254-1 (e.g., may be substantially continuous with the first portion 254-1), as Figure 18B and Figure 18D shown. In still other embodiments, the third portion 254-3 may extend through the thickness of the glass core 110 and be attached to both the first portion 254-1 and the second portion 254-2 (may be substantially continuous with both the first portion 254-1 and the second portion 254-2) (not specifically shown in Figures 18A-18D but as shown in Figure 16C ). In yet other embodiments, the anchor 252 may have the first and second portions 254-1, 254-2, but not include the third portion 244-3 (also not specifically shown in Figures 18A-18D but as shown in Figure 16D ). In some embodiments, the individual portions 254 may include a plurality of through-holes 256 and pads 258 in different sub-layers of the stacked layer 206. One such through-hole 256 and one such pad 258 are marked in Figure 18A but, to avoid cluttering the drawings, in Figures 18B-18DThere is no separate marking. Dividing portion 254 into vias 256 and pads 258 can be due to the fact that in some embodiments, these portions of portion 254 can be formed layer by layer as different sub - layers of stack 206 are formed, similar to the formation of conductive vias and conductive traces in various layers. In some embodiments, different vias 256 and pads 258 among the vias 256 and pads 258 of a given portion 254 can be stacked substantially above each other (e.g., arranged symmetrically), as shown in Figure 18A and Figure 18B whereas in other embodiments, different vias 256 and pads 258 among the vias 256 and pads 258 of a given portion 254 can be staggered, as shown in Figure 18C and Figure 18D as shown.

[0094] Figure 17A and 17B illustrate that the anchor 252 can extend at the periphery of the glass core 110, e.g., along the edge 194 in the edge region 196 of the glass core 110. In some embodiments, the anchor 252 can extend as a continuous anchor around at least one of the edges 194 (e.g., the anchor 252 at one of the edges 194 in Figure 17A ), or as a continuous anchor around two or more of the edges 194 (e.g., the anchor 252 extends continuously along all the edges 194, as shown in Figure 17A ). In such embodiments, the continuous anchor 252 can extend similar to the trench 202 or the embodiments of the continuous self - healing opening 222 described above. In other embodiments, the anchor 252 can also extend along at least one of the edges 194, but in a discontinuous form, as shown in Figure 17B . In such embodiments, the discontinuous anchor 252 can extend similar to the discontinuous opening 212 or the embodiments of the discontinuous self - healing opening 222 described above. For embodiments where the anchor 252 is a discontinuous anchor, the dimension of the anchor 252 along the direction parallel to the nearest edge 194 can be greater than the dimension of the anchor 252 along the direction perpendicular to the nearest edge 194. In various embodiments, any one of the anchors 252 implemented as a continuous anchor or a discontinuous anchor can include a combination of cross - sectional profiles shown in Figures 18A-18D . For example, in some embodiments, a single continuous portion of the anchor 252 (such as the anchor 252 along the entire edge 194 as shown in Figure 17A or as shown in Figure 17BThe continuous portion of the anchor 252 along a portion of the edge 194 as shown may include a continuous first portion 244-1 and a continuous second portion 244-2, but the third portion 244-3 may vary between two or more variants of the third portion 244-3 along the length of the continuous portion of the anchor 252, as shown in FIG. 18. In another example, in some embodiments, a single continuous portion of the anchor 252 (such as the anchor 252 along the entire edge 194 as shown in Figure 17A , or the continuous portion of the anchor 252 along a portion of the edge 194 as shown in Figure 17B ) may include a continuous first portion 244-1 and a continuous second portion 244-2, but the first stacking portion 254-1 and / or the second stacking portion 254-2 may vary between stacking and interleaving variations of the first stacking portion 254-1 and / or the second stacking portion 254-2 along the length of the continuous portion of the anchor 252, as shown in Figures 18A-18D . Figure 17A the anchor 252 along the entire edge 194 as shown, or as Figure 17B the continuous portion of the anchor 252 along a portion of the edge 194 as shown may include a continuous first portion 244-1 and a continuous second portion 244-2, but the first stacking portion 254-1 and / or the second stacking portion 254-2 may vary between stacking and interleaving variations of the first stacking portion 254-1 and / or the second stacking portion 254-2 along the length of the continuous portion of the anchor 252, as Figures 18A-18D shown.

[0095] Although Figures 17A-17B and Figures 18A-18D illustrate the anchor 252 in the edge region 196 of the glass core 110, the anchor 252 as described herein may also be provided in the edge region of the glass panel 182 (e.g., around multiple glass cores 110). Thus, the anchor 252 as described herein may be provided as a continuous or discontinuous anchor 252 in the periphery (i.e., in the edge region) of the glass panel 182 including two or more individual glass units 186 or individual glass cores 110.

[0096] Another example of an edge feature based on reducing edge stress in the glass core 110 is shown in FIGS. 19-20, which illustrate an edge feature in the form of a daisy chain.

[0097] Figures 19A-19B A top-down view of a glass panel 182 according to some embodiments of the present disclosure is provided, which illustrates different examples of edge features in the form of daisy chains 262. Figure 19A Illustrated is a single daisy chain 262 extending continuously along the edge 194 (e.g., in the edge region 196) of an individual glass unit 186, which will later form the glass core 110. Figure 19BIllustrated, in some embodiments, a plurality of daisy chain loops 262 may be nested along the edge 194, shown as a first daisy chain loop 262-1 and a second daisy chain loop 262-2 surrounding the first daisy chain loop 262-1. Thus, the second daisy chain loop 262-2 may be the outer loop (i.e., the loop closest to the edge 194), while the first daisy chain loop 262-1 may be the inner loop (i.e., a loop further away from the edge 194 but still within the edge region 196 as described above). In other embodiments, more than two daisy chain loops 262 may be nested within each other. According to some embodiments of the present disclosure, Figure 19A The dashed contour shown therein illustrates a portion 260 of the glass core 110, for which various examples of cross-sectional side views having cross-sections taken along the daisy chain loop 262 are shown in Figures 20A-20C Any one of the one or more daisy chain loops 262 along the edge 194 of the glass core 110 may take the form of any one of those in Figures 20A-20C

[0098] As shown in Figures 20A-20C , the daisy chain loop 262 may include a first portion 264-1 in a recess in the first face 190-1 of the glass core 110, a second portion 264-2 in a recess in the second face 190-2 of the glass core 110, and a third portion 264-3 embedded in the glass core 110 (e.g., between the first face 190-1 and the second face 190-2) and connecting the first portion 264-1 and the second portion 264-2 in a daisy chain form. Any two or more of the portions 264-1, 264-2, and 264-3 may be collectively referred to as "portion 264". In some embodiments, the portion 264 of the daisy chain loop 262 may be or may include a metal such as copper, or any other suitable material that can counteract the stress applied to the glass core 110, e.g., to counteract the stress imposed by the CTE mismatch of the dielectric material of the build-up layer later placed on top and / or bottom of the glass core 110. In other embodiments, the portion 264 may include any one of the materials described with reference to the fill material 204. Figure 20A Illustrates an embodiment in which the third portion 264-3 is substantially perpendicular to the face 190 of the glass core 110. Figure 20B Illustrates an embodiment in which the third portion 264-3 is at an angle with respect to the face 190 of the glass core 110 (i.e., at an angle other than 90 degrees). Figure 20C ​Illustrated is an embodiment in which the third portion 264-3 is angled with respect to the face 190 of the glass core 110 and in which the first and second portions 264-1, 264-2 just contact the corresponding first and second faces 190-1, 190-2. In various other embodiments, the pitch, depth, and width of the different portions 264 of the daisy chain 262 can be modified as desired. When multiple daisy chains 262 are implemented around the effective area of the glass core 110, the size, pitch, stitching pattern, etc. can vary between each pair of daisy chains 262.

[0099] Yet another example of an edge feature based on reducing edge stress in the glass core 110 is shown in FIGS. 21-22, which illustrate an edge feature in the form of an edge clamp.

[0100] Figures 21A-21B A top-down view and a cross-sectional side view of a glass core 110 according to some embodiments of the present disclosure are provided, which illustrate a first example of an edge feature in the form of an edge clamp 272. Figures 22A-22B A top-down view and a cross-sectional side view of a glass core 110 according to some embodiments of the present disclosure are provided, which illustrate a second example of an edge feature in the form of an edge clamp 272. In Figure 21A and 22A the dashed outlines illustrate a portion 270 of the glass core 110 according to some embodiments of the present disclosure, and examples of cross-sectional side views of the portion 270 are shown in Figure 21B and 22B respectively. As shown in Figure 21A in some embodiments, the edge clamp 272 can extend around all the edges 194 of the glass core 110. However, in other embodiments, the edge clamp 272 can extend around only one of the edges 194, or around two or more but not all of the edges 194. In some embodiments, the edge clamp 272 can extend along at least 50% of the length of a given edge 194. In some embodiments, the edge clamp 272 can extend along the entire length of a given edge 194. In still other embodiments, the edge clamp 272 can be one of a plurality of edge clamps 272 along a given edge 194, and the plurality of edge clamps 272 are materials that are discontinuous with each other (e.g., similar to the discontinuous openings 232 along the saw track 184).

[0101] Figure 21BThe figure shows that the edge clamp 272 can wrap around the edge 194 as it can have a first portion 274-1 on the first side 190-1 of the glass core 110, a second portion 274-2 on the second side 190-2 of the glass core 110, and a third portion 274-3 on the edge 194 that connects the first portion 274-1 and the second portion 274-2. Any two or more of the portions 274-1, 274-2, and 274-3 can be collectively referred to as "portion 274". In some embodiments, adjacent portions 274 in the portion 274 can be substantially continuous with each other (e.g., one end of the third portion 274-3 can be substantially continuous with the first portion 274-1, and the other end of the third portion 274-3 can be substantially continuous with the second portion 274-2). As Figure 22A shown, in other embodiments, the edge clamp 272 can extend along the edge 194 but be inserted from the edge 194 within the edge region 196. Figure 22B The figure shows that such an edge clamp 272 can also have a first portion 274-1 on the first side 190-1 of the glass core 110, a second portion 274-2 on the second side 190-2 of the glass core 110, and a third portion 274-3 that is embedded between the first side 190-1 and the second side 190-2 and extends between the first portion 274-1 and the second portion 274-2. In addition to the material of the edge clamp 272, Figures 22A-22B the edge clamp 272 can be similar to Figure 15B the discontinuous anchor 242 shown. In both FIGS. 21 and 22, the edge clamp 272 can be made of a negative CTE material (i.e., a material that shrinks when heated and expands when cooled). Some examples of negative CTE materials that can be used to implement the edge clamp 272 include zirconium tungstate (ZrW2O8), gallium arsenide (GaAs), cuprous oxide (Cu2O), or certain polymers such as liquid crystal polymers (e.g., poly(p-phenylene benzobisoxazole) (PBO or Zylon)). The negative CTE material can act as a "clamp" to counteract the stresses that cause crack formation and propagation because the negative CTE of these materials opposes the direction of the stress by shrinking rather than expanding under thermal stress.

[0102] Although Figures 21A-21B and Figures 22A-22B show the edge clamp 272 in the edge region 196 of the glass core 110, the edge clamp 272 as described herein can also be provided in the edge region of the glass panel 182 (e.g., around multiple glass cores 110). Thus, the edge clamp 272 as described herein can be provided as a continuous or discontinuous edge clamp 272 in the periphery (i.e., in the edge region) of the glass panel 182, which glass panel 182 includes two or more individual glass units 186 or individual glass cores 110.

[0103] Advantageously, the various edge features described above can be readily fabricated in parallel with conventional fabrication techniques for glass core substrates. As Figures 1-2 shown in FIG. 2, the various arrangements of the microelectronic component 100 and the glass core 110 do not represent an exhaustive set of microelectronic components and glass cores in which the various edge features described herein can be used, but merely provide some illustrative examples. In particular, Figures 1-2 the number and positioning of the various elements shown in FIG. 2 are purely illustrative, and in various other embodiments, other numbers of these elements provided in other positions relative to each other can be used in accordance with the general architectural considerations described herein. For example, although not specifically shown in the current figures, in some embodiments, the microelectronic component 100 can include a redistribution layer (RDL) between any pair of layers shown in Figure 1 and Figure 2 which includes a plurality of interconnect structures (e.g., wires and conductive vias) to assist in routing signals and / or power between components. In another example, although also not specifically shown in this figure, in some embodiments, the package substrate 102 of the microelectronic component 100 can include one or more recesses. In such embodiments, the bottom surface of the recess in the package substrate 102 can be provided by the solid material of the package substrate 102. The recesses can be formed in the package substrate 102 in any suitable manner (e.g., via three-dimensional printing, laser cutting, or drilling recesses in an existing package substrate, etc.). At least a portion of the substrate 107 or the glass core 110 can be positioned above or at least partially within such recesses. In yet another example, Figures 1-2 the features of any one of FIG. 2 can be combined with Figures 1-2 the features of any other one of FIG. 2.

[0104] The microelectronic component 100 and / or the glass core 110 disclosed herein, particularly the glass core 110 having one or more edge features as described herein, can be included in any suitable electronic component. Figures 23-26 Illustrated are various examples of devices that can include or be included in any one of the microelectronic component 100 and / or the glass core 110 disclosed herein.

[0105] Figure 231 is a top view of a wafer 1500 and die 1502, which may be included in any microelectronic assembly 100 as described herein. For example, die 1502 may be any of the dies 114 described herein. Wafer 1500 may be comprised of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is complete, wafer 1500 may undergo a singulation process in which die 1502 are separated from one another to provide discrete “chips” of a semiconductor product. Die 1502 may include one or more transistors (e.g., transistors discussed below). Figure 24 Some of the transistors 1640) and / or supporting circuits to route electrical signals to the transistors, as well as any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be combined with a processing device (e.g., a processor) configured to store information in the memory devices or to execute instructions stored in the memory array. Figure 26 Processing devices 1802) or other logic are formed on the same die 1502.

[0106] Figure 24 1 is a side cross-sectional view of an IC device 1600 that can be included in any of the microelectronic assemblies 100 described herein. For example, the IC device 1600 can be provided on / in any of the dies 114 described herein. The IC device 1600 can be formed on a substrate 1602 (e.g., Figure 23 1500) and may be included in a die (e.g., Figure 23into the die 1502). The substrate 1602 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 can include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 can be formed using alternative materials that can or cannot be combined with silicon, the alternative materials including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group III-V materials (i.e., materials from groups III and V of the periodic table), group II-VI materials (i.e., materials from groups II and VI of the periodic table), or group IV materials (i.e., materials from group IV of the periodic table) can also be used to form the substrate 1602. Although several examples of materials from which the substrate 1602 can be formed are described herein, any material that can serve as a basis for the IC device 1600 can be used. The substrate 1602 can be a singulated die (e.g., Figure 23 the die 1502) or a part of a wafer (e.g., Figure 23 the wafer 1500).

[0107] The IC device 1600 can include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 can include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 can include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 that controls the current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 that route electrical signals to / from the S / D regions 1620. For clarity, the transistor 1640 can include additional features not depicted, such as device isolation regions, gate contacts, and the like. The transistor 1640 is not limited to Figure 24 the types and configurations depicted therein, and can include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors can include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors can include FinFET transistors, such as double-gate transistors or triple-gate transistors, and gate-all-around or fully-gate-all-around transistors, such as nanoribbon and nanowire transistors.

[0108] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include a single layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0109] Depending on whether the transistor 1640 is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, the gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. For other purposes, further metal layers, such as barrier layers, may be included. For PMOS transistors, the metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, the metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0110] In some embodiments, when viewing a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure that includes a bottom portion that is substantially parallel to the substrate surface and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0111] In some embodiments, sidewall spacer pairs may be formed on opposite sides of the gate stack to serve as a support for the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two sidewall spacer pairs, three sidewall spacer pairs, or four sidewall spacer pairs may be formed on opposite sides of the gate stack.

[0112] The S / D regions 1620 may be formed in the substrate 1602 adjacent to the gates 1622 of each transistor 1640. For example, an implantation / diffusion process or an etch / deposition process may be used to form the S / D regions 1620. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate 1602 to form the S / D regions 1620. An annealing process to activate the dopants and cause them to further diffuse into the substrate 1602 may be performed after the ion implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S / D regions 1620. Then an epitaxial deposition process may be carried out to fill the recesses with the material for fabricating the S / D regions 1620. In some implementations, silicon alloys such as silicon germanium or silicon carbide may be used to fabricate the S / D regions 1620. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or III-V materials or alloys. In further embodiments, one or more metal and / or metal alloy layers may be used to form the S / D regions 1620.

[0113] Electrical signals such as power and / or input / output (I / O) signals may be routed to and / or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers (illustrated in Figure 24 as interconnect layers 1606, 1608, and 1610) disposed on the device layer 1604. For example, the conductive features (e.g., gates 1622 and S / D contacts 1624) of the device layer 1604 may be electrically coupled to the interconnect structures 1628 of the interconnect layers 1606, 1608, and 1610. The one or more interconnect layers 1606, 1608, and 1610 may form the metallization stack (also referred to as the "ILD stack") 1619 of the IC device 1600.

[0114] The interconnect structures 1628 may be arranged within the interconnect layers 1606 - 1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited toFigure 24 the specific configuration of the interconnect structure 1628 depicted in. Although Figure 24 a specific number of interconnect layers 1606, 1608, and 1610 are depicted in, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than those depicted.

[0115] In some embodiments, the interconnect structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material such as metal. The wires 1628a may be arranged to route electrical signals in a plane direction substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, from Figure 24 the perspective of, the wires 1628a may route electrical signals in the direction in and out of the page. The vias 1628b may be arranged to route electrical signals in a plane direction substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple the wires 1628a of different interconnect layers 1606, 1608, and 1610 together.

[0116] The interconnect layers 1606, 1608, and 1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as Figure 24 shown in. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different interconnect layers of the interconnect layers 1606, 1608, and 1610 may have different compositions; in other embodiments, the compositions of the dielectric material 1626 between the different interconnect layers 1606, 1608, and 1610 may be the same.

[0117] The first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, as shown, the first interconnect layer 1606 may include wires 1628a and / or vias 1628b. The wires 1628a of the first interconnect layer 1606 may be coupled to contacts (e.g., S / D contacts 1624) of the device layer 1604.

[0118] The second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the wires 1628a of the second interconnect layer 1608 to the wires 1628a of the first interconnect layer 1606. Although, for clarity, the wires 1628a and vias 1628b are depicted structurally using wires within each interconnect layer (e.g., within the second interconnect layer 1608), in some embodiments, the wires 1628a and vias 1628b may be structurally and / or substantially continuous (e.g., filled simultaneously during a dual damascene process).

[0119] Based on similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606, a third interconnect layer 1610 (and additional interconnect layers, as desired) can be successively formed on the second interconnect layer 1608. In some embodiments, the interconnect layers that are "higher level" (i.e., further from the device layer 1604) in the metallization stack 1619 in the IC device 1600 can be thicker.

[0120] The IC device 1600 can include a solder mask material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606, 1608, and 1610. In Figure 24 , the conductive contacts 1636 are illustrated as taking the form of bond pads. The conductive contacts 1636 can be electrically coupled to the interconnect structure 1628 and are configured to route electrical signals of the transistor(s) 1640 to other external devices. For example, a solder bond can be formed on one or more of the conductive contacts 1636 to mechanically and / or electrically couple the chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 can include additional or alternative structures to route electrical signals from the interconnect layers 1606, 1608, and 1610; for example, the conductive contacts 1636 can include other similar features (e.g., pillars) that route electrical signals to external components.

[0121] Figure 25 is a side cross-sectional view of an IC device assembly 1700, which can include a glass core having one or more edge features according to any of the embodiments disclosed herein. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (e.g., which can be a main board). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and a second, opposite side 1742 of the circuit board 1702; generally, components can be disposed on one or both of the sides 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 can take the form of any of the embodiments of the microelectronic component 100 discussed above, e.g., can include one or more microelectronic components 100 as discussed with reference to Figure 1 and Figure 2 discussed, and / or can include one or more glass cores as discussed with reference to Figure 3-2 2.

[0122] In some embodiments, circuit board 1702 can be a PCB including multiple metal layers, the multiple metal layers being separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to circuit board 1702. In other embodiments, circuit board 1702 can be a non-PCB substrate.

[0123] Figure 25 The IC device assembly 1700 illustrated in FIG. includes an on-interposer package structure 1736 coupled to the first surface 1740 of circuit board 1702 through a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the on-interposer package structure 1736 to circuit board 1702 and can include solder balls (as Figure 25 shown), male and female parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0124] The on-interposer package structure 1736 can include an IC package 1720 coupled to the package interposer 1704 through a coupling component 1718. The coupling component 1718 can take any suitable form for the application, such as the form discussed above with reference to the coupling component 1716. Although Figure 25 a single IC package 1720 is shown, multiple IC packages can be coupled to the package interposer 1704; in fact, additional interposers can be coupled to the package interposer 1704. The package interposer 1704 can provide an intermediate substrate for bridging circuit board 1702 and IC package 1720. The IC package 1720 can be or can include, for example, a die (die 1502 of FIG. 5), an IC device (e.g., any one of the IC devices described herein, or any combination of such IC devices), or any other suitable component. Generally, the package interposer 1704 can extend connections to a wider pitch or reroute connections to different connections. For example, the package interposer 1704 can couple the IC package 1720 (e.g., a die) to a ball grid array (BGA) conductive contact set of the coupling component 1716 for coupling to circuit board 1702. In Figure 25 the illustrated embodiment, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 can be attached to the same side of the package interposer 1704. In some embodiments, three or more components can be interconnected through the package interposer 1704.

[0125] In some embodiments, the encapsulation interposer 1704 can be formed as a glass core having one or more edge features, e.g., any embodiment of the glass core 110 as described herein. In some embodiments, the encapsulation interposer 1704 can be formed as a PCB. In some embodiments, the encapsulation interposer 1704 can be formed of epoxy resin, glass fiber-reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the encapsulation interposer 1704 can be formed of alternative rigid or flexible materials, which can include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. In any of these embodiments, the encapsulation interposer 1704 can include multiple metal layers, which are separated from each other by dielectric material layers and interconnected by conductive vias. The encapsulation interposer 1704 can include metal lines 1710 and vias 1708, including but not limited to conductive vias 1706. If the encapsulation interposer 1704 is a glass core, e.g., as the glass core 110 described herein, the conductive via 1706 can be the TGV 115 as described herein. The encapsulation interposer 1704 can further include embedded devices 1714, including both passive and active devices. Such devices can include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices can also be formed on the encapsulation interposer 1704. The on-interposer package structure 1736 can take the form of any of the on-interposer package structures known in the art.

[0126] The IC device assembly 1700 can include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 via a coupling component 1722. The coupling component 1722 can take the form of any of the embodiments discussed above with reference to the coupling component 1716, and the IC package 1724 can take the form of any of the embodiments discussed above with reference to the IC package 1720.

[0127] Figure 25The IC device assembly 1700 illustrated in the figure includes a package - on - package structure 1734 coupled to the second side 1742 of the circuit board 1702 through a coupling component 1728. The package - on - package structure 1734 may include an IC package 1726 and an IC package 1732, which are coupled together through a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package - on - package structure 1734 may be configured according to any of the package - on - package structures known in the art.

[0128] Figure 26 is a block diagram of an exemplary communication device 1800, which may include one or more microelectronic components 100 and / or one or more glass cores 110 according to any of the embodiments disclosed herein. A handheld communication device or a laptop communication device may be an example of the communication device 1800. Any suitable component of the communication device 1800 may include one or more of the microelectronic components 100, IC packages 1720, 1724, IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. In particular, any suitable component of the communication device 1800 may include one or more glass cores 110 as described herein, for example, as part of a microelectronic component 100 as described herein. In Figure 26 FIG. illustrates a plurality of components as included in the communication device 1800, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the communication device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system - on - a - chip (SoC) die.

[0129] Additionally, in various embodiments, the communication device 1800 may not include Figure 26One or more of the components illustrated in the figure, but the communication device 1800 may include interface circuitry for coupling to one or more components. For example, the communication device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the communication device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0130] The communication device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The communication device 1800 may include a memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM DRAM), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or hard disk drives. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. The memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).

[0131] In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured to manage wireless communication for transmitting data to and from the communication device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not include any wires, although in some embodiments they may not. The communication module 1812 may be or may include any one of the microelectronic components 100 disclosed herein.

[0132] The communication module 1812 may implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project along with any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which stands for the acronym of Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed the compliance and interoperability tests of the IEEE 802.16 standard. The communication module 1812 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication module 1812 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication module 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivative protocols, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication module 1812 may operate according to other wireless protocols. The communication device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions). The antenna 1822 may include one or more microelectronic components 100 and / or one or more glass cores 110 as described herein, for example, as part of the microelectronic components 100 described herein.

[0133] In some embodiments, the communication module 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As pointed out above, the communication module 1812 may include multiple communication modules. For example, a first communication module 1812 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication module 1812 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or the like. In some embodiments, the first communication module 1812 may be dedicated to wireless communications, and the second communication module 1812 may be dedicated to wired communications. In some embodiments, the communication module 1812 may support millimeter-wave communications.

[0134] The communication device 1800 may include a battery / power circuit 1814. The battery / power circuit 1814 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the communication device 1800 to an energy source (e.g., AC line power) separate from the communication device 1800.

[0135] The communication device 1800 may include a display device 1806 (or a corresponding interface circuit, as discussed above). The display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0136] The communication device 1800 may include an audio output device 1808 (or a corresponding interface circuit, as discussed above). The audio output device 1808 may include any device that generates an auditory indicator, such as a speaker, headphones, or earbuds.

[0137] The communication device 1800 may include an audio input device 1824 (or a corresponding interface circuit, as discussed above). The audio input device 1824 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0138] The communication device 1800 may include a GPS device 1818 (or a corresponding interface circuit, as discussed above). As is known in the art, the GPS device 1818 may communicate with a satellite-based system and may receive the location of the communication device 1800.

[0139] The communication device 1800 may include another output device 1810 (or a corresponding interface circuit, as discussed above). Examples of the another output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0140] The communication device 1800 may include another input device 1820 (or a corresponding interface circuit, as discussed above). Examples of the another input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a Radio Frequency Identification (RFID) reader.

[0141] The communication device 1800 can have any desired form factor, such as a handheld or mobile communication device (e.g., a cellular phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop communication device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable communication device. In some embodiments, the communication device 1800 can be any other electronic device that processes data.

[0142] The following paragraphs provide examples of various embodiments disclosed herein.

[0143] Example 1 provides a microelectronic component that includes a glass core (e.g., a glass layer including a rectangular prism volume), the glass core having a first face, a second face opposite the first face, an edge between an end of the first face and an end of the second face, and an edge region (e.g., less than about 5% or less than about 1%) extending from the edge into the glass core a distance of less than about 10% of the width of the glass core (the width being measured in a direction substantially parallel to the first face and perpendicular to a line at which the edge intersects the first face); and an opening in the edge region that extends from the first face toward the second face and includes a filling material.

[0144] Example 2 provides the microelectronic component according to Example 1, wherein the filling material includes an organic insulator material.

[0145] Example 3 provides the microelectronic component according to Example 1 or 2, wherein the filling material includes an inorganic insulator material.

[0146] Example 4 provides the microelectronic component according to any of the preceding examples, wherein the filling material includes a polymer.

[0147] Example 5 provides the microelectronic component according to any of the preceding examples, wherein the filling material includes ABF.

[0148] Example 6 provides the microelectronic component according to any of the preceding examples, wherein the Young's modulus of the filling material is less than about 10 GPa.

[0149] Example 7 provides the microelectronic component according to any of the preceding examples, wherein the Poisson's ratio of the filling material is less than about 0.25.

[0150] Example 8 provides the microelectronic component according to any of the preceding examples, wherein the CTE of the filling material is less than about 15 ppm / K, e.g., less than about 10 ppm / K or less than about 5 ppm / K.

[0151] Example 9 provides a microelectronic component according to any of the foregoing examples, wherein the filling material comprises a conductive material.

[0152] Example 10 provides a microelectronic component according to any of the foregoing examples, wherein the filling material comprises a metal.

[0153] Example 11 provides a microelectronic component according to any of the foregoing examples, wherein the filling material comprises a self-healing material.

[0154] Example 12 provides a microelectronic component according to Example 11, wherein the self-healing material comprises a matrix material and particles dispersed in the matrix material, and the particles contain a self-healing agent.

[0155] Example 13 provides a microelectronic component according to Example 12, wherein the self-healing material comprises a polymer.

[0156] Example 14 provides a microelectronic component according to Example 12 or 13, wherein the self-healing agent comprises poly(urea-formaldehyde) (PUF), polyurethane, poly(melamine-urea-formaldehyde) (PMUF), or poly(melamine-formaldehyde) (PMF).

[0157] Example 15 provides a microelectronic component according to any one of Examples 12-14, wherein the matrix material comprises a thermosetting material (e.g., one or more of phenolic resin, alkyd resin, vinyl ester, unsaturated polyester, polyurethane, or aminoplast).

[0158] Example 16 provides a microelectronic component according to any of Examples 1-15, wherein the opening is a groove extending parallel to the edge.

[0159] Example 17 provides a microelectronic component according to Example 16, wherein the groove extends from the first surface to a depth between approximately 51% and 60% of the glass core thickness.

[0160] Example 18 provides a microelectronic component according to Example 16, wherein the groove extends from the first surface to a depth between approximately 60% and 80% of the glass core thickness.

[0161] Example 19 provides a microelectronic component according to any of Examples 1-15, wherein: the opening is a first opening, the groove is a first groove, the microelectronic component further comprises a second opening in the edge region, the second opening extends from the second surface towards the first surface and comprises a filling material, and the second opening is a second groove extending parallel to the edge.

[0162] Example 20 provides a microelectronic component according to Example 19, wherein the covered area of the first trench (e.g., the projection on the first and / or second faces of the glass core) is offset with respect to the covered area of the second trench.

[0163] Example 21 provides a microelectronic component according to Example 19 or 20, wherein the trench extends from the second face to a depth between approximately 51% and 60% of the glass core thickness.

[0164] Example 22 provides a microelectronic component according to Example 19 or 20, wherein the trench extends from the second face to a depth between approximately 60% and 80% of the glass core thickness.

[0165] Example 23 provides a microelectronic component according to any one of Examples 16 - 22, wherein the cross-sectional profile of the trench is semi-circular.

[0166] Example 24 provides a microelectronic component according to any one of Examples 16 - 22, wherein the cross-sectional profile of the trench is elliptical.

[0167] Example 25 provides a microelectronic component according to any one of Examples 16 - 22, wherein the cross-sectional profile of the trench is polygonal.

[0168] Example 26 provides a microelectronic component according to any one of Examples 1 - 15, wherein the opening is one of a plurality of openings in an edge region extending parallel to the edge.

[0169] Example 27 provides a microelectronic component according to Example 26, wherein the individual opening is an opening according to any one of Examples 16 - 25.

[0170] Example 28 provides a microelectronic component according to any one of Examples 1 - 15, wherein the opening extends between the first face and the second face.

[0171] Example 29 provides a microelectronic component according to Example 28, wherein the opening is one of a plurality of openings in an edge region extending parallel to the edge.

[0172] Example 30 provides a microelectronic component according to Example 29, wherein the plurality of openings are aligned at the edge.

[0173] Example 31 provides a microelectronic component comprising a glass core having a first face and a second face (e.g., a glass layer including a rectangular prism), wherein the second face is opposite the first face; and an anchor, comprising a first pad above the first face of the glass core, a second pad above the second face of the glass core, and a pin, wherein the pin is attached to the first pad and extends from the first pad into the glass core.

[0174] Example 32 provides a microelectronic component according to Example 31, wherein the pins are in blind vias in the glass core (i.e., the pins do not reach the second side of the glass core).

[0175] Example 33 provides a microelectronic component according to Example 32, wherein the pins extend through the glass core and are further attached to a second pad.

[0176] Example 34 provides a microelectronic component according to any one of Examples 31-33, wherein the anchor includes a material having a negative CTE.

[0177] Example 35 provides a microelectronic component according to any one of Examples 31-34, wherein the anchor includes an insulating material, a polymer, or ABF.

[0178] Example 36 provides a microelectronic component according to any one of Examples 31-35, wherein the anchor includes metal.

[0179] Example 37 provides a microelectronic component according to Example 36, wherein the anchor is electrically isolated from all ground, signal, and power paths.

[0180] Example 38 provides a microelectronic component according to any one of Examples 31-37, wherein: the anchor is in the edge region of the glass core, and the edge region is the region between the edge of the glass core and a plane parallel to the edge, the plane being separated from the edge by a distance less than about 10% (e.g., less than about 5% or less than about 1%) of the width of the glass core (the width being measured in a direction substantially parallel to the first side and perpendicular to the line at which the edge intersects the first side).

[0181] Example 39 provides a microelectronic component according to Example 38, wherein the first pad is larger in size in a direction perpendicular to the edge of the glass core than the pins are in a direction perpendicular to the edge of the glass core.

[0182] Example 40 provides a microelectronic component according to Example 39, wherein the first pad is larger in size in a direction parallel to the edge of the glass core than it is in a direction perpendicular to the edge of the glass core.

[0183] Example 41 provides a microelectronic component including a glass core having a first side and a second side (e.g., a glass layer including a rectangular prism), wherein the second side is opposite the first side; and a daisy chain structure embedded in the glass core near the edge of the glass core, the daisy chain structure having a first portion in a recess in the first side and a second portion in a recess in the second side.

[0184] Example 42 provides a microelectronic component according to Example 41, wherein the distance between the edge and the daisy chain structure is less than about 10% of the width of the glass core (e.g., less than about 5% or less than about 1%).

[0185] Example 43 provides a microelectronic component according to Example 41 or 42, wherein the daisy chain structure further includes a third portion embedded in the glass core, and wherein the individual third portions are connected to the ends of one of the first portions and the ends of one of the second portions.

[0186] Example 44 provides a microelectronic component according to Example 43, wherein the third portion is substantially perpendicular to the first face.

[0187] Example 45 provides a microelectronic component according to Example 43, wherein the third portion forms an angle of less than 90 degrees with respect to the first face.

[0188] Example 46 provides a microelectronic component according to any one of Examples 41-45, wherein: the daisy chain structure is one of a plurality of daisy chain structures, the edge is one of a plurality of edges of the glass core, and the daisy chain structures are connected in a loop along the plurality of edges of the glass core.

[0189] Example 47 provides a microelectronic component according to any one of Examples 41-46, wherein the daisy chain structure includes a polymer.

[0190] Example 48 provides a microelectronic component according to any one of Examples 41-47, wherein the daisy chain structure includes an insulator material.

[0191] Example 49 provides a microelectronic component according to any one of Examples 41-48, wherein the daisy chain structure includes ABF.

[0192] Example 50 provides a microelectronic component according to any one of Examples 41-49, wherein the daisy chain structure includes metal.

[0193] Example 51 provides a microelectronic component, comprising: a glass core (e.g., a glass layer including a rectangular prism), the glass core having a first face, a second face opposite the first face, and an edge between the ends of the first face and the ends of the second face; and a clamp structure surrounding the edge, the clamp structure having a first portion at the first face, a second portion at the second face, and a third portion at the edge, wherein the third portion is attached to the first portion and the second portion.

[0194] Example 52 provides a microelectronic component according to Example 51, wherein the third portion is substantially continuous with the first portion and the second portion.

[0195] Example 53 provides a microelectronic component according to Example 51 or 52, wherein the first portion extends above the first side to a distance from the edge that is less than about 10% of the width of the glass core (e.g., less than about 5% or less than about 1%).

[0196] Example 54 provides a microelectronic component according to any one of Examples 51-53, wherein the clamp structure comprises a material having a negative CTE.

[0197] Example 55 provides a microelectronic component according to any one of Examples 51-54, wherein the clamp structure extends along at least 50% of the edge length.

[0198] Example 56 provides a microelectronic component according to any one of Examples 51-55, wherein the clamp structure extends along the entire length of the edge.

[0199] Example 57 provides a microelectronic component according to any one of Examples 51-56, wherein: the clamp structure is one of a plurality of clamp structures, the edge is one of a plurality of edges of the glass core, and the clamp structures are connected in a loop along the plurality of edges of the glass core.

[0200] Example 58 provides a microelectronic component according to any one of Examples 51-56, wherein the clamp structure is one of a plurality of clamp structures surrounding the edge.

[0201] Example 59 provides a microelectronic component according to Example 58, wherein the clamp structures of the plurality of clamp structures are substantially discontinuous from each other.

[0202] Example 60 provides a microelectronic component according to any one of the foregoing examples, wherein: the microelectronic component includes a glass panel, the glass panel includes a plurality of glass cores, and the glass core is one of the plurality of glass cores.

[0203] Example 71 provides a microelectronic component according to any one of the foregoing examples, wherein the glass core is a solid glass layer.

[0204] Example 72 provides a microelectronic component according to any one of the foregoing examples, wherein the cross-section of the glass core in a plane perpendicular to the surface of the component is substantially rectangular.

[0205] Example 73 provides a microelectronic component according to any one of the foregoing examples, wherein the cross-section of the glass core in a plane parallel to the surface of the component is substantially rectangular.

[0206] Example 74 provides a microelectronic component according to any one of the foregoing examples, wherein the glass core is a glass layer comprising at least 23% silicon by weight.

[0207] Example 75 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer comprising oxygen in an amount of at least 26% by weight.

[0208] Example 76 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer comprising silicon in an amount of at least 23% by weight and oxygen in an amount of at least 26% by weight.

[0209] Example 77 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer comprising aluminum in an amount of at least 5% by weight.

[0210] Example 78 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer that does not include an organic binder or organic material.

[0211] Example 79 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer having a thickness in the range of 50 micrometers (μm) to 1.4 millimeters (mm), a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0212] Example 80 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer having a thickness in the range of 50 μm to 1.4 mm.

[0213] Example 81 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer having a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0214] Example 82 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer comprising a rectangular prism volume.

[0215] Example 83 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer comprising a rectangular prism volume having a first side and a second side perpendicular to the first side, the length of the first side being in the range of 10 mm to 250 mm, and the length of the second side being in the range of 10 mm to 250 mm.

[0216] Example 84 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer comprising a rectangular prism volume and a through-hole extending from a first side of the rectangular prism volume to a second side of the rectangular prism volume, the through-hole comprising metal.

[0217] The above description of the illustrated implementations of the present disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific implementations and examples of the present disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be recognized by those of ordinary skill in the relevant art. These modifications may be made to the present disclosure in light of the above detailed description.

Claims

1. A microelectronic assembly comprising: a glass core having a first face, a second face opposite the first face, an edge between an end of the first face and an end of the second face, and an edge region extending from the edge into the glass core a distance less than about 10% of a width of the glass core; and An opening in the edge region extends from the first face toward the second face and includes a filling material. 2 . The microelectronic assembly of claim 1 , wherein the fill material comprises an inorganic insulator material. The microelectronic assembly of claim 1 , wherein the fill material comprises a polymer.

4. The microelectronic assembly of claim 1, wherein the Young's modulus of the filler material is less than about 10 GPa.

5. The microelectronic assembly of claim 1, wherein the fill material comprises metal, wherein the metal is electrically isolated from all signal paths, ground paths, and power paths in the microelectronic assembly.

6. The microelectronic assembly of claim 1, wherein the filling material comprises a matrix material and particles dispersed in the matrix material, the particles containing a self-healing agent.

7. The microelectronic assembly of claim 6, wherein the self-healing agent comprises poly(urea-formaldehyde), polyurethane, poly(melamine-urea-formaldehyde), or poly(melamine-formaldehyde).

8. A microelectronic assembly as claimed in claim 6, wherein the matrix material comprises a thermoset material.

9. The microelectronic assembly of claim 6, wherein the fill material or glass core comprises ruthenium.

10. A microelectronic assembly as claimed in any one of claims 1 to 9, wherein the opening is a groove extending parallel to the edge.

11. The microelectronic assembly of claim 10, wherein the grooves extend from the first face to a depth that is less than about 60% of the thickness of the glass core.

12. The microelectronic assembly of claim 10, wherein: The opening is a first opening, The groove is a first groove, The microelectronic assembly further includes a second opening in the edge region, the second opening extending from the second face toward the first face and including a filler material, and The second opening is a second trench extending parallel to the edge, wherein the footprint of the first trench is offset with respect to the footprint of the second trench.

13. A microelectronic assembly as claimed in any one of claims 1 to 9, wherein the opening extends between the first side and the second side.

14. The microelectronic assembly of claim 13, wherein the opening is one of a plurality of openings in an edge region extending parallel to the edge.

15. The microelectronic assembly of claim 14, wherein the plurality of openings are aligned at an edge.

16. A microelectronic assembly comprising: a glass core having a first side and a second side, wherein the second side is opposite to the first side; and An anchor includes a first pad over a first side of a glass core, a second pad over a second side of the glass core, and a pin, wherein the pin is attached to the first pad and extends from the first pad into the glass core, and wherein the anchor includes a material having a negative coefficient of thermal expansion.

17. The microelectronic assembly of claim 16, wherein the pins are in blind vias in the glass core.

18. A microelectronic assembly according to any one of claims 16 to 17, wherein: The anchor is in the edge region of the glass core, and The edge region is a region between an edge of the glass core and a plane parallel to the edge, the plane being separated from the edge by a distance less than about 10% of the width of the glass core.

19. A microelectronic assembly comprising: a glass core having a first side and a second side, wherein the second side is opposite to the first side; and A daisy chain structure is embedded in the glass core near an edge of the glass core, the daisy chain structure comprising a polymer and having a first portion in the recess in the first side and a second portion in the recess in the second side.

20. The microelectronic assembly of claim 19, wherein: The daisy chain structure is one of a plurality of daisy chain structures, The edge is one of a plurality of edges of the glass core, and The daisy chain structure is connected into a loop along the plurality of edges of the glass core.

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