Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate; a first unit structure and a second unit structure on the substrate; a molding layer covering the first unit structure and the second unit structure; and a conductive via within the molding layer and electrically connected to the substrate, in which each of the first cell structure and the second cell structure includes: an interposer; a lower unit chip; an upper unit chip; a lower redistribution layer; and an upper redistribution layer, in which each of the lower unit chip and the upper unit chip has an active surface facing the interposer and a passive surface opposite the active surface, and in which the passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package having a reduced thickness and a method of manufacturing the same. Background Art

[0002] With the continuous progress of the electronics industry, there is an increasing demand for high performance, fast response speed, and miniaturization of electronic components. To meet such requirements, semiconductor packaging technologies have developed packages with multiple semiconductor chips stacked on a single package substrate and a package on package (POP) structure with multiple packages stacked.

[0003] For example, a semiconductor package may include multiple stacked semiconductor chips electrically connected to a substrate through a wire bonding process. However, to prevent lead leakage or damage to the leads and chips during laser marking, the wire bonding process requires additional space within the package. Such space requirements result in an increase in the thickness of the package.

[0004] Although the Through Silicon Via (TSV) technology can help reduce the package thickness to some extent, its manufacturing process is complex and prone to defects, which can have a negative impact on the overall reliability of the package. Summary of the Invention

[0005] Example embodiments of the present disclosure provide a semiconductor package having a reduced thickness and enhanced reliability and a method of manufacturing the same.

[0006] Example embodiments of the present disclosure provide a semiconductor package including: a substrate; a first unit structure and a second unit structure stacked on the substrate in sequence; a molding layer located on the substrate and covering the first unit structure and the second unit structure; and conductive vias located within the molding layer and electrically connected to the substrate, wherein each of the first unit structure and the second unit structure includes: an interposer; a lower unit chip located below the interposer; an upper unit chip located above the interposer; a lower redistribution layer located between the lower unit chip and the interposer and electrically connected to the interposer, the lower unit chip, and the conductive vias; an upper redistribution layer located between the upper unit chip and the interposer and electrically connected to the interposer, the upper unit chip, and the conductive vias, wherein each of the lower unit chip and the upper unit chip has an active surface facing the interposer and a passive surface opposite to the active surface, and wherein the passive surface of the upper unit chip of the first unit structure faces the passive surface of the lower unit chip of the second unit structure.

[0007] Example embodiments of the present disclosure provide a semiconductor package, which includes: a substrate; a first chip located in a recess of the substrate; a first unit structure located above the first chip; a second unit structure located above the first unit structure; a molding layer located on the substrate and covering the first unit structure and the second unit structure; and conductive vias located in the molding layer and electrically connected to the substrate. Wherein, each of the first unit structure and the second unit structure includes: a lower unit chip and an upper unit chip, both including an active surface and a passive surface opposite to the active surface; a conductive bump located between the lower unit chip and the upper unit chip and directly connected to one of the lower unit chip and the upper unit chip; and a redistribution layer located between the lower unit chip and the upper unit chip and directly connected to the conductive bump, the conductive via, and the other of the lower unit chip and the upper unit chip. Wherein, in each of the first unit structure and the second unit structure, the active surface of the lower unit chip and the active surface of the upper unit chip face each other, and wherein, the passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other.

[0008] Example embodiments of the present disclosure provide a method for manufacturing a semiconductor package, the method including the following steps: preparing a first unit structure and a second unit structure, each of the first unit structure and the second unit structure including: an interposer; a lower unit chip located below the interposer; an upper unit chip located above the interposer; a lower redistribution layer located between the lower unit chip and the interposer and electrically connected to the interposer, the lower unit chip, and the conductive via; and an upper redistribution layer located between the upper unit chip and the interposer and electrically connected to the interposer, the upper unit chip, and the conductive via. Each of the lower unit chip and the upper unit chip has an active surface facing the interposer and a passive surface opposite to the active surface; disposing the first unit structure on the substrate; disposing the second unit structure on the first unit structure such that the passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other; forming a molding layer on the substrate to cover the first unit structure and the second unit structure, and forming conductive vias in the molding layer and electrically connecting the conductive vias to the substrate.

[0009] Example embodiments of the present disclosure provide a method for manufacturing a semiconductor package, wherein the step of preparing the first unit structure and the second unit structure includes: forming a lower redistribution layer and an upper redistribution layer on the lower surface and the upper surface of the interposer respectively; attaching a lower pattern layer of the lower unit chip to the lower redistribution layer, and attaching an upper pattern layer of the upper unit chip to the upper redistribution layer.

[0010] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package. The step of disposing a first unit structure on a substrate includes: bonding a passive surface of a lower unit chip of the first unit structure to a top surface of the substrate using an adhesive layer.

[0011] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package. The step of disposing a second unit structure on the first unit structure includes: bonding a passive surface of a lower unit chip of the second unit structure to a passive surface of an upper unit chip of the first unit structure using an adhesive layer.

[0012] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package. The step of forming a molding layer and conductive vias includes: forming a first molding layer covering the first unit structure and the second unit structure on the substrate; forming conductive vias penetrating the first molding layer to electrically connect the conductive vias to a lower redistribution layer and an upper redistribution layer; and forming a second molding layer on the first molding layer and the conductive vias.

[0013] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package. The method includes the following steps: preparing a first unit structure and a second unit structure, each of the first unit structure and the second unit structure including: a lower unit chip and an upper unit chip, both including an active surface and a passive surface opposite to the active surface; a conductive bump located between the lower unit chip and the upper unit chip and directly connected to one of the lower unit chip and the upper unit chip; a redistribution layer located between the lower unit chip and the upper unit chip and directly connected to the conductive bump, the conductive vias, and the other of the lower unit chip and the upper unit chip; disposing the first chip in a groove of the substrate; disposing the first unit structure on the first chip; disposing the second unit structure on the first unit structure such that the passive surface of the upper unit chip of the first unit structure faces the passive surface of the lower unit chip of the second unit structure; forming a molding layer covering the first unit structure and the second unit structure on the substrate and forming conductive vias in the molding layer to electrically connect the conductive vias to the substrate.

[0014] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package. The step of preparing the first unit structure and the second unit structure includes: forming a redistribution layer on an active surface of the lower unit chip; forming a conductive bump on an active surface of the upper unit chip; and attaching the conductive bump to the redistribution layer.

[0015] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package. The step of preparing the first unit structure and the second unit structure includes: forming a redistribution layer on an active surface of the upper unit chip; forming a conductive bump on an active surface of the lower unit chip; and attaching the conductive bump to the redistribution layer.

[0016] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package, wherein a first chip is disposed on an upper surface of a substrate, and wherein the step of disposing the first chip on the upper surface of the substrate includes: forming bottom conductive bumps on an active surface of the first chip; and bonding the bottom conductive bumps to pads on a top surface of the substrate.

[0017] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package, wherein the step of disposing a first unit structure on the first chip includes: bonding a passive surface of a lower unit chip of the first unit structure to a top surface of the first chip using an adhesive layer.

[0018] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package, wherein the first chip is disposed in a groove of a substrate, and wherein the step of disposing the first chip in the groove of the substrate includes: placing the first chip in the groove of the substrate such that an active surface of the first chip faces an opening side of the groove; forming bottom conductive bumps on the active surface of the first chip; bonding a bottom interposer to the first chip through the bottom conductive bumps; and filling the groove with a sealing material to form a bottom molding layer covering the first chip.

[0019] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package, wherein the step of disposing a first unit structure on the first chip includes: bonding a passive surface of a lower unit chip of the first unit structure to a top surface of the bottom interposer using an adhesive layer.

[0020] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package, wherein the step of disposing a second unit structure on the first unit structure includes: bonding a passive surface of a lower unit chip of the second unit structure to a passive surface of an upper unit chip of the first unit structure using an adhesive layer.

[0021] Example embodiments of the present disclosure provide a method of manufacturing a semiconductor package, wherein the steps of forming a molding layer and conductive vias include: forming a first molding layer covering the first unit structure and the second unit structure on the substrate; forming conductive vias penetrating the first molding layer such that the conductive vias are electrically connected to a lower redistribution layer and an upper redistribution layer; and forming a second molding layer on the first molding layer and the conductive vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features of the present disclosure will become apparent from the following detailed description of some example embodiments taken in conjunction with the accompanying drawings. In the drawings, the same reference numerals will always indicate the same elements. In the drawings: Figure 1 is a cross-sectional view showing a semiconductor package according to a first example embodiment of the present disclosure; Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 are cross-sectional views showing intermediate stages of a method of manufacturing a semiconductor package according to a first exemplary embodiment of the present disclosure; Figure 8 , Figure 9 and Figure 10 are cross-sectional views showing intermediate stages of another method of manufacturing a semiconductor package according to a first exemplary embodiment of the present disclosure; Figure 11 is a cross-sectional view showing a semiconductor package according to a second exemplary embodiment of the present disclosure; Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 are cross-sectional views showing intermediate stages of a method of manufacturing a semiconductor package according to a second exemplary embodiment of the present disclosure; Figure 22 is a cross-sectional view showing a semiconductor package according to a third exemplary embodiment of the present disclosure; and Figure 23 , Figure 24 , Figure 25 , Figure 26 and Figure 27 are cross-sectional views showing intermediate stages of a method of manufacturing a semiconductor package according to a third exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. However, the present disclosure may have various forms and should not be limited to the specific embodiments described herein. Instead, these embodiments are provided to ensure a thorough and complete understanding of the disclosure and to fully convey the scope of the present disclosure to those skilled in the art. For clarity, the dimensions of layers and regions in the drawings may be exaggerated.

[0024] For ease of illustration, certain details may be omitted from the drawings. Therefore, the drawings should not be construed in any way as limiting the scope of the present disclosure.

[0025] For ease of description, spatially relative terms such as "below", "beneath", "under", "lower", "on", "above", "over", "upper" and like terms are used to indicate a relationship between elements or features shown in the drawings. These terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" another element may instead be oriented "above" the other element. Similarly, the term "below" can refer to both "above" and "below" depending on the orientation. The device may also be positioned at different angles (rotated 90 degrees or in orientation), and the spatially relative descriptors may be interpreted accordingly.

[0026] It will be understood that when an element such as a layer, film, region, zone or substrate is referred to as being "on" or "above" another element, the element can be directly on the other element or there can also be intervening elements. When an element is referred to as being "directly on" another element, there are no intervening elements. Further, in this specification, the words "on" or "above" can refer to being positioned above or disposed below a target portion and do not necessarily refer to being placed on the upper side of the target portion with respect to the direction of gravity.

[0027] Although the terms "same", "equal" or "equivalent" are used in the description of the exemplary embodiments, it should be understood that there can be minor variations. Thus, when an element or value is referred to as being the same as another element or value, it should be interpreted to mean that the element or value is the same within an acceptable manufacturing or operating tolerance range (e.g., ±10%).

[0028] When the terms "about" or "substantially" are used in this specification in connection with a numerical value, they refer to the stated value including manufacturing or operating tolerances (e.g., ±10%). Further, when the terms "about" or "substantially" are used in connection with a geometric shape, they imply that absolute precision is not required and reasonable variations within the scope of the present disclosure are allowed. Additionally, whether a numerical value or shape is modified with "about" or "substantially", they should be interpreted to include manufacturing or operating tolerances (e.g., ±10%) near the stated numerical value or shape.

[0029] Hereinafter, a semiconductor package and a method of manufacturing the same according to an exemplary embodiment of the present disclosure will be described.

[0030] The present disclosure relates to a semiconductor package and a method of manufacturing the same, which is designed to reduce the package thickness while improving reliability and electrical performance. The package is characterized by a stacked unit structure, each unit structure including an interposer, a lower die chip, an upper unit chip, and a redistribution layer for electrical connection. Instead of traditional wire bonding or through-silicon vias (TSVs), the present disclosure uses conductive vias within a molding layer to establish electrical connections, thereby simplifying manufacturing and increasing the yield. In addition, the passive surfaces of adjacent unit structures are joined together to form a compact and stable stack that maintains electrical integrity.

[0031] By utilizing thin chips and bonding layers to achieve structural stability, this design significantly reduces the total package height while improving mechanical strength and reliability. Some embodiments directly bond a base chip (e.g., a system-on-chip (SoC) chip) onto or within a substrate, thereby further minimizing the thickness. The scalability of this method allows for additional stacked unit structures, making it an ideal choice for high-performance memory devices, SoC applications, and advanced computing solutions. Compared with traditional semiconductor packaging technologies, this innovation ensures higher bandwidth, improved electrical performance, and better manufacturability.

[0032] Figure 1 is a cross-sectional view showing a semiconductor package 100 according to a first exemplary embodiment of the present disclosure.

[0033] Referring to Figure 1 , the semiconductor package 100 according to the first exemplary embodiment of the present disclosure includes a substrate SUB, a first unit structure US1, a second unit structure US2, a molding layer MD, and a conductive via VIA.

[0034] The substrate SUB can be any substrate commonly used for manufacturing semiconductor packages. In an exemplary embodiment, the substrate SUB can be formed of an insulating material such as quartz, glass, silicon nitride, silicon oxynitride, or an organic resin. In an exemplary embodiment, the substrate SUB can be formed of a semiconductor material. For example, the substrate SUB can be a silicon substrate or can include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0035] The substrate SUB can have a conductive path CW. For example, the conductive path CW can include pads provided on the top surface of the substrate SUB and wirings and vias provided within the substrate SUB.

[0036] The first unit structure US1 and the second unit structure US2 can be sequentially stacked on the substrate SUB. As Figure 1As shown, the first unit structure US1 can be disposed on the substrate SUB, and the second unit structure US2 can be disposed on the first unit structure US1. For example, the first unit structure US1 can be bonded to the top surface of the substrate SUB through the adhesive layer BL.

[0037] Each of the first unit structure US1 and the second unit structure US2 can be a chip structure with double-sided patterns, and the chip structure with double-sided patterns can include an interposer and unit chips located on both sides of the interposer. For example, as Figure 1 shown, each of the first unit structure US1 and the second unit structure US2 can include an interposer ITP, a lower redistribution layer LRD and an upper redistribution layer URD respectively located on both sides of the interposer ITP. In addition, each of the first unit structure US1 and the second unit structure US2 can include a lower unit chip LC and an upper unit chip UC located on both sides of the interposer ITP.

[0038] Specifically, as Figure 1 shown, the lower redistribution layer LRD can be located below the interposer ITP, and the lower unit chip LC can be located below the lower redistribution layer LRD; the upper redistribution layer URD can be located above the interposer ITP, and the upper unit chip UC can be located above the upper redistribution layer URD. In other words, the lower unit chip LC and the upper unit chip UC can be respectively located on the lower surface and the upper surface of the interposer ITP, the lower redistribution layer LRD can be located between the lower surface of the interposer ITP and the lower unit chip LC, and the upper redistribution layer URD can be located between the upper surface of the interposer ITP and the upper unit chip UC.

[0039] The interposer ITP can be a silicon interposer. Conductive paths including pads, vias, wirings, etc. can be provided in the interposer ITP so that elements located on both sides of the interposer ITP can transmit information to each other.

[0040] The lower redistribution layer LRD and the upper redistribution layer URD can be respectively provided between the lower unit chip LC and the interposer ITP and between the upper unit chip UC and the interposer ITP. Each of the lower redistribution layer LRD and the upper redistribution layer URD can include pads, vias, wirings and insulating layers. The lower redistribution layer LRD and the upper redistribution layer URD can be electrically connected to the wirings in the interposer ITP.

[0041] The lower unit chip LC and the upper unit chip UC can be chips with relatively thin thicknesses. For example, the thicknesses of the upper unit chip UC and the lower unit chip LC can be less than or equal to 25 μm.

[0042] Each of the lower unit chip LC and the upper unit chip UC may have an active surface facing the interposer ITP and a passive surface opposite to the active surface. As Figure 1 shown, the passive surface of the upper unit chip UC of the first unit structure US1 may face the passive surface of the lower unit chip LC of the second unit structure US2, and they may be joined to each other through the bonding layer BL.

[0043] Each of the lower unit chip LC and the upper unit chip UC may include a substrate layer and a pattern layer. For example, as Figure 1 shown, the lower unit chip LC may include a lower substrate layer LBS and a lower pattern layer LPT, and the upper unit chip UC may include an upper substrate layer UBS and an upper pattern layer UPT. In the lower unit chip LC, the lower substrate layer LBS may be located below the lower pattern layer LPT, and in the upper unit chip UC, the upper substrate layer UBS may be located above the upper pattern layer UPT.

[0044] The lower pattern layer LPT and the upper pattern layer UPT may be located on two opposite surfaces of the interposer ITP. In other words, the lower pattern layer LPT and the upper pattern layer UPT may be located on the lower redistribution layer LRD and the upper redistribution layer URD respectively. For example, as Figure 1 shown, the lower pattern layer LPT is located below the lower redistribution layer LRD, and the lower redistribution layer LRD is located between the lower pattern layer LPT and the interposer ITP. The upper pattern layer UPT is located above the upper redistribution layer URD, and the upper redistribution layer URD is located between the upper pattern layer UPT and the interposer ITP.

[0045] The lower pattern layer LPT may be electrically connected to the lower redistribution layer LRD, and the upper pattern layer UPT may be electrically connected to the upper redistribution layer URD. For example, the lower pattern layer LPT may be in direct contact with the lower redistribution layer LRD, and the upper pattern layer UPT may be in direct contact with the upper redistribution layer URD. Therefore, the lower unit chip LC may be electrically connected to the lower redistribution layer LRD through the lower pattern layer LPT and then to the interposer ITP. The upper unit chip UC may be electrically connected to the upper redistribution layer URD through the upper pattern layer UPT and then to the interposer ITP. Thus, the lower unit chip LC and the upper unit chip UC may be electrically connected to each other via the lower redistribution layer LRD, the interposer ITP, and the upper redistribution layer URD, allowing mutual information transmission.

[0046] Each of the lower pattern layer LPT and the upper pattern layer UPT may include components such as transistors, capacitors, resistors, etc., and an insulating layer covering these components.

[0047] The lower substrate layer LBS and the upper substrate layer UBS can be located on two opposite surfaces of the interposer layer ITP. In other words, the lower substrate layer LBS and the upper substrate layer UBS can be located on the lower pattern layer LPT and the upper pattern layer UPT, respectively. For example, as Figure 1 shown in, the lower substrate layer LBS is located below the lower pattern layer LPT, and the lower pattern layer LPT is located between the lower substrate layer LBS and the lower redistribution layer LRD. The upper substrate layer UBS is located above the upper pattern layer UPT, and the upper pattern layer UPT is located between the upper substrate layer UBS and the upper redistribution layer URD.

[0048] The lower substrate layer LBS and the upper substrate layer UBS can be substrates for forming the lower pattern layer LPT and the upper pattern layer UPT, respectively. Each of the lower substrate layer LBS and the upper substrate layer UBS can be formed of a semiconductor material. For example, each of the lower substrate layer LBS and the upper substrate layer UBS can be a silicon substrate, or can include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0049] As described above, the first unit structure US1 and the second unit structure US2 can be configured to include an interposer layer and a double-sided pattern chip structure of redistribution layers and unit chips symmetrically disposed on both sides of the interposer layer. Each of the first unit structure US1 and the second unit structure US2 can be or include a dynamic random access memory (DRAM) chip or a system-on-chip (SoC) chip.

[0050] The molding layer MD can be disposed on the substrate SUB and cover the first unit structure US1 and the second unit structure US2. The molding layer MD can include an epoxy molding compound (EMC) or be formed of an epoxy molding compound (EMC).

[0051] The conductive via VIA can be disposed within the molding layer MD. For example, the conductive via VIA can penetrate a part of the molding layer MD and extend to the top surface of the substrate SUB. The conductive via VIA can be electrically connected to the conductive path CW of the substrate SUB. For example, the conductive via VIA can be in direct contact with the conductive path CW. In addition, the conductive via VIA can be electrically connected to the lower redistribution layer LRD and the upper redistribution layer URD of each of the first unit structure US1 and the second unit structure US2. For example, the conductive via VIA can be in direct contact with the lower redistribution layer LRD and the upper redistribution layer URD. Therefore, each of the first unit structure US1 and the second unit structure US2 can be electrically connected to the conductive path CW in the substrate SUB through the lower redistribution layer LRD, the upper redistribution layer URD, and the conductive via VIA.

[0052] As Figure 1As shown, the side surfaces of the lower redistribution layer LRD and the upper redistribution layer URD may contact the conductive vias VIA, and the widths of the lower redistribution layer LRD and the upper redistribution layer URD may each be equal to the distance between two conductive vias VIA. The side surface of the interposer ITP may also contact the conductive vias VIA, and the width of the interposer ITP may also be equal to the distance between two conductive vias VIA. The side surfaces of the lower pattern layer LPT and the upper pattern layer UPT and the side surfaces of the lower substrate layer LBS and the upper substrate layer UBS may be spaced apart from the conductive vias VIA. In this case, a gap may be formed between the conductive vias VIA and the side surfaces of the lower pattern layer LPT and the upper pattern layer UPT and the side surfaces of the lower substrate layer LBS and the upper substrate layer UBS. The widths of the lower pattern layer LPT and the upper pattern layer UPT and the widths of the lower substrate layer LBS and the upper substrate layer UBS may be less than the distance between two conductive vias VIA.

[0053] In an exemplary embodiment, the interposer ITP may have a first width, the lower redistribution layer LRD and the upper redistribution layer URD may have a second width, the lower pattern layer LPT and the upper pattern layer UPT may have a third width, and the lower substrate layer LBS and the upper substrate layer UBS may have a fourth width. The first width may be equal to the second width, the third width may be equal to the fourth width, and the first width and the second width may be greater than the third width and the fourth width.

[0054] In addition, as Figure 1 shown, the semiconductor package 100 may further include solder balls SB disposed on the bottom surface of the substrate SUB. The solder balls SB may serve as connection terminals for connecting the semiconductor package 100 to an external device. The solder balls SB may be electrically connected to a conductive path CW in the substrate SUB. For example, the solder balls SB may be in direct contact with the conductive path CW. Accordingly, each of the first unit structure US1 and the second unit structure US2 may be electrically connected to an external device through the solder balls SB.

[0055] Although the semiconductor package 100 is shown in Figure 1 as including only two unit structures, the present disclosure is not limited thereto. The semiconductor package 100 may include one or more additional unit structures stacked on the second unit structure US2, each additional unit structure having a structure substantially the same as that of the first unit structure US1 and the second unit structure US2.

[0056] The semiconductor package 100 according to the first exemplary embodiment of the present disclosure includes a unit structure configured as a double-sided patterned chip structure, and thus has a reduced thickness and improved reliability. For example, the semiconductor package 100 may be fabricated without using a wire bonding process or a through-silicon via process, thereby minimizing the thickness, improving the reliability, and enhancing the electrical performance (such as increased bandwidth).

[0057] Hereinafter, a method of manufacturing a semiconductor package 100 according to a first exemplary embodiment of the present disclosure will be described.

[0058] Figures 2 to 7 is a cross-sectional view showing an intermediate stage of a method of manufacturing a semiconductor package 100 according to a first exemplary embodiment of the present disclosure.

[0059] Referring to Figure 2 , a lower redistribution layer LRD and an upper redistribution layer URD may be formed on the lower surface and the upper surface of the interposer ITP, respectively. For example, the lower redistribution layer LRD and the upper redistribution layer URD may face each other.

[0060] For example, the lower redistribution layer LRD may be first formed on the lower surface of the interposer ITP, and then the upper redistribution layer URD may be formed on the upper surface of the interposer ITP, but the present disclosure is not limited thereto. For example, the upper redistribution layer URD may be first formed on the upper surface of the interposer ITP, and then the lower redistribution layer LRD may be formed on the lower surface of the interposer ITP.

[0061] For example, the lower redistribution layer LRD and the upper redistribution layer URD may be formed by the following steps: First, a metal layer is deposited on the surface of the interposer ITP, and then the metal layer is patterned by an etching process to form metal wirings. Then, an insulating layer is deposited to cover the metal wirings, and thereafter vias are formed in the insulating layer to establish electrical connections with the metal wirings. Finally, pads electrically connected to the vias are formed on the surface of the insulating layer. The lower redistribution layer LRD and the upper redistribution layer URD may include a single-layer structure or a multi-layer structure.

[0062] Referring to Figure 3 , a lower unit chip LC and an upper unit chip UC may be attached to the lower redistribution layer LRD and the upper redistribution layer URD, respectively, to obtain a unit structure (e.g., a first unit structure US1). This process may be repeated to obtain another unit structure (e.g., a second unit structure US2).

[0063] For example, a lower pattern layer LPT of the lower unit chip LC and an upper pattern layer UPT of the upper unit chip UC may be attached to pads of the lower redistribution layer LRD and pads of the upper redistribution layer URD, respectively. Such an arrangement ensures that the lower pattern layer LPT (or the active surface) of the lower unit chip LC and the upper pattern layer UPT (or the active surface) of the upper unit chip UC face the interposer ITP, and the passive surfaces of the lower unit chip LC and the upper unit chip UC face away from the interposer ITP.

[0064] For example, the attachment may be achieved by a metal bonding process (such as Cu-to-Cu bonding) or by a thermosonic process. However, the present disclosure is not limited thereto.

[0065] Referring to Figure 4 , the first unit structure US1 and the second unit structure US2 can be stacked on the substrate SUB sequentially.

[0066] For example, the first unit structure US1 can be attached to the substrate SUB through the adhesive layer BL, and the second unit structure US2 can be attached to the first unit structure US1 through the adhesive layer BL.

[0067] Referring to Figure 5 , a first sub-molding layer MD1 can be formed on the substrate SUB.

[0068] For example, a preliminary first sub-molding layer covering the first unit structure US1 and the second unit structure US2 can be formed on the substrate SUB first. Then, a planarization process can be performed on the preliminary first sub-molding layer to obtain the first sub-molding layer MD1. The first sub-molding layer MD1 can include an epoxy molding compound (EMC) or be formed of an epoxy molding compound (EMC). As Figure 5 shown, the top surface of the first sub-molding layer MD1 and the passive surface of the upper unit chip UC of the second unit structure US2 can be substantially coplanar. In other words, the top of the first sub-molding layer MD1 can be substantially coplanar with the top surface of the upper base layer UBS of the second unit structure US2. However, the present disclosure is not limited thereto, and the top surface of the first sub-molding layer MD1 can also be higher than the passive surface of the upper unit chip UC of the second unit structure US2. For example, the distance from the top surface of the first sub-molding layer MD1 to the top surface of the substrate SUB can be equal to or greater than the distance from the passive surface of the upper unit chip UC of the second unit structure US2 to the top surface of the substrate SUB. In other words, the distance from the top surface of the first sub-molding layer MD1 to the top surface of the substrate SUB can be equal to or greater than the distance from the top surface of the upper base layer UBS of the second unit structure US2 to the top surface of the substrate SUB.

[0069] Referring to Figure 6 , a conductive via VIA penetrating the first sub-molding layer MD1 can be formed.

[0070] For example, a drilling process can be performed on the first sub-molding layer MD1 first to form a through hole penetrating the first sub-molding layer MD1. The through hole can expose the side surfaces of the interposer ITP, the lower redistribution layer LRD, and the upper redistribution layer URD of each of the first unit structure US1 and the second unit structure US2. Then, an electroplating process can be performed in the through hole to form the conductive via VIA.

[0071] The conductive via VIA can be electrically connected to the conductive path CW of the substrate SUB, and can also establish electrical connections with the lower redistribution layer LRD and the upper redistribution layer URD of each of the first unit structure US1 and the second unit structure US2.

[0072] Referring to Figure 7 , a second sub-molding layer MD2 can be formed to cover the passive surface of the first sub-molding layer MD1, the conductive via VIA, and the upper unit chip UC of the second unit structure US2. The second sub-molding layer MD2 can be formed by a process substantially the same as the process for forming the first sub-molding layer MD1. The second sub-molding layer MD2 can include or be formed of an epoxy molding compound (EMC). The thickness of the second sub-molding layer MD2 can be referred to as the mold gap. The second sub-molding layer MD2 can have a relatively small thickness, which helps to reduce the overall thickness of the semiconductor package 100 compared to packages formed using wire bonding processes.

[0073] The second sub-molding layer MD2 can include the same material as the first sub-molding layer MD1. The first sub-molding layer MD1 and the second sub-molding layer MD2 can constitute the molding layer MD.

[0074] Next, referring to Figure 1 , solder balls SB can be formed on the bottom surface of the substrate SUB, thereby completing the manufacture of the semiconductor package 100 according to the first exemplary embodiment of the present disclosure.

[0075] Figures 8 to 10 is a cross-sectional view showing an intermediate stage of another method of manufacturing the semiconductor package 100 according to the first exemplary embodiment of the present disclosure.

[0076] Referring to Figure 8 , a redistribution layer (e.g., the lower redistribution layer LRD) can be formed on the unit chip (e.g., the lower unit chip LC).

[0077] Specifically, the unit chip (e.g., the lower unit chip LC) can be disposed on the carrier substrate CS. For example, the lower unit chip LC can be disposed within the carrier substrate CS such that the active surface (e.g., the surface of the lower pattern layer LPT) of the lower unit chip LC is coplanar with the surface of the carrier substrate CS. Then, the lower redistribution layer LRD can be formed on the surface of the lower pattern layer LPT and the carrier substrate CS.

[0078] Referring to Figure 9 , the interposer ITP can be attached to the lower redistribution layer LRD. For example, the pads on the surface of the interposer ITP can be bonded to the pads on the surface of the lower redistribution layer LRD.

[0079] Referring to Figure 10, an upper redistribution layer URD can be formed on the upper surface of the interposer ITP, and the upper unit chip UC can be attached to the upper redistribution layer URD, thereby obtaining a unit structure (e.g., the first unit structure US1). This process can be repeated to obtain another unit structure (e.g., the second unit structure US2).

[0080] Then, the carrier substrate CS can be removed from the obtained unit structure, and the processes of Figures 4 to 7 and Figure 1 can be performed to complete the manufacturing of the semiconductor package 100 according to the first exemplary embodiment of the present disclosure.

[0081] As described above, the manufacturing method of the semiconductor package 100 can eliminate the need for wire bonding and through-silicon via processes, thereby achieving a simplified process and improved yield.

[0082] Hereinafter, a semiconductor package and a manufacturing method thereof according to another exemplary embodiment of the present disclosure will be described.

[0083] Figure 11 is a cross-sectional view showing a semiconductor package 200 according to the second exemplary embodiment of the present disclosure.

[0084] Referring to Figure 11 , the semiconductor package 200 according to the second exemplary embodiment of the present disclosure includes a substrate SUB, a first chip CP1, a first unit structure US1', a second unit structure US2', a molding layer MD, and a conductive via VIA. In Figure 11 , the same reference numerals denote the same or similar elements as in Figure 1 . Therefore, redundant descriptions will be omitted, and the focus will be on the differences from the first embodiment.

[0085] The first chip CP1 can be disposed on the top surface of the substrate SUB. For example, the chip pads of the first chip CP1 can be electrically connected to the pads on the top surface of the substrate SUB through bottom conductive bumps UBP. The first chip CP1 can be a SoC chip.

[0086] The first unit structure US1' and the second unit structure US2' can be sequentially stacked on the first chip CP1. As shown in Figure 11 , the first unit structure US1' can be disposed on the first chip CP1, and the second unit structure US2' can be disposed on the first unit structure US1'. For example, the first unit structure US1' can be bonded to the top surface of the first chip CP1 through an adhesive layer BL, and the second unit structure US2' can be bonded to the first unit structure US1' through an adhesive layer BL.

[0087] Each of the first unit structure US1' and the second unit structure US2' can be a chip structure with a double-sided pattern. For example, each of the first unit structure US1' and the second unit structure US2' can include a lower unit chip LC', an upper unit chip UC', a conductive bump BP, and a redistribution layer RD located between the lower unit chip LC' and the upper unit chip UC'. Each of the lower unit chip LC' and the upper unit chip UC' has an active surface and a passive surface opposite to the active surface. The active surfaces of the lower unit chip LC' and the upper unit chip UC' can face each other and are electrically connected through the conductive bump BP and the redistribution layer RD. The redistribution layer RD can be in direct contact with the conductive bump BP.

[0088] The passive surface of the upper unit chip UC' of the first unit structure US1' and the passive surface of the lower unit chip LC' of the second unit structure US2' can face each other and are joined together through an adhesive layer BL.

[0089] The lower unit chip LC' and the upper unit chip UC' can be DRAM chips.

[0090] Each of the lower unit chip LC' and the upper unit chip UC' can include a pattern layer provided on the active surface. As Figure 11 shown, the lower unit chip LC' can include a lower pattern layer LPT' provided on the active surface, and the upper unit chip UC' can include an upper pattern layer UPT' provided on the active surface. The lower pattern layer LPT' and the upper pattern layer UPT' can face each other.

[0091] The conductive bump BP and the redistribution layer RD can be provided between the lower unit chip LC' and the upper unit chip UC'. As Figure 11 shown, the redistribution layer RD is provided on the lower pattern layer LPT' of the lower unit chip LC', and the conductive bump BP is provided on the upper pattern layer UPT' of the upper unit chip UC'. More specifically, the conductive bump BP is also in direct contact with the upper pattern layer UPT' of the upper unit chip UC'. In other words, the redistribution layer RD is provided above the lower unit chip LC', the conductive bump BP is provided above the redistribution layer RD, and the upper unit chip UC' is provided above the conductive bump BP. However, the present disclosure is not limited thereto. In other embodiments, the conductive bump BP can be provided above the lower unit chip LC', the redistribution layer RD can be provided above the conductive bump BP, and the upper unit chip UC' can be provided above the redistribution layer RD.

[0092] The redistribution layer RD can be electrically connected to a conductive via VIA, thereby realizing the electrical connection between the lower unit chip LC' and the conductive via VIA through the redistribution layer RD. Similarly, the upper unit chip UC' can be electrically connected to the conductive via VIA through the conductive bump BP and the redistribution layer RD.

[0093] The substrate SUB, conductive vias VIA, and molding layer MD of the semiconductor package 200 of the second exemplary embodiment have a similar structure to the substrate SUB, conductive vias VIA, and molding layer MD of the semiconductor package 100 of the first exemplary embodiment, and thus a detailed description thereof will be omitted.

[0094] Although the semiconductor package 200 is shown in Figure 11 as including only two unit structures, the present disclosure is not limited thereto. The semiconductor package 200 may include one or more additional unit structures stacked on the second unit structure US2', each additional unit structure having substantially the same structure as the first unit structure US1' and the second unit structure US2'.

[0095] The semiconductor package 200 according to the second exemplary embodiment of the present disclosure includes a unit structure configured as a double-sided patterned chip structure, and thus has a reduced thickness and improved reliability. For example, the semiconductor package 200 may be fabricated without using a wire bonding process or a through-silicon via process, thereby minimizing the thickness and improving the reliability.

[0096] Hereinafter, a method of manufacturing the semiconductor package 200 of the second exemplary embodiment according to the embodiment of the present disclosure will be described.

[0097] Figures 12 to 21 is a cross-sectional view showing an intermediate stage of a method of manufacturing the semiconductor package 200 according to the second exemplary embodiment of the present disclosure.

[0098] Referring to Figure 12 , a first cut may be performed to form a redistribution layer RD.

[0099] For example, the surface of the wafer opposite to the surface on which the patterned layer (e.g., the lower patterned layer LPT') is formed may be attached to the first tape TP1. Subsequently, an initial redistribution layer may be formed on the patterned layer of the wafer. Then, a first cutting process may be performed on the initial redistribution layer to form the redistribution layer RD.

[0100] For example, two redistribution layers RD are shown in Figure 12 , but the present disclosure is not limited thereto. The number of redistribution layers RD may vary based on the area of the wafer.

[0101] Referring to Figure 13 , a second cut may be performed to form unit chips (e.g., lower unit chips LC').

[0102] For example, as shown in Figure 13As shown, the first tape TP1 can be removed, and then the second tape TP2 can be attached to the redistribution layer RD. A second cutting process can be performed on the surface of the wafer opposite to the surface on which the patterned layer is formed, thereby forming a lower unit chip (e.g., the lower unit chip LC'). In other exemplary embodiments, the formed unit chip can also serve as the upper unit chip UC'.

[0103] Referring to Figure 14 , the cut-off edge portion of the wafer can be removed.

[0104] For example, the third tape TP3 can be attached to the surface of the wafer opposite to the surface on which the patterned layer is formed. Then, the cut-off edge portion of the wafer is removed by peeling off the third tape TP3. Through this process, the redistribution layer RD can protrude from the side surface of the lower unit chip LC'.

[0105] Referring to Figure 15 , the lower unit chip LC' and the redistribution layer RD can be attached to the fourth tape TP4.

[0106] For example, the second tape TP2 can be removed, and then the passive surface of the lower unit chip LC' can be attached to the fourth tape TP4.

[0107] Referring to Figure 16 , a unit structure can be formed.

[0108] For example, conductive bumps BP can be formed on the active surface (e.g., the upper patterned layer UPT') of the upper unit chip UC'. Then, the conductive bumps BP can be attached to the redistribution layer RD using a chip-to-wafer bonding process, thereby forming a unit structure configured as a double-sided patterned chip structure.

[0109] Referring to Figure 17 , the wafer can be cut to form individual unit structures. The above steps can be repeated to form multiple unit structures.

[0110] Referring to Figure 18 , a stacked structure of a substrate SUB, a first chip CP1, a first unit structure US1', and a second unit structure US2' can be formed.

[0111] For example, the first chip CP1 can be attached to the substrate SUB first. Specifically, the bottom conductive bumps UBP of the first chip CP1 can be attached to the pads on the top surface of the substrate SUB. Then, the first unit structure US1' can be attached to the top surface of the first chip CP1 using the adhesive layer BL. After that, the second unit structure US2' can be attached to the first unit structure US1' using the adhesive layer BL, so as to ensure that the passive surfaces of the upper unit chip UC' of the first unit structure US1' and the lower unit chip LC' of the second unit structure US2' face each other.

[0112] Referring to Figure 19 , a first sub-molding layer MD1 can be formed on the substrate SUB.

[0113] For example, a preliminary first sub-molding layer covering the first unit structure US1' and the second unit structure US2' can be formed on the substrate SUB first. Then, a planarization process can be performed on the first sub-molding layer to obtain the first sub-molding layer MD1. The first sub-molding layer MD1 can include an epoxy molding compound (EMC) or be formed of an epoxy molding compound (EMC). As Figure 19 shown, the top surface of the first sub-molding layer MD1 and the passive surface of the upper unit chip UC' of the second unit structure US2' can be substantially coplanar. However, the present disclosure is not limited to this configuration, and the top surface of the first sub-molding layer MD1 can also be higher than the passive surface of the upper unit chip UC' of the second unit structure US2'. For example, the distance from the top surface of the first sub-molding layer MD1 to the top surface of the substrate SUB can be equal to or greater than the distance from the passive surface of the upper unit chip UC' of the second unit structure US2' to the top surface of the substrate SUB.

[0114] Referring to Figure 20 , a conductive via VIA penetrating the first sub-molding layer MD1 can be formed.

[0115] For example, a drilling process can be performed on the first sub-molding layer MD1 first to form a through hole penetrating the first sub-molding layer MD1. The through hole can expose the side surfaces of the redistribution layers RD of each of the first unit structure US1' and the second unit structure US2'. Then, an electroplating process can be performed in the through hole to form the conductive via VIA.

[0116] The conductive via VIA can be electrically connected to the conductive path CW of the substrate SUB and can also establish an electrical connection with the redistribution layer RD of each of the first unit structure US1' and the second unit structure US2'.

[0117] Referring to Figure 21, a second sub-molding layer MD2 can be formed to cover the passive surface of the upper unit chip UC' of the first sub-molding layer MD1, the conductive vias VIA, and the second unit structure US2'. A process similar to the process used to form the first sub-molding layer MD1 can be used to form the second sub-molding layer MD2. The second sub-molding layer MD2 can include an epoxy molding compound (EMC) or be formed of an epoxy molding compound (EMC). The thickness of the second sub-molding layer MD2 (referred to as the mold gap) can be relatively small, which helps to reduce the thickness of the semiconductor package 100 compared to packages formed using wire bonding processes.

[0118] The second sub-molding layer MD2 can include the same material as the first sub-molding layer MD1. The first sub-molding layer MD1 and the second sub-molding layer MD2 can constitute the molding layer MD.

[0119] Next, referring to Figure 11 , solder balls SB can be formed on the bottom surface of the substrate SUB, thereby completing the manufacturing of the semiconductor package 200 according to the second exemplary embodiment of the present disclosure.

[0120] As described above, the manufacturing method of the semiconductor package 200 can eliminate the need for wire bonding processes and through-silicon via processes. Therefore, the semiconductor package 200 benefits from a simplified manufacturing process and improved yield.

[0121] Hereinafter, a semiconductor package and a manufacturing method thereof according to still another exemplary embodiment of the present disclosure will be described.

[0122] Figure 22 is a cross-sectional view showing a semiconductor package 300 according to a third exemplary embodiment of the present disclosure.

[0123] Referring to Figure 22 , the semiconductor package 300 according to the third exemplary embodiment of the present disclosure includes a substrate SUB, a first chip CP1, a bottom interposer UITP, a first unit structure US1', a second unit structure US2', a molding layer MD, and conductive vias VIA. In Figure 22 , the same reference numerals denote the same or similar elements as in Figure 11 . Therefore, redundant descriptions will be omitted, and the focus will be on the differences from the second embodiment.

[0124] The substrate SUB can have a groove GV. For example, the groove GV can be located on the top surface of the substrate SUB.

[0125] The first chip CP1 can be disposed in the groove GV of the substrate SUB. In other words, the first chip CP1 can be disposed within the substrate SUB. The passive surface of the first chip CP1 can face the bottom surface of the substrate SUB, and the active surface of the first chip CP1 can face the opening side of the groove GV or the top surface of the substrate SUB. The first chip CP1 can be a SoC chip.

[0126] The first chip CP1 can be covered by a bottom molding layer UMD. For example, the bottom molding layer UMD can fill a part of the groove GV of the substrate SUB. More specifically, the bottom molding layer UMD can fill the part of the groove GV located between the first chip CP1 and the substrate SUB.

[0127] The bottom interposer UITP can be located above the first chip CP1. For example, the bottom interposer UITP can be located above the bottom molding layer UMD and is electrically connected to the chip pads of the first chip CP1 through bottom conductive bumps UBP. The top surface of the bottom interposer UITP can be substantially coplanar with the top surface of the substrate SUB. The bottom interposer UITP can be stacked with the groove GV such that the bottom interposer UITP covers the bottom molding layer UMD.

[0128] The first unit structure US1' and the second unit structure US2' can be sequentially stacked on the first chip CP1. As Figure 22 shown, the first unit structure US1' can be disposed on the bottom interposer UITP, and the second unit structure US2' can be disposed on the first unit structure US1'. For example, the first unit structure US1' can be joined to the bottom interposer UITP through an adhesive layer BL, and the second unit structure US2' can be joined to the first unit structure US1' through an adhesive layer BL.

[0129] The first unit structure US1' and the second unit structure US2' of the semiconductor package 300 according to the third exemplary embodiment of the present disclosure can have substantially the same structure as the first unit structure US1' and the second unit structure US2' of the semiconductor package 200 shown in Figure 11 Therefore, their descriptions will not be repeated here.

[0130] The substrate SUB, the conductive vias VIA, and the molding layer MD of the semiconductor package 300 according to the third exemplary embodiment of the present disclosure can have a structure similar to that of the substrate SUB, the conductive vias VIA, and the molding layer MD of the semiconductor package 100 of the first exemplary embodiment and the semiconductor package 200 of the second exemplary embodiment. Therefore, the detailed description will be omitted.

[0131] Although the semiconductor package 300 is in Figure 22is shown as including only two unit structures, but the present disclosure is not limited to such a configuration. The semiconductor package 300 may include one or more additional unit structures stacked on the second unit structure US2', each additional unit structure having a structure substantially the same as that of the first unit structure US1' and the second unit structure US2'.

[0132] The semiconductor package 300 according to the third exemplary embodiment of the present disclosure is configured as a unit structure of a double-sided patterned chip structure, and thus has a reduced thickness and enhanced reliability. For example, the semiconductor package 300 may be fabricated without using a wire bonding process or a through-silicon via process, thereby minimizing the thickness and improving the reliability.

[0133] In addition, the first chip CP1 of the semiconductor package 300 according to the third exemplary embodiment of the present disclosure is disposed in the groove GV of the substrate SUB, and thus the overall thickness of the semiconductor package 300 can be further reduced.

[0134] Hereinafter, a method of manufacturing the semiconductor package 300 according to the embodiment of the present disclosure will be described.

[0135] Figures 23 to 27 is a cross-sectional view showing an intermediate stage of a method of manufacturing the semiconductor package 300 according to the third exemplary embodiment of the present disclosure.

[0136] First, referring to Figures 12 to 17 , a plurality of unit structures may be prepared using steps substantially the same as those employed in manufacturing the semiconductor package 200 according to the second exemplary embodiment of the present disclosure.

[0137] Next, referring to Figure 23 , a substrate SUB with a groove GV may be prepared, and the first chip CP1 may be placed in the groove GV of the substrate SUB such that the active surface of the first chip CP1 faces the opening side of the groove GV (e.g., the upper opening side of the groove GV). Then, bottom conductive bumps UBP may be formed on the chip pads of the first chip CP1, and the bottom interposer UITP may be bonded to the first chip CP1 through the bottom conductive bumps UBP, ensuring that the top surface of the bottom interposer UITP is substantially coplanar with the top surface of the substrate SUB. Thereafter, a sealing material such as an epoxy molding compound (EMC) may be filled into the groove GV to form a bottom molding layer UMD covering the first chip CP1.

[0138] Referring to Figure 24 , a stacked structure of the first chip CP1, the first unit structure US1' and the second unit structure US2' may be formed.

[0139] For example, the first unit structure US1' can be attached to the top surface of the bottom interposer UITP by using the adhesive layer BL. Thereafter, the second unit structure US2' can be attached to the first unit structure US1' by using the adhesive layer BL, such that the passive surface of the upper unit chip UC' of the first unit structure US1' and the passive surface of the lower unit chip LC' of the second unit structure US2' face each other.

[0140] Referring to Figure 25 , a first sub-molding layer MD1 can be formed on the substrate SUB.

[0141] For example, a preliminary first sub-molding layer covering the first unit structure US1' and the second unit structure US2' can be first formed on the substrate SUB. Then, a planarization process can be performed on the first sub-molding layer to obtain the first sub-molding layer MD1. The first sub-molding layer MD1 can include an epoxy molding compound (EMC) or be formed of an epoxy molding compound (EMC). As Figure 25 shown, the top surface of the first sub-molding layer MD1 and the passive surface of the upper unit chip UC' of the second unit structure US2' can be substantially coplanar. However, the present disclosure is not limited thereto, and the top surface of the first sub-molding layer MD1 can also be higher than the passive surface of the upper unit chip UC' of the second unit structure US2'. For example, the distance from the top surface of the first sub-molding layer MD1 to the top surface of the substrate SUB can be equal to or greater than the distance from the passive surface of the upper unit chip UC' of the second unit structure US2' to the top surface of the substrate SUB.

[0142] Referring to Figure 26 , a conductive via VIA penetrating the first sub-molding layer MD1 can be formed.

[0143] For example, a drilling process can be first performed on the first sub-molding layer MD1 to form a through hole penetrating the first sub-molding layer MD1. The through hole can expose the side surfaces of the redistribution layers RD of each of the first unit structure US1' and the second unit structure US2'. Then, an electroplating process can be performed on the through hole to form the conductive via VIA.

[0144] The conductive via VIA can be electrically connected to the conductive path CW of the substrate SUB and can be electrically connected to the redistribution layer RD of each of the first unit structure US1' and the second unit structure US2'.

[0145] Referring to Figure 27, a second sub-molding layer MD2 can be formed to cover the passive surface of the upper unit chip UC' of the first sub-molding layer MD1, the conductive vias VIA, and the second unit structure US2'. The second sub-molding layer MD2 can be formed by a process substantially the same as the process for forming the first sub-molding layer MD1. The second sub-molding layer MD2 can include an epoxy molding compound (EMC) or be formed of an epoxy molding compound (EMC). The thickness of the second sub-molding layer MD2 can be referred to as a mold gap. The second sub-molding layer MD2 can have a relatively small thickness, which helps to reduce the thickness of the semiconductor package 100 compared to a package formed using a wire bonding process.

[0146] The second sub-molding layer MD2 can include the same material as the first sub-molding layer MD1. The first sub-molding layer MD1 and the second sub-molding layer MD2 can constitute the molding layer MD.

[0147] Next, referring to Figure 22 , solder balls SB can be formed on the bottom surface of the substrate SUB, thereby completing the manufacture of the semiconductor package 300 according to the third exemplary embodiment of the present disclosure.

[0148] As described above, the manufacturing method of the semiconductor package 300 can eliminate the need for wire bonding and through-silicon via processes, thereby achieving a simplified process and improved yield. In addition, since the first chip CP1 is located in the groove GV of the substrate SUB, the overall thickness of the semiconductor package 300 can be further reduced.

[0149] A semiconductor package according to an exemplary embodiment of the present disclosure includes a unit structure configured as a double-sided patterned chip structure. This design can reduce thickness, enhance reliability, and improve electrical performance.

[0150] Although the present disclosure has been specifically shown and described with reference to some exemplary embodiments of the present disclosure, it will be understood that various changes in form and detail can be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: substrate; A first unit structure and a second unit structure are sequentially stacked on a substrate; a molding layer, located on the substrate and covering the first unit structure and the second unit structure; as well as Conductive vias, located within the molding layer and electrically connected to the substrate, Each of the first unit structure and the second unit structure includes: an interposer; a lower unit chip located below the interposer; an upper unit chip located above the interposer; a lower redistribution layer located between the lower unit chip and the interposer and electrically connected to the interposer, the lower unit chip and the conductive via; an upper redistribution layer located between the upper unit chip and the interposer and electrically connected to the interposer, the upper unit chip and the conductive via, wherein each of the lower unit chip and the upper unit chip has an active surface facing the interposer and a passive surface opposite to the active surface, and The passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other.

2. The semiconductor package according to claim 1, wherein: The lower unit chip includes a lower base layer and a lower pattern layer located between the lower base layer and the lower redistribution layer, the lower pattern layer is electrically connected to the lower redistribution layer, and The upper unit chip includes an upper base layer and an upper pattern layer located between the upper base layer and the upper redistribution layer, and the upper pattern layer is electrically connected to the upper redistribution layer.

3. The semiconductor package according to claim 1, wherein: The molding layer includes a first sub-molding layer and a second sub-molding layer, wherein the conductive via penetrates the first sub-molding layer, and The second sub-molding layer covers the first sub-molding layer and the conductive via.

4. The semiconductor package according to claim 3, wherein: A distance from a top surface of the first sub-mold layer to a top surface of the substrate is equal to or greater than a distance from an inactive surface of an upper unit chip of the second unit structure to a top surface of the substrate.

5. The semiconductor package according to claim 1, wherein: A side surface of the interposer, a side surface of the lower redistribution layer, and a side surface of the upper redistribution layer contact the conductive via, and The side surface of the lower unit chip and the side surface of the upper unit chip are spaced apart from the conductive via.

6. The semiconductor package according to claim 2, wherein: The interposer has a first width, wherein the lower redistribution layer and the upper redistribution layer have a second width, wherein the lower pattern layer and the upper pattern layer have a third width, wherein the lower substrate layer and the upper substrate layer have a fourth width, Wherein, the first width is equal to the second width, wherein the third width is equal to the fourth width, and The first width is greater than the third width.

7. The semiconductor package according to claim 1, wherein: The semiconductor package further includes a third unit structure located above the second unit structure, and The third unit structure has the same structure as the first unit structure and the second unit structure.

8. A semiconductor package, comprising: substrate; A first chip is located in the groove of the substrate; A first unit structure, located above the first chip; A second unit structure, located above the first unit structure; a molding layer, located on the substrate and covering the first unit structure and the second unit structure; as well as Conductive vias, located within the molding layer and electrically connected to the substrate, Each of the first unit structure and the second unit structure includes: a lower unit chip and an upper unit chip, each including an active surface and a passive surface opposite to the active surface; a conductive bump located between the lower unit chip and the upper unit chip and directly connected to one of the lower unit chip and the upper unit chip; a redistribution layer located between the lower unit chip and the upper unit chip and directly connected to the conductive bump and the conductive via and the other of the lower unit chip and the upper unit chip, wherein, in each of the first unit structure and the second unit structure, an active surface of a lower unit chip and an active surface of an upper unit chip face each other, and The passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other.

9. The semiconductor package according to claim 8, wherein: The redistribution layer is located between the lower unit chip and the conductive bumps, and The conductive bump is located between the upper unit chip and the redistribution layer.

10. The semiconductor package according to claim 8, wherein: The conductive bump is located between the lower unit chip and the redistribution layer, and The redistribution layer is located between the upper unit chip and the conductive bumps.

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