Clock phase adjusting method and device and electronic equipment

Abstract

The invention discloses a clock phase adjustment method and device and electronic equipment. The method comprises the following steps: sampling a received test data signal by adopting a clock signal; determining a phase state corresponding to the current clock phase based on a sampled data signal obtained by sampling; the phase state represents the relationship between the sampling data signal and the test data signal; based on the phase state, taking the target clock phase movement amount as a single movement amount, taking the current clock phase as a starting point, moving in the phase searching direction until a clock phase critical value is searched, and enabling the target clock phase movement amount to be matched with the current phase state; the clock phase critical value corresponds to transition between different phase states; and determining a target clock phase based on the clock phase critical value.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and in particular, to a clock phase adjustment method, apparatus, and electronic device. Background Art

[0002] In the data transmission process of an interface circuit in a modern electronic communication system, the mismatch in the arrival times of data and a clock signal at a receiving end is a common problem. This mismatch may cause the data to be sampled incorrectly at the receiving end, thereby compromising the reliability and integrity of data transmission. To solve this problem, a clock delay circuit (DDL) can be added to adjust the delay of the clock signal so that it matches the arrival time of the data signal, thereby ensuring that the data can be sampled at the correct moment.

[0003] However, simply adjusting the delay of the clock signal is not sufficient to fully guarantee the accuracy of sampling. Since the clock signal is periodic and there are multiple different time points (i.e., clock phases) within each period, the data signal states corresponding to these different clock phases may vary. If the selected clock phase is inappropriate, even if the delay of the clock signal has been adjusted properly, the sampling result may still be inaccurate. Therefore, based on adjusting the clock delay, how to select an appropriate clock phase becomes a problem. Summary of the Invention

[0004] In view of the above problems, the technical solutions provided by the present application are as follows:

[0005] A first aspect of the present application provides a clock phase adjustment method, including:

[0006] Sampling the received test data signal using a clock signal;

[0007] Based on the sampled data signal obtained by sampling, determining a phase state corresponding to the current clock phase; the phase state characterizes the relationship between the sampled data signal and the test data signal;

[0008] Based on the phase state, with a target clock phase shift amount as the single shift amount, starting from the current clock phase, moving along the phase search direction until reaching a clock phase critical value, the target clock phase shift amount matching the current phase state; the clock phase critical value corresponds to the transition between different phase states;

[0009] Based on the clock phase critical value, determining a target clock phase.

[0010] The determining, based on the sampled data signal obtained by sampling, a phase state corresponding to the current clock phase includes:

[0011] Compare whether the sampled sampling data signal is consistent with the received test data signal to obtain a comparison result;

[0012] In response to the comparison result indicating consistency, determine that the phase state corresponding to the current clock phase is the first type of phase state;

[0013] In response to the comparison result indicating inconsistency, determine that the phase state corresponding to the current clock phase is the second type of phase state;

[0014] The target clock phase shift amount corresponding to the first type of phase state is greater than the target clock phase shift amount corresponding to the second type of phase state.

[0015] The first type of phase state includes: the first phase state and the third phase state; the second type of phase state includes: the second phase state and the fourth phase state;

[0016] In response to the comparison result indicating consistency and not yet searching to the first clock phase critical value, determine that the phase state corresponding to the current clock phase is the first phase state;

[0017] In response to the comparison result indicating inconsistency and not yet searching to the first clock phase critical value, determine that the phase state corresponding to the current clock phase is the second phase state;

[0018] In response to the comparison result indicating consistency, having searched to the first clock phase critical value and not yet searching to the second clock phase boundary value, determine that the phase state corresponding to the current clock phase is the third phase state;

[0019] In response to the comparison result indicating inconsistency and having searched to the second clock phase critical value, determine that the phase state corresponding to the current clock phase is the fourth phase state;

[0020] The phase search direction is the phase change direction from the first clock phase critical value to the second clock phase critical value.

[0021] Based on the phase state, with the target clock phase shift amount as the single shift amount, starting from the current clock phase, move along the phase search direction until the clock phase critical value is searched to, including:

[0022] Based on the third phase state, with the target clock phase shift amount corresponding to the first type of phase state as the single - shift amount, starting from the current clock phase, move along the phase search direction. If a transition between the third phase state and the fourth phase state occurs, with the target clock phase shift amount corresponding to the first type of phase state as the single - shift amount, starting from the clock phase where the transition occurs, move along the direction opposite to the phase search direction;

[0023] With the target clock phase shift amount corresponding to the second type of phase state as the single - shift amount, starting from the new current clock phase, move along the phase search direction until the second clock phase boundary value is searched.

[0024] The degree to which the test data signal is affected by signal timing jitter is different in different time periods; the signal timing jitter characterizes the deviation between the actual arrival time and the theoretical arrival time of the edge position of the test data signal.

[0025] The clock phase adjustment method further includes:

[0026] Based on the received initial test data signal, generate two processed test data signals, and alternately output the two processed test data signals in time; the time distribution ranges of the data signal edges generated by the two processed test data signals affected by the signal timing jitter are different.

[0027] The generating two processed test data signals based on the received initial test data signal and alternately outputting the two processed test data signals in time includes:

[0028] Adjust the duty cycle of the received initial test data signal to obtain two processed test data signals with different duty cycles, and alternately output the two processed test data signals with different duty cycles in time.

[0029] Adjusting the duty cycle of the received initial test data signal to obtain two processed test data signals with different duty cycles and alternately outputting the two processed test data signals with different duty cycles in time includes:

[0030] Increase the duty cycle of the received initial test data signal to obtain the first test data signal;

[0031] Decrease the duty cycle of the received initial test data signal to obtain the second test data signal;

[0032] Based on the received clock signal, generate a divided - by - two clock signal;

[0033] Based on the divided-by-two clock signal, one signal is alternately selected from the first test data signal and the second test data signal for output.

[0034] On the other hand, the present application provides a clock phase adjustment device, including:

[0035] A sampling module, configured to sample the received test data signal by using a clock signal;

[0036] A first determination module, configured to determine the phase state corresponding to the current clock phase based on the sampled data signal obtained by sampling; the phase state characterizes the relationship between the sampled data signal and the test data signal;

[0037] A search module, configured to, based on the phase state, use the target clock phase shift amount as the single-step shift amount, start from the current clock phase, and move along the phase search direction until the clock phase critical value is searched, where the target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to the transition between different phase states;

[0038] A second determination module, configured to determine the target clock phase based on the clock phase critical value.

[0039] On the third aspect, the present application provides an electronic device, including:

[0040] A hardware adjustment module, configured to adjust the duty cycle of the received test data signal to obtain two processed test data signals with different duty cycles, and alternately output the two processed test data signals with different duty cycles in time;

[0041] A processor, configured to:

[0042] Sample the two processed test data signals with different duty cycles by using a clock signal;

[0043] Determine the phase state corresponding to the current clock phase based on the sampled data signal obtained by sampling; the phase state characterizes the relationship between the sampled data signal and the test data signal;

[0044] Based on the phase state, use the target clock phase shift amount as the single-step shift amount, start from the current clock phase, and move along the phase search direction until the clock phase critical value is searched, where the target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to the transition between different phase states;

[0045] Determine the target clock phase based on the clock phase critical value. Description of the Drawings

[0046] In combination with the accompanying drawings and with reference to the following specific embodiments, the above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic and the original components and elements are not necessarily drawn to scale.

[0047] Figure 1 It is a schematic flowchart of a clock phase adjustment method provided in Embodiment 1 of the present application;

[0048] Figure 2 It is a schematic flowchart of a clock phase adjustment method provided in Embodiment 1 of the present application;

[0049] Figure 3 It is a schematic flowchart of a clock phase adjustment method provided in Embodiment 3 of the present application;

[0050] Figure 4 It is a schematic diagram of clock phase search provided by the present application;

[0051] Figure 5 It is another schematic diagram of clock phase search provided by the present application;

[0052] Figure 6 It is a schematic flowchart of a clock phase adjustment method provided in Embodiment 6 of the present application;

[0053] Figure 7 It is a schematic flowchart of a clock phase adjustment method provided in Embodiment 7 of the present application;

[0054] Figure 8 It is a schematic diagram of data eye diagram comparison provided by the present application;

[0055] Figure 9 It is a schematic structural diagram of a clock phase adjustment device provided by the present application;

[0056] Figure 10 It is a schematic structural diagram of an electronic device provided by the present application;

[0057] Figure 11 It is a schematic structural diagram of a hardware adjustment module provided by the present application;

[0058] Figure 12 It is an interaction schematic diagram between a hardware adjustment module and a processor provided by the present application. Specific Embodiments

[0059] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terms used in the embodiments of the present application are only for explaining the specific embodiments of the present application and are not intended to limit the present application.

[0060] The embodiments of the present application will be described below in conjunction with the accompanying drawings. Those of ordinary skill in the art will understand that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0061] The terms "first", "second", etc. in the description and claims of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device comprising a series of units need not be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices.

[0062] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0063] Referring to Figure 1 , which is a schematic flowchart of a clock phase adjustment method provided for Embodiment 1 of the present application. As Figure 1 shown, the method may include but is not limited to the following steps:

[0064] Step S101: Sample the received test data signal using a clock signal.

[0065] In this embodiment, the receiving end may determine sampling points based on the local clock signal of the receiving end, and at each sampling point, read the level state of the received test data signal.

[0066] Of course, if the receiving end receives a clock signal synchronized with the test data signal while receiving the test data signal, however, due to various factors (such as transmission delay, line loss, noise, etc.) during the transmission of the clock signal, the clock signal received by the receiving end may be distorted or offset.

[0067] To accurately sample the received test data signal, the receiving end may recover a clock signal as consistent as possible with the clock signal sent by the sending end. Once the receiving end successfully recovers the clock signal, the receiving end may sample the received test data signal based on the recovered clock signal.

[0068] Step S102: Determine the phase state corresponding to the current clock phase based on the sampled data signal.

[0069] In this embodiment, the phase state corresponding to the current clock phase can characterize the relationship between the sampled data signal and the test data signal.

[0070] The phase state characterizing the relationship between the sampled data signal and the test data signal can be used to guide the search direction and the amount of clock phase movement starting from the current clock phase.

[0071] Step S103: Based on the phase state, with the target clock phase movement amount as the single movement amount, starting from the current clock phase, move along the phase search direction until the clock phase critical value is reached, and the target clock phase movement amount matches the current phase state.

[0072] In this embodiment, as the search progresses, new current clock phases can be continuously generated, and the phase states corresponding to the new current clock phases can be determined. This dynamic process can determine various different phase states. The target clock phase movement amounts corresponding to different phase states may vary. This variation is not limited to each phase state corresponding to a unique target clock phase movement amount. It can also be that some phase states share the same target clock phase movement amount, while another part of the phase states each correspond to different target clock phase movement amounts.

[0073] The clock phase critical value can correspond to the transition between different phase states.

[0074] Step S104: Based on the clock phase critical value, determine the target clock phase.

[0075] The clock phase critical value can correspond to the transition between different phase states, that is, the clock phase critical value can coincide with the vicinity of the rising edge or falling edge of the test data signal. If sampling is performed based on the clock phase critical value, it is easy to sample the rising edge or falling edge, resulting in sampling errors.

[0076] To obtain a more reliable sampling result, a relatively stable clock phase can be determined as the target clock phase based on the clock phase critical value. The target clock phase can coincide with the high-level stable segment or the low-level stable segment of the test data signal. Because in the high-level stable segment or the low-level stable segment, the level of the test data signal is relatively stable. Sampling the high-level stable segment or the low-level stable segment of the test data signal based on the target clock phase can accurately determine the signal level logic state and ensure the accuracy of the sampling result.

[0077] When applying the target clock phase to actual data signal sampling, it can ensure that sampling occurs in the high-level stable segment or the low-level stable segment of the actual data signal, reducing the possibility of sampling errors.

[0078] In this embodiment, the received test data signal is sampled by using a clock signal. Based on the sampled data signal obtained by sampling, the phase state corresponding to the current clock phase is determined. The phase state can characterize the relationship between the sampled data signal and the test data signal, providing an important basis for determining the subsequent search direction and movement amount. Next, based on the phase state, with the target clock phase movement amount as the single movement amount, a search is carried out starting from the current clock phase. It can be ensured that during the search process, the target clock phase movement amount is not fixed. This flexible movement method can ensure that the clock phase critical value can be searched more quickly. On this basis, based on the clock phase critical value, the target clock phase is determined, which can improve the adjustment efficiency and accuracy.

[0079] As another optional embodiment of the present application, refer to Figure 2 , which is a schematic flowchart of a clock phase adjustment method provided for Embodiment 2 of the present application. This embodiment is mainly an implementation manner of the above step S102. As Figure 2 shown, step S102 may include but is not limited to:

[0080] Step S1021: Compare whether the sampled data signal obtained by sampling is consistent with the received test data signal to obtain a comparison result.

[0081] In this embodiment, the received test data signal can be sampled by using a single data bit sampling method. Correspondingly, the sampled data signal can be the value of a single data bit. If this value is consistent with the corresponding bit in the received test data signal, it is determined to be consistent; otherwise, it is determined to be inconsistent.

[0082] Alternatively, the received test data signal can also be sampled by using a continuous sampling method. Correspondingly, the sampled data signal can be a series of continuous data bits, which together form a complete data sequence, such as "1000011110". In this case, only when each bit in the data sequence is exactly the same as the corresponding bit in the received test data signal, are the two considered to be consistent. If any bit in the data sequence is incorrect, it will be determined to be inconsistent.

[0083] Of course, the received test data signal can also be sampled by using a periodic interval sampling method. Correspondingly, the sampled data signal can be composed of several data sequences obtained by interval sampling. For this method, each bit in each data sequence must be exactly the same as the corresponding bit in the received test data signal to be determined as consistent. If any bit is incorrect, it will be determined to be inconsistent.

[0084] Step S1022: In response to the comparison result indicating consistency, determine that the phase state corresponding to the current clock phase is the phase state of the first type.

[0085] When the comparison result indicates consistency, that is, when the current clock phase coincides with the high-level stable segment or the low-level stable segment of the test data signal, it can be determined that the phase state corresponding to the current clock phase is the phase state of the first type.

[0086] The proportion of the high-level stable segment or the low-level stable segment of the test data signal in the test data signal can be greater than the proportion of the rising edge or the falling edge in the test data signal. Correspondingly, the clock phase interval corresponding to the high-level stable segment or the low-level stable segment (which can be regarded as the stable sampling interval) is greater than the clock phase interval corresponding to the rising edge or the falling edge (which can be regarded as the unstable sampling interval).

[0087] The clock phase critical value corresponds to the transition between the comparison result indicating consistency and inconsistency, that is, the clock phase critical value often lies at the critical point between the stable sampling interval and the unstable sampling interval.

[0088] If the clock phase is already within the stable sampling interval (that is, the clock phase corresponds to the phase state of the first type), since the stable sampling interval is relatively large, in order to quickly locate the critical point between the stable sampling interval and the unstable sampling interval, a relatively large target clock phase shift amount is required for a single clock phase movement to quickly move out of the stable sampling interval. Therefore, in the phase state of the first type, in order to quickly locate the critical point between the stable sampling interval and the unstable sampling interval, a relatively large target clock phase shift amount can be adopted.

[0089] Step S1023: In response to the comparison result indicating inconsistency, determine that the phase state corresponding to the current clock phase is the phase state of the second type.

[0090] When the comparison result indicates inconsistency, that is, when the current clock phase coincides with the rising edge or the falling edge of the test data signal, it can be determined that the phase state corresponding to the current clock phase is the phase state of the second type.

[0091] If the clock phase is already within the unstable sampling interval (that is, the clock phase corresponds to the phase state of the second type), in order to locate the critical point between the stable sampling interval and the unstable sampling interval, it is necessary to move out of the unstable sampling interval.

[0092] Since the unstable sampling interval is relatively small, in order to ensure that the critical point between the stable sampling interval and the unstable sampling interval is not missed during movement, a cautious movement strategy can be adopted. For example, the amount of target clock phase movement for a single movement can be small to ensure that the clock phase can carefully sweep past the vicinity of the critical point during movement, increasing the accuracy of locating the critical point. Therefore, in the second type of phase state, in order to ensure that the critical point between the stable sampling interval and the unstable sampling interval is not missed, a smaller amount of target clock phase movement can be used.

[0093] In this embodiment, the amount of target clock phase movement corresponding to the first type of phase state can be greater than the amount of target clock phase movement corresponding to the second type of phase state.

[0094] Correspondingly, step S103 may include but is not limited to:

[0095] Step S1031, based on the first type of phase state or the second type of phase state, with the corresponding amount of target clock phase movement as the amount of single movement, starting from the current clock phase, move along the phase search direction until the clock phase critical value is searched.

[0096] In this embodiment, comparing whether the sampled sampling data signal is consistent with the received test data signal to obtain a comparison result, in response to the comparison result indicating consistency, determining that the phase state corresponding to the current clock phase is the first type of phase state, and based on the amount of target clock phase movement corresponding to the first type of phase state as the amount of single movement, starting from the current clock phase, moving along the phase search direction until the clock phase critical value is searched can avoid unnecessary detailed search within the stable sampling interval and improve the search efficiency.

[0097] In response to the comparison result indicating inconsistency, determining that the phase state corresponding to the current clock phase is the second type of phase state, and based on the amount of target clock phase movement corresponding to the second type of phase state as the amount of single movement, starting from the current clock phase, moving along the phase search direction until the clock phase critical value is searched can precisely control the movement of the clock phase within the unstable sampling interval and reduce the risk of missing the clock phase critical value due to too fast movement.

[0098] As another optional embodiment of the present application, referring to Figure 3 , it is a schematic flowchart of a clock phase adjustment method provided in Embodiment 3 of the present application. This embodiment is mainly an implementation manner of the above steps S1022 and S1023. As Figure 3 shown, step S1022 may include but is not limited to:

[0099] Step S11: In response to the comparison result indicating consistency and the first clock phase critical value not being searched yet, determine that the phase state corresponding to the current clock phase is the first phase state.

[0100] When, relative to the initial clock phase, the comparison result corresponding to a certain clock phase (i.e., the result of comparing the sampled data signal obtained by sampling the received test data signal based on a certain clock phase with the test data signal) indicates inconsistency, and the comparison result corresponding to the previous clock phase of this clock phase (i.e., the result of comparing the sampled data signal obtained by sampling the received test data signal based on the previous clock phase of this clock phase value with the test data signal) indicates consistency, this clock phase can be regarded as the first clock phase critical value.

[0101] When, relative to the first clock phase critical value, the comparison result corresponding to a certain clock phase (i.e., the result of comparing the sampled data signal obtained by sampling the received test data signal based on a certain clock phase with the test data signal) indicates consistency, and the comparison result corresponding to the next clock phase of this clock phase (i.e., the result of comparing the sampled data signal obtained by sampling the received test data signal based on the previous clock phase of this clock phase value with the test data signal) indicates inconsistency, this clock phase can be regarded as the second clock phase critical value.

[0102] The first phase state belongs to one of the first type of phase states.

[0103] Step S1023 may include, but is not limited to:

[0104] Step S12: In response to the comparison result indicating inconsistency and the first clock phase critical value not being searched yet, determine that the phase state corresponding to the current clock phase is the second phase state.

[0105] The second phase state belongs to one of the second type of phase states.

[0106] Step S1022 may also include, but is not limited to:

[0107] Step S13: In response to the comparison result indicating consistency, the first clock phase critical value being searched, and the second clock phase boundary value not being searched yet, determine that the phase state corresponding to the current clock phase is the third phase state.

[0108] The third phase state belongs to one of the first type of phase states.

[0109] Step S1023 may also include, but is not limited to:

[0110] Step S14, in response to the comparison result indicating inconsistency and the second clock phase critical value being searched, determine that the phase state corresponding to the current clock phase is the fourth phase state.

[0111] The fourth phase state is one of the phase states of the second type.

[0112] The target clock phase shift amount corresponding to the fourth phase state can be the same as the target clock phase shift amount corresponding to the phase states of the second type.

[0113] Step S1031 may include but is not limited to:

[0114] Step S10311, based on the first phase state and / or the second phase state, with the corresponding first target clock phase shift amount as the single-step shift amount, starting from the current clock phase, move along the phase search direction until the first clock phase critical value is searched, and based on the third phase state and / or the fourth phase state, with the corresponding second target clock phase shift amount as the single-step shift amount, starting from the first clock phase critical value, move along the phase search direction until the second clock phase critical value is searched. The first target clock phase shift amount is greater than the second target clock phase shift amount.

[0115] The first target clock phase shift amount can be the same as the target clock phase shift amount corresponding to the phase states of the first type.

[0116] The second target clock phase shift amount can be the same as the target clock phase shift amount corresponding to the phase states of the second type.

[0117] The phase search direction can be the phase change direction from the first clock phase critical value to the second clock phase critical value.

[0118] Step S104 may include but is not limited to:

[0119] Step S1041, based on the first clock phase critical value and the second clock phase critical value, determine the target clock phase.

[0120] In this embodiment, a clock phase can be selected from the clock phase interval between the first clock phase critical value and the second clock phase critical value as the target clock phase. For example, but not limited to, the average value of the first clock phase critical value and the second clock phase critical value can be used as the target clock phase, that is, the target clock phase is located at the middle position between the first clock phase critical value and the second clock phase critical value, with equal distance from the two clock phase critical values and reaching the maximum. However, setting the target clock phase at the middle position between the two clock phase critical values is not the only or mandatory choice. In other embodiments, it is not limited to this position.

[0121] In this embodiment, the clock phase within the clock phase interval between the first clock phase critical value and the second clock phase critical value can reduce the possibility of sampling errors caused by clock offset or signal jitter, ensuring that the data signal can be accurately sampled.

[0122] Furthermore, taking the average value of the first clock phase critical value and the second clock phase critical value as the target clock phase can ensure that the target clock phase coincides with the region with higher stability in the high-level stable section or the low-level stable section of the data signal. Since the region with higher stability in the high-level stable section or the low-level stable section of the data signal is relatively less affected by noise and other interferences, the accuracy of sampling based on the target clock phase is relatively higher.

[0123] In this embodiment, the clock phase adjustment method will be described in combination with the data eye diagram. For example, as Figure 4 shown, the initial clock phase can be 0. Based on the initial clock phase, the received test data signal is sampled to obtain the sampled data signal. If RxData = Txdata (RxData can represent the sampled data signal, and Txdata can represent the received test data signal), it enters the first phase state (which can be represented as State0). If RxData ≠ Txdata, it enters the second phase state (which can be represented as State1).

[0124] In the first phase state (State0), the target clock phase shift amount (which can be represented as Step) can be N (N is a natural number greater than 1). Taking N as the single shift amount (i.e., N minimum phase shift unit amounts), starting from the current clock phase (i.e., the clock phase at the start of the first phase state), it moves along the phase search direction. After each move, the test data signal is resampled based on the new clock phase, and it is checked whether RxData and Txdata are still equal. Once the condition RxData ≠ Txdata is satisfied, it transfers to the second phase state (State1). The phase shift unit amount is related to the system phase control accuracy.

[0125] In the second phase state (State1), the target clock phase shift amount can be 1 (i.e., 1 minimum phase shift unit amount). Taking 1 as the single shift amount, starting from the clock phase when entering the second phase state (i.e., the clock phase when RxData ≠ Txdata was last satisfied), it moves along the phase search direction. After each move, it is resampled and checked whether RxData and Txdata are still equal. When RxData = Txdata is satisfied again, mark the current clock phase as the first clock phase critical value and transfer to the third phase state (which can be represented as State2).

[0126] In the third phase state (State2), the target clock phase shift amount can be N. Taking N as the single shift amount, starting from the clock phase when entering the third phase state (i.e., the first clock phase critical value), moving along the phase search direction, after each move, re-sampling is performed and it is checked whether RxData and Txdata are still equal. Once the condition of RxData ≠ Txdata is met, the second clock phase critical value can be determined according to the clock phase at this time (for example, taking the clock phase at this time as the second clock phase critical value, or taking the result of subtracting M from the clock phase at this time as the second clock phase critical value, where M is less than N), and then transitioning to the fourth phase state (which can be denoted as State3).

[0127] In this embodiment, when the comparison result indicates consistency and the first clock phase critical value has not been searched yet, the current clock phase is determined to be the first phase state. The first phase state can indicate that the current clock phase has been within the stable sampling interval. Therefore, a relatively large target clock phase shift amount (such as N, N > 1) can be used for fast search, which can avoid unnecessary detailed search within the stable sampling interval, thereby improving the search efficiency.

[0128] When the comparison result indicates inconsistency and the first clock phase critical value has not been searched yet, the current clock phase is determined to be the second phase state. The second phase state can indicate that the current clock phase is within the unstable sampling interval. Therefore, a relatively small target clock phase shift amount (such as 1) can be used for detailed search to ensure that the first clock phase critical value is not missed.

[0129] When the first clock phase critical value has been searched and the second clock phase critical value has not been searched yet, the current clock phase is determined to be the third phase state. Similar to the first phase state, the third phase state also indicates that the current clock phase is within the stable sampling interval. Therefore, a relatively large target clock phase shift amount can continue to be used for fast search to improve the efficiency of searching for the second clock phase critical value.

[0130] As another optional embodiment of the present application, a clock phase adjustment method provided for Embodiment 4 of the present application. This embodiment is mainly an implementation manner based on the third phase state and / or the fourth phase state, taking the corresponding second target clock phase shift amount as the single shift amount, starting from the first clock phase critical value, and moving along the phase search direction until the second clock phase critical value is searched. Specifically, it can include but is not limited to:

[0131] Step S21: Based on the third phase state, using the target clock phase shift amount corresponding to the first type of phase state as the single-step shift amount, starting from the current clock phase (i.e., the first clock phase critical value), move along the phase search direction. If a transition occurs between the third phase state and the fourth phase state, use the target clock phase shift amount corresponding to the first type of phase state as the single-step shift amount, and starting from the clock phase where the transition occurs, move in the direction opposite to the phase search direction (i.e., backtrack).

[0132] In this embodiment, after each move, the test data signal is resampled based on the new clock phase, and it is checked whether RxData and Txdata are still equal. Once the condition RxData≠Txdata is met, it can be determined that a transition has occurred between the third phase state and the fourth phase state. For example, as Figure 5 shown, if a transition occurs between the third phase state (State2) and the fourth phase state (State3), using N (i.e., an embodiment of the target clock phase shift amount corresponding to the first type of phase state) as the single-step shift amount, starting from the clock phase where the transition occurs, move in the direction opposite to the phase search direction.

[0133] Step S22: Using the target clock phase shift amount corresponding to the second type of phase state as the single-step shift amount, starting from the new current clock phase, move along the phase search direction until the second clock phase boundary value is reached.

[0134] For example, as Figure 5 shown, during the search from State2 to State3, first Step = N. After the condition RxData≠Txdata is first met, i.e., backtrack a certain phase amount, it can backtrack N, and then gradually move with the search step amount in the State3 state. It can use 1 (i.e., an embodiment of the target clock phase shift amount corresponding to the second type of phase state) as the single-step shift amount, starting from the new current clock phase after the reverse move, move along the phase search direction until the second clock phase boundary value is reached. Although it may still be in State2 after the reverse move, this step provides a basis for the subsequent fine search, reduces the search step amount near the clock phase critical value, and can improve the search accuracy.

[0135] In this embodiment, based on the third phase state, using the target clock phase shift amount corresponding to the first type of phase state as the single-step shift amount, starting from the current clock phase (i.e., the first clock phase critical value), move along the phase search direction, which can quickly approach the second clock phase critical value, helping to reduce the search time and improve the efficiency.

[0136] If a transition occurs between the third phase state and the fourth phase state, since the search step size at State2 is relatively large, the phase at which RxData≠Txdata occurs may have skipped the clock phase critical value that first causes RxData≠Txdata to be satisfied, that is, the second clock phase critical value between State2 and State3 (as shown in the position of the red dotted line in Figure 5 ), therefore, taking the target clock phase shift amount corresponding to the first type of phase state as the single shift amount, starting from the clock phase at which the transition occurs and moving in the direction opposite to the phase search direction can ensure that the search process will not cross the correct second clock phase critical value and improve the search accuracy.

[0137] Then, taking the target clock phase shift amount corresponding to the second type of phase state as the single shift amount, starting from the new current clock phase and moving along the phase search direction for a detailed search can more accurately determine the second clock phase critical value.

[0138] As another optional embodiment of the present application, a clock phase adjustment method provided in Embodiment 5 of the present application, this embodiment is mainly an implementation manner for test data signals, specifically:

[0139] The degree to which the test data signal is affected by signal timing jitter can be different in different time periods.

[0140] The signal timing jitter can represent the deviation between the actual arrival time and the theoretical arrival time of the edge position of the test data signal.

[0141] In this embodiment, the degree to which the test data signal is affected by signal timing jitter can be different in different time periods, which can affect the widths of the clock phase intervals corresponding to the high-level stable segment or the low-level stable segment (which can be regarded as stable sampling intervals) and the clock phase intervals corresponding to the rising edge or the falling edge (which can be regarded as unstable sampling intervals).

[0142] For example, if the degree to which the test data signal is affected by signal timing jitter is different in different time periods, it can cause the time distribution range of the rising edge or the falling edge of the test data signal to expand (that is, the difference between the earliest occurrence time and the latest occurrence time of the rising edge or the falling edge increases), resulting in the widening of the clock phase interval corresponding to the rising edge or the falling edge of the test data signal (that is, the unstable sampling interval). In this way, even if a relatively large target clock phase shift amount is used, it will not easily move out of the unstable sampling interval during a single movement, thereby effectively searching for the clock phase boundary value.

[0143] As another optional embodiment of the present application, referring toFigure 6 , which is a schematic flowchart of a clock phase adjustment method provided in Embodiment 6 of the present application. As Figure 6 shown, the method may include but is not limited to:

[0144] Step S201: Based on the received initial test data signal, generate two processed test data signals, and alternately output the two processed test data signals in time; the time distribution ranges of the data signal edges generated by the two processed test data signals affected by the signal timing jitter are different.

[0145] For example, the time distribution range (i.e., the difference between the earliest arrival time and the latest arrival time of the data signal edge) of the data signal edge generated by one processed test data signal affected by the signal timing jitter becomes narrower, and the time distribution range of the data signal edge generated by the other processed test data signal affected by the signal timing jitter becomes wider.

[0146] By making the time distribution ranges of the data signal edges generated by the two processed test data signals affected by the signal timing jitter different, the total width of the clock phase interval (i.e., the unstable sampling interval) corresponding to the rising edge or falling edge of the test data signal can be expanded.

[0147] Step S202: Sample the two alternately output processed test data signals using a clock signal.

[0148] Step S203: Based on the sampled data signal obtained by sampling, determine the phase state corresponding to the current clock phase; the phase state characterizes the relationship between the sampled data signal and the test data signal.

[0149] Step S204: Based on the phase state, with the target clock phase shift amount as the single shift amount, starting from the current clock phase, move along the phase search direction until the clock phase critical value is searched; the target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to the transition between different phase states.

[0150] Step S205: Based on the clock phase critical value, determine the target clock phase.

[0151] In this embodiment, by making the time distribution ranges of the data signal edges generated by the two processed test data signals affected by the signal timing jitter different, the total width of the clock phase interval (i.e., the unstable sampling interval) corresponding to the rising edge or falling edge of the test data signal can be expanded. In this way, even if a relatively large target clock phase shift amount is used, it will not easily move out of the unstable sampling interval during a single move, thereby effectively searching for the clock phase boundary value.

[0152] As another optional embodiment of the present application, referring to Figure 7 , which is a schematic flowchart of a clock phase adjustment method provided in Embodiment 7 of the present application. This embodiment is mainly an implementation manner of the above step S201. As Figure 7 shown, step S201 may include but is not limited to:

[0153] Step S2011: Adjust the duty cycle of the received initial test data signal to obtain two processed test data signals with different duty cycles, and alternately output the two processed test data signals with different duty cycles in time.

[0154] In this embodiment, by adjusting the duty cycle of the received initial test data signal, two processed test data signals with different duty cycles are obtained. The high-level durations of the two processed test data signals with different duty cycles are different, which can cause the data signal edges (such as, falling edges) in the two processed test data signals to appear at different time points.

[0155] Subsequently, alternately outputting the two processed test data signals with different duty cycles in time can cause the data signal edges in the two processed test data signals to alternately appear at different time points, which can expand the time distribution range of the data signal edges. Correspondingly, the expansion of the time distribution range of the data signal edges can directly lead to the expansion of the clock phase interval (i.e., the unstable sampling interval) corresponding to the data signal edges.

[0156] After the expansion of the clock phase interval (i.e., the unstable sampling interval) corresponding to the data signal edges, even when using a relatively large target clock phase shift amount, it will not easily move out of the unstable sampling interval during a single movement, thereby effectively searching for the clock phase boundary value.

[0157] In this embodiment, it can be verified and displayed through the data eye diagram. For example, as Figure 8 shown, it can be reflected from the data eye diagram of the initial test data signal that the data signal edges of the initial test data signal are concentrated in a relatively narrow time window, corresponding to a relatively narrow unstable sampling interval. It can be reflected from the data eye diagrams of the two processed test data signals with different duty cycles that the data signal edges of the two processed test data signals with different duty cycles spread to a wider range, directly reflecting the expansion of the unstable sampling interval. This expansion can ensure that even when using a relatively large target clock phase shift amount, it will not easily move out of the unstable sampling interval during a single movement, thereby effectively searching for the clock phase boundary value.

[0158] As another alternative embodiment of the present application, a clock phase adjustment method provided for Embodiment 8 of the present application. This embodiment is mainly an implementation manner of the above step S2011, and step S2011 may include but is not limited to:

[0159] Step S31: Increase the duty cycle of the received initial test data signal to obtain a first test data signal.

[0160] In this embodiment, the high-level duration of the first test data signal can be higher than that of the initial test data signal. For example, the period of the initial test data signal is 200 ps, the duty cycle is 50%, and the high-level duration is 100 ps. After increasing the duty cycle of the initial test data signal, the duty cycle of the first test data signal is 60%. Accordingly, the high-level duration can be 120 ps, and the low-level duration can be 80 ps.

[0161] Step S32: Decrease the duty cycle of the received initial test data signal to obtain a second test data signal.

[0162] In this embodiment, the high-level duration of the second test data signal can be lower than that of the initial test data signal. For example, the period of the initial test data signal is 200 ps, the duty cycle is 50%, and the high-level duration is 100 ps. After decreasing the duty cycle of the initial test data signal, the duty cycle of the second test data signal is 40%. Accordingly, the high-level duration can be 80 ps, and the low-level duration can be 120 ps.

[0163] Step S33: Generate a divided-by-two clock signal based on the received clock signal.

[0164] In this embodiment, the frequency of the received clock signal can be divided by two and the period can be doubled to obtain a divided-by-two clock signal. For example, the period of the received clock signal is 100 ps, and the period of the divided-by-two clock signal is 200 ps.

[0165] Step S34: Based on the divided-by-two clock signal, alternately select one of the first test data signal and the second test data signal for output.

[0166] In this embodiment, the first test data signal can be selected based on the rising edge of the divided-by-two clock signal, and the second test data signal can be selected based on the falling edge of the divided-by-two clock signal. For example, within the first 100 ps of each period of the divided-by-two clock signal, the first test data signal is output, and the second test data signal is output in the next 100 ps.

[0167] In this embodiment, by increasing the duty cycle of the received initial test data signal, a first test data signal is obtained, and by decreasing the duty cycle of the received initial test data signal, a second test data signal is obtained. The high-level durations of the first test data signal and the second test data signal are different, which can cause the data signal edges of the first test data signal and the second test data signal to appear at different time points.

[0168] Subsequently, by alternately outputting the first test data signal and the second test data signal in time, the data signal edges of the first test data signal and the second test data signal can alternately appear at different time points, expanding the time distribution range of the data signal edges. Correspondingly, the expansion of the time distribution range of the data signal edges can directly lead to the expansion of the clock phase interval (i.e., the unstable sampling interval) corresponding to the data signal edges.

[0169] After the expansion of the clock phase interval (i.e., the unstable sampling interval) corresponding to the data signal edges, even if a relatively large target clock phase shift amount is used, it will not easily move out of the unstable sampling interval during a single movement, thereby effectively searching for the clock phase boundary value.

[0170] Next, the clock phase adjustment device provided by the present application will be introduced. The clock phase adjustment method device described below can be correspondingly referred to the clock phase adjustment method described above.

[0171] Refer to Figure 9 , the clock phase adjustment device includes: a sampling module 100, a first determination module 200, a search module 300, and a second determination module 400.

[0172] The sampling module 100 is configured to sample the received test data signal using a clock signal.

[0173] The first determination module 200 is configured to determine the phase state corresponding to the current clock phase based on the sampled data signal; the phase state characterizes the relationship between the sampled data signal and the test data signal.

[0174] The search module 300 is configured to, based on the phase state, use the target clock phase shift amount as the single movement amount, start from the current clock phase, and move along the phase search direction until the clock phase critical value is searched. The target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to the transition between different phase states.

[0175] The second determination module 400 is configured to determine the target clock phase based on the clock phase critical value.

[0176] The first determination module 200 may specifically be configured to:

[0177] Compare whether the sampled sampling data signal is consistent with the received test data signal to obtain a comparison result;

[0178] In response to the comparison result indicating consistency, determine that the phase state corresponding to the current clock phase is the first type of phase state;

[0179] In response to the comparison result indicating inconsistency, determine that the phase state corresponding to the current clock phase is the second type of phase state.

[0180] The target clock phase shift amount corresponding to the first type of phase state is greater than the target clock phase shift amount corresponding to the second type of phase state.

[0181] The first determination module 200, in response to the comparison result indicating consistency, determining that the phase state corresponding to the current clock phase is the first type of phase state may include:

[0182] In response to the comparison result indicating consistency and not yet searching to the first clock phase critical value, determine that the phase state corresponding to the current clock phase is the first phase state.

[0183] The first determination module 200, in response to the comparison result indicating inconsistency, determining that the phase state corresponding to the current clock phase is the second type of phase state, may include:

[0184] In response to the comparison result indicating inconsistency and not yet searching to the first clock phase critical value, determine that the phase state corresponding to the current clock phase is the second phase state.

[0185] The first determination module 200, in response to the comparison result indicating consistency, determining that the phase state corresponding to the current clock phase is the first type of phase state may include:

[0186] In response to the comparison result indicating consistency and having searched to the first clock phase critical value and not yet searching to the second clock phase boundary value, determine that the phase state corresponding to the current clock phase is the third phase state.

[0187] The first determination module 200, in response to the comparison result indicating inconsistency, determining that the phase state corresponding to the current clock phase is the second type of phase state, may include:

[0188] In response to the comparison result indicating inconsistency and having searched to the second clock phase critical value, determine that the phase state corresponding to the current clock phase is the fourth phase state.

[0189] The phase search direction is the phase change direction from the first clock phase critical value to the second clock phase critical value.

[0190] The search module 300 can be specifically used for:

[0191] Based on the third phase state, with the target clock phase shift amount corresponding to the first type of phase state as the single shift amount, starting from the current clock phase, move along the phase search direction. If a transition occurs between the third phase state and the fourth phase state, with the target clock phase shift amount corresponding to the first type of phase state as the single shift amount, starting from the clock phase where the transition occurs, move along the direction opposite to the phase search direction;

[0192] With the target clock phase shift amount corresponding to the second type of phase state as the single shift amount, starting from the new current clock phase, move along the phase search direction until reaching the second clock phase boundary value.

[0193] In this embodiment, the degree to which the test data signal is affected by signal timing jitter is different in different time periods; the signal timing jitter represents the deviation between the actual arrival time and the theoretical arrival time of the edge position of the test data signal.

[0194] In another embodiment of the present application, an electronic device is provided. Refer to Figure 10 , the electronic device includes: a hardware adjustment module 10 and a processor 20.

[0195] The hardware adjustment module 10 is used to adjust the duty cycle of the received test data signal to obtain two processed test data signals with different duty cycles, and alternately output the two processed test data signals with different duty cycles in time.

[0196] The processor 20 is used for:

[0197] Sampling the two processed test data signals with different duty cycles using a clock signal;

[0198] Based on the sampled data signal obtained by sampling, determine the phase state corresponding to the current clock phase; the phase state represents the relationship between the sampled data signal and the test data signal;

[0199] Based on the phase state, with the target clock phase shift amount as the single shift amount, starting from the current clock phase, move along the phase search direction until reaching the clock phase critical value, and the target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to the transition between different phase states;

[0200] Based on the clock phase critical value, determine the target clock phase.

[0201] As Figure 11 shown, the hardware adjustment module 10 may include but is not limited to:

[0202] A first unbalanced inverter (which may be denoted as Dcc_Up) 101, configured to increase the duty cycle of the received initial test data signal to obtain a first test data signal.

[0203] A second unbalanced inverter (which may be denoted as Dcc_Down) 102, configured to decrease the duty cycle of the received initial test data signal to obtain a second test data signal.

[0204] A clock frequency division module (which may be denoted as DFF) 103, configured to generate a divided-by-two clock signal based on the received clock signal.

[0205] A multiplexer (which may be denoted as MUX) 104, configured to alternately select one of the first test data signal and the second test data signal for output based on the divided-by-two clock signal.

[0206] In this embodiment, the hardware adjustment module 10 may further include: a first buffer (which may be denoted as Buffer1) 105, configured to denoise the received initial test data signal.

[0207] The first unbalanced inverter 101 may specifically be configured to increase the duty cycle of the initial test data signal after denoising to obtain a first test data signal.

[0208] The second unbalanced inverter 102 may specifically be configured to decrease the duty cycle of the initial test data signal after denoising to obtain a second test data signal.

[0209] In this embodiment, the hardware adjustment module 10 may be in a normally open state. Alternatively, the hardware adjustment module 10 may be turned on or off as needed. For example, as Figure 12 shown, in the case where it is determined that the data signal edges of the initial test data signal are concentratedly distributed in a relatively narrow time window, the hardware adjustment module 10 may be turned on, and the hardware adjustment module 10 alternately outputs the two processed test data signals with different duty cycles in time to the processor 20. In the case where it is determined that the time distribution range of the data signal edges of the initial test data signal is relatively wide, the hardware adjustment module 10 may be turned off, and the initial test data signal is directly output to the processor 20 after being denoised by a second buffer (which may be denoted as Buffer2) 30.

[0210] In addition, it should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided in this application, the connection relationships between the modules indicate that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0211] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits, or dedicated circuits. However, for this application, software program implementation is a better implementation method in more cases. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disc of a computer, and includes several instructions to enable a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods described in various embodiments of this application.

[0212] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0213] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center by wired means (such as coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless means (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

Claims

1. A clock phase adjustment method, comprising: Using a clock signal to sample a received test data signal; Determine the phase state corresponding to the current clock phase based on the sampled data signal obtained by sampling; The phase state characterizes the relationship between the sampled data signal and the test data signal; Based on the phase state, taking the target clock phase shift amount as a single shift amount, starting from the current clock phase, moving along the phase search direction until searching for a clock phase critical value, the target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to a transition between different phase states; Based on the clock phase threshold, a target clock phase is determined.

2. The clock phase adjustment method according to claim 1, wherein determining the phase state corresponding to the current clock phase based on the sampled data signal obtained by sampling comprises: Comparing whether the sampled data signal obtained by the sampling is consistent with the received test data signal to obtain a comparison result; In response to the comparison result indicating consistency, determining that the phase state corresponding to the current clock phase is a first type of phase state; In response to the comparison result indicating inconsistency, determining that the phase state corresponding to the current clock phase is a second type of phase state; The target clock phase shift amount corresponding to the first type of phase state is greater than the target clock phase shift amount corresponding to the second type of phase state.

3. The clock phase adjustment method according to claim 2, wherein the first type of phase state comprises: a first phase state and a third phase state; The second type of phase state includes: a second phase state and a fourth phase state; In response to the comparison result indicating consistency and the first clock phase critical value not being searched, determining that the phase state corresponding to the current clock phase is the first phase state; In response to the comparison result indicating inconsistency and the first clock phase critical value not being searched, determining that the phase state corresponding to the current clock phase is the second phase state; In response to the comparison result indicating consistency, and the first clock phase critical value has been searched for and the second clock phase boundary value has not been searched for, determining that the phase state corresponding to the current clock phase is a third phase state; In response to the comparison result indicating inconsistency and the second clock phase critical value having been searched, determining that the phase state corresponding to the current clock phase is a fourth phase state; The phase search direction is a phase change direction from a first clock phase threshold value to a second clock phase threshold value.

4. The clock phase adjustment method according to claim 3, wherein based on the phase state, taking the target clock phase movement amount as a single movement amount, starting from the current clock phase, moving along the phase search direction until the clock phase critical value is searched, comprises: Based on the third phase state, taking the target clock phase shift amount corresponding to the first type of phase state as a single shift amount, starting from the current clock phase, moving along the phase search direction, if a transition between the third phase state and the fourth phase state occurs, taking the target clock phase shift amount corresponding to the first type of phase state as a single shift amount, starting from the clock phase where the transition occurs, moving in a direction opposite to the phase search direction; The target clock phase movement amount corresponding to the second type of phase state is used as a single movement amount, and the new current clock phase is used as a starting point to move along the phase search direction until the second clock phase boundary value is searched.

5. According to the clock phase adjustment method of claim 1, the test data signal is affected by signal timing jitter to different degrees in different time periods; the signal timing jitter represents the deviation between the actual arrival time and the theoretical arrival time of the edge position of the test data signal.

6. The clock phase adjustment method according to claim 5, further comprising: Based on the received initial test data signal, two processed test data signals are generated, and the two processed test data signals are output alternately in time; the time distribution range of the data signal edges generated by the two processed test data signals under the influence of the signal timing jitter is different.

7. The clock phase adjustment method according to claim 6, wherein the generating two processed test data signals based on the received initial test data signal and outputting the two processed test data signals alternately in time comprises: The duty cycle of the received initial test data signal is adjusted to obtain two processed test data signals with different duty cycles, and the two processed test data signals with different duty cycles are output alternately in time.

8. The clock phase adjustment method according to claim 7, adjusting the duty cycle of the received initial test data signal to obtain two processed test data signals with different duty cycles, and outputting the two processed test data signals with different duty cycles alternately in time, comprising: Increasing the duty cycle of the received initial test data signal to obtain a first test data signal; reducing the duty cycle of the received initial test data signal to obtain a second test data signal; Based on the received clock signal, generate a clock signal with a frequency divided by two; Based on the two-frequency-divided clock signal, one signal is alternately selected from the first test data signal and the second test data signal for output.

9. A clock phase adjustment device, comprising: A sampling module, used for sampling a received test data signal using a clock signal; A first determination module is used to determine a phase state corresponding to a current clock phase based on a sampled data signal obtained by sampling; the phase state represents a relationship between the sampled data signal and the test data signal; A search module is used to, based on the phase state, take the target clock phase shift amount as a single shift amount, start from the current clock phase, and move along the phase search direction until a clock phase critical value is searched, wherein the target clock phase shift amount matches the current phase state; and the clock phase critical value corresponds to a transition between different phase states; The second determination module is used to determine a target clock phase based on the clock phase critical value.

10. An electronic device, comprising: A hardware adjustment module, used for adjusting the duty cycle of the received test data signal to obtain two processed test data signals with different duty cycles, and outputting the two processed test data signals with different duty cycles alternately in time; Processor for: Using a clock signal to sample the two processed test data signals having different duty cycles; Determine a phase state corresponding to a current clock phase based on a sampled data signal obtained by sampling; the phase state represents a relationship between the sampled data signal and the test data signal; Based on the phase state, taking the target clock phase shift amount as a single shift amount, starting from the current clock phase, moving along the phase search direction until searching for a clock phase critical value, the target clock phase shift amount matches the current phase state; the clock phase critical value corresponds to a transition between different phase states; Based on the clock phase threshold, a target clock phase is determined.

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