Three-dimensional ferroelectric memory array and preparation method and operation method thereof

Abstract

The invention discloses a three-dimensional ferroelectric memory array and a preparation method and an operation method thereof, and belongs to the technical field of microelectronics and integrated circuits. The three-dimensional ferroelectric memory array comprises memory units which are distributed on a substrate in an array mode in the vertical direction and the horizontal direction. Each memory unit is sequentially provided with a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a channel layer from left to right or from right to left in the horizontal direction. The floating gate metal layer is additionally arranged in the ferroelectric NAND Flash memory, so that electric field distribution between the ferroelectric material layer and the channel layer can be homogenized, local electric field change caused by non-ferroelectric phase is reduced, the influence of non-ferroelectric phase relative threshold voltage in the ferroelectric material layer is effectively shielded, fluctuation of the threshold voltage is reduced, and storage logic states are increased.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronics and integrated circuits, and particularly relates to a three-dimensional ferroelectric memory array, a preparation method thereof, and an array operation method. Background Art

[0002] With the continuous progress of process technologies, the stacking layers of 3D NAND Flash gradually increase, and the density of the memory continuously improves. However, with the increase in the stacking layers, the existing etching process becomes increasingly difficult to meet the production requirements. Especially in the preparation process of memories above the thousand-layer level, how to effectively control the etching accuracy and the height of each layer has become a major challenge. In order to continue to increase the stacking layers to improve the storage density, it is necessary to reduce the height of each layer.

[0003] However, the existing 3D NAND Flash has a relatively high operating voltage. When the height of each layer is thinned, the interference between adjacent cells increases, resulting in a decline in the storage performance and reliability of the device. Ferroelectric NAND (FeNAND), as an emerging storage technology, due to its relatively low operating voltage and the ability to stack at a relatively low height, has become one of the potential alternative solutions for thousand-layer NAND Flash. The characteristics of ferroelectric materials enable FeNAND to operate stably at low voltages. However, the phase distribution inside the ferroelectric layer will cause fluctuations in the threshold voltage of the device, thereby reducing the storage window and further affecting the stability of data reading and writing. Summary of the Invention

[0004] The purpose of the present invention is to propose a three-dimensional ferroelectric memory array, a preparation method thereof, and an operation method, which can shield the influence of non-ferroelectric regions inside the ferroelectric material layer on the threshold voltage of the device, improve the distribution, and increase the storage logic states of the three-dimensional NAND Flash.

[0005] The technical solution of the present invention is as follows:

[0006] A three-dimensional ferroelectric NAND Flash memory array, characterized in that it includes memory cells arrayed in the vertical and horizontal directions on a substrate. The memory cells are, from left to right or from right to left in the horizontal direction, a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer, and a channel layer in sequence. Among them, the floating gate metal layer serves as a conductive layer for uniforming the electric field distribution between the ferroelectric material layer and the channel layer, and an isolation dielectric layer is provided between the gate metal layers or the channel layers of adjacent memory cells.

[0007] Preferably, the materials of the gate metal layer and the floating gate metal layer are generally one or more of aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), gold (Au), tantalum (Ta), platinum (Pt), ruthenium (Ru), nickel (Ni), or alloys of the above materials, or metal oxides such as titanium nitride (TiN), indium oxide (In 2 O 3 , indium tin oxide (ITO), indium zinc oxide (InZnO x ), etc., or other low-resistivity materials such as tungsten silicide (WSi x , cobalt silicide (CoSi x ), graphite, etc. The height of the gate metal layer is 10 - 40 nm, and the thickness of the floating gate metal layer is 5 - 10 nm.

[0008] Preferably, the material of the ferroelectric material layer is generally a doped hafnium oxide system, such as hafnium zirconium oxide (HfZrO x , hafnium silicon oxide (HfSiO x , hafnium aluminum oxide (HfAlO x , hafnium lanthanum oxide (HfLaO x ), as well as ferroelectric materials such as aluminum nitride (AlN), aluminum scandium nitride (AlScN x ). The thickness of the ferroelectric material layer is 5 - 20 nm.

[0009] Preferably, the materials of the first and second isolation layers and the isolation dielectric layer are generally silicon oxide (SiO 2 , silicon nitride (Si 3 N 4 , aluminum oxide (Al 2 O 3 , niobium pentoxide (Nb 2 O 5 , hafnium oxide (HfO 2 , silicon oxynitride (SiO x N y ), or electrically insulating materials such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG). The thickness of the first and second isolation layers is 5 - 20 nm, and the thickness of the isolation dielectric layer is 10 - 30 nm.

[0010] Preferably, the material of the channel layer is generally single-crystalline silicon, polycrystalline silicon, silicon germanium alloy (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium oxide (In 2 O 3 , indium tungsten oxide (IWO), indium zinc oxide (InZnO x , indium gallium oxide (InGaO x ), etc., or transition metal sulfides such as molybdenum disulfide (MoS 2 , molybdenum diselenide (MoSe 2 , tungsten diselenide (WSe 2 , tungsten disulfide (WS 2Two-dimensional materials such as these. The thickness of the channel layer is 5-30 nm.

[0011] The present invention further provides a method for preparing a three-dimensional ferroelectric memory array, and its steps include the following:

[0012] 1) Deposit multiple layers of isolation layer / sacrificial layer stack on the substrate in sequence;

[0013] 2) Form a trench area through photolithography and etching;

[0014] 3) Etch away the sacrificial layer;

[0015] 4) Grow a gate metal layer to fill the position of the original sacrificial layer;

[0016] 5) Grow a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer, and a growth protection layer along the sidewalls in sequence;

[0017] 6) Etch away the second isolation layer, the floating gate metal layer, the ferroelectric material layer, and the first isolation layer at the bottom of the trench, and etch away the sidewall protection layer;

[0018] 7) Grow a channel layer;

[0019] 8) Grow an isolation dielectric layer to fill the trench and perform planarization.

[0020] Furthermore, a method for preparing a three-dimensional ferroelectric memory array is provided, and its steps include the following:

[0021] 1) Deposit multiple isolation dielectric layer / gate metal layer stacks on the substrate in sequence;

[0022] 2) Form a trench area through photolithography and etching;

[0023] 3) Grow a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer along the sidewalls in sequence, and grow a protection layer;

[0024] 4) Etch away the second isolation layer, the floating gate metal layer, the ferroelectric material layer, and the first isolation layer at the bottom of the trench, and use etching to remove the sidewall protection layer;

[0025] 5) Grow a channel layer;

[0026] 6) Grow an isolation dielectric layer to fill the trench and perform planarization.

[0027] Furthermore, a method for preparing a three-dimensional ferroelectric memory array is provided, and its steps include the following:

[0028] 1) Deposit multiple isolation dielectric layer / sacrificial layer stacks on the substrate in sequence;

[0029] 2) Form a trench area through photolithography and etching;

[0030] 3) Grow a first isolation layer, a ferroelectric material layer, a floating gate metal layer, and a second isolation layer in sequence along the sidewall, and grow a protective layer;

[0031] 4) Etch away the second isolation layer, the floating gate metal layer, the ferroelectric material layer, and the first isolation layer at the bottom of the trench, and use etching to remove the protective layer on the sidewall;

[0032] 5) Grow a channel layer;

[0033] 6) Grow an isolation dielectric layer to fill the trench and perform planarization;

[0034] 7) Etch away the sacrificial layer;

[0035] 8) Grow a gate metal layer to fill the position of the original sacrificial layer.

[0036] The present invention further provides an operation method for a ferroelectric NAND Flash memory array as follows:

[0037] 1) Programming: Apply a 0V voltage to the bit line where the selected memory cell is located, apply an inhibition voltage to the bit lines of the unselected memory cells, ground all source lines, apply a programming voltage to the word line where the selected memory cell is located, and apply a conduction voltage to the word lines of the unselected memory cells;

[0038] 2) Erasing: Apply a 0V voltage to all bit lines and all word lines, apply an erase voltage to the source line of the selected memory cell, and erase the entire string;

[0039] 3) Reading: Apply a read voltage to the bit line where the selected memory cell is located, apply a 0V voltage to the bit lines of the unselected memory cells, ground all source lines, apply a 1V voltage to the word line where the selected memory cell is located, float the word line voltage of the unselected memory cells, and read the bit line current of the selected memory cell and compare its magnitude with the reference current.

[0040] The present invention has the following advantages:

[0041] In the storage device structure of the FeNAND Flash memory array of the present invention, from left to right (from right to left) are a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer, a channel layer, and an isolation dielectric layer. Among them, there are unevenly distributed ferroelectric phases, antiferroelectric phases, and paraelectric phases in the ferroelectric material layer, and only the ferroelectric phase has a non-volatile storage function. The non-ferroelectric phase region does not have the characteristic of spontaneous polarization and usually has a low dielectric constant. The uneven distribution of the ferroelectric material layer and the non-ferroelectric region will affect the distribution of the gate electric field, thereby affecting the threshold voltage. The floating gate metal layer, as a conductive layer, can homogenize the electric field distribution between the ferroelectric material layer and the channel, reduce the local electric field change caused by the non-ferroelectric phase, effectively shield the influence of the non-ferroelectric phase inside the ferroelectric material layer on the threshold voltage, reduce the fluctuation of the threshold voltage, and increase the stored logic states. Description of the Drawings

[0042] Figure 1 Schematic diagram of the structure of a column of ferroelectric NAND Flash memory of the present invention;

[0043] Figure 2 Flow chart of the preparation of a ferroelectric NAND Flash string in the first embodiment of the present invention;

[0044] Figures 3 - 10 Cross-sectional view of the preparation process of a ferroelectric NAND Flash string in the first embodiment of the present invention;

[0045] Figure 11 For Figures 1 - 10 legend;

[0046] Figure 12 Schematic diagram of the topology of a ferroelectric NAND Flash string array of the present invention. Detailed Embodiments

[0047] The following combines the drawings to specifically illustrate the implementation manners of the present invention.

[0048] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention. However, those skilled in the art can understand that: without departing from the spirit and scope of the present invention and the appended claims, various substitutions and modifications are possible. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection required by the present invention is defined by the scope of the claims.

[0049] As Figure 1 shown, a three-dimensional ferroelectric NAND Flash memory in the first specific embodiment of the present invention. It is a device structure stacked in the vertical direction. Each memory, from left to right, is a gate metal layer TiN, a first isolation layer SiO 2 , a ferroelectric layer HfZrOx , a floating gate metal layer TiN, a second isolation layer SiO 2 and a channel layer Si, wherein there are non-ferroelectric phase regions with uneven distribution in the ferroelectric material layer located between the first isolation layer and the floating gate metal layer. Herein, the floating gate metal layer serves as a conductive layer for uniforming the electric field distribution between the ferroelectric material layer and the channel layer, and an isolation dielectric layer is provided between the gate metal layers or the channel layers of adjacent memory cells.

[0050] The preparation process of the String of the present invention is as Figure 2 shown, and specifically includes the following steps:

[0051] 1) Deposit a multi-layer isolation layer SiO 2 / sacrificial layer Si 3 N 4 stack on the substrate. The isolation layer is grown by chemical vapor deposition to be 20 nm of SiO 2 , and the sacrificial layer is grown by chemical vapor deposition to be 20 nm of Si 3 N 4 , as Figure 3 shown;

[0052] 2) Form a trench region through photolithography and etching, as Figure 4 shown;

[0053] 3) Etch away the sacrificial layer Si 3 N 4 , as Figure 5 shown;

[0054] 4) Use physical vapor deposition to grow the gate metal layer TiN to fill the original position of the sacrificial layer, as Figure 6 shown;

[0055] 5) Grow a 5 nm first isolation layer SiO 2 , a 10 nm ferroelectric material layer HfZrO x , a 5 nm floating gate metal layer TiN, and a 5 nm second isolation layer SiO 2 in sequence along the sidewalls. Grow a protective layer Si 3 N 4 . The first and second isolation layers and the protective layer are grown by chemical vapor deposition, and the ferroelectric material layer and the floating gate metal layer are grown by atomic layer deposition, as Figure 7 shown;

[0056] 6) Vertically dry-etch away the second isolation layer, the floating gate metal layer, the ferroelectric material layer, and the first isolation layer at the bottom of the trench, and use etching to remove the sidewall protective layer, as Figure 8 shown;

[0057] 7) Use chemical vapor deposition to grow a 10 nm polysilicon channel, asFigure 9 as shown;

[0058] 8) Grow the isolation dielectric layer SiO 2 to fill the trench, and perform planarization by chemical mechanical polishing, as Figure 10 shown.

[0059] The present invention further provides another preparation process, including the following steps:

[0060] 1) Sequentially deposit multiple interlayer isolation layer / gate metal layer stacks on the substrate, where the interlayer isolation layer is grown by plasma enhanced chemical vapor deposition of 20 nm of Si 3 N 4 , and the gate metal layer is grown by physical vapor deposition of 20 nm of TiN;

[0061] 2) Form a trench region for filling a ferroelectric material layer and a channel layer, etc. through lithography and etching;

[0062] 3) Sequentially grow a 5 nm first isolation layer SiO 2 , a 10 nm ferroelectric material layer HfZrO x , a 5 nm floating gate metal layer TiN, and a 5 nm second isolation layer SiO 2 , grow a protective layer Si 3 N 4 , where the first and second isolation layers and the protective layer are grown by chemical vapor deposition, and the ferroelectric material layer and the floating gate metal layer are grown by atomic layer deposition;

[0063] 4) Vertically dry etch to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer, and the first isolation layer at the bottom of the trench, and use etching to remove the sidewall protective layer;

[0064] 5) Grow a 10 nm polysilicon channel by chemical vapor deposition;

[0065] 6) Grow SiO 2 to fill the trench, and perform planarization by chemical mechanical polishing.

[0066] The present invention further provides another preparation method, and the specific steps are as follows:

[0067] 1) Sequentially deposit a multi-layer isolation layer SiO 2 / sacrificial layer Si 3 N 4 stack on the substrate, where the isolation layer is grown by chemical vapor deposition of 20 nm of SiO 2 , and the sacrificial layer is grown by chemical vapor deposition of 20 nm of Si 3 N 4 ;

[0068] 2) Form a trench region filled with a ferroelectric material layer and a channel layer, etc. through photolithography and etching;

[0069] 3) Grow a 5-nm first isolation layer SiO 2 , a 10-nm ferroelectric material layer HfZrO x , a 5-nm floating gate metal layer TiN, and a 5-nm second isolation layer SiO 2 in sequence along the sidewalls, and grow a protective layer Si 3 N 4 , where the first and second isolation layers and the protective layer are grown by chemical vapor deposition, and the ferroelectric material layer and the floating gate metal layer are grown by atomic layer deposition;

[0070] 4) Vertically dry-etch to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer, and the first isolation layer at the bottom of the trench, and use etching to remove the sidewall protective layer;

[0071] 5) Grow a 10-nm polysilicon channel by chemical vapor deposition;

[0072] 6) Grow an isolation dielectric layer SiO 2 to fill the trench, and perform planarization by chemical mechanical polishing;

[0073] 7) Etch to remove the sacrificial layer Si 3 N 4 ;

[0074] 8) Grow a gate metal layer TiN by physical vapor deposition to fill the position of the original sacrificial layer.

[0075] The topological structure of the String array of the present invention is as Figure 12 shown, and the array operation method is as follows:

[0076] Programming: Taking the programming of the first cell of the first string as an example, apply a 0-V voltage to the bit line BL1, apply a 2.5-V suppression voltage to the bit lines BL2 and BL3, ground all source lines, apply a programming voltage V program (4 V) to the word line WL1, and apply a conduction voltage V pass (2 V) to the word lines WL2 and WL3;

[0077] Erasing: Taking the erasing of the first string as an example, apply a 0-V voltage to all bit lines and all word lines, apply an erasing voltage V erase (4 V) to the source line SL1, and apply a 0-V voltage to the source lines SL2 and SL3;

[0078] Reading: Taking the reading of the first cell of the first string as an example, apply a reading voltage V read(0.2–2V), a voltage of 0V is applied to bit lines BL2 and BL3, a voltage of 1V is applied to word line WL1, word lines WL2 and WL3 are floating, and all source lines are grounded. If the current of bit line BL1 is higher than the reference current I ref , the data information stored in the first cell is "1"; if the current of bit line BL1 is lower than the reference current I ref , the data information stored in the first cell is "0".

[0079] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify it into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A three-dimensional ferroelectric memory array, characterized in that: The invention comprises memory cells arranged in an array along the vertical direction and the horizontal direction on a substrate, wherein the memory cells are sequentially composed of a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a channel layer from left to right or from right to left in the horizontal direction, wherein the floating gate metal layer is used as a conductive layer for uniformly distributing the electric field between the ferroelectric material layer and the channel layer, and an isolation dielectric layer is provided between the gate metal layers or the channel layers of adjacent memory cells.

2. The three-dimensional ferroelectric memory array according to claim 1, characterized in that: The gate metal layer and the floating gate metal layer are made of aluminum Al, tungsten W, titanium Ti, cobalt Co, gold Au, tantalum Ta, platinum Pt, ruthenium Ru, nickel Ni or one or more of the alloys of the above materials, or titanium nitride TiN, indium oxide In2O3, indium tin oxide ITO, indium zinc oxide InZnO x Metal oxide, or tungsten silicide WSi x 、Cobalt silicide CoSi x , graphite material, the floating gate metal layer has a thickness of 5-10nm, and the gate metal layer has a thickness of 10-40nm.

3. The three-dimensional ferroelectric memory array according to claim 1, wherein: The ferroelectric material layer is hafnium zirconium oxide HfZrO x 、HfSiO x 、HfAlO x 、HfLaO x , as well as aluminum nitride AlN, aluminum scandium nitride AlScN x Ferroelectric material, the thickness of the ferroelectric material layer is 5-20nm.

4. The three-dimensional ferroelectric memory array according to claim 1, wherein: The materials of the first and second isolation layers and the isolation dielectric layer are silicon oxide SiO2, silicon nitride Si3N4, aluminum oxide Al2O3, niobium pentoxide Nb2O5, hafnium oxide HfO2, silicon oxynitride SiO x N y , or phosphosilicate glass PSG, borophosphosilicate glass BPSG electrical insulating material, the thickness of the first and second isolation layers is 5-20nm, and the thickness of the isolation layer is 10-30nm.

5. The three-dimensional ferroelectric memory array according to claim 1, wherein: The channel layer material is single crystal silicon, polycrystalline silicon, silicon germanium alloy SiGe, silicon carbide SiC, gallium arsenide GaAs, gallium nitride GaN, or indium gallium zinc oxide IGZO, indium oxide In2O3, tungsten-doped indium oxide IWO, indium zinc oxide InZnO x 、Indium Gallium Oxide InGaO x , or molybdenum disulfide MoS2, molybdenum diselenide MoSe2, tungsten diselenide WSe2, tungsten disulfide WS2 two-dimensional material, the channel layer thickness is 5-30nm.

6. A method for preparing the three-dimensional ferroelectric memory array as claimed in claim 1, wherein the steps include: 1) depositing multiple isolation layer / sacrificial layer stacks on the substrate in sequence; 2) forming a groove region by photolithography and etching; 3) etching to remove the sacrificial layer; 4) growing a gate metal layer to fill the position of the original sacrificial layer; 5) growing a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a growth protection layer in sequence along the side wall; 6) etching and removing the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching and removing the sidewall protection layer; 7) growing a channel layer; 8) Grow an isolation dielectric layer to fill the trench and perform planarization.

7. A method for preparing a three-dimensional ferroelectric memory array as claimed in claim 1, comprising the following steps: 1) depositing a plurality of isolation dielectric layer / gate metal layer stacks on the substrate in sequence; 2) forming a groove region by photolithography and etching; 3) growing a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer, and a protective layer in sequence along the sidewall; 4) etching and removing the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and removing the sidewall protection layer by etching; 5) growing a channel layer; 6) Grow an isolation dielectric layer to fill the trench and perform planarization.

8. A method for preparing the three-dimensional ferroelectric memory array as claimed in claim 1, comprising the following steps: 1) depositing a plurality of isolation dielectric layer / sacrificial layer stacks on the substrate in sequence; 2) forming a groove region by photolithography and etching; 3) growing a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer, and a protective layer in sequence along the sidewall; 4) etching and removing the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and removing the sidewall protection layer by etching; 5) growing a channel layer; 6) growing an isolation dielectric layer to fill the trench and perform planarization; 7) etching to remove the sacrificial layer; 8) Grow a gate metal layer to fill the position of the original sacrificial layer.

9. The method for operating a three-dimensional ferroelectric memory array as claimed in claim 1, wherein the steps include: 1) Programming: 0V voltage is applied to the bit line where the selected memory cell is located, inhibition voltage is applied to the bit line of the unselected memory cell, all source lines are grounded, programming voltage is applied to the word line where the selected memory cell is located, and conduction voltage is applied to the word line of the unselected memory cell; 2) Erase: 0V voltage is applied to all bit lines and all word lines, and the source line of the selected memory cell is applied with erase voltage to erase the entire string; 3) Reading: A read voltage is applied to the bit line of the selected memory cell, a 0V voltage is applied to the bit lines of the unselected memory cells, all source lines are grounded, a 1V voltage is applied to the word line of the selected memory cell, the word line voltage of the unselected memory cells is floated, the bit line current of the selected memory cell is read and compared with the reference current.

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