3D-RRAM structure and preparation method thereof
By forming a 3D structure in RRAM, the problem of slow storage writing and erasing of planar RRAM is solved, and a higher storage rate and overall chip operation rate are achieved.
Patent Information
- Application Number
- CN202510330736.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-06-13
AI Technical Summary
In the prior art, the RRAM storage write and erase speed of planar structures is slow, resulting in a lower overall chip operation rate.
Using a 3D-RRAM structure, the lower electrode layer, the solid dielectric layer and the upper electrode layer are formed in sequence by forming the lower electrode layer, the solid dielectric layer and the upper electrode layer in the grooves that penetrate through the dielectric layer and exposed the surface of the underlying metal layer.
The 3D-RRAM structure makes more efficient use of physical space, improves the area of the RRAM solid dielectric layer, significantly improves the speed of RRAM storage writing and erasing, thereby improving the overall chip operation rate.
Smart Images
Figure CN120152296A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device fabrication, and particularly to a 3D-RRAM structure and a method for fabricating the same. Background Art
[0002] The embedded flash technology of traditional non-volatile memory (NOR Flash) has reached the physical limit at the semiconductor 40-nanometer process node. In the process nodes below 40 nanometers, the high-k metal gate (HKMG) material technology cannot be directly applied to the polysilicon process of traditional NOR Flash memory cells, resulting in complex processes and a significant increase in costs. Currently, no embedded NOR Flash suppliers have achieved mass production at the 28-nanometer and below process nodes, which poses a major challenge to embedded memory technology.
[0003] Meanwhile, the emergence of the novel embedded non-volatile memory back-end capacitance process technology has broken the limitation of the traditional front-end process device size at the process nodes below 40 nanometers. Among them, the resistive random access memory (RRAM), as a leading technology in the novel embedded non-volatile memory, stores and erases data by changing the resistivity of the solid dielectric in the material. When storing data, the RRAM solid dielectric material forms a conductive "filament" under the action of an external electric field and enters the low-resistance state; when erasing data, the "filament" is broken by reverse biasing and enters the high-resistance state. However, the existing RRAM is usually a planar structure, which has the problems of slow storage writing and erasing speeds, resulting in a low overall operating rate of the chip. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a 3D-RRAM structure and a method for fabricating the same, which are used to solve the problem that the planar-structured RRAM in the prior art has slow storage writing and erasing speeds, resulting in a low overall operating rate of the chip.
[0005] To achieve the above object and other related objects, the present invention provides a 3D-RRAM structure, which sequentially includes, from bottom to top: a bottom metal layer, a dielectric layer, an isolation layer, and a redistribution layer; and further includes:
[0006] a groove that penetrates the dielectric layer and exposes the surface of the bottom metal layer;
[0007] a lower electrode layer, a solid dielectric layer, and an upper electrode layer that are sequentially formed on the bottom wall and side walls of the groove;
[0008] a first interconnect metal layer that fills the groove;
[0009] the redistribution layer penetrates the isolation layer and is in contact connection with the first interconnect metal layer.
[0010] Optionally, the rewiring layer further includes: a logical area electrical lead-out hole that penetrates through the isolation layer and the dielectric layer and exposes the surface of the bottom metal layer, and a second interconnect metal layer that fills the logical area electrical lead-out hole; the rewiring layer is in contact connection with the second interconnect metal layer.
[0011] Optionally, the dielectric layer sequentially includes, from bottom to top: an etch stop layer, an insulating protection layer, and a ULK dielectric layer.
[0012] Furthermore, the material of the etch stop layer is SiCN; the material of the insulating protection layer is TEOS; the material of the ULK dielectric layer is silicon oxide; the rewiring layer includes a wiring dielectric layer and a wiring metal layer, the material of the wiring dielectric layer is silicon oxide, the material of the wiring metal layer is copper; the material of the first interconnect metal layer is copper; the material of the isolation layer is SiCN or SiN.
[0013] Optionally, a contact layer is formed on the surface of the bottom wall and the side wall of the groove, and the material of the contact layer is titanium nitride.
[0014] Optionally, the thickness of the solid dielectric layer is not greater than
[0015] The present invention also provides a preparation method of a 3D-RRAM structure, and the preparation method includes:
[0016] S1. Provide a semiconductor structure, on which a bottom metal layer is formed.
[0017] S2. Form a dielectric layer on the bottom metal layer.
[0018] S3. Form a groove that penetrates through the dielectric layer.
[0019] S4. Sequentially form a lower electrode layer, a solid dielectric layer, and an upper electrode layer in the groove and on the dielectric layer.
[0020] S5. Deposit a first interconnect metal layer on the upper surface of the upper electrode layer, and the first interconnect metal layer at least fills the groove.
[0021] S6. Thin and planarize the upper surface of the obtained structure until the top surface of the dielectric layer is exposed.
[0022] S7. Form an isolation layer on the surface of the obtained structure.
[0023] S8. Form a rewiring layer on the isolation layer, and the rewiring layer penetrates through the isolation layer and is in contact connection with the first interconnect metal layer.
[0024] Optionally, before forming the lower electrode layer in step S4, a contact layer is formed on the surface of the groove and the surface of the dielectric layer.
[0025] Optionally, in step S8, a dual damascene process is used to form the rewiring layer, and when forming the rewiring layer, it further includes forming a logical region electrical lead-out hole that penetrates through the isolation layer and the dielectric layer and exposes the surface of the bottom metal layer, and filling the logical region electrical lead-out hole with a second interconnection metal layer, and the step of the rewiring layer being in contact connection with the second interconnection metal layer.
[0026] Further, the method for forming the rewiring layer in step S8 includes:
[0027] S81, forming a wiring dielectric layer on the isolation layer;
[0028] S82, using photolithography to etch the wiring dielectric layer, the isolation layer and the dielectric layer to obtain the logical region electrical lead-out hole, an interconnection hole that exposes the surface of the first interconnection metal layer, and a wiring metal layer pattern groove;
[0029] S83, forming a filling metal layer on the surface of the obtained structure, and the filling metal layer at least fills the logical region electrical lead-out hole, the interconnection hole and the wiring metal layer pattern groove;
[0030] S84, using a chemical mechanical polishing process to remove the filling metal layer on the surface of the wiring dielectric layer to obtain the rewiring layer.
[0031] As described above, the 3D-RRAM structure and its manufacturing method of the present invention have the following beneficial effects: adopting the back-end capacitor process technology, it can be used as a substitute for Flash embedded memory in future process nodes below 40 nanometers. It forms a 3D-structured RRAM by sequentially forming a lower electrode layer, a solid dielectric layer and an upper electrode layer in a groove that penetrates through the dielectric layer and exposes the surface of the bottom metal layer. Compared with the planar structure in the prior art, the 3D-RRAM structure makes more effective use of physical space. When the RRAM structure density in the layout design is the same, the 3D-RRAM structure greatly increases the area of the RRAM solid dielectric layer, improves the speed of RRAM storage writing and erasing, and thus improves the overall chip operation rate. Description of the Drawings
[0032] Figure 1 It shows a cross-sectional structure schematic diagram of the 3D-RRAM structure of the present invention.
[0033] Figure 2 It shows a flow schematic diagram of the manufacturing method of the 3D-RRAM structure of the present invention.
[0034] Figures 3 to 12 It shows the structural schematic diagrams presented in each step of the present invention when preparing the 3D-RRAM structure.
[0035] Element number description
[0036] 10 Bottom metal layer
[0037] 11 Dielectric layer
[0038] 111 Etch stop layer
[0039] 112 Insulating protection layer
[0040] 113 ULK dielectric layer
[0041] 12 Isolation layer
[0042] 13 Rewiring layer
[0043] 14 Groove
[0044] 15 Contact layer
[0045] 16 Lower electrode layer
[0046] 17 Solid dielectric layer
[0047] 18 Upper electrode layer
[0048] 19 First interconnection metal layer
[0049] 20 Electrical lead-out hole in the logic area
[0050] 21 Second interconnection metal layer
[0051] 22 Wiring dielectric layer
[0052] 23 Wiring metal layer
[0053] 24 Interconnection hole
[0054] 25 Wiring metal layer pattern groove
[0055] 26 Filling metal layer
[0056] Steps S1 to S8 Specific implementation manners
[0057] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0058] Please refer toFigures 1 to 12 It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0059] As shown in Figure 1 this embodiment provides a 3D-RRAM structure, which sequentially includes, from bottom to top: a bottom metal layer 10, a dielectric layer 11, an isolation layer 12, and a redistribution layer 13; it also includes:
[0060] a groove 14 that penetrates the dielectric layer 11 and exposes the surface of the bottom metal layer 10;
[0061] a lower electrode layer 16, a solid dielectric layer 17, and an upper electrode layer 18 that are sequentially formed on the bottom wall and side walls of the groove 14;
[0062] a first interconnect metal layer 19 that fills the groove 14;
[0063] the redistribution layer 13 penetrates the isolation layer 12 and is in contact connection with the first interconnect metal layer 19.
[0064] The 3D-RRAM structure of this embodiment adopts a back-end capacitor process technology and can be used as a substitute for Flash embedded memory in future process nodes below 40 nanometers. It forms a 3D structure of RRAM by sequentially forming a lower electrode layer, a solid dielectric layer, and an upper electrode layer in a groove that penetrates the dielectric layer and exposes the surface of the bottom metal layer. Compared with the planar structure in the prior art, the 3D-RRAM structure makes more effective use of physical space. When the RRAM structure density in the layout design is the same, the 3D-RRAM structure greatly increases the area of the RRAM solid dielectric layer, improves the speed of RRAM storage writing and erasing, and thus improves the overall chip operation rate.
[0065] As an example, as shown in Figure 1 the redistribution layer 13 further includes: a logic area electrical lead-out hole 20 that penetrates the isolation layer 12 and the dielectric layer 11 and exposes the surface of the bottom metal layer 10, and a second interconnect metal layer 21 that fills the logic area electrical lead-out hole 20; the redistribution layer 13 is in contact connection with the second interconnect metal layer 21, enabling the 3D-RRAM memory cell to be tightly integrated with other functional modules (such as processors, controllers, etc.) of the system on chip (SoC), reducing additional process steps and costs.
[0066] As an example, as shown in Figure 1As shown, the dielectric layer 11 sequentially includes, from bottom to top: an etch stop layer 111, an insulating protection layer 112, and a ULK dielectric layer 113.
[0067] Further, the material of the etch stop layer 111 is preferably nitride-doped silicon carbide (SiCN), so that the good blocking performance of SiCN can be utilized to reduce or even avoid the diffusion of the material of the bottom metal layer 10 (such as copper) into the insulating protection layer 112, thereby improving the stability and reliability of the RRAM structure.
[0068] Further, the material of the insulating protection layer 112 is TEOS; the rewiring layer 13 includes a wiring dielectric layer 22 and a wiring metal layer 23, the material of the bottom metal layer 10 is preferably copper; the material of the wiring metal layer 23 is preferably copper; the material of the first interconnection metal layer 19 is preferably copper, so as to significantly reduce the signal transmission delay by utilizing the low resistivity of copper and improve the overall operation speed of the chip.
[0069] Further, the material of the ULK (ultra-low dielectric constant) dielectric layer 113 is preferably silicon oxide, the material of the wiring dielectric layer 22 is preferably silicon oxide, and the materials of the ULK dielectric layer 113 and the wiring dielectric layer 22 are both ULK materials, so as to reduce the leakage current of the RRAM structure, reduce the capacitance effect between wires, and further reduce the signal transmission delay and improve the overall operation speed of the chip.
[0070] Further, the material of the isolation layer 12 can be SiCN or SiN (silicon nitride) to effectively prevent the leakage or interference of electrical signals between the structure in the groove 14 and the structure above it, and ensure the stability of the RRAM structure.
[0071] As an example, a contact layer 15 is formed on the surfaces of the bottom wall and side walls of the groove 14, and the material of the contact layer 15 includes but is not limited to titanium nitride. In this embodiment, the material of the contact layer 15 is titanium nitride to form a lower contact resistance between the bottom metal layer 10 and the lower electrode layer 16.
[0072] When the non-volatile memory performs data storage and writing, the material of the solid dielectric layer 17 forms a conductive "filament" and enters the low resistance state under the action of an external electric field. When data is erased, by applying reverse voltage, the "filament" is broken and enters the high resistance state. The thinner the thickness of the solid dielectric layer 17, the lower the forward voltage (V form ) required to form the conductive "filament". The lower V form can significantly improve the writing speed of the memory. Preferably, the thickness of the solid dielectric layer 17 used in this embodiment is not greater than to reduce the energy required for the electric field to penetrate the solid dielectric layer 17 and lower V form so as to improve the speed of the non-volatile memory when performing data storage writing.
[0073] This embodiment also provides a preparation method for a 3D-RRAM structure for preparing the above-mentioned 3D-RRAM structure, but is not limited thereto, and other suitable preparation methods are also applicable. The foregoing content can be fully cited herein, and will not be repeated hereinafter for the sake of brevity. As Figure 2 shown, the preparation method includes:
[0074] S1, providing a semiconductor structure, on which a bottom metal layer is formed;
[0075] S2, forming a dielectric layer on the bottom metal layer;
[0076] S3, forming a groove penetrating the dielectric layer;
[0077] S4, sequentially forming a lower electrode layer, a solid dielectric layer and an upper electrode layer in the groove and on the dielectric layer;
[0078] S5, depositing a first interconnection metal layer on the upper surface of the upper electrode layer, and the first interconnection metal layer at least fills the groove;
[0079] S6, thinning and planarizing the upper surface of the obtained structure until the top surface of the dielectric layer is exposed;
[0080] S7, forming an isolation layer on the surface of the obtained structure;
[0081] S8, forming a rewiring layer on the isolation layer, and the rewiring layer penetrates the isolation layer and is in contact connection with the first interconnection metal layer.
[0082] The preparation method of the 3D-RRAM structure in this embodiment adopts the back-end capacitor process technology and can be used as a substitute for the Flash embedded memory in future process nodes below 40 nanometers. It forms a 3D structure RRAM by sequentially forming a lower electrode layer, a solid dielectric layer and an upper electrode layer in the groove that penetrates the dielectric layer and exposes the surface of the bottom metal layer. Compared with the planar structure in the prior art, the 3D-RRAM structure makes more effective use of physical space. When the RRAM structure density in the layout design is the same, the 3D-RRAM structure greatly increases the area of the RRAM solid dielectric layer, improves the speed of RRAM storage writing and erasing, and thus improves the overall chip operation rate.
[0083] The following will specifically describe the preparation method of the 3D-RRAM structure in this embodiment with reference to the accompanying drawings.
[0084] As shown Figure 3 in FIG. 1, first, step S1 is performed to provide a semiconductor structure on which a bottom metal layer 10 is formed, and then step S2 is performed to form a dielectric layer 11 on the bottom metal layer 10.
[0085] As an example, the dielectric layer 11 sequentially includes, from bottom to top: an etch stop layer 111, an insulating protection layer 112, and a ULK dielectric layer 113.
[0086] As shown Figure 4 in FIG. 2, then step S3 is performed to form a groove 14 penetrating through the dielectric layer 11.
[0087] As shown Figure 6 in FIG. 3, then step S4 is performed to sequentially form a lower electrode layer 16, a solid dielectric layer 17, and an upper electrode layer 18 in the groove 14 and on the dielectric layer 11.
[0088] As an example, as shown Figure 5 in FIG. 4, a contact layer 15 is formed on the surface of the groove 14 and the surface of the dielectric layer 11 before forming the lower electrode layer 16.
[0089] As shown Figure 7 in FIG. 5, then step S5 is performed to deposit a first interconnect metal layer 19 on the upper surface of the upper electrode layer 18, and the first interconnect metal layer 19 at least fills the groove 14.
[0090] As an example, the first interconnect metal layer 19 can be formed by physical vapor deposition process, or other suitable processes, which are not overly limited here.
[0091] As shown Figure 8 in FIG. 6, then step S6 is performed to thin and planarize the upper surface of the obtained structure as shown Figure 7 in FIG. 7 until the top surface of the dielectric layer 11 is exposed.
[0092] As an example, chemical mechanical polishing (CMP) process can be used to thin and planarize the upper surface of the structure as shown Figure 7 in FIG. 8.
[0093] As shown Figure 9 in FIG. 9, then step S7 is performed to form an isolation layer 12 on the surface of the obtained structure.
[0094] As shown Figure 12 in FIG. 10, then step S8 is performed to form a re - wiring layer 13 on the isolation layer 12, and the re - wiring layer 13 penetrates through the isolation layer 12 and is in contact connection with the first interconnect metal layer 19.
[0095] As an example, in step S8, the rewiring layer 13 is formed by a dual damascene process, and as Figure 12 shown, when forming the rewiring layer 13, it also includes forming a logical area electrical lead hole 20 that penetrates through the isolation layer 12 and the dielectric layer 11 and exposes the surface of the underlying metal layer 10 (as Figure 10 and Figure 12 shown), and a step of filling the logical area electrical lead hole 20 with a second interconnect metal layer 21, and the rewiring layer 13 is in contact connection with the second interconnect metal layer 21.
[0096] As a further example, as Figures 10 to 12 shown, the method of forming the rewiring layer 13 in step S8 includes:
[0097] S81, as Figure 10 shown, forming a wiring dielectric layer 22 on the isolation layer 12.
[0098] S82, as Figure 10 shown, using a lithography process to etch the wiring dielectric layer 22, the isolation layer 12, and the dielectric layer 11 to obtain the logical area electrical lead hole 20, an interconnect hole 24 that exposes the surface of the first interconnect metal layer 19, and a wiring metal layer pattern groove 25.
[0099] S83, as Figure 11 shown, forming a filling metal layer 26 on the surface of the obtained structure, and the filling metal layer 26 at least fills the logical area electrical lead hole 20, the interconnect hole 24, and the wiring metal layer pattern groove 25.
[0100] S84, as Figure 12 shown, using a chemical mechanical polishing process to remove the filling metal layer 26 on the surface of the wiring dielectric layer 22 to obtain the rewiring layer 13; it should be noted here that the remaining (not removed) filling metal layer 26, the logical area electrical lead hole 20, the interconnect hole 24, and the wiring metal layer pattern groove 25 together form the rewiring layer 13.
[0101] In summary, for the 3D-RRAM structure and its manufacturing method of the present invention, the back-end capacitor process technology is adopted, which can be used as a substitute for Flash embedded memory in future process nodes below 40 nm. By sequentially forming a lower electrode layer, a solid dielectric layer, and an upper electrode layer in a groove that penetrates the dielectric layer and exposes the surface of the underlying metal layer, a 3D structure of RRAM is formed. Compared with the planar structure in the prior art, the 3D-RRAM structure makes more effective use of physical space. When the RRAM structure density in the layout design is the same, the 3D-RRAM structure greatly increases the area of the RRAM solid dielectric layer, improves the storage writing and erasing speed of the RRAM, and thus improves the overall chip operation speed. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0102] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A 3D-RRAM structure, characterized in that: The 3D-RRAM structure includes, from bottom to top, a bottom metal layer, a dielectric layer, an isolation layer, and a rewiring layer; and further includes: A groove penetrating the dielectric layer and exposing the surface of the underlying metal layer; A lower electrode layer, a solid dielectric layer and an upper electrode layer are sequentially formed on the bottom wall and the side wall of the groove; A first interconnect metal layer filling the groove; The rewiring layer passes through the isolation layer and is in contact with and connected to the first interconnect metal layer.
2. The 3D-RRAM structure according to claim 1, characterized in that: The rewiring layer also includes: a logic area electrical lead-out hole that penetrates the isolation layer and the dielectric layer and exposes the surface of the bottom metal layer, and a second interconnect metal layer that fills the logic area electrical lead-out hole; the rewiring layer is in contact with the second interconnect metal layer.
3. The 3D-RRAM structure according to claim 1, characterized in that: The dielectric layer includes, from bottom to top, an etching stop layer, an insulating protection layer and a ULK dielectric layer.
4. The 3D-RRAM structure according to claim 3, characterized in that: The material of the etching stop layer is SiCN; the material of the insulating protection layer is TEOS; the material of the ULK dielectric layer is silicon oxide; the rewiring layer includes a wiring dielectric layer and a wiring metal layer, the material of the wiring dielectric layer is silicon oxide, and the material of the wiring metal layer is copper; the material of the first interconnect metal layer is copper; the material of the isolation layer is SiCN or SiN.
5. The 3D-RRAM structure according to claim 1, characterized in that: A contact layer is formed on the surface of the bottom wall and the side wall of the groove, and the material of the contact layer is titanium nitride.
6. The 3D-RRAM structure according to claim 1, characterized in that: The thickness of the solid dielectric layer is not greater than 7. A method for preparing a 3D-RRAM structure, characterized in that: The preparation method comprises: S1, providing a semiconductor structure, wherein a bottom metal layer is formed on the semiconductor structure; S2, forming a dielectric layer on the bottom metal layer; S3, forming a groove penetrating the dielectric layer; S4, sequentially forming a lower electrode layer, a solid dielectric layer and an upper electrode layer in the groove and on the dielectric layer; S5, depositing a first interconnect metal layer on the upper surface of the upper electrode layer, wherein the first interconnect metal layer at least fills the groove; S6, thinning and flattening the upper surface of the obtained structure until the top surface of the dielectric layer is exposed; S7, forming an isolation layer on the surface of the obtained structure; S8, forming a rewiring layer on the isolation layer, wherein the rewiring layer penetrates the isolation layer and contacts and connects with the first interconnect metal layer.
8. The method for preparing a 3D-RRAM structure according to claim 7, characterized in that: In step S4, before forming the lower electrode layer, a contact layer is formed on the surface of the groove and the surface of the dielectric layer.
9. The method for preparing a 3D-RRAM structure according to claim 7, characterized in that: In step S8, the dual damascene process is used to form the rewiring layer, and the formation of the rewiring layer also includes the steps of forming a logic area electrical lead-out hole that penetrates the isolation layer and the dielectric layer and exposes the surface of the underlying metal layer, and using a second interconnect metal layer to fill the logic area electrical lead-out hole, and the rewiring layer is in contact with the second interconnect metal layer.
10. The method for preparing a 3D-RRAM structure according to claim 9, characterized in that: The method of forming the rewiring layer in step S8 includes: S81, forming a wiring dielectric layer on the isolation layer; S82, etching the wiring dielectric layer, the isolation layer and the dielectric layer by a photolithography process to obtain the electrical lead-out holes of the logic area, the interconnection holes exposing the surface of the first interconnection metal layer and the wiring metal layer pattern grooves; S83, forming a filling metal layer on the surface of the obtained structure, wherein the filling metal layer at least fills the electrical lead-out holes of the logic area, the interconnection holes and the wiring metal layer pattern grooves; S84, removing the filling metal layer on the surface of the wiring dielectric layer by a chemical mechanical polishing process to obtain the rewiring layer.