A silicon carbide power device with low specific on-resistance and high reliability and a method for manufacturing the same

Abstract

The present invention discloses a silicon carbide power device with low specific on-resistance and high reliability and a method for manufacturing the same. The invention provides a first conductive type semiconductor carrier diffusion layer below a portion of a second conductive type semiconductor well region, that is, directly below a first conductive type semiconductor source region, to reduce the specific on-resistance of the device. Furthermore, the protruding semiconductor well regions adjacent to the left and right sides of the semiconductor carrier diffusion layer and the second conductive type semiconductor shielding region at the bottom of the first trench jointly modulate the gate oxide electric field, which can further reduce the gate oxide electric field compared to introducing only the semiconductor shielding region at the bottom of the trench, thereby improving the reliability of the device. By setting up a series of structures in the present invention, without increasing the complexity of the process, not only the specific on-resistance and reliability of the device are optimized, but also the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices, and more particularly to a silicon carbide power device with low specific on-resistance and high reliability and a manufacturing method thereof. Background Art

[0002] In recent years, silicon carbide planar MOSFETs have developed by leaps and bounds. However, as the unit cell size gradually shrinks, the JFET resistance becomes larger and larger, which ultimately makes it meaningless to optimize the device's specific on-resistance by reducing the unit cell size. Silicon carbide trench MOSFETs can solve this contradiction because they eliminate the JFET resistance, which can greatly increase the unit cell density and channel density, thereby significantly reducing the device's specific on-resistance. How silicon carbide trench MOSFETs can achieve low specific on-resistance while ensuring high reliability is a key focus of researchers. The present invention uses a pattern after photolithography of the first conductive type semiconductor source region for ion implantation to prepare a first conductive type carrier diffusion layer, which not only optimizes the device's specific on-resistance, but also modulates the gate oxide electric field without adding a mask. At the same time, the present invention also introduces a second trench in the contact hole preparation process. By adjusting its width and depth, the device can also achieve low specific on-resistance and high reliability. Summary of the Invention

[0003] (1) Technical problems solved

[0004] In response to the problems existing in the prior art, the present invention provides a silicon carbide power device with low specific on-resistance and high reliability to solve the technical problems mentioned in the background technology.

[0005] (2) Technical solution

[0006] To achieve the above object, the present invention provides the following technical solution: a silicon carbide power device with low specific on-resistance and high reliability, comprising a semiconductor drain region, which is a semiconductor material heavily doped with a first conductivity type;

[0007] a semiconductor buffer region, which is a slightly heavily doped semiconductor material of the first conductivity type;

[0008] a semiconductor drift region, which is a lightly doped semiconductor material of a first conductivity type;

[0009] A second conductive type semiconductor well region located at a top of the semiconductor drift region;

[0010] a first conductive type semiconductor source region located at a top middle position of a second conductive type semiconductor well region; and a second conductive type semiconductor heavily doped region located at the second conductive type semiconductor well region and away from the middle position;

[0011] A first conductive type carrier diffusion layer is located between the second conductive type semiconductor well region and the second conductive type semiconductor shielding region;

[0012] a first trench located in the middle of the semiconductor drift region and extending from the first conductive type semiconductor source region into the semiconductor drift region;

[0013] The second conductive type semiconductor shielding region surrounds the bottom of the first trench;

[0014] The gate dielectric layer is located on the inner wall of the first trench;

[0015] a gate electrode located on the gate dielectric layer of the first trench;

[0016] an interlayer dielectric layer located above the gate electrode;

[0017] A contact hole is provided in the interlayer dielectric layer;

[0018] Over-etching silicon carbide during contact hole preparation, thereby forming a second trench in the silicon carbide;

[0019] a source metal electrode, located above the interlayer dielectric, and forming an ohmic contact with the first conductive type semiconductor source region and the second conductive type semiconductor heavily doped region through the second trench;

[0020] The drain metal electrode is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0021] The present invention is further configured such that the first conductive type carrier diffusion layer with a thickness of T1 can be ion-implanted on the pattern after photolithography of the first conductive type semiconductor source region, and its doping concentration is less than the doping concentration of the second conductive type semiconductor well region, such as 1×10 17 pieces / cm 3 The preparation of the first conductive type carrier diffusion layer is different from the conventional process of adding a mask to manufacture the first conductive type carrier diffusion layer.

[0022] The present invention is further configured such that the thickness T1 of the first conductive type carrier diffusion layer includes a portion of the first conductive type carrier diffusion layer compounded by diffusion from the bottom of the second conductive type semiconductor well region resulting in a low concentration region, so the first conductive type carrier diffusion layer is distributed in an arc shape away from the first trench side; the width W1 of the first conductive type carrier diffusion layer is smaller than the width W2 of the second conductive type semiconductor well region, such as W2-W1>0.1um.

[0023] The present invention is further configured such that the carrier diffusion layer is prepared so that the thickness of the second conductive type semiconductor well region away from the first trench side is greater than the thickness close to the first trench side, so that the second conductive type semiconductor well region protruding away from the first trench side and the second conductive type semiconductor shielding region at the bottom of the trench jointly optimize the gate oxide electric field.

[0024] The present invention is further configured such that the second conductive type semiconductor well region protruding away from the first trench side can optimize the short-circuit current and avalanche breakdown energy of the device.

[0025] The present invention is further configured such that the thickness of the second conductive type semiconductor heavily doped region is greater than the thickness of the second conductive type semiconductor well region. On the one hand, it modulates the gate oxide electric field together with the second conductive type semiconductor shielding region, and on the other hand, it can also optimize the short-circuit current and avalanche breakdown energy of the device.

[0026] The present invention is further configured as a second trench with a thickness of T2, wherein the thickness T2 is greater than the thickness T3 of the first conductive type semiconductor source region, but does not exceed the bottom of the second conductive type semiconductor heavily doped region, such as T2>0.3um; the width W4 of the second trench can be smaller than the width of the second conductive type semiconductor heavily doped region to obtain a smaller cell size and improve the specific on-resistance.

[0027] The present invention is further configured such that when the second conductive type semiconductor heavily doped region can be implanted with high-energy ions so that its thickness is much greater than the thickness of the second conductive type semiconductor well region, defects will be generated near the surface of the second conductive type semiconductor heavily doped region by the implantation, and the second trench can eliminate such defects.

[0028] The present invention is further configured such that the second conductive type semiconductor shielding region needs to be connected to the source metal to improve the device quality factor. In order to reduce the loss of the conductive channel, the shielding region lead-out ends can be arranged alternately or symmetrically in the local area of ​​the strip-shaped groove.

[0029] The present invention is further configured such that the gate dielectric silicon oxide in the first trench can be formed by thermal growth or prepared by deposition, wherein the gate dielectric layer can also be a high dielectric constant dielectric such as lead zirconate titanate, aluminum oxide, or a combination of silicon oxide and high-K dielectric.

[0030] The present invention also includes a method for manufacturing a silicon carbide power device with low specific on-resistance and high reliability, comprising the following steps:

[0031] Step 1: Prepare a semiconductor drain region heavily doped with a first conductive type semiconductor material, such as a crystal with an impurity atom concentration of 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3The semiconductor buffer region is slightly heavily doped with a first conductive type semiconductor material, such as a crystal with an impurity atom concentration of 1×10 18 pieces / cm 3 -3~5×10 18 pieces / cm 3 A lightly doped semiconductor drift region is formed on the slightly heavily doped semiconductor buffer region, wherein the doping concentration of the semiconductor drift region is 1.0×10 15 pieces / cm 3 -1.0×10 17 pieces / cm 3 ;

[0032] Step 2: Multiple injections of aluminum atoms are made into the top of the semiconductor drift region to form a second conductive type semiconductor well region. The injection dose is 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted multiple times in the middle of the top of the second conductive type semiconductor well region, with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region is formed between the two regions, with a thickness of T3, and then multiple implantations with a dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 Aluminum atoms are formed to form a heavily doped semiconductor region of the second conductivity type;

[0033] Step 3: Ion implantation is performed through the pattern after photolithography of the first conductive type semiconductor source region to form a first conductive type carrier diffusion layer. The thickness of the first conductive type carrier diffusion layer is T1. The thickness T1 includes the first conductive type carrier diffusion layer and a low concentration area caused by diffusion from the bottom of the second conductive type semiconductor well region. Therefore, the first conductive type carrier diffusion layer is distributed in an arc shape away from the side of the first trench; the width W1 of the first conductive type carrier diffusion layer is less than the width W2 of the second conductive type semiconductor well region, such as W2-W1>0.1um.

[0034] Step 4: Deposit a layer of silicon oxide on the semiconductor surface as a hard mask layer HM1. Then, a window is etched in the hard mask. Next, dry-coupled plasma etching, reactive ion etching, or a combination of the two is used to etch the semiconductor drift region to form a first trench. The depth of the trench is less than the thickness of the semiconductor drift region and greater than the sum of the thickness of the second-conductivity-type semiconductor well region adjacent to the first trench and the thickness of the gate dielectric. Ion implantation is then performed using the hard mask layer HM1 as a barrier to form a second-conductivity-type semiconductor shield region at the bottom of the trench. The hard mask layer HM1 is then removed.

[0035] Step 5: Using the hard mask layer HM2 as a barrier, the second conductive type semiconductor shielding region lead-out terminal is prepared by oblique ion implantation. The second conductive type semiconductor shielding region lead-out terminal shorts the second conductive type semiconductor shielding region to the source metal, and its doping concentration is 1 to 10 times that of the second conductive type semiconductor shielding region. In order to reduce the loss of the conductive channel, the shielding region lead-out terminal can be arranged in an alternating manner in the local area of ​​the strip-shaped groove. After removing the hard mask layer HM2, a carbon film is covered on the semiconductor surface and annealed in an inert gas atmosphere at 1600 to 1800°C for about 10 to 60 minutes to activate the impurity activity. The carbon film is then removed.

[0036] Step 6: Deposit or thermally oxidize to form a gate dielectric layer, wherein the gate dielectric layer can also be a high-k dielectric such as lead zirconate titanate, aluminum oxide, or a combination of silicon oxide and high-K dielectric, and its thickness can be 0.02-1 μm. Then, a gate electrode is formed on the gate dielectric layer, wherein the gate electrode can be heavily doped polysilicon;

[0037] Step 7: A certain thickness of undoped silicon oxide and borophosphosilicate glass is deposited above the gate electrode to form an interlayer dielectric layer, the total thickness of which is generally 0.4-1 μm. Then, a through hole is etched in the interlayer dielectric layer. During the contact hole preparation process, silicon carbide is overetched, thereby forming a second trench with a width of W4 and a thickness of T2 in the silicon carbide;

[0038] Step 8: Sputter and etch the front metal above the interlayer dielectric to form a source metal electrode, and sputter a conductive metal below the semiconductor drain region to form a drain metal electrode. Both the source and drain metals form ohmic contacts with the semiconductor.

[0039] (3) Beneficial effects

[0040] Compared with the prior art, the present invention provides a silicon carbide power device with low specific on-resistance and high reliability and a manufacturing method thereof, which has the following beneficial effects:

[0041] 1. The present invention performs ion implantation on the pattern after photolithography of the first conductive type semiconductor source region to prepare a first conductive type carrier diffusion layer through the structure set up, which not only optimizes the specific on-resistance of the device, but also the protruding second conductive type semiconductor well region modulates the gate oxide electric field without adding a mask; further, the second conductive type semiconductor well region protruding away from the first trench side can not only optimize the short-circuit current capability of the device but also optimize the avalanche breakdown energy of the device; further, the second conductive type semiconductor heavily doped region can be implanted with high-energy ions to make its thickness greater than the thickness of the second conductive type semiconductor well region, but the high-energy ion implantation area will produce defects, and the second trench can eliminate such defects; further, the thicker second conductive type semiconductor heavily doped region can not only optimize the gate oxide electric field, but also optimize the short-circuit current capability and avalanche breakdown energy of the device; further, the width of the second trench can be smaller than the width of the semiconductor body contact region to obtain a smaller unit cell size. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic structural diagram of Example 1 of the present application;

[0043] Figure 2 This is a schematic diagram of the initial structure of Example 1 of the present application;

[0044] Figure 3 1 is a schematic structural diagram of forming an active area in Example 1 of the present application;

[0045] Figure 4 This is a schematic structural diagram of forming a first conductive type carrier diffusion layer according to Example 1 of the present application;

[0046] Figure 5 This is a schematic structural diagram of the second conductive type semiconductor shielding region according to embodiment 1 of the present application;

[0047] Figure 6 This is a schematic diagram of the structure of the lead-out end of the second conductive type semiconductor shielding region formed in embodiment 1 of the present application. Figure 1 ;

[0048] Figure 7 This is a schematic diagram of the structure of the lead-out end of the second conductive type semiconductor shielding region formed in Example 1 of the present application. Figure 2 ;

[0049] Figure 8 This is a schematic diagram of the structure of the lead-out end of the second conductive type semiconductor shielding region formed in Example 1 of the present application. Figure 3 ;

[0050] Figure 9 This is a schematic diagram of forming a gate structure according to Example 1 of the present application;

[0051] Figure 10This is a schematic diagram of the structure of the contact hole formed in Example 1 of the present application Figure 1 ;

[0052] Figure 11 This is a schematic diagram of the structure of the contact hole formed in Example 1 of the present application Figure 2 ;

[0053] Figure 12 This is a schematic diagram of the structure of the metal electrode formed in Example 1 of the present application;

[0054] Figure 13 This is a schematic diagram of the structure of Example 2 of the present application;

[0055] Figure 14 This is a schematic structural diagram of Example 3 of the present application;

[0056] Figure 15 This is a schematic structural diagram of Example 4 of the present application;

[0057] In the figure: 1. Semiconductor drain region; 2. Semiconductor buffer region; 3. Semiconductor drift region; 4. Second conductive type semiconductor well region; 5. First conductive type semiconductor source region; 6. Second conductive type semiconductor heavily doped region; 7. First conductive type carrier diffusion layer; 8. First trench; 9. Second conductive type semiconductor shielding region; 10. Gate dielectric layer; 11. Gate electrode; 12. Interlayer dielectric layer; 13-1. Contact hole; 13-2. Second trench; 14. Source metal electrode; 15. Drain metal electrode; 16. Second conductive type semiconductor shielding region lead-out terminal. DETAILED DESCRIPTION

[0058] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0059] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0060] In the present invention, unless otherwise specified, directions such as "up" and "down" are generally used with respect to the directions shown in the drawings, or with respect to the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "left" and "right" are generally used with respect to the left and right shown in the drawings; "inside" and "outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directions are not used to limit the present invention.

[0061] Example 1

[0062] See also Figure 1-15A low-specific on-resistance and high-reliability silicon carbide power device and a manufacturing method thereof, comprising a semiconductor drain region 1, the semiconductor drain region 1 being a heavily doped first-conductivity-type semiconductor material, a semiconductor cache region 2 being provided at the upper end of the semiconductor drain region 1, the semiconductor cache region 2 being a slightly heavily doped first-conductivity-type semiconductor material, a semiconductor drift region 3 being provided at the upper end of the semiconductor cache region 2, the semiconductor drift region 3 being a lightly doped first-conductivity-type semiconductor material, a second-conductivity-type semiconductor well region 4 being provided at the top end of the semiconductor drift region 3, a first-conductivity-type semiconductor source region 5 being provided at the middle position of the top end of the second-conductivity-type semiconductor well region 4, a second-conductivity-type semiconductor heavily doped region 6 being provided away from the middle position of the second-conductivity-type semiconductor well region 4, a first trench 8 being provided at the middle position of the semiconductor drift region 3, the first trench A second conductive type semiconductor shielding region 9 is arranged around the bottom of 8, a gate dielectric layer 10 is arranged on the inner wall of the first trench 8, a gate electrode 11 is arranged on the gate dielectric layer 10, an interlayer dielectric layer 12 is arranged on the gate electrode 11, a source metal electrode 14 is arranged above the interlayer dielectric, and the source metal electrode 14 forms an ohmic contact with the first conductive type semiconductor source region 5 and the second conductive type semiconductor heavily doped region 6 through the second trench 13-2; a drain metal electrode 15 is arranged below the semiconductor drain region 1 and forms an ohmic contact with the semiconductor drain region 1, the first trench 8 extends from the first conductive type semiconductor source region 5 into the semiconductor drift region 3, a contact hole 13-1 is provided in the interlayer dielectric layer 12, and a second trench 13-2 is formed by over-etching into the silicon carbide during the preparation of the contact hole 13-1;

[0063] A method for manufacturing a silicon carbide power device with low specific on-resistance and high reliability comprises the following steps: first, ion implantation of a first conductive type carrier diffusion layer 7 with a thickness of T1 on a pattern of a first conductive type semiconductor source region 5 after photolithography, wherein the doping concentration of the first conductive type carrier diffusion layer 7 is less than the doping concentration of the second conductive type semiconductor well region 4, such as 1×10 17 pieces / cm 3 The preparation of the first conductive type carrier diffusion layer 7 is different from the conventional process of adding a mask to manufacture the first conductive type carrier diffusion layer 7;

[0064] Second, the thickness of the first conductive type carrier diffusion layer 7 is T1. The thickness T1 includes the first conductive type carrier diffusion layer 7 compounding a portion of the low-concentration region caused by diffusion from the bottom of the second conductive type semiconductor well region 4. Therefore, the first conductive type carrier diffusion layer 7 is distributed in an arc shape away from the first trench 8. The width W1 of the first conductive type carrier diffusion layer 7 is smaller than the width W2 of the second conductive type semiconductor well region 4, such as W2-W1>0.1 μm.

[0065] Third, the preparation of the first conductive type carrier diffusion layer makes the thickness of the second conductive type semiconductor well region 4 away from the first trench 8 greater than the thickness close to the first trench 8. Therefore, the second conductive type semiconductor well region 4 protruding away from the first trench 8 and the second conductive type semiconductor shielding region 9 at the bottom of the trench jointly optimize the gate oxide electric field;

[0066] Fourth, the thickness of the second conductive type semiconductor heavily doped region 6 can be greater than the thickness of the second conductive type semiconductor well region 4. On the one hand, it can modulate the gate oxide electric field together with the second conductive type semiconductor shielding region 9. On the other hand, it can also optimize the short-circuit current and avalanche breakdown energy of the device. The second conductive type semiconductor well region 4 protruding away from the side of the first trench 8 can optimize the short-circuit current and avalanche breakdown energy of the device.

[0067] Fifth, the thickness of the second trench 13-2 is T2, which is greater than the thickness T3 of the first conductive type semiconductor source region 5 but does not exceed the bottom of the second conductive type semiconductor heavily doped region 6, for example, T2>0.3 μm; the width W4 of the second trench 13-2 can be smaller than the width of the second conductive type semiconductor heavily doped region 6 to obtain a smaller unit cell size and improve the specific on-resistance. When the second conductive type semiconductor heavily doped region 6 is implanted with high-energy ions so that its thickness is much greater than the thickness of the second conductive type semiconductor well region 4, defects may be generated near the surface of the second conductive type semiconductor heavily doped region 6 due to the implantation, and the second trench 13-2 can eliminate such defects;

[0068] Sixth, in order to reduce the loss of the conductive channel, the shielding area lead-out terminals can be arranged alternately or symmetrically in the local area of ​​the strip-shaped trench, and the second conductive type semiconductor shielding area 9 needs to be connected to the source metal to improve the device quality factor;

[0069] 7. The gate dielectric silicon oxide in the first trench 8 is formed by thermal growth or prepared by deposition, wherein the gate dielectric layer 10 can also be a high dielectric constant dielectric such as lead zirconate titanate, aluminum oxide, or a combination of silicon oxide and high-K dielectric.

[0070] See also Figure 2 As an initial manufacturing method, specifically, the semiconductor drain region 1 is a semiconductor material heavily doped with the first conductivity type, such as a crystal with an impurity atom concentration of 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 The semiconductor buffer region 2 is slightly heavily doped with a first conductive type semiconductor material, such as a crystal with an impurity atom concentration of 1×10 18 pieces / cm 3 -3~5×10 18 pieces / cm 3A lightly doped semiconductor drift region 3 is formed on the slightly heavily doped semiconductor buffer region 2, wherein the doping concentration of the semiconductor drift region 3 is 1.0×10 15 pieces / cm 3 -1.0×10 17 pieces / cm 3 .

[0071] See also Figure 3 As an implementation method for forming an active region, specifically, aluminum atoms are implanted multiple times at the top of the semiconductor drift region 3 to form a second conductive type semiconductor well region 4, with an implantation dose of 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted multiple times in the middle of the top of the second conductive type semiconductor well region 44, with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region 5 is formed between the two regions, with a thickness of T3, and then multiple injections with a dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 Aluminum atoms are formed to form a second conductive type semiconductor heavily doped region 6, the thickness of which is greater than T3.

[0072] See also Figure 4 As an implementation method for forming the first conductive type carrier diffusion layer 7, specifically, ion implantation is performed through the pattern after photolithography of the first conductive type semiconductor source region 5 to form the first conductive type carrier diffusion layer 7. The thickness T1 of the first conductive type carrier diffusion layer 7 includes the first conductive type carrier diffusion layer 7 and a low concentration region caused by diffusion from the bottom of the second conductive type semiconductor well region 4. Therefore, the first conductive type carrier diffusion layer 7 is distributed in an arc shape away from the side of the first trench 8; the width W1 of the first conductive type carrier diffusion layer 7 is smaller than the width W2 of the second conductive type semiconductor well region 4, such as W2-W1>0.1um.

[0073] See also Figure 5As an implementation method for forming the second conductive type semiconductor shielding region 9, specifically, a layer of silicon oxide is deposited on the upper surface of the semiconductor as a hard mask layer HM1, and then a window is etched on the hard mask. Then, the semiconductor drift region 3 is etched by dry coupled plasma etching, reactive ion etching, or a combination of the two to form a first trench 8, the depth of which is less than the thickness of the semiconductor drift region 3 and greater than the sum of the thickness of the second conductive type semiconductor well region 4 adjacent to the first trench 8 and the thickness of the gate dielectric. Then, ion implantation is performed with the hard mask layer HM1 as a barrier to form the second conductive type semiconductor shielding region 9 at the bottom of the trench, and then the hard mask layer HM1 is removed.

[0074] See also Figure 6 , as an implementation method for forming the second conductive type semiconductor shielding region lead-out terminal 16, specifically, wherein Figure 6 Using the hard mask layer HM2 as a barrier, an oblique-angle ion implantation is performed to prepare a second conductive type semiconductor shielding region lead-out terminal 16. The second conductive type semiconductor shielding region lead-out terminal 16 short-circuits the second conductive type semiconductor shielding region 9 with the source metal. The doping concentration thereof is 1 to 10 times that of the second conductive type semiconductor shielding region 9. The top view of the second conductive type semiconductor shielding region lead-out terminal 16 after fabrication is shown in FIG. Figure 7 In order to reduce the loss of the conductive channel, the shielding area leads can be arranged alternately in the local area of ​​the strip groove, where the spacing between the leads is L / 2, which is also an integer multiple of the unit cell size (pitch), that is, L / 2 = n × pitch (n = 1, 2, 3...n). In order to improve the quality factor of the device, the smaller the n, the better. Figure 6 Yes Yan Figure 7 Middle BB' section, Figure 5 It is the AA' section along 7. Figure 8 Figure 1 shows an alternating arrangement of shield region leads. This arrangement allows for better grounding of the second conductivity type semiconductor shield region 9, but increases conductive channel losses. After removing the hard mask layer HM2, a carbon film is applied to the semiconductor surface. This is then annealed in an inert gas atmosphere at 1600-1800°C for approximately 10-60 minutes to activate the impurities. The carbon film is then removed.

[0075] See also Figure 7 As an implementation method for forming a gate structure, specifically, a gate dielectric layer 10 is formed by deposition or thermal oxidation, wherein the gate dielectric layer 10 can also be a high dielectric constant dielectric such as lead zirconate titanate, aluminum oxide, or a combination of silicon oxide and high-K dielectric, and its thickness can be 0.02-1μm, and then a gate electrode 11 is prepared on the gate dielectric layer, wherein the gate electrode 11 can be heavily doped polysilicon.

[0076] See also Figure 8As an implementation method for forming the contact hole 13-113-1, specifically, a certain thickness of undoped silicon oxide and borophosphosilicate glass are deposited above the gate electrode 11 to form an interlayer dielectric layer 12, whose total thickness is generally 0.4-1 μm, and then the contact hole 13-1 is etched in the interlayer dielectric layer 12. During the preparation of the contact hole 13-1, silicon carbide is over-etched, thereby forming a second trench 13-2 with a width of W4 and a thickness of T2 in the silicon carbide.

[0077] See also Figure 9 As an implementation method for forming metal electrodes, specifically, a front metal is sputtered and etched above the interlayer dielectric to form a source metal electrode 14. A conductive metal is sputtered below the semiconductor drain region 1 to form a drain metal electrode 15. Both the source and drain metals form ohmic contacts with the semiconductor.

[0078] Example 2

[0079] See also Figure 13 As an implementation method of Example 2, specifically, by performing slightly higher energy ion implantation on the pattern after photolithography of the first conductive type semiconductor source region 5, the bottom of the first conductive type carrier diffusion layer 7 is made to exceed the bottom of the second conductive type semiconductor shielding region 9, so that this embodiment can obtain a lower specific on-resistance.

[0080] Example 3

[0081] See also Figure 14 As an implementation method of Example 3, specifically, by using high-energy ion implantation in the second conductive type semiconductor heavily doped region 6, the bottom of the second conductive type semiconductor heavily doped region 6 is made to exceed the bottom of the first conductive type carrier diffusion layer 7. The second conductive type semiconductor heavily doped region 6 of this embodiment and the second conductive type semiconductor shielding region 9 jointly optimize the gate oxide electric field. In addition, the second conductive type semiconductor heavily doped region 6 of this embodiment helps to optimize the short-circuit current capability and avalanche breakdown energy of the device; at the same time, a second trench 13-2 is prepared in the semiconductor body contact region of this embodiment, which can eliminate the defects of the second conductive type semiconductor heavily doped region 6 caused by high-energy ion implantation, thereby improving the reliability of the device.

[0082] Example 4

[0083] See also Figure 15As an implementation method of Example 4, specifically, a first conductive type carrier diffusion layer 7 is prepared by performing bulk implantation in the first conductive type semiconductor source region 5 and then performing ion implantation on the pattern after photolithography of the first conductive type semiconductor source region 5. The first conductive type carrier diffusion layer 7 in the bulk area helps to reduce the specific on-resistance of the device. Furthermore, since the second conductive type semiconductor heavily doped region 6 is not implanted with low energy during the multi-step ion implantation, its surface concentration is low and the first conductive type semiconductor source region 5 cannot be recombined and inverted. Therefore, even if the lateral width of the contact hole 13-1 is smaller than the width of the second conductive type semiconductor heavily doped region 6, the bottom and sidewalls of the second trench 13-2 can form good ohmic contact with the second conductive type semiconductor heavily doped region 6 and the first conductive type semiconductor source region 5. Therefore, in order to reduce the cell size, the width of the contact hole 13-1 can be reduced as much as possible, thereby improving the specific on-resistance of the device.

[0084] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0085] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0086] In all the schemes mentioned above, the connection between the two parts can be selected according to actual conditions by welding, bolt and nut connection, bolt or screw connection or other well-known connection methods, which will not be described here one by one. In the above, all fixed connections are preferably considered to be welding. Although the embodiments of the present invention have been shown and described, it can be understood by ordinary technicians in this field that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A silicon carbide power device with low specific on-resistance and high reliability, characterized in that: include: A semiconductor drain region (1) is a semiconductor material heavily doped with a first conductivity type; a semiconductor buffer region (2) made of a slightly heavily doped semiconductor material of the first conductivity type; A semiconductor drift region (3) made of a lightly doped semiconductor material of a first conductivity type; A second conductive type semiconductor well region (4) located at the top of the semiconductor drift region (3); a first conductive type semiconductor source region (5) located at a top middle position of a second conductive type semiconductor well region (4); and a second conductive type semiconductor heavily doped region (6) located at the second conductive type semiconductor well region (4) and away from the middle position; a first conductive type carrier diffusion layer (7) located between the second conductive type semiconductor well region (4) and the second conductive type semiconductor shielding region (9); A first trench (8) is located in the middle of the semiconductor drift region (3) and extends from the first conductive type semiconductor source region (5) into the semiconductor drift region (3); A second conductive type semiconductor shielding region (9) surrounds the bottom of the first trench (8); The gate dielectric layer (10) is located on the inner wall of the first trench (8); a gate electrode (11) located on the gate dielectric layer (10) of the first trench (8); an interlayer dielectric layer (12) located above the gate electrode (11); A contact hole (13-1) is provided in the interlayer dielectric layer (12); During the preparation of the contact hole (13-1), silicon carbide is overetched, thereby forming a second trench (13-2) in the silicon carbide; A source metal electrode (14) is located above the interlayer dielectric and forms an ohmic contact with the first conductive type semiconductor source region (5) and the second conductive type semiconductor heavily doped region (6) through the second trench (13-2); A drain metal electrode (15) is located below the semiconductor drain region (1) and forms an ohmic contact with the semiconductor drain region (1).

2. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The first conductive type carrier diffusion layer (7) with a thickness of T1 can be ion-implanted on the pattern of the first conductive type semiconductor source region (5) after photolithography, and its doping concentration is less than the doping concentration of the second conductive type semiconductor well region (4), such as 1×10 17 pieces / cm 3 The preparation of the first conductive type carrier diffusion layer (7) is different from the conventional process of adding a mask plate to manufacture the first conductive type carrier diffusion layer (7).

3. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The thickness T1 of the first conductive type carrier diffusion layer (7) includes a low concentration region caused by diffusion from the bottom of the second conductive type semiconductor well region (4) and a composite portion of the first conductive type carrier diffusion layer (7). Therefore, the first conductive type carrier diffusion layer (7) is distributed in an arc shape away from the side of the first trench (8); the width W1 of the first conductive type carrier diffusion layer (7) is smaller than the width W2 of the second conductive type semiconductor well region (4), such that W2-W1>0.1 μm.

4. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The carrier diffusion layer is prepared so that the thickness of the second conductive type semiconductor well region (4) away from the first trench (8) is greater than the thickness on the side close to the first trench (8), so the second conductive type semiconductor well region (4) protruding away from the side of the first trench (8) and the second conductive type semiconductor shielding region (9) at the bottom of the trench jointly optimize the gate oxide electric field.

5. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The second conductive type semiconductor well region (4) protruding away from the first trench (8) can optimize the short-circuit current and avalanche breakdown energy of the device.

6. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The thickness of the second conductive type semiconductor heavily doped region (6) is greater than the thickness of the second conductive type semiconductor well region (4). On the one hand, the heavily doped region and the second conductive type semiconductor shielding region (9) can modulate the gate oxide electric field, and on the other hand, can also optimize the short-circuit current and avalanche breakdown energy of the device.

7. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The second trench (13-2) has a thickness T2, wherein the thickness T2 is greater than the thickness T3 of the first conductive type semiconductor source region (5), but does not exceed the bottom of the second conductive type semiconductor heavily doped region (6), such as T2>0.3um; the width W4 of the second trench (13-2) can be smaller than the width of the second conductive type semiconductor heavily doped region (6) to obtain a smaller unit cell size and improve the specific on-resistance.

8. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: When the second conductive type semiconductor heavily doped region (6) can be implanted with high-energy ions so that its thickness is much greater than the thickness of the second conductive type semiconductor well region (4), defects will be generated near the surface of the second conductive type semiconductor heavily doped region (6) due to the implantation, and the second trench (13-2) can eliminate such defects.

9. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that: The second conductive type semiconductor shielding region (9) needs to be connected to the source metal to improve the device quality factor. In order to reduce the loss of the conductive channel, the shielding region lead-out end can be arranged alternately or symmetrically in the local area of ​​the strip-shaped groove.

10. A silicon carbide power device with low specific on-resistance and high reliability according to claim 1, characterized in that The gate dielectric silicon oxide in the first trench (8) can be formed by thermal growth or deposition, wherein the gate dielectric layer (10) can also be a high dielectric constant dielectric such as lead zirconate titanate, aluminum oxide, or a combination of silicon oxide and high-K dielectric.

11. The present invention also includes a method for manufacturing a silicon carbide power device with low specific on-resistance and high reliability, characterized in that: These include: Step 1: Prepare a semiconductor drain region heavily doped with a first conductive type semiconductor material (1) such as a crystal with an impurity atom concentration of 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 The semiconductor buffer region (2) is slightly heavily doped with a first conductive type semiconductor material, such as a crystal with an impurity atom concentration of 1×10 18 pieces / cm 3 -3~5×10 18 pieces / cm 3 A lightly doped semiconductor drift region (3) is formed on the slightly heavily doped semiconductor buffer region (2), wherein the doping concentration of the semiconductor drift region (3) is 1.0×10 15 pieces / cm 3 -1.0×10 17 pieces / cm 3 ; Step 2: Multiple injections of aluminum atoms are made into the top of the semiconductor drift region (3) to form a second conductive type semiconductor well region (4). The injection dose is 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted multiple times in the middle of the top of the second conductive type semiconductor well region (4), with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region (5) is formed between the two regions, and its thickness is T3. Then, multiple injections with a dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 Aluminum atoms are added to form a second conductive type semiconductor heavily doped region (6); Step 3: Ion implantation is performed through the pattern after photolithography of the first conductive type semiconductor source region (5) to form a first conductive type carrier diffusion layer (7). The thickness T1 of the first conductive type carrier diffusion layer (7) includes a low concentration region caused by diffusion from the bottom of the second conductive type semiconductor well region (4) by the first conductive type carrier diffusion layer (7). Therefore, the first conductive type carrier diffusion layer (7) is distributed in an arc shape away from the side of the first trench (8); the width W1 of the first conductive type carrier diffusion layer (7) is less than the width W2 of the second conductive type semiconductor well region (4), such as W2-W1>0.1um; Step 4: depositing a layer of silicon oxide as a hard mask layer HM1 on the upper surface of the semiconductor, then etching a window on the hard mask, and then etching the semiconductor drift region (3) by dry coupled plasma etching, reactive ion etching, or a combination of the two to form a first trench (8), the depth of which is less than the thickness of the semiconductor drift region (3) and greater than the sum of the thickness of the second conductive type semiconductor well region (4) adjacent to the first trench (8) and the thickness of the gate dielectric; then, using the hard mask layer HM1 as a barrier, ion implantation is performed to form a second conductive type semiconductor shielding region (9) at the bottom of the trench, and then the hard mask layer HM1 is removed; Step 5: Using the hard mask layer HM2 as a barrier, a second conductive type semiconductor shielding region lead-out terminal 16 is prepared by oblique angle ion implantation. The second conductive type semiconductor shielding region lead-out terminal 16 short-circuits the second conductive type semiconductor shielding region (9) with the source metal, and its doping concentration is 1 to 10 times that of the second conductive type semiconductor shielding region (9). In order to reduce the loss of the conductive channel, the shielding region lead-out terminal can be arranged in an alternating manner in a local area of ​​the strip-shaped groove. After removing the hard mask layer HM2, a carbon film is covered on the semiconductor surface, and annealed in an inert gas atmosphere at 1600 to 1800° C. for about 10 to 60 minutes to activate the impurity activity, and then the carbon film is removed. Step 6: forming a gate dielectric layer (10) by deposition or thermal oxidation, wherein the gate dielectric layer (10) may be a high dielectric constant dielectric such as lead zirconate titanate, aluminum oxide, or a combination of silicon oxide and a high-K dielectric, and its thickness may be 0.02-1 μm, and then forming a gate electrode (11) on the gate dielectric layer, wherein the gate electrode (11) may be heavily doped polysilicon; Step 7: Depositing a certain thickness of non-doped silicon oxide and borophosphosilicate glass above the gate electrode (11) to form an interlayer dielectric layer (12), the total thickness of which is generally 0.4-1 μm. Then, etching a through hole in the interlayer dielectric layer (12). During the preparation of the contact hole (13-1), silicon carbide is overetched, thereby forming a second trench (13-2) with a width of W4 and a thickness of T2 in the silicon carbide. Step 8: sputter and etch the front metal above the interlayer dielectric to form a source metal electrode (14); sputter a conductive metal below the semiconductor drain region (1) to form a drain metal electrode (15). Both the source and drain metals form ohmic contacts with the semiconductor.

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