Manufacturing method of SGT device
By using a field dielectric layer with superimposed structure in SGT device manufacturing and performing chemical mechanical grinding, the residual problem of polycrystalline silicon gate etching caused by excessive field oxygen thickness is solved, and the high yield and benign characteristics of the device are achieved.
Patent Information
- Application Number
- CN202510381997.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-06-13
AI Technical Summary
During the manufacturing process of SGT devices, polysilicon gate etching remains due to excessively thick field oxygen thickness, resulting in the problem of device G/S shorting and contact holes not being opened normally.
A field dielectric layer composed of the first oxide layer, the second silicon nitride layer and the third oxide layer are used to superimpose the field dielectric layer by chemical mechanical polishing to ensure the correct etching of the polycrystalline silicon gate.
Effectively eliminate the residual polysilicon gate etching, avoid the problem of device G/S shorting and contact holes that cannot be opened normally, and improve product yield.
Smart Images
Figure CN120152364A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a shielded gate trench (SGT) device. Background Art
[0002] With the increase in the voltage segment of UDSGT products, the field oxide thickness becomes thicker and thicker. During the wafer fabrication process, it is found that due to the increasing thickness of the field oxide, the oxide layer thickness in the area outside the active region (AA) also becomes thicker and thicker. Moreover, there is a step difference at the junction between the AA region and the surrounding terminal regions, namely the guard ring (GR) region or the dummy structure (Dummy) region. During the subsequent gate (Gate) polysilicon (Poly) etching process, Poly residues will be formed in the oxide layer thickness transition region and the position where the oxide layer thickness is relatively thick; the Poly residue in the oxide layer thickness transition region will connect the Gate connection (Linkup) region with the source (Source) Linkup region, resulting in a short circuit between the gate and the source of the device; in addition, the Poly residue in the region with a relatively thick oxide layer causes the contact hole (CT) to not be opened normally, resulting in a decrease in the breakdown voltage (BV). The gate structure of the SGT device includes a left-right type structure and an up-down type structure. UDSGT represents the up-down type structure, which means that the source polysilicon and the polysilicon gate are in an up-down structure.
[0003] Currently, the Poly residues in the oxide layer thickness transition region and the region with a relatively thick oxide layer of the SGT are too thick. Simply increasing the overetching (0E) amount of the Poly etching will cause overetching of the Gate Poly, i.e., the polysilicon gate, in the device cell (Cell) region, affecting the channel length and the connection between the N+(Nplus) region, i.e., the N+ source region, and the channel. Therefore, it is necessary to optimize and innovate from the process perspective. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing an SGT device, which can eliminate the etching residue of the polysilicon gate caused by the too thick field dielectric layer while ensuring that the thickness of the field dielectric layer is relatively thick to meet the withstand voltage requirements.
[0005] To solve the above technical problem, the method for manufacturing an SGT device provided by the present invention includes the steps of:
[0006] Form a trench in a semiconductor substrate.
[0007] Form a field dielectric layer composed of a first oxide layer, a second silicon nitride layer, and a third oxide layer on the inner surface of the trench and the surface of the semiconductor substrate outside the trench.
[0008] Form a source polysilicon layer to fill the trench and make the top surface of the source polysilicon layer flush with the top surface of the semiconductor substrate.
[0009] Perform chemical mechanical polishing with the second silicon nitride layer as the stop layer to thin the field dielectric layer on the surface of the semiconductor substrate.
[0010] Form a first mask layer to open the active region and cover the terminal regions on the periphery of the active region.
[0011] Perform the first polysilicon etching to lower the top surface of the source polysilicon layer in the active region to the desired position.
[0012] Perform the first oxide layer etching to remove the third oxide layer exposed on the sidewalls of the trenches in the active region.
[0013] Remove the first mask layer.
[0014] Perform the first silicon nitride etching to remove the second silicon nitride layer outside the trenches and exposed on the sidewalls of the trenches in the active region.
[0015] Remove the first oxide layer on the sidewalls of the trenches above the top surface of the source polysilicon layer in the active region and form an inter-poly dielectric layer, a gate dielectric layer, and a polysilicon gate in the trenches above the top surface of the source polysilicon layer in the active region.
[0016] A further improvement is that the semiconductor substrate includes a silicon substrate.
[0017] A further improvement is that the first oxide layer is formed by a thermal oxidation process.
[0018] The second nitride layer is formed by a chemical vapor deposition (CVD) process or a furnace process.
[0019] The third oxide layer is formed by a CVD process.
[0020] A further improvement is that the thickness of the first oxide layer is greater than and less than or equal to
[0021] A further improvement is that the source polysilicon layer is formed by a polysilicon deposition process plus polysilicon etching.
[0022] A further improvement is that after the source polysilicon layer is formed, it further includes: forming a liner oxide layer on the top surface of the source polysilicon layer.
[0023] After the chemical mechanical polishing is completed, it further includes: removing the liner oxide layer.
[0024] A further improvement is that the liner oxide layer is removed by wet cleaning.
[0025] A further improvement is that the first mask layer is composed of photoresist.
[0026] A further improvement is that the first polysilicon etching is performed by dry etching.
[0027] A further improvement is that the first oxide layer etching is performed by wet etching.
[0028] A further improvement is that the first silicon nitride etching is performed by wet etching.
[0029] A further improvement is that after the first silicon nitride etching, the following steps are further included:
[0030] A fourth oxide layer is formed by using a high-density plasma (HDP) CVD process. The fourth oxide layer completely fills the trench above the top surface of the source polysilicon layer in the active region and extends to the surface outside the trench.
[0031] A second oxide layer etching is performed to remove both the fourth oxide layer and the first oxide layer located above the top surface of the source polysilicon layer in the active region and in the terminal region.
[0032] A further improvement is that the second oxide layer etching is performed by wet etching.
[0033] A further improvement is that after the second oxide layer etching, the inter-poly dielectric layer and the gate dielectric layer are simultaneously formed by a thermal oxidation process. The inter-poly dielectric layer is located on the top surface of the source polysilicon layer in the active region, and the gate dielectric layer is located on the side surface of the trench above the top surface of the source polysilicon layer.
[0034] A further improvement is that the polysilicon gate is formed by a polysilicon deposition process plus polysilicon etching.
[0035] In the present invention, the field oxide layer is replaced by a field dielectric layer formed by stacking a first oxide layer, a second silicon nitride layer, and a third oxide layer. The three-layer stacked structure can ensure the thickness of the field dielectric layer, so that the field dielectric layer meets the breakdown voltage requirement between the source polysilicon layer and the semiconductor substrate. Therefore, the present invention can obtain a relatively thick field dielectric layer and meet the device breakdown voltage requirement.
[0036] Meanwhile, in the three-layer structure of the field dielectric layer of the present invention, the third oxide layer on the surface of the platform area between the trenches can be removed by chemical mechanical polishing with the second silicon nitride layer as the stop layer; after the source polysilicon in the active area is etched to the required depth position, the second silicon nitride layer and the first oxide layer on the surface of the platform area can also be removed respectively. In this way, the field oxide layer in the platform area is removed, which can eliminate the problem that a relatively thick field oxide layer remains in the platform area of the terminal area in the existing process and the resulting polysilicon residue generated in the subsequent polysilicon gate etching process. Thus, the problems of gate-source short circuit and abnormal opening of contact holes caused by polysilicon production can be eliminated, and the product yield can be improved.
[0037] In addition, the second silicon nitride layer of the present invention can also protect the first oxide layer during the etching process of the third oxide layer after the source polysilicon in the active area is etched to the required depth position. In this way, after the second silicon nitride layer is removed, the side walls and the outer surface of the trenches at the top of the source polysilicon layer in the active area still retain the first oxide layer. At this time, the first oxide layer can prevent the etching effect in the subsequent HDPCVD from chamfering the top corners of the trenches, thereby preventing the change in the channel depth caused by the chamfering of the top corners of the trenches and the leakage problem caused by the shallowing of the channel depth. Brief Description of the Drawings
[0038] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:
[0039] Figure 1 is a flowchart of the manufacturing method of the SGT device according to an embodiment of the present invention;
[0040] Figures 2A - 2N is a schematic diagram of the device structure in each step of the manufacturing method of the SGT device according to an embodiment of the present invention;
[0041] Figure 3A is a photo of the chamfering of the top corners of the platform areas on both sides of the trenches caused by the HDPCVD process in the manufacturing method of the existing SGT device;
[0042] Figure 3B is a photo of the HDPCVD process in the manufacturing method of the SGT device according to an embodiment of the present invention without chamfering the top corners of the platform areas on both sides of the trenches. Detailed Description of the Embodiments
[0043] As Figure 1 shown, it is a flowchart of the manufacturing method of the SGT device according to an embodiment of the present invention; as Figures 2A to 2N shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the SGT device according to an embodiment of the present invention; the manufacturing method of the SGT device according to an embodiment of the present invention includes the steps:
[0044] Step S101, as Figure 2AAs shown, a trench 102 is formed on a semiconductor substrate 101.
[0045] Figure 2A In this case, the inner surface of the trench 102 is separately represented by a mark 102a.
[0046] In the trench 102, a source polysilicon layer 104 and a polysilicon gate 108 need to be formed simultaneously. Therefore, the depth of the trench 102 is generally deeper than that of a trench for forming only a polysilicon gate, and the trench 102 is also generally referred to as a deep trench. The depth of the trench 102 refers to the longitudinal extension dimension of the trench 102 in the semiconductor substrate 101.
[0047] In an embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.
[0048] The steps of forming the trench 102 include:
[0049] Form a hard mask layer 102 and perform patterned etching on the hard mask layer 102. After the patterned etching, an opening will be formed in the hard mask layer 102 in the formation region of the trench 102.
[0050] After that, use the hard mask layer 102 as a mask to etch the semiconductor substrate 101 to form the trench 102.
[0051] After that, remove the hard mask layer 102.
[0052] SGT devices will be formed in both the active region 101a and the terminal region 101b. Figure 2A In this case, the active region 101a and the terminal region 101b are respectively located on both sides of the AA line. Figure 2A This is only a cross-sectional view of a partial area of the SGT device. Generally, the terminal region 101b will surround the active region 101a. The active region 101a is mainly used to form the unit structure of the SGT device. An electrode lead-out structure such as a source lead-out structure will be formed in the terminal region 101b.
[0053] Step S102: Form a field dielectric layer 103 composed of a first oxide layer 103a, a second silicon nitride layer 103b, and a third oxide layer 103c on the inner surface of the trench 102 and the surface of the semiconductor substrate 101 outside the trench 102.
[0054] In an embodiment of the present invention, as Figure 2B shown, the first oxide layer 103a is formed by a thermal oxidation process. The quality of the oxide layer formed by the thermal oxidation process is better. The first oxide layer 103a can ensure a good contact interface with the semiconductor substrate 101 and guarantee the quality of the entire field dielectric layer 103.
[0055] In some embodiments, the thickness of the first oxide layer 103a is greater than and less than or equal to
[0056] As Figure 2C shown, the second nitride layer is formed by using a CVD process or a furnace tube process.
[0057] As Figure 2D shown, the third oxide layer 103c is formed by using a CVD process. A thicker oxide layer can be obtained by using the CVD process, so the thickness of the field dielectric layer 103 can be ensured by the third oxide layer 103c.
[0058] Step S103: As Figure 2E shown, a source polysilicon layer 104 is formed to fill the trench 102 and make the top surface of the source polysilicon layer 104 flush with the top surface of the semiconductor substrate 101.
[0059] In the embodiment of the present invention, the source polysilicon layer 104 is formed by using a polysilicon deposition process plus polysilicon etching.
[0060] Step S104: As Figure 2G shown, chemical mechanical polishing (CMP) is performed using the second silicon nitride layer 103b as a stop layer to thin the field dielectric layer 103 on the surface of the semiconductor substrate 101.
[0061] Figure 2G In, the area shown by the dashed box 203 is the area where the field dielectric layer 103 on the corresponding platform area is removed. It can be seen that the third oxide layer 103c above the top surface of the semiconductor substrate 101 outside the trench 102 is removed.
[0062] It can be seen that the second silicon nitride layer 103b is used as the endpoint of the oxide removal CMP above the mesa area. Compared with the existing CMP that controls the endpoint by time, the in-plane uniformity of the oxide removal in the embodiment of the present invention is good, and the problem of poor in-plane uniformity in the existing method of removing oxide can be eliminated.
[0063] In the embodiment of the present invention, after the source polysilicon layer 104 is formed and before step S104, it further includes: As Figure 2F shown, a liner oxide 202 is formed on the top surface of the source polysilicon layer 104.
[0064] After the chemical mechanical polishing is completed, it further includes: As Figure 2HAs shown, the inner lining oxide layer 202 is removed. Preferably, the inner lining oxide layer 202 is removed by dip cleaning.
[0065] In an embodiment of the present invention, the use of the inner lining oxide layer 202 can solve the problem of mismatched CMP contamination properties. In other embodiments, if Poly bare CMP is supported, the steps of forming and removing the inner lining oxide layer 202 can be omitted.
[0066] Step S105, as Figure 2I shown, a first mask layer 204 is formed to open the active region 101a and cover the terminal region 101b on the periphery of the active region 101a.
[0067] In an embodiment of the present invention, the first mask layer 204 is composed of photoresist.
[0068] Step S106, as Figure 2I shown, a first polysilicon etching is performed to lower the top surface of the source polysilicon layer 104 in the active region 101a to a desired position.
[0069] Figure 2I In [description], a source electrode lead-out structure will be formed in the terminal region 101b. Therefore, it is necessary to keep the top surface of the source polysilicon layer 104 in the terminal region 101b flush with the top surface of the semiconductor substrate 101 to facilitate the formation of a contact hole on the top surface of the source polysilicon layer 104.
[0070] In an embodiment of the present invention, the first polysilicon etching uses dry etching.
[0071] Step S107, as Figure 2J shown, a first oxide layer etching is performed to remove the third oxide layer 103c exposed on the side of the trench 102 in the active region 101a.
[0072] Figure 2J In [description], the removal area of the third oxide layer 103c is as shown by the dashed box 204 and is located on the side of the exposed trench 102. Before the first oxide layer etching, after the chemical mechanical polishing is completed, the third oxide layer 103c outside the trench 102 is removed. Therefore, in the first oxide layer etching, only the third oxide layer 103c exposed on the side of the trench 102 needs to be removed.
[0073] In an embodiment of the present invention, the first oxide layer etching uses wet etching.
[0074] Due to the protection of the second silicon nitride layer 103b, in the first oxide layer etching, the first oxide layer 103a is not affected by wet etching, and the exposure of the Si surface can be prevented.
[0075] Step S108, as Figure 2K shown, remove the first mask layer 204.
[0076] Step S109, as Figure 2K shown, perform a first silicon nitride etching to remove the second silicon nitride layer 103b exposed outside the trench 102 and on the side surfaces of the trench 102 in the active region 101a. The removal area of the second silicon nitride layer 103b is as shown by the dashed box 205, including the side surfaces of the exposed trench 102 in the active region 101a and the surfaces of each platform region, i.e., between the trenches 102, i.e., the surface of the semiconductor substrate 101. In the terminal region 101b, the top portion of the side surface of the trench 102 of the second silicon nitride layer 103b is removed and a depression is formed. Similarly, in the active region 101a, depressions are also formed on both sides of the top surface of the source polysilicon layer 104 after the second silicon nitride layer 103b and the third oxide layer 103c are etched.
[0077] In the embodiment of the present invention, the first silicon nitride etching is performed by wet etching.
[0078] Step S110, remove the first oxide layer 103a on the side surface of the trench 102 above the top surface of the source polysilicon layer 104 in the active region 101a, and form an inter-poly dielectric layer 106, a gate dielectric layer 107, and a polysilicon gate 108 in the trench 102 above the top surface of the source polysilicon layer 104 in the active region 101a.
[0079] In the embodiment of the present invention, after the first silicon nitride etching, the following steps are further included:
[0080] As Figure 2L shown, form a fourth oxide layer 105 by using the HDPCVD process. The fourth oxide layer 105 completely fills the trench 102 above the top surface of the source polysilicon layer 104 in the active region 101a and extends to the surface outside the trench 102.
[0081] As Figure 2L can be seen, the fourth oxide layer 105 also fills the depressions at the top portions of the side surfaces of the trench 102 in the terminal region 101b and the depressions on both sides of the top surface of the source polysilicon layer 104 in the active region 101a.
[0082] When performing the HDPCVD process, in the embodiment of the present invention, the semiconductor substrate 101 is not exposed, so chamfering of the platform region corners will not occur, effectively improving the channel depth variation caused by chamfering, and then effectively improving the leakage problem caused by the shallowing of the channel depth.
[0083] It can be seen from Figure 2M that a second oxide layer etching is performed to remove both the fourth oxide layer 105 and the first oxide layer 103a in the terminal region 101b and above the top surface of the source polysilicon layer 104 in the active region 101a. At the same time, it can be seen from Figure 2M that after the second oxide layer etching, oxide layers 206 without depressions are formed on both sides of the source polysilicon layer 104 in the active region 101a.
[0084] In an embodiment of the present invention, the second oxide layer etching is performed by wet etching.
[0085] As Figure 2N shown, after the second oxide layer etching, a thermal oxidation process is used to simultaneously form the inter-poly dielectric layer 106 and the gate dielectric layer 107. The inter-poly dielectric layer 106 is located on the top surface of the source polysilicon layer 104 in the active region 101a, and the gate dielectric layer 107 is located on the side surface of the trench 102 above the top surface of the source polysilicon layer 104. At this time, both the inter-poly dielectric layer 106 and the gate dielectric layer 107 are oxide layers. Since the source polysilicon layer 104 is a polycrystalline structure and the oxidation rate is faster, the thickness of the inter-poly dielectric layer 106 is thicker. The inter-poly dielectric layer 106 is an inter-poly oxide (IPO).
[0086] After that, a polysilicon deposition process and a polysilicon etching are used to form the polysilicon gate 108.
[0087] In an embodiment of the present invention, the field oxide layer is replaced with a field dielectric layer 103 formed by stacking a first oxide layer 103a, a second silicon nitride layer 103b, and a third oxide layer 103c. The three-layer stacked structure can ensure the thickness of the field dielectric layer 103, so that the field dielectric layer 103 meets the breakdown voltage requirement between the source polysilicon layer 104 and the semiconductor substrate 101. Therefore, the embodiment of the present invention can obtain a thicker field dielectric layer 103 and meet the device breakdown voltage requirement.
[0088] Meanwhile, in the three-layer structure of the field dielectric layer 103 in the embodiment of the present invention, the third oxide layer 103c on the surface of the platform region between the trenches 102 can be removed by chemical mechanical polishing with the second silicon nitride layer 103b as the stop layer; after the source polysilicon in the active region 101a is etched to the required depth position, the second silicon nitride layer 103b and the first oxide layer 103a on the surface of the platform region can also be removed respectively. In this way, the field oxide layers in the platform region are all removed, which can eliminate the problem that a relatively thick field oxide layer remains in the platform region of the terminal region 101b in the existing process and the resulting polysilicon residue generated in the subsequent polysilicon gate 108 etching process, thereby eliminating the problems of gate-source short circuit and abnormal opening of contact holes caused by polysilicon production, and improving the product yield.
[0089] In addition, the second silicon nitride layer 103b in the embodiment of the present invention can also protect the first oxide layer 103a during the etching process of the third oxide layer 103c after the source polysilicon in the active region 101a is etched to the required depth position. In this way, after the second silicon nitride layer 103b is removed, the first oxide layer 103a still remains on the side and outer surface of the trench 102 at the top of the source polysilicon layer 104 in the active region 101a. At this time, the first oxide layer 103a can prevent the etching effect in the HDPCVD from chamfering the top angle of the trench 102 in the subsequent HDPCVD, thereby preventing the channel depth change caused by the chamfering of the top angle of the trench 102 and the leakage problem caused by the shallowing of the channel depth. That is, Figure 2L In the corresponding step of forming the fourth oxide layer 105, in the prior art, the top region of the semiconductor substrate in the platform region is exposed, and chamfering will occur under the etching action of the plasma in the HDPCVD process, such as Figure 3A shown, the top angle of the semiconductor substrate located between the trenches marked by the label 301 alone will generate a chamfer as shown in the dotted circle 302. In the embodiment of the present invention, Figure 2L in, the surface of the semiconductor substrate 101 is not exposed, and the top region of the platform region still covers the first oxide layer 103a, so chamfering will not occur in the HDPCVD process; as Figure 3B shown, the label 101' alone marks the semiconductor substrate after the process of the embodiment of the present invention. It can be seen that no chamfering occurs in the top angle region corresponding to the dotted circle 303 between the trenches.
[0090] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.
Claims
1. A method for manufacturing a SGT device, characterized in that: Includes steps: forming a trench in a semiconductor substrate; Forming a field dielectric layer formed by stacking a first oxide layer, a second silicon nitride layer and a third oxide layer on the inner surface of the trench and the surface of the semiconductor substrate outside the trench; forming a source polysilicon layer to fill the trench and make the top surface of the source polysilicon layer flush with the top surface of the semiconductor substrate; Performing chemical mechanical polishing using the second silicon nitride layer as a stop layer to thin the field dielectric layer on the surface of the semiconductor substrate; Forming a first mask layer to open the active area and cover the terminal area around the active area; performing a first polysilicon etch to lower the top surface of the source polysilicon layer in the active area to a desired position; Performing a first oxide layer etching to remove the third oxide layer exposed on the side of the trench in the active area; removing the first mask layer; Performing a first silicon nitride etching to remove the second silicon nitride layer exposed outside the trench and on the side of the trench in the active area; The first oxide layer on the side of the trench above the top surface of the source polysilicon layer in the active area is removed, and an inter-polysilicon dielectric layer, a gate dielectric layer and a polysilicon gate are formed in the trench above the top surface of the source polysilicon layer in the active area.
2. The method for manufacturing a SGT device according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.
3. The method for manufacturing a SGT device according to claim 1, wherein: The first oxide layer is formed by a thermal oxidation process; The second nitride layer is formed by a CVD process or a furnace tube process; The third oxide layer is formed by using a CVD process.
4. The method for manufacturing a SGT device according to claim 1, wherein: The thickness of the first oxide layer is greater than and less than or equal to 5. The method for manufacturing a SGT device according to claim 1, wherein: The source polysilicon layer is formed by a polysilicon deposition process plus polysilicon etching.
6. The method for manufacturing a SGT device according to claim 1, wherein: After the source polysilicon layer is formed, the method further includes: forming a liner oxide layer on the top surface of the source polysilicon layer; After the chemical mechanical polishing is completed, the method further includes: removing the liner oxide layer.
7. The method for manufacturing a SGT device according to claim 6, wherein: The liner oxide layer is removed by wet cleaning.
8. The method for manufacturing a SGT device according to claim 1, wherein: The first mask layer is composed of photoresist.
9. The method for manufacturing a SGT device according to claim 1, wherein: The first polysilicon etching is performed by dry etching.
10. The method for manufacturing a SGT device according to claim 1, wherein: The first oxide layer etching is performed by wet etching.
11. The method for manufacturing a SGT device according to claim 1, wherein: The first silicon nitride etching is performed by wet etching.
12. The method for manufacturing a SGT device according to claim 1, wherein: After the first silicon nitride etching, the process further comprises the following steps: forming a fourth oxide layer by using a HDPCVD process, wherein the fourth oxide layer completely fills the trench above the top surface of the source polysilicon layer in the active area and extends to the surface outside the trench; A second oxide layer etching is performed to remove the fourth oxide layer and the first oxide layer located above the top surface of the source polysilicon layer in the active area and the terminal area.
13. The method for manufacturing a SGT device according to claim 12, wherein: The second oxide layer etching is performed by wet etching.
14. The method for manufacturing a SGT device according to claim 12, wherein: After the second oxide layer etching, the inter-polysilicon dielectric layer and the gate dielectric layer are simultaneously formed by a thermal oxidation process, wherein the inter-polysilicon dielectric layer is located on the top surface of the source polysilicon layer in the active area, and the gate dielectric layer is located on the side of the groove above the top surface of the source polysilicon layer.
15. The method for manufacturing a SGT device according to claim 14, wherein: The polysilicon gate is formed by a polysilicon deposition process plus polysilicon etching.