Back contact battery with specific emitter and preparation method and application thereof

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell with a specific emitter and a preparation method and application of the back contact cell with the specific emitter. The second semiconductor layer comprises a first intrinsic silicon layer, a doped silicon dielectric layer and a second doped amorphous silicon layer which are sequentially arranged on the back surface, the doped silicon dielectric layer and the second doped amorphous silicon layer have the same doping type and are n-type or p-type, and the doped silicon dielectric layer is silicon carbide, silicon oxide or silicon oxycarbide of the corresponding doping type; the thickness of the doped silicon dielectric layer is 1-3 nm, and the ratio of the thickness of the doped silicon dielectric layer to the thickness of the first intrinsic silicon layer to the thickness of the second doped amorphous silicon layer is 1: (2-5): (3-7). According to the invention, rapid separation of photon-generated carriers is promoted, recombination is reduced, and open-circuit voltage of the cell is improved, so that cell efficiency and stability are improved, and cell efficiency attenuation in severe environments such as humid and hot environments is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery with a specific emitter, and a preparation method and application thereof. Background Art

[0002] The existing back-contact battery includes an n-type monocrystalline silicon wafer, an intrinsic amorphous silicon layer and an antireflection layer sequentially arranged on the front surface of the silicon wafer, an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, a transparent conductive film layer and a metal grid line layer sequentially arranged on the surface of the p-region on the back surface of the silicon wafer, and an intrinsic amorphous silicon layer, an n-type amorphous silicon layer, a transparent conductive film layer and a metal grid line layer sequentially arranged on the surface of the n-region on the back surface of the silicon wafer.

[0003] However, in the above battery structure, due to the weak built-in electric field, there is a disadvantage of poor ability to effectively collect carriers, resulting in a decrease in battery performance such as short-circuit current and open-circuit voltage, poor battery stability and serious efficiency decay.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects that the battery efficiency and battery stability of the existing back-contact battery need to be further improved, and to provide a back-contact battery with a specific emitter, and a preparation method and application thereof, which are beneficial to promoting the rapid separation of photo-generated carriers, reducing recombination, increasing the open-circuit voltage of the battery, thereby improving the battery efficiency and its stability, and effectively reducing the battery efficiency decay in harsh environments such as high humidity and high temperature.

[0006] To achieve the above object, in a first aspect, the present invention provides a back-contact battery with a specific emitter, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a first intrinsic silicon layer, a doped silicon dielectric layer and a second doped amorphous silicon layer sequentially arranged on the back surface, the doped silicon dielectric layer has the same doping type as the second doped amorphous silicon layer and the doping type is n-type or p-type, the doped silicon dielectric layer is silicon carbide, silicon oxide or silicon oxycarbide of the corresponding doping type; the thickness of the doped silicon dielectric layer is 1-3 nm, and the thickness ratio of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer is 1:(2-5):(3-7).

[0007] Preferably, in the present invention, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus and its corresponding doping element shows an increasing distribution in the direction away from the back surface of the silicon wafer; and / or, the corresponding doping element in the second doped amorphous silicon layer is boron or phosphorus and its doping concentration of the corresponding doping element shows an increasing distribution in the direction away from the back surface of the silicon wafer.

[0008] In some preferred embodiments of the present invention, the atomic content ratio of hydrogen element to silicon element in the second doped amorphous silicon layer is (0.05 - 0.33):1, and / or the hydrogen element content in the second doped amorphous silicon layer in terms of atomic content is 5% - 25%.

[0009] In some preferred embodiments of the present invention, the hydrogen element content in the second doped amorphous silicon layer shows a decreasing distribution along the direction away from the back surface of the silicon wafer.

[0010] In some preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence or is an initial film layer and an outermost film layer arranged in sequence. The hydrogen element content in the initial film layer in terms of atomic content is 15% - 25%, the hydrogen element content in the intermediate film layer in terms of atomic content is 10% - 15%, and the hydrogen element content in the outermost film layer in terms of atomic content is 5% - 12%.

[0011] In some preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence. The film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1:(1 - 2):(1 - 3).

[0012] Preferably in the present invention, the second doped amorphous silicon layer is an initial film layer and an outermost film layer arranged in sequence, and the film thickness ratio of the initial film layer to the outermost film layer is 1:(1 - 4).

[0013] In some preferred embodiments of the present invention, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus; wherein, the doping concentration of the corresponding doping element of the doped silicon dielectric layer is 1e18 cm -3 -5e19 cm -3 , and / or the doping concentration ratio of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer is (0.01 - 0.5):1.

[0014] In some preferred embodiments of the present invention, one of the first doped silicon layer and the second doped amorphous silicon layer is n-type and the other is p-type. The phosphorus doping concentration of the corresponding doping layer of the n-type is 5e19 cm -3 -5e21 cm -3 , and the boron doping concentration of the corresponding doping layer of the p-type is 2e18 cm -3 -8e20 cm -3 .

[0015] In some preferred embodiments of the present invention, the first intrinsic silicon layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer. The thickness of the first intrinsic silicon layer is 5 - 12 nm, and the thickness of the second doped amorphous silicon layer is 6 - 15 nm.

[0016] In some preferred embodiments of the present invention, the first passivation layer is a tunneling oxide layer, the first doped silicon layer is a doped polysilicon layer, and the thickness ratio of the tunneling oxide layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(3 - 6):(1 - 2).

[0017] In some preferred embodiments of the present invention, the first passivation layer is an intrinsic silicon layer, the first doped silicon layer is doped amorphous silicon or doped microcrystalline silicon, and the thickness ratio of the intrinsic silicon layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(1 - 1.5):(0.8 - 2.5).

[0018] In some preferred embodiments of the present invention, the back contact battery further includes at least one of the following structures: Structure 1: The back contact battery further includes a front passivation layer and an antireflection layer sequentially disposed on the front side of the silicon wafer. The front passivation layer is a stack of a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially disposed on the front side or is a second intrinsic amorphous silicon layer. When the front passivation layer is a stack, the thickness ratio of the second intrinsic amorphous silicon layer contained therein to the microcrystalline silicon oxide layer and the first intrinsic silicon layer is 1:(1.5 - 4):(1.1 - 2.5); Structure 2: Both ends of the second semiconductor layer extend outward to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the region between them is an interval region; in the interval region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer; Structure 3: The back contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is formed in the conductive film layer.

[0019] In a second aspect, the present invention provides a method for manufacturing a back contact battery with a specific emitter, which is used to manufacture the back contact battery with a specific emitter described in the first aspect. The manufacturing method includes the following steps: S1. Provide a double-sided polished silicon wafer; S2. Form a first semiconductor layer and a mask layer sequentially on the back surface of the silicon wafer; S3. Perform a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4. Texturing and cleaning, and then select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer according to needs; S6. Deposit a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer sequentially on the back surface to form a second semiconductor layer.

[0020] In some preferred embodiments of the present invention, the doping types of both the doped silicon dielectric layer and the second doped amorphous silicon layer are p-type doping; wherein the preset PECVD film formation temperatures in the corresponding preparation processes of the doped silicon dielectric layer and the second doped amorphous silicon layer are independently 140 - 250 °C; the deposition conditions for preparing the doped silicon dielectric layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 100 - 1000 Pa, the average flow rate of silane to be 10 - 2000 sccm, and the average flow rate of hydrogen to be 20000 - 200000 sccm; the deposition conditions for preparing the second doped amorphous silicon layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 40 - 500 Pa, the average flow rate of silane to be 100 - 2000 sccm, and the average flow rate of hydrogen to be 5000 - 100000 sccm.

[0021] In some preferred embodiments of the present invention, the preparation method further includes the following steps: S5. After S4, a front passivation layer is sequentially formed on the front surface of the silicon wafer, and then S6 is carried out; S6. Further includes forming a protective sacrificial layer on the outer surface of the second doped amorphous silicon layer, the protective sacrificial layer being a silicon oxide layer and / or a silicon nitride layer, and the thickness of the protective sacrificial layer being 5 - 50 nm; then S7 is carried out; S7. An antireflection layer is formed outside the front passivation layer on the front surface of the silicon wafer; S8. A second etching opening is carried out on a part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then cleaning is carried out, and the protective sacrificial layer is removed during the cleaning process; S9. A conductive film layer is deposited on the back surface obtained in S8; S10. A third etching opening is carried out on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove; S11. Metal electrodes are respectively formed on the outer surfaces of the conductive film layers corresponding to the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0022] In a third aspect, the present invention provides a battery assembly, which includes the back contact battery with a specific emitter described in the first aspect, or includes a back contact battery prepared by the preparation method of the back contact battery with a specific emitter described in the second aspect.

[0023] Beneficial effects: Through the above technical solutions, the present invention particularly uses a specific emitter formed by including a specific first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer as the second semiconductor layer. The doped silicon dielectric layer is silicon carbide, silicon oxide, or silicon carbon oxide of the corresponding doping type. Since the doped silicon dielectric layer with a specific composition has a larger optical bandgap than the second doped amorphous silicon layer, it is beneficial to form a larger band bending at the pn junction interface to enhance the built-in electric field, thereby facilitating the rapid separation of photo-generated carriers, reducing recombination, increasing the open-circuit voltage of the battery, improving the battery efficiency and its stability, and effectively reducing the attenuation of the battery efficiency under harsh environments such as high humidity and heat. Among them, controlling the thickness ratio of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer within an appropriate range, and cooperating with controlling an appropriately thin doped silicon dielectric layer, can provide good interface passivation and is more conducive to effectively separating photo-generated carriers.

[0024] In a preferred embodiment of the present invention, the specific second semiconductor layer cooperates with controlling the hydrogen element content of the second doped amorphous silicon layer to decrease along the direction away from the back surface of the silicon wafer, which can reduce the density of defect states while improving the denseness of the thin film, and is more conducive to enhancing the reliability and stability of the back contact battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0027] DESCRIPTION OF THE REFERENCE NUMERALS 101 - silicon wafer; 201 - tunneling oxide layer; 202 - n-type polysilicon layer; 401 - first intrinsic amorphous silicon layer; 501 - second intrinsic amorphous silicon layer; 601 - p-type doped silicon carbide; 602 - p-type amorphous silicon layer; 701 - antireflection layer; 801 - transparent conductive film layer; 901 - metal electrode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] In the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0029] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0030] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0031] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0032] The hydrogen content in the film layer of the present invention is obtained by Fourier infrared spectroscopy.

[0033] In a first aspect, the present invention provides a back-contact battery with a specific emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, the first semiconductor layer comprising a first passivation layer and a first doped silicon layer, the second semiconductor layer comprising a first intrinsic silicon layer, a doped silicon dielectric layer and a second doped amorphous silicon layer sequentially arranged on the back side, the doped silicon dielectric layer and the second doped amorphous silicon layer having the same doping type and being n-type or p-type, the doped silicon dielectric layer being silicon carbide, silicon oxide or silicon oxycarbide of the corresponding doping type; the thickness of the doped silicon dielectric layer is 1-3 nm, and the ratio of the thickness of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer is 1:(2-5):(3-7).

[0034] The doping type of the doped silicon dielectric layer is the same as that of the second doped amorphous silicon layer and is n-type or p-type, which means that when the second doped amorphous silicon layer is n-type, the doped silicon dielectric layer is also n-type, and when the second doped amorphous silicon layer is p-type, the doped silicon dielectric layer is also p-type. The doped silicon dielectric layer is silicon carbide, silicon oxide or silicon oxycarbide of the corresponding doping type, which means that if the doped silicon dielectric layer is n-type, the doped silicon dielectric layer is n-type doped silicon carbide, n-type doped silicon oxide or n-type doped silicon oxycarbide; if the doped silicon dielectric layer is p-type, the doped silicon dielectric layer is p-type doped silicon carbide, p-type doped silicon oxide or p-type doped silicon oxycarbide.

[0035] In the present invention, one of the first doped silicon layer and the second doped amorphous silicon layer is n-type and the other is p-type. In some preferred embodiments of the present invention, in the first doped silicon layer and the second doped amorphous silicon layer, the phosphorus doping concentration of the corresponding doped layer of the n-type is 5e19 cm -3 -5e21 cm -3 , and the boron doping concentration of the corresponding doped layer of the p-type is 2e18 cm -3 -8e20 cm -3 . It can be understood that if the first doped silicon layer is n-type, the corresponding doped layer of the n-type is the first doped silicon layer.

[0036] In some preferred embodiments of the present invention, the atomic content ratio of hydrogen element to silicon element in the second doped amorphous silicon layer is (0.05 - 0.33):1, preferably (0.05 - 0.15):1. Using the second doped amorphous silicon layer with an appropriate ratio of silicon to hydrogen content is more conducive to balancing the passivation effect and conductivity of the film layer and improving the stability of the film layer.

[0037] Preferably in the present invention, the hydrogen element content in the second doped amorphous silicon layer is 5% - 25% by atomic content, more preferably 5% - 20%, and further preferably 8% - 17%. Using the second doped amorphous silicon layer with an appropriate hydrogen element content, hydrogen can passivate the dangling bonds in the second doped amorphous silicon layer, reduce the density of defect states, shift the Fermi level towards the valence band top, and thereby improve the hole mobility and conductivity of the second doped amorphous silicon layer; moreover, when the hydrogen element content is within an appropriate range, it can effectively avoid structural defects such as microvoids in the amorphous silicon thin film, the second doped amorphous silicon layer has good film compactness, so the film has good acid and alkali resistance and is not easily damaged during the corresponding preparation process (such as being cleaned with chemical solutions in subsequent patterning processes), thus being conducive to maintaining a high battery efficiency.

[0038] In some preferred embodiments of the present invention, the hydrogen element content of the second doped amorphous silicon layer shows a decreasing distribution in the direction away from the back surface of the silicon wafer, which can reduce the density of defect states while improving the compactness of the thin film, and is more conducive to enhancing the reliability and stability of the back contact battery.

[0039] In some more preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence or is the initial film layer and the outermost film layer arranged in sequence. The hydrogen element content of the initial film layer in terms of atomic content is 15% - 25%, preferably 15% - 24%; the hydrogen element content of the intermediate film layer in terms of atomic content is 10% - 15%, preferably 10% - 14%; the hydrogen element content of the outermost film layer in terms of atomic content is 5% - 12%, preferably 5% - 9%. In the preferred solution of the present invention, the initial film layer having a suitably high hydrogen element content is conducive to forming a more stable interface and helps to reduce the interface state density; the outermost film layer having a suitably low hydrogen element content is conducive to increasing the effective doping concentration and the film denseness. Since patterning needs to be performed on the film during the preparation of the back contact battery, the improvement of the film denseness can reduce the influence of the chemical solution during the patterning process of the back contact battery, which is conducive to maintaining the quality of the film and further conducive to improving the stability and reliability of the battery.

[0040] In some preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence. The film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1:(1 - 2):(1 - 3), preferably 1:(1 - 2):(1.5 - 3). Adopting this preferred solution is more conducive to reducing the interface and bulk defect state density and reducing the microvoids in the film layer, and improving the stability of the film layer.

[0041] In some preferred embodiments of the present invention, the second doped amorphous silicon layer is the initial film layer and the outermost film layer arranged in sequence. The film thickness ratio of the initial film layer and the outermost film layer is 1:(1 - 4), preferably 1:(1.5 - 4).

[0042] Preferably in the present invention, the corresponding doping element in the second doped amorphous silicon layer is boron or phosphorus and the doping concentration of the corresponding doping element shows an increasing distribution in the direction away from the back surface of the silicon wafer, which is more conducive to improving the effective transport of carriers, thereby improving the battery efficiency and its stability.

[0043] Preferably in the present invention, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus and the corresponding doping element shows an increasing distribution in the direction away from the back surface of the silicon wafer, which is more conducive to promoting the separation and transport of carriers.

[0044] Among them, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus, which respectively corresponds to p-type or n-type.

[0045] In some preferred embodiments of the present invention, the doping concentration of the corresponding doping element of the doped silicon dielectric layer is 1e18 cm -3 - 5e19 cm -3 、preferably 1e18 cm -3 - 3e19 cm-3 , which is more conducive to forming a gradually changing energy band structure, promoting the transport of holes to the electrode, and at the same time blocking the reverse diffusion of electrons.

[0046] Preferably, in the present invention, the doping concentration ratio of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer is (0.01 - 0.5):1, preferably (0.02 - 0.5):1. Adopting this preferred scheme is more conducive to reducing lattice distortion, reducing the contact barrier with the transparent conductive film layer, and reducing carrier transport loss. It should be noted that the doping concentration ratio of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer in the present invention refers to that the ratio of the maximum doping concentration of the corresponding doping element of the doped silicon dielectric layer to the maximum doping concentration of the corresponding doping element of the second doped amorphous silicon layer is within the above range, and the ratio of the minimum doping concentration of the corresponding doping element of the doped silicon dielectric layer to the minimum doping concentration of the corresponding doping element of the second doped amorphous silicon layer is within the above range.

[0047] In some preferred embodiments of the present invention, the first intrinsic silicon layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer, and the former is more preferred.

[0048] Further preferably, the thickness of the first intrinsic silicon layer is 5 - 12 nm.

[0049] Preferably, the thickness of the second doped amorphous silicon layer is 6 - 15 nm.

[0050] In some preferred embodiments of the present invention, the first passivation layer is a tunneling oxide layer, and the first doped silicon layer is a doped polysilicon layer. Adopting the combined passivation structure in cooperation with the specific emitter of the present application as the second semiconductor layer is more conducive to improving the passivation ability and stability of the back-contact battery.

[0051] Further preferably, the thickness ratio of the tunneling oxide layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(3 - 6):(1 - 2), preferably 1:(4 - 6):(1.1 - 2), which is more conducive to the effective separation of electrons and holes, thereby improving the battery efficiency and its stability.

[0052] The thickness and doping concentration of the doped polysilicon layer in the present invention can refer to the prior art respectively. For example, the thickness of the doped polysilicon layer can be 30 - 250 nm, and the doping concentration is greater than 5e18 cm -3 .

[0053] In some preferred embodiments of the present invention, the first passivation layer is an intrinsic silicon layer, and the first doped silicon layer is doped amorphous silicon or doped microcrystalline silicon. The intrinsic silicon layer is intrinsic amorphous silicon or intrinsic microcrystalline silicon.

[0054] Further preferably, the thickness ratio of the intrinsic silicon layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(1 - 1.5):(0.8 - 2.5), which is more conducive to balancing surface passivation and conductivity, and improving the final conversion efficiency of the battery.

[0055] In some preferred embodiments of the present invention, the back contact battery further includes a front passivation layer and an antireflection layer sequentially disposed on the front surface of the silicon wafer.

[0056] Further preferably, the front passivation layer is a stack of a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially disposed on the front surface or is the second intrinsic amorphous silicon layer. Adopting this specific front passivation layer and cooperating with the specific back passivation structure of the present invention is more conducive to improving the effective utilization rate of photo-generated carriers.

[0057] Further preferably, when the front passivation layer is a stack, the thickness ratio of the second intrinsic amorphous silicon layer contained therein to the microcrystalline silicon oxide layer and the first intrinsic silicon layer is 1:(1.5 - 4):(1.1 - 2.5), which is more conducive to improving surface passivation and carrier transport ability.

[0058] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outward to cover a part of the back surface of the adjacent first semiconductor layer respectively, and a first semiconductor opening area that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening area is formed between adjacent first semiconductor layers. The second semiconductor opening area and the first semiconductor opening area are arranged at intervals, and the area between them is an interval area.

[0059] In the present invention, in the interval area, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer.

[0060] In some preferred embodiments of the present invention, the back contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on the conductive film layer to prevent the first semiconductor layer and the second semiconductor layer from short-circuiting. The isolation groove is located in the area where the interval area is located. It can be understood that the metal electrode is disposed on the outer surface of the conductive film layer corresponding to the second semiconductor opening area and the first semiconductor opening area respectively. The settings of the conductive film layer, the metal electrode and the isolation groove can refer to the prior art and can all be used in the present invention, and will not be elaborated here.

[0061] In the second aspect, the present invention provides a method for manufacturing a back contact battery with a specific emitter, which is used to manufacture the back contact battery with a specific emitter described in the first aspect. The manufacturing method includes the following steps: S1. Provide a double-sided polished silicon wafer; S2. Form a first semiconductor layer and a mask layer sequentially on the back surface of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, texturing and cleaning, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S6. Depositing a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer in sequence on the back side to form a second semiconductor layer.

[0062] In some preferred embodiments of the present invention, the doping types of the doped silicon dielectric layer and the second doped amorphous silicon layer are both p-type doping.

[0063] Preferably, the preset PECVD film forming temperatures in the corresponding preparation processes of the doped silicon dielectric layer and the second doped amorphous silicon layer are independently controlled to be 140-250° C. A suitable film forming temperature is more conducive to forming a corresponding doped silicon layer with moderate and uniform doping, and having a more stable Si-Si network structure, which is conducive to improving battery stability.

[0064] Preferably, in the present invention, the deposition conditions corresponding to the preparation of the doped silicon dielectric layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 100-1000Pa, the average silane flow rate to be 10-2000sccm, and the average hydrogen flow rate to be 20000-200000sccm. The required doping gas source is determined according to the doping type and type corresponding to the doped silicon dielectric layer, as long as the doped film layer with the target doping concentration is obtained; illustratively, when the doping type corresponding to the doped silicon dielectric layer is p-type and the type corresponding to the doped silicon dielectric layer is silicon carbide, the required doping gas source can be diborane and methane, the average diborane flow rate is 1-50sccm, and the average methane flow rate is 5-200sccm.

[0065] Preferably, in the present invention, the deposition conditions corresponding to the preparation of the second doped amorphous silicon layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to 40-500Pa, the average silane flow rate to 100-2000sccm, and the average hydrogen flow rate to 5000-100000sccm. The required doping gas source is determined according to the doping type and type corresponding to the doped silicon dielectric layer, as long as the doped film layer with the target doping concentration is obtained; illustratively, when the doping type corresponding to the second doped amorphous silicon layer is p-type, the required doping gas source may include diborane, and the average diborane flow rate is 10-200sccm. Among them, the average flow rate of the doping gas source and / or the average flow rate of hydrogen can be adjusted to adjust the content trend of the doping element and / or hydrogen.

[0066] The texturing cleaning in S4 of the present invention can remove the residual mask layer and the first semiconductor layer in the second semiconductor opening area, and simultaneously form a texturing surface on the front side of the silicon wafer and the second semiconductor opening area.

[0067] In some preferred embodiments of the present invention, the preparation method further includes the following steps: S5. After S4, a front passivation layer is sequentially formed on the front side of the silicon wafer, and then S6 is carried out.

[0068] In some preferred embodiments of the present invention, the preparation method further includes the following steps: S6 further includes forming a protective sacrificial layer on the outer surface of the second doped amorphous silicon layer, and removing the protective sacrificial layer during the cleaning process of S7. Further preferably, the protective sacrificial layer is a silicon oxide layer and / or a silicon nitride layer. Further preferably, the thickness of the protective sacrificial layer is 5 - 50 nm. The present invention provides the protective sacrificial layer, which can reduce the influence of the second doped amorphous silicon layer during subsequent chemical solution cleaning in battery preparation and protect it from damage, thereby being more conducive to maintaining the battery efficiency.

[0069] In some preferred embodiments of the present invention, the preparation method further includes the following steps: S7. Form an antireflection layer on the front side of the silicon wafer; S8. Perform a second etching opening on a part of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then perform cleaning, and remove the protective sacrificial layer during the cleaning process; S9. Deposit a conductive film layer on the back side obtained in S8; S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove; S11. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

[0070] In the third aspect, the present invention provides a battery assembly, which includes the back contact battery with a specific emitter described in the first aspect, or includes a back contact battery prepared by the preparation method of the back contact battery with a specific emitter described in the second aspect.

[0071] The following details the embodiments of the present invention, which are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0072] Example 1 A back contact battery has a structure as Figure 1 shown, including an n-type silicon wafer 101, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer 101. The second semiconductor layer includes a first intrinsic silicon layer (i.e., the first intrinsic amorphous silicon layer 401), a doped silicon dielectric layer, and a second doped amorphous silicon layer (p-type amorphous silicon layer 602) sequentially arranged on the back side. The doped silicon dielectric layer is p-type doped silicon carbide 601. It is specifically obtained by the following method: S1. Provide a double-sided polished silicon wafer 101; S2. Form a first semiconductor layer and a mask layer on the back side of the silicon wafer 101 in sequence; the first semiconductor layer includes a tunneling oxide layer 201 with a thickness of 1.5 nm and a first doped silicon layer (n-type polysilicon layer 202 with a thickness of 120 nm and a phosphorus doping concentration of 5e20 cm -3 ). S3. Conduct a first etching opening on the back side obtained in S2 to form a second semiconductor opening region; S4. Perform texturing cleaning to remove the residual mask layer and the first semiconductor layer in the second semiconductor opening region, and at the same time form a textured surface on the front side of the silicon wafer 101 and the second semiconductor opening region, and then remove the mask layer; S5. Form a front passivation layer on the front side of the silicon wafer 101; the front passivation layer is a second intrinsic amorphous silicon layer 501 with a thickness of 6 nm.

[0073] S6. Deposit a first intrinsic silicon layer (i.e., intrinsic amorphous silicon layer) with a thickness of 7.5 nm, a doped silicon dielectric layer, and a second doped amorphous silicon layer (p-type amorphous silicon layer 602) with a thickness of 10 nm on the back side in sequence to form a second semiconductor layer. After calculation, the thickness ratio of the second intrinsic amorphous silicon layer 501 to the first intrinsic silicon layer is 1:1.25. The doped silicon dielectric layer is p-type doped silicon carbide 601 with a thickness of 2 nm. The specific method for depositing p-type doped silicon carbide 601 is as follows: first preset the PECVD film-forming temperature to 200 °C, then introduce a mixed gas of silane, diborane, hydrogen, and methane, the reaction gas pressure is 600 Pa, the average flow rate of silane is 70 sccm, the average flow rate of diborane is 1.4 sccm; the average flow rate of methane is 20 sccm, and the average flow rate of hydrogen is 50000 sccm. The boron doping concentration of p-type doped silicon carbide 601 is 2e18 cm -3 -2e19 cm -3 and shows an increasing distribution in the direction away from the back side of the silicon wafer 101. The boron doping concentration is controlled to change incrementally by controlling the flow rate change of diborane. After conversion, the thickness ratio of the tunneling oxide layer 201 to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:5:1.3.

[0074] The specific method for depositing the p-type amorphous silicon layer 602 is as follows: First, preset the PECVD film-forming temperature at 210 °C, then introduce a mixed gas of silane, diborane, and hydrogen. The reaction gas pressure is 300 Pa, the average flow rate of silane is 400 sccm, the average flow rate of diborane is 20 sccm, and the average flow rate of hydrogen is 20000 sccm. It is divided into an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence. Control the hydrogen content of the initial film layer at 20%, the hydrogen content of the intermediate layer at 13%, and the hydrogen content of the outermost layer at 8%, where the hydrogen content is calculated by atomic content. The total film thickness is 10 nm, and the film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1:1:2. The boron doping concentration of the p-type amorphous silicon layer 602 is 4e18 cm -3 -8e20 cm -3 and shows an increasing distribution in the direction away from the back surface of the silicon wafer 101. After conversion, the ratio of the boron doping concentration of the doped silicon dielectric layer to that of the second doped amorphous silicon layer is (0.025 - 0.5):1. Through Fourier transform infrared spectroscopy (FT-IR) testing, in the direction away from the back surface of the silicon wafer, the atomic content ratio of hydrogen and silicon elements in the p-type amorphous silicon layer 602 is (0.10 - 0.14):1.

[0075] S7. Form an antireflection layer 701 on the front surface of the silicon wafer obtained in S6; S8. Perform a second etching opening on a part of the second semiconductor layer on the back surface of the silicon wafer 101 to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then perform cleaning; S9. Deposit a transparent conductive film layer 801 on the back surface obtained in S8; S10. Perform a third etching opening on a part of the transparent conductive film layer 801 located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove; S11. Form metal electrodes 901 on the outer surfaces of the corresponding transparent conductive film layer 801 in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

[0076] Example 2 It is carried out with reference to Example 1, except that the doped silicon dielectric layer is p-type doped silicon oxide with the same thickness and boron doping concentration. The specific method for depositing p-type doped silicon oxide: First, preset the PECVD film-forming temperature at 210 °C, then introduce a mixed gas of silane, diborane, hydrogen, and carbon dioxide. The reaction gas pressure is 500 Pa, the average flow rate of silane is 85 sccm, the average flow rate of diborane is 3 sccm, the average flow rate of carbon dioxide is 50 sccm, and the average flow rate of hydrogen is 50000 sccm, and deposit to the target thickness and target doping concentration.

[0077] Example 3 It is carried out with reference to Example 1, except that the doped silicon dielectric layer is a p-type doped carbon oxide silicon, and the thickness and boron doping concentration remain unchanged. The specific method for depositing the p-type doped carbon oxide silicon: First, preset the PECVD film-forming temperature to 200 °C, and then introduce a mixed gas of silane, diborane, hydrogen, methane, and carbon dioxide. The reaction gas pressure is 600 Pa, the average flow rate of silane is 90 sccm, the average flow rate of diborane is 2.5 sccm; the average flow rate of methane is 20 sccm, the average flow rate of carbon dioxide is 60 sccm, and the average flow rate of hydrogen is 50000 sccm, and deposit to the target thickness and target doping concentration.

[0078] Example 4 It is carried out with reference to Example 1, except that the hydrogen element content in the second doped amorphous silicon layer is adjusted: the hydrogen element content in the initial film layer is 25% in atomic content, the hydrogen element content in the intermediate film layer is 15% in atomic content, and the hydrogen element content in the outermost film layer is 10% in atomic content; however, the decreasing distribution trend of the hydrogen element content remains unchanged, and the film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer remains unchanged; the specific modified process parameters corresponding to the preparation process are: the reaction gas pressure is 200 Pa, and the average flow rate of silane is 500 sccm. After the same test, in the direction away from the back surface of the silicon wafer, the atomic content ratio of hydrogen element and silicon element in the second doped amorphous silicon layer is (0.12 - 0.16):1.

[0079] Example 5 It is carried out with reference to Example 1, except that the intermediate film layer is not formed in the second doped amorphous silicon layer, so it is composed of the initial film layer and the outermost film layer.

[0080] Example 6 It is carried out with reference to Example 1, except that the doping concentration of the corresponding doping element in the doped silicon dielectric layer is adjusted to 5e18 cm -3 -4e19 cm -3 , and after conversion, the ratio of the boron doping concentration of the doped silicon dielectric layer to the second doped amorphous silicon layer is (0.04 - 0.5):1.

[0081] Example 7 It is carried out with reference to Example 1, except that in S6, a protective sacrificial layer is further formed on the outer surface of the second doped amorphous silicon layer. The protective sacrificial layer is a silicon oxide layer, the thickness of the protective sacrificial layer is 10 nm, and the protective sacrificial layer is removed during the cleaning process in S7.

[0082] Comparative Example 1 It is carried out with reference to Example 1, except that the doped silicon dielectric layer is not provided.

[0083] Comparative Example 2 Performed with reference to Example 1, except that the thickness of the doped silicon dielectric layer is 4 nm. After conversion, the thickness ratio of the doped silicon dielectric layer to the first intrinsic amorphous silicon layer and the second doped amorphous silicon layer is 1:1.875:2.5.

[0084] Test Example The back contact batteries obtained in the above Examples and Comparative Examples were subjected to the same performance tests, and the results are shown in Table 1. Among them, the efficiency decay ratio after damp heat test refers to testing the back contact battery in a damp heat environment at 85% humidity and 85 °C for 48 h to obtain the battery efficiency after the damp heat test, and then calculating the efficiency decay ratio before and after the damp heat test: (battery efficiency before damp heat test - battery efficiency after damp heat test) / battery efficiency before damp heat test. The battery efficiency in Table 1 refers to the battery efficiency before damp heat test. And among them, each performance index of each Example and Comparative Example was respectively converted with Comparative Example 1 as the reference benchmark. The data of Comparative Example 1 is the normalization benchmark 1.000, and other examples were converted based on Comparative Example 1. For example, the efficiency decay ratio before and after damp heat test of Example 1 / the efficiency decay ratio before and after damp heat test of Comparative Example 1 is 0.619.

[0085] Table 1

[0086] From the above results, it can be seen that compared with the Comparative Examples, adopting the embodiment scheme of the present invention is beneficial to promoting the rapid separation of photo-generated carriers, reducing recombination, increasing the open circuit voltage of the battery, thereby increasing the battery efficiency, reducing the efficiency decay before and after damp heat test, and improving the reliability and stability of the back contact battery.

[0087] Furthermore, according to Example 1 and Examples 2-7, it can be seen that adopting the preferred scheme of the present invention is more conducive to improving the battery efficiency, reducing the efficiency decay before and after damp heat test, and further improving the reliability and stability.

[0088] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A back-contact cell with a specific emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, wherein the first semiconductor layer comprises a first passivation layer and a first doped silicon layer, characterized in that: The second semiconductor layer includes a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer arranged in sequence on the back side. The doped silicon dielectric layer and the second doped amorphous silicon layer have the same doping type and are n-type or p-type. The doped silicon dielectric layer is silicon carbide, silicon oxide, or silicon oxycarbide of the corresponding doping type. The thickness of the doped silicon dielectric layer is 1-3 nm, and the ratio of the thickness of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer is 1:(2-5):(3-7).

2. The back contact cell with a specific emitter according to claim 1, characterized in that: The corresponding doping element of the doped silicon dielectric layer is boron or phosphorus and its corresponding doping element is distributed in an increasing manner along the direction away from the back side of the silicon wafer; and / or, the corresponding doping element in the second doped amorphous silicon layer is boron or phosphorus and the doping concentration of its corresponding doping element is distributed in an increasing manner along the direction away from the back side of the silicon wafer.

3. The back contact cell with a specific emitter according to claim 1 or 2, characterized in that: The hydrogen content of the second doped amorphous silicon layer is distributed decreasingly in a direction away from the back side of the silicon wafer, and / or, The atomic content ratio of hydrogen element to silicon element in the second doped amorphous silicon layer is (0.05-0.33):1, and the atomic content of hydrogen element in the second doped amorphous silicon layer is 5%-25%.

4. The back contact cell with a specific emitter according to claim 3, characterized in that: The second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer and an outermost film layer arranged in sequence, or an initial film layer and an outermost film layer arranged in sequence, the initial film layer has a hydrogen content of 15%-25% by atomic content, the intermediate film layer has a hydrogen content of 10%-15% by atomic content, and the outermost film layer has a hydrogen content of 5%-12% by atomic content.

5. The back contact cell with a specific emitter according to claim 4, characterized in that: The second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer and an outermost film layer arranged in sequence, and the film thickness ratio of the initial film layer, the intermediate film layer and the outermost film layer is 1:(1-2):(1-3); or, The second doped amorphous silicon layer is an initial film layer and an outermost film layer arranged in sequence, and the film thickness ratio of the initial film layer and the outermost film layer is 1:(1-4).

6. The back contact cell with a specific emitter according to claim 1, characterized in that: The corresponding doping element of the doped silicon dielectric layer is boron or phosphorus; wherein, The doping concentration of the corresponding doping element in the doped silicon dielectric layer is 1e18cm -3 -5e19cm -3 , and / or, the ratio of the doping concentration of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer is (0.01-0.5):

1.

7. The back contact cell with a specific emitter according to claim 1 or 6, characterized in that: One of the first doped silicon layer and the second doped amorphous silicon layer is n-type and the other is p-type. The phosphorus doping concentration of the corresponding doped layer of the n-type is 5e19cm -3 -5e21cm -3 The boron doping concentration of the corresponding p-type doping layer is 2e18cm -3 -8e20cm -3 ; and / or, The first intrinsic silicon layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer, the thickness of the first intrinsic silicon layer is 5-12 nm, and the thickness of the second doped amorphous silicon layer is 6-15 nm.

8. The back contact cell with a specific emitter according to claim 1, characterized in that: The first passivation layer is a tunneling oxide layer, the first doped silicon layer is a doped polysilicon layer, and the thickness ratio of the tunneling oxide layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(3-6):(1-2).

9. The back contact cell with a specific emitter according to claim 1, characterized in that: The first passivation layer is an intrinsic silicon layer, the first doped silicon layer is doped amorphous silicon or doped microcrystalline silicon, and the thickness ratio of the intrinsic silicon layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(1-1.5):(0.8-2.5).

10. The back contact cell with a specific emitter according to claim 1, characterized in that: The back contact cell also includes at least one of the following structures: Structure 1: The back contact cell further comprises a front passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, the front passivation layer is a stack of a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially arranged on the front side or is a second intrinsic amorphous silicon layer, and when the front passivation layer is a stack, the thickness ratio of the second intrinsic amorphous silicon layer to the microcrystalline silicon oxide layer and the first intrinsic silicon layer is 1:(1.5-4):(1.1-2.5); Structure 2: Both ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, a second semiconductor opening region is formed between adjacent first semiconductor layers, the second semiconductor opening region is arranged at intervals from the first semiconductor opening region, and the region between them is a spacing region; in the spacing region, a mask layer is arranged between the first semiconductor layer and the second semiconductor layer, or no mask layer is arranged; Structure 3: The back-contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is provided on the conductive film layer.

11. A method for preparing a back contact battery with a specific emitter, characterized in that: It is used to prepare a back contact battery with a specific emitter as described in any one of claims 1 to 10, and the preparation method comprises the following steps: S1, provide double-sided polished silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, texturing and cleaning, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S6. Depositing a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer in sequence on the back side to form a second semiconductor layer.

12. The method for preparing a back contact battery with a specific emitter according to claim 11, characterized in that: The doping types of the doped silicon dielectric layer and the second doped amorphous silicon layer are both p-type doping; wherein the preset PECVD film forming temperatures in the corresponding preparation processes of the doped silicon dielectric layer and the second doped amorphous silicon layer are independently controlled to be 140-250° C.; The deposition conditions corresponding to the preparation of the doped silicon dielectric layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to 100-1000Pa, the average silane flow rate to 10-2000sccm, and the average hydrogen flow rate to 20000-200000sccm; the deposition conditions corresponding to the preparation of the second doped amorphous silicon layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to 40-500Pa, the average silane flow rate to 100-2000sccm, and the average hydrogen flow rate to 5000-100000sccm; And / or, the preparation method further comprises the following steps: S5, after S4, forming a front passivation layer on the front side of the silicon wafer in sequence, and then proceeding to S6; S6, further comprising forming a protective sacrificial layer on the outer surface of the second doped amorphous silicon layer, the protective sacrificial layer being a silicon oxide layer and / or a silicon nitride layer, and the thickness of the protective sacrificial layer being 5-50 nm; and then performing S7; S7, forming an anti-reflection layer outside the front passivation layer on the front side of the silicon wafer; S8, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; then performing cleaning, during which the protective sacrificial layer is removed; S9, depositing a conductive film layer on the back surface obtained in S8; S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S11, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

13. A battery assembly, characterized in that: It comprises the back-contact cell with a specific emitter as claimed in any one of claims 1 to 10, or comprises a back-contact cell prepared by the method for preparing a back-contact cell with a specific emitter as claimed in claim 11 or 12.

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